Data processing apparatus and methods

Background of the invention

The DVB-T (Digital Video Broadcasting-Terrestrial) standard uses Orthogonal Frequency Division Multiplexing OFDM to send video and audio data to receivers using a radio signal. There are two modes of the DVB-T standard, which are known as 2k and 8k modes. 2k mode provides 2048 subcarrier signals and 8k 8192 signals. Similarly, in the case of the DVB-1-1 (Digital Video Broadcasting-Handheld) standard, the 4k mode has been introduced, whose number of subcarrier signals is 4096.

Error correction coding schemes, such as LDPC / BCH coding, which were proposed for DVB-T2, are more effective when noise and degradation of symbol values ​​resulting from communication are not correlated. Land broadcast channels may suffer from fading in both time and frequency. In this case, separating coded data bits into different data symbols and separating data symbol communications into different OFDM symbol subcarrier signals to the maximum extent possible can improve error correction coding schemes.

To improve the integrity of data transmitted using DVB-T or DVB-1-1, it is a known way to introduce a symbol interleaving unit to translate the input data symbols because they are mapped to OFDM symbol subcarrier signals. For 2k and 8k mode, the DVB-T standard has the ability to generate addresses to enable mapping. The same applies to the 4k mode in the DVB-H standard, European Patent Application 04251667.4. describes the possibility of generating addresses for the purposes of mapping and the address generator implementing the mapping. The address generator contains a register of linear feedback signals that is used to generate a pseudo random bit sequence and a permutation system. The permutation system permutes the order of contents of the linear register of feedback signals to generate the address. The address provides information on the memory location of the interleaver to write the input data symbol in or read the input data symbol from between the interleaving units for mapping onto one of the OFDM symbol subcarrier signals. Similarly, the address generator in the receiver is set to generate the interleaving unit memory address to save the received data symbols in or read data symbols from the interleaving unit memory from the output symbol stream.

- 2 In accordance with the further improvement of the DVB-T standard, known as DVB-T2, the need for further improvement of data bits communication is combined, and more specifically, the need to improve the interleaving system of data bits encoded with LDPC codes and data symbols to OFDM subcarrier signals.

In the article "A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T" by Horvath and others, published in ISCAS '99, materials from 1999

IEEE International Symposium on Circuits and Systems, in Orlando, Florida, USA from May 30 - June 2, 1999 revealed a reconfigurable signal demapping algorithm that can be used in DVB-T receivers (Digital Video Broadcasting Terrestrial version). The algorithm / architecture supports both hierarchical and non-hierarchical transmission modes for systems that use different modulation and coding schemes. The receiver includes a symbol interleaving unit and a bit interleaving unit.

Documents EP 1 463 255 and EP 1 463 256 disclose an interleaving unit for mapping data symbols to OFDM symbol subcarriers. The interleaving unit includes an address generator. The interleaving unit reads a predetermined number of data symbols stored in its memory and reads data symbols on the OFDM symbol subcarriers, the reading order is different from the loading order, which is determined based on the set of addresses with the result that the data symbols are interleaved. The set of addresses generated by the address generator provides interlacing in 4k mode of the DVB transmitter or receiver.

In the article entitled "IEEE 802.16 TG4 OFDM PHY Proposal for the 802.l6b PHY

Layer "of the IEEE 802.16 working group on access to wireless broadband networks, by Segal Y. et al., Of March 4, 2001 (2001-03-04), pages 1-53, a physical layer specification has been disclosed that includes a data transfer system using OFDM symbols.

Document US 6,353,900 discloses an interleaving unit that is equipped with an address generator for generating the memory address of the interleaving by means of a pseudo-random number generator. The data is stored in the interleaving unit memory in sequential order, and then read from the address generator using the addresses specified by the address generator.

Summary of the Invention

According to the inventions, a data processing device is provided ready for operation for recovering data bits from data symbols obtained from a predetermined number of subcarrier orthogonal frequency division multiplexing (OFDM) signals to form an output bit stream. The data processing apparatus includes a symbol interleaving de-interleaving system capable of loading into the memory of the symbol interleaving, a predetermined number of data symbols from the OFDM subcarrier signals, and from reading from the memory of the symbol interleaving data symbol to the output symbol stream for mapping, the reading being in a different order than loading, with the order being determined from the set

- 3 addresses, with the result that data symbols are eliminated from interleaving the OFDM subcarrier signals into the output symbol stream. The demapping unit is capable of generating, from the data symbols of the output symbol stream, interleaved evenly encoded LDPC data bits by converting each of the data symbols of the output symbol stream representing the modulation symbol of the OFDM subcarrier signals into data bits according to the modulation scheme. The reverse permutation system is adapted to perform the reverse permutation process to obtain a reverse permutation process applied to the interleaved LDPC encoded data bits for performing permutations of LDPC encoded data bits so that many of the LDPC encoded data bits corresponding to the value 1 in any row of information matrix corresponding to the information bits the LDPC code that was used to encode the data bits, was not included in the same symbol. The LDPC decoder is adapted to perform LDPC decoding on LDPC encoded data bits on which the reverse permutation process has been performed to create the output data bits. The symbol interleaving de-interleaving system includes an address generator capable of generating a set of addresses, an generated address for each of the received data symbols to indicate the OFDM subcarrier signal from which the received data symbol is to be mapped to the output symbol stream. The address generator includes a linear register of feedback signals that contains a fixed number of register steps and which works to generate a pseudo random bit sequence in accordance with the generator polynomial;

permutation system receiving the contents of the register steps and performing the permutation of bits present in the register stage in accordance with the permutation code, and to generate the address from one of the OFDM subcarrier signals, and a control unit cooperating with the address control system, generating the address when the generated address exceeds the specified maximum valid address, and wherein the predetermined maximum valid address is in principle four thousand and ninety six, the linear reverse shift register has eleven degrees of register, with a polynomial generator for the linear reverse shift register - "· - · - ⁼ and the permutation order creates the 11-bit address Ri [n] for the i-th data symbol from the n-th bit - "· - - of the register according to the table:

<td>R'i [n] for n =</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Ri [n] for n =</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

In one example, in which the OFDM symbol is generated according to the 4k mode, the predefined maximum valid address is, in principle, four thousand and ninety six, the linear reverse shift register contains eleven stages of the register with the generator polynomial for the linear reverse shift register - "· --- ⁼ and the permutation order creates the 11-bit address Ri [n] for the i-th

- 4 data symbols from the bit present in the n-th degree - "· - '- register according to the following table:

<td>R'i [n] for n =</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Ri [n] for n =</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

In another example, in which the OFDM symbol is generated according to the 32k mode, the specified maximum valid address is approximately thirty-two thousand, the linear feedback register contains fourteen stages with the generator polynomial for the needs of the linear feedback generator and the form of permutation codes with an additional bit, fifteen-bit address Ri [n] for the i-th data symbol based on the bit present in the n-th step of register Ri [n] according to the following table:

<td>Position of R'i bits</td><td> 13</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions Ri</td><td> 6</td><td> 5</td><td> 0</td><td> 10</td><td> 8</td><td> 1</td><td> 11</td><td> 12</td><td> 2</td><td> 9</td><td> 4</td><td> 3</td><td> 13</td><td> 7</td>

In other modes, the maximum valid address, number of steps of the linear reverse register, generator polynomial and permutation code can be adjusted according to the specific number of subcarrier signals per OFDM symbol in each mode.

Embodiments of the invention include a bit interleaving unit that combines a symbol interleaving unit to improve the operation of a PFDM communication system that uses LDPC error correction coding. The bit interleaving unit consists of a permuter which, when transmitting and receiving two or more code bits of the LDPC code as a symbol, performs a permutation process that permutes the bits of LDPC codes so that many code bits corresponding to the value 1 in any row of the information matrix corresponding to the information bits LDPC code has not been included in the same symbol.

The data processing device may be an independent device, but may also be an internal system operating in a device such as a transmitter or in other examples at a receiver.

LDPC codes can provide a high degree of error correction on communication paths, other than AWGN (Additive White Gaussian Noise) channels, which override convolutional codes or Reed Solomon (RS) combined convolutional codes. This solution can be used for communication channels that show a series of errors leading to deletion. Therefore, there is a need to develop a method of increasing the resistance to a series of errors or deleting while maintaining the efficiency of the AWGN communication path.

The invention has been developed in the light of the above circumstances and provides a data processing device and method that can increase fault tolerance in LDPC code bits, such as error series or deletion by combining a bit interleaving unit for encoded LDPC data bits with a signal interleaving unit.

This means that according to the invention, the parity interleaving is performed on the LDPC code obtained by performing the LDPC coding in accordance with the parity check matrix together with the step parity matrix corresponding to the code parity bits.

LDPC so that the LDPC parity bits are interleaved to different places of parity bits.

Various operating modes of the OFDM system have been developed, in which the invention finds application. For example, to obtain a DVB containing a positive parser within a single frequency network, the 32k mode was proposed. To accomplish the 32k trim, prepare a symbol interleaving unit to map the input data symbols to the OFDM symbol subcarrier signals.

Embodiments of the invention show a data processing device operating as a symbol interleaving unit for mapping data symbols of an OFDM symbol interleaved data consisting of about thirty-two thousand subcarrier signals. In one embodiment, the number of subcarrier signals may be a value comprised between twenty four thousand and thirty two thousand seven hundred sixty eight. In addition, the OFDM symbol may contain pilot subcarrier signals that are set to carry known symbols, and the specific maximum valid address depends on the number of pilot subcarrier symbols present in the OFDM symbol. In this form, the 32k mode can be proposed for example for a DVB standard such as DVB-T2, DVBCable2, DVB-T or DVB-H.

Mapping data symbols sent to OFDM symbol subcarrier signals, where the number of subcarrier signals is about thirty-two thousand, is a technical problem requiring simulation analysis and tests to determine the correct generator polynomial for a linear feedback register and permutation order. This is due to the fact that mapping requires symbols to be interleaved into subcarrier signals with the result that subsequent symbols from the input data stream are separated in frequency by the highest possible value to optimize the performance of error correction coding schemes.

As explained below, through performance simulation analyzes that a polynomial generator of a linear feedback register in combination with the permutation system described above provides adequate performance. In addition, by developing a system that implements address generation for each of the 2k, 4k and 8k modes by changing the value of the polynomial generator of the linear feedback register and the permutation order, an inexpensive symbol interleaving unit for the 32k mode can be developed. Further, the transmitters and receiver can be switched between 1k, 2k, 4k, 8k, 16k and 32k modes by changing the generator polynomial and permutation order. This function can be accessed via software (or thanks to built-in signaling), which enables flexible implementation.

Various embodiments and features of the invention are defined in the appended claims. Other aspects of the invention include a data processing device capable of mapping symbols received from a predetermined number of subcarrier orthogonal symbol multiplexing (OFDM) signals into an output stream

- 6 symbols as well as a receiver.

Short description of the drawing

Examples of the invention will now be described based on an example referring to the respective drawings in which the same parts have the same reference numbers:

Figure 1 is a block diagram of an encoded OFDM transmitter that can be used, for example, in the DVB-T2 standard;

Figure 2 shows an example of an LDPC H parity check matrix;

Figure 3 is a diagram illustrating the procedure for decoding an LDPC code;

Figure 4 shows an example of an LDPC code parity check matrix;

Figure 5 is a Tanner plot of a parity check matrix;

Figure 6 shows a variable node;

Figure 7 shows a control node;

Figure 8 is a block diagram showing an example of a transmitter configuration;

Figure 9 shows a parity check matrix;

Figure 10 shows a parity matrix;

Figures 11a and 11b show the LDPC code parity matrix and weighted columns defined in the DVB-S.2 specification;

Figures 12A and 12B show the arrangement of 12 QAM signal points;

Figure 13 shows the arrangement of signal points 64QAM;

Figure 14 shows the arrangement of signal points 64QAM;

Figure 15 shows the layout of 64QAM signal points;

Figures 16 a to 16d show the operation of the demultiplexer 25;

Figures 17a to 17d show the operation of the demultiplexer 25;

Figure 18 is a Tanner chart for decoding LDPC code;

Figure 19a and 19b shows an HT parity matrix having a crotch structure and a Tanner chart corresponding to an HT parity matrix;

Figure 20 shows the parity matrix HT of the parity H matrix corresponding to the LDPC code after performing the parity interleaving on the LDPC code;

Figures 21a and 21b show a converted parity check matrix;

Figure 22 shows the operation of the column interleaving unit 24;

Figure 23 shows the number of memory columns 31 required to perform column interleaving and the start position write address;

Figure 24 shows the number of columns of memory 31 required to be carried out

- 7 column interleaving and start address saving address;

Figure 25 is a diagram illustrating a transmission procedure;

Figure 26a and 26b show the communication path model used during the simulation;

Figures 27 show the relationship between Doppler frequencies td and error rate in simulations;

Figures 28 show the relationship between Doppler frequencies fd and error rate in simulations;

Figure 29 is a block diagram of an encoded OFDM receiver that can be used, for example, in the DVB-T2 standard;

Figure 30 is a diagram illustrating a reception procedure;

Figure 31 shows an example of an LDPC code parity matrix;

Figure 32 shows the matrix (converted parity check matrix) obtained after performing row permutation and column permutation in the parity check matrix;

Figure 33 shows a converted parity check matrix divided into 5 x 5 matrix units;

Figure 34 is a block diagram illustrating an example configuration of a decoding device that performs parallel calculations of the node P;

Figure 35 shows an example of the configuration of an LDPC decoder 56;

Figure 36 is a block diagram illustrating an example configuration of an embodiment of a computer in which the invention is implemented;

Figure 37 is a block diagram of a part of the transmitter shown in Figure 1, in which the symbol mapping unit and frame builder show the operation of the interleaving unit;

Figure 38 is a block diagram of the symbol interleaving unit shown in Figure 37;

Figure 39 is a block diagram of the memory of the interleaver shown in Figure 38 and the corresponding symbol of a back interleaver in a receiver;

Figure 40 is a block diagram of the address generator shown in Figure 38 for the 32k mode;

Figure 41 (a) is a diagram showing the results of interleaving using the generator shown in Figure 40 for positive symbols, Figure 41 (b) is a diagram showing design results of simulations for odd symbols, Figure 41 (c) is a diagram showing comparable results of the address generator using different permutation codes for a positive symbol, and Figure 41 (d) shows the corresponding odd symbol scheme;

Figure 42 is a block diagram of a symbol back interleaving unit

- 8 shown in Figure 29;

Figure 43 (a) shows the results of the interleaving unit using the address generator shown in Figure 40 for even OFDM symbols, and Figure 43 (b) is a diagram showing results for odd OFDM symbols; Figures 44 (a) and 44 (b) are graphs of the distance of the output data of the subcarrier interleaver output that were adjacent to the input of the interleaver;

Figure 44 is a block diagram of the symbol interleaving unit shown in Figure 38, showing an operating mode during which interleaving is performed according to only the odd interleaving mode and

Figure 45 is a block diagram of the symbol back interleaving unit shown in Figure 42 showing an operating mode during which interleaving is performed according to only the odd interleaving mode.

Description of preferred embodiments

Figure 1 shows a block diagram of an OFDM transmitter that can be used, for example, to transfer video images and audio signals in accordance with the DVB-T2 standard. In Figure 1, the program source generates data transmitted by an OFDM transmitter. The video encoder 2, audio encoder 4 and data encoder 6 generate video, audio and other transmitted data which are fed to the program multiplexer 10. The output of the program multiplexer 10 forms a multiplexed stream together with other information necessary to send video, audio and other data signals. Multiplexer 10 generates a stream on the connecting channel 13. There can be many such multiplexed streams that are fed to different branches A, B, etc. For convenience, only branch A is described.

As shown in Figure 1, the OFDM transmitter 11 receives the stream on the multiplexer adapter and energy propagation block 20. The multiplexer adapter and energy dissipation block 20 randomizes the data and supplies the correct data to the further error correction encoder 21, which performs stream error correction coding. The bit interleaving unit 22 provides interleaving of the coded data bits, which in the case of DVB-T2 are the output of the LDCP encoder. The output from the bit interleaving unit 22 is input into the bit in the constellation mapping unit 26, which maps the bit groups to the constellation point, which is used to carry the encoded data bits. The output from the bit to the constellation mapping unit 26 are constellation point labels that reflect real and imaginary elements. Constellation point labels represent data symbols formed of two or more bits depending on the modulation scheme used. They will be called data cells. These data cells are transmitted by a time interleaving unit 30, the purpose of which is to interleave data cells originating from multiple words of the LDPC code. Data cells derived from time interleaving 30 are then sent to modulation and a frame builder 27, which maps data cells to modulation symbols to perform transmission.

Data cells are received in the modulation unit 27 by the frame builder 32 together with

- 9 data cells generated in branch B, etc. in Figure 1, via other channels 31. The frame builder 32 then creates a plurality of data cells into sequences transmitted on OFDM symbols, where the OFDM symbol has many data cells, each of which is mapped to one subcarrier symbol. The number of subcarrier symbols will depend on the system mode, which may include one of the 1k, 2k, 4k, 8k, 16k or 32k modes, each of which provides a different number of subcarrier signals, as per the table, for example:

<td>Mode</td><td>signals Lift</td>

<td>1K</td><td> 756</td>

<td>2K</td><td> 1512</td>

<td>4K</td><td> 3024</td>

<td>8K</td><td> 6048</td>

<td>16K</td><td> 12096</td>

<td>32K</td><td> 24192</td>

The number of subcarrier signals adapted in DVB-T / H

Thus, in one example, the number of subcarrier signals in the 32k mode is twenty four thousand one hundred and ninety two. In the case of the DVB-T2 system, the number of subcarrier signals per OFDM symbol may vary depending on the number of pilot bearers and other reserved bearers. Therefore, in the DVB-T2 system, unlike the DVB-T system, the number of subcarrier signals used for data transmission is not fixed. Broadcasters can choose one of the 1k, 2k, 4k, 8k, 16k, 32k operating modes, each of which provides the appropriate range of subcarrier signals per OFDM symbol of 1024, 2048, 4096, 8192, 16384, 32768, respectively. In the DVB- system T2, the physical layer frame consists of many OFDM symbols. Typically, the frame starts with one or more OFDM P2 intakes or symbols, followed by a data packet carrying OFDM symbols. The end of the physical frame of the layer is marked with symbols that close the frame. In each operating mode, the number of subcarrier signals may vary for each type of symbol. In addition, it may vary depending on whether the bandwidth extension has been selected, or a tone reservation has been initiated, as well as depending on which of the pilot subcarrier patterns has been chosen. In this case, it is difficult to generalize to a certain number of subcarrier signals per OFDM symbol. However, the frequency interleaving unit for each mode can translate any symbol whose number of subcarrier signals is less than or the same as the maximum number of subcarrier signals available for that mode. For example, in the 1k mode, the interleaving unit can operate on symbols with a number of subcarrier signals less than or equal to 1024, and in 16k mode on a number of subcarrier signals less than or equal to 16384.

The order of the data cells carried in each OFDM symbol is then transferred to the symbol interleaving unit 33. The OFDM symbol is then generated

- through the OFDM symbol builder's block 37, which introduces pilot signals and synchronizes signals supplied by the pilot and by the built-in signal generator 36. The OFDM modulator 38 then creates the OFDM symbol in time, which is fed to the protecting introducer 40 to generate a protected period of time between the symbols, then to the converter 42 digital signals to analog (D / A) and finally to the RF amplifier of the RF device 44 for virtual transmission through an OFDM transmitter using an antenna 46.

Embodiments of the invention describe an OFDM communication system that consists of an interleaving unit performing interleaving of coded bits using an LDPC encoder in combination with a symbol interleaving unit that interleaves symbols that reflect one or more interleaved and coded bits into OFDM symbol subcarrier signals. Both the bit interleaving unit and the symbol interleaving unit according to an embodiment of the invention are described in the following paragraphs, starting with the bit interleaving unit which is described together with the LDPC encoding: The bit interleaving unit for the LDPC encoding

LDPC error correction codes

LDPC codes have a high possibility of error correction and have recently been used in communication schemes, including digital satellite transmission such as DVBS.2, which began to be used in Europe (for example, see DVB-S.2: ETSI EN 302 307 V1 1.2 (2006-06)). The use of LDPC codes during terrestrial digital transmissions is also a matter of discussion.

Recent studies have shown that the effectiveness of LDPC codes is approaching the Shannon border, as the code length increases, as with turbo codes. Individual LDPC codes have the property that the minimum distance is proportional to the length of the code; LDPC codes have an advantage in that their probability characteristics are excellent, and the "error floor" type error, which is associated with the decoding characteristics of turbo codes and the like, is very rare.

The LDPC codes will now be discussed in detail. LDPC codes are linear codes. Although they do not have to be binary codes, the following description will apply to LDPC binary codes.

The most important function of LDPC codes is that the parity control matrix defining each LDPC code is a rare matrix that has a very small number of "1" elements, ie its elements are mostly "0".

Figure 2 shows an example of an LDPC H parity check matrix.

Each column of the parity H matrix in Figure 2 has a weighted value of 3 (i.e. 3 elements "1"), and each row has a weighted value of 6 (i.e. 6 elements "1").

Coding based on LDPC codes (i.e. LDPC coding) is accomplished, for example, by counting the G-forming matrix based on the H parity check matrix and multiplying the G-forming matrix by the information bits to generate the word

- 11 code (LDPC code).

In particular, first the LDPC encoder calculates the G matrix that satisfies the equation GHT = 0 using the transposed matrix HT parity check matrix

H. In this case, when the G matrix is ​​equal to the K x N matrix, the encoder multiplies the G matrix by a sequence of K-bit information bits (vector u) to generate the N-bit code word (= uG). The code word (LDPC code) generated by the encoder is received on the receiving side by means of a communication path.

The LDPC code can be decoded thanks to the message transfer algorithm proposed by Gallager and called the "probabilistic decoding algorithm". The message transmission algorithm uses BP propagation on the Tanner chart together with variable nodes (also called communication nodes) and control nodes. In the following description, each of the variable and control nodes will simply be referred to as the "node".

Figure 3 shows the procedure for decoding the LDPC code.

In the following, the actual value, which expresses, in the form of a likelihood ratio, the probability that the i-th bit of the LDPC code (code word) received on the receiving side is "0" is called the received value u01, when applicable. In addition, the output of the message from the control node is called uj, and the output from the variable node as vi.

The LPDC code is decoded as follows. First, as shown in Figure 3, in step S11 the LPDS code is received, the message (control node message) uw is initialized as "0" and the variable k, which has an integer value as an iterative process counter, is initialized as "0" . The process then proceeds to step S12. In step S12, calculations (calculations of the variable node) in the form of Equation (1) are carried out based on the received uoi value obtained by receiving the LDPC code to obtain a message (variable node message) vi, and calculations (calculations of the control node) in the form of Equation (2) are then carried out based on the vi message to obtain the uw message.

EQUALITY 1

<img file="PL2403147T3_D0001.tif" />

EQUALITY 2

<img file="PL2403147T3_D0002.tif" />

dv and dc in Equation (1) and Equation (2) are any parameters that reflect specific numbers 1s in the vertical direction (column) and in the horizontal direction (order) of the H parity matrix. For example, dv = 3 and dc = 6 in code case (3.6).

The relevant ranges used in the calculations of the Equations (1) variable node and the Equations (2) control node calculations are from 1 to dv-1 and from 1 to dc-1 because the message received from the edge (i.e. the line connecting the variable node and the node control with itself), which sends the message, is excluded from calculations in Equations (1) and (2). In fact, the control node of Equation (2) is performed recursively using, as shown in Equation (4), the previously prepared function table R (v1, v2), shown in Equation (3), which is defined as one output in relation to two input data v1 and v2.

EQUATION 3 x = 2tanh^_1 (tanh (ν_Ί/ 2) tanh (Vi / 2) {= R (v- |, v₂)

EQUALITY 4

Uj = R (V, R (v₂. R (v₃. —R (v_dc-2, v_dc_₁)))) ₍₄₎

At step S12, the variable k is increased by "1" and the procedure proceeds to step S13. In step S13, it is determined whether the variable k is greater than the fixed number of iterations for decoding C. If in step S13 it is determined that the variable k is not greater than C, the procedure returns to step S12 to repeat the same process.

If it is determined in step S13 that the variable k is greater than C, the procedure proceeds to step S14 to perform the calculations reflected by Equation (5) to obtain and send the message vi as the final decoding result. Then, the LDPC code decoding procedure ends.

EQUALITY 5

- 13 Vj = u_Oi+ Σ Uj j “1 ... (5)

Here, unlike the calculation of the variable node Equations (1), the calculations in Equation (5) are carried out using uj from all edges connected to the variable node.

Figure 4 shows an exemplary H parity check matrix LDPC (3.6) with code significance ½ and code length 12.

As with the H parity check matrix in Figure 2, the parity check matrix in Figure 4 has a column value of 3 and a row value of 6.

Figure 5 is the Tanner plot of the parity H matrix shown in Figure 4.

In Figure 5, "+" means the control node and "=" the variable node. The control nodes and the variable nodes correspond respectively to the rows and columns of the H parity control matrix. Each connecting line between a pair of control and variable nodes constitutes the edge corresponding to the "1" element of the H parity control matrix.

In particular, when the element of the j-th order and i-th column of the parity check matrix is ​​"1", the i-th node = "(counted from above) and the i-th control node" + "(counted from above) connected are the edge as in Figure 5. Edge means that the code bit corresponding to the variable node has a limit corresponding to the control node.

The sum product algorithm, which is the LDPC code decoding algorithm, constantly performs variable node calculations and control node calculations.

Figure 6 shows the variable node calculations performed on the variable node.

The vi message corresponding to the edge during calculations is obtained in accordance with the calculations of the variable node Equations (1) using the values ​​uoi and messages u1 and u2 received from the other edges connected to the variable node. Messages corresponding to other edges are obtained in the same way.

Figure 7 shows the control node calculations performed at the control node.

The above Equation (2) during calculations in the control node can be written as Equation (6) using a dependent equation in which the sign (x) is 1 when x&gt; 0 and -1 when x &lt;0.

EQUATION 6

<img file="PL2403147T3_D0003.tif" />

In addition, when the function 0 (x) = ln (tanh (x / 2)) is defined, when x&gt; 0, the equation 0-1 (x) = 2tanh-1 (ex) is met, and therefore Equation (6) can be transform into Equation (7). EQUALITY 7

<img file="PL2403147T3_D0004.tif" />

At the control node, the calculations of the control node Equation (2) are carried out in accordance with Equation (7).

That is, at the control node, the message corresponding to the calculation edge is obtained based on the calculations of the control node Equation (7) using messages v1, v2, v3, v4 and v5 from the other edges connected to the control node, as shown in Figure 7. Messages corresponding to other edges are obtained in the same way.

The function 0 (x) in Equation (7) can also be expressed as 0 (x) = ln ((ex + 1) / (ex-1)) and 0 (x) = 0-1 (x) when x&gt; 0 . When functions 0 (x) = 0-1 (x) are installed in the device, they can be used using the same reference table (Look Up Table - LUT).

Despite the fact that LDPC codes are known to have very high efficiency on communication paths (AWGN), it is also known that LDPC codes guarantee high error correction on other paths, compared to convolutional codes or Reed Solomon (RS) combined convolutional codes.

This means that when you select a code that has excellent performance on an AWGN path, that code also generally exhibits excellent performance on other communication paths compared to other codes.

For example, because LDPC codes are used during terrestrial digital broadcasting, it has been suggested that LDPC codes defined in the DVB-S.2 specification and modulation schemes defined in the DVB-T specification be combined and an interleaving unit

- 15 bits that interleaves the bits of LDPC codes have been enabled between the LDPC encoder and the modulator to increase the efficiency of LDPC codes on the AWGN communication path.

However, deletions or series of errors may appear on communication paths that are considered to be ground waves. For example, in an Orthogonal Frequency Division Multiplexed (OFDM) system, a specific symbol (i.e. lowered to zero in power), due to the echo delay, which is a path other than the main path in multi-path environments, in which the Desired to Undesirable Signal Ratio (D / U) is 0 dB, so that the power of the main path as the desired power is equal to the power echoes as undesirable power.

When D / U equals 0 dB, all OFDM symbols at a given time can also be removed (i.e. dropped to zero in power) due to the trembling Doppler frequency, which is the communication path to which the delayed Doppler echo has been added "0".

In addition, a series of errors may appear due to the unstable power or the poor condition of the cables between the antennas and the receivers.

In the prior art, error coding codes having excellent performance on AWGN paths are also often used on communication paths, which appear in a series of errors or erasures.

On the other hand, when the LDPC code is decoded, the variable node corresponding not only to the H parity column column, but also the LDPC code bit is calculated according to Equation (1), which requires the addition of the code bit (the obtained uoi value) of the LDPC as shown in Figure 6. Therefore, the accuracy of the received messages is reduced if an error appears in the code bit used during the calculations of the variable node.

In addition, when the LDPC code is decoded, the control node is calculated according to Equation (7) using a message obtained in the variable node connected to the control node. Therefore, decoding efficiency is reduced if an error having an erase occurs simultaneously (multiple bits of LDPC code) on multiple variable nodes connected to each large control node.

More specifically, for example, when two or more variable nodes connected to a control node are simultaneously wiped out, the control node returns a "0" probability message, which corresponds to a "1" probability, to each variable node connected from the control node. In this case, the control node returning an equal probability message '0' and '1' does not apply to one decoding process, which is a set of variable node calculations and control node calculations. This increases the number of necessary decoding processes, thereby reducing decoding efficiency and increasing the power consumption of the receiver that carries out LDPC code decoding operations.

Therefore, there is a need to develop a method of increasing resistance to a series of errors or

- 16 deletes while maintaining the efficiency of the AWGN communication path.

Here, it will be possible to increase decoding efficiency when the bit interleaving unit that interleaves bits of the LDPC code is introduced between the LDPC encoder and the modulator to increase the performance of LDPC codes on the AWGN communication paths as described above and if the bit interleaving unit is designed in such a way, so that she can do interlacing, to reduce the likelihood of simultaneous error occurrence (multiple bits of LDCP code) on multiple variable nodes connected to a control node.

The invention was developed in the light of the above circumstances and provides a data processing device and method that can increase fault tolerance in LDPC code bits such as series of errors or deletions.

The data interleaving data processing apparatus of the preferred embodiment of the present invention consists of a parity interleaving unit that interleaves the parity of the encoded LDCP data bits by performing the LDCP encoding in accordance with the LDCP code parity check matrix which includes the parity matrix corresponding to the LDPC code parity bits; the parity matrix has a step structure, so the LDPC parity bit is interleaved to another position of the parity bit.

The data processing method used in the data processing device according to a preferred embodiment of the invention comprises a step that causes the data processing device to interleave the LDCP data by performing the LDCP encoding in accordance with the LDCP code parity check matrix which includes the parity matrix corresponding to the parity bits LDPC code; the parity matrix has a step structure, so the LDPC parity bit is interleaved to another position of the parity bit.

That is, according to embodiments of the invention, the parity interleaving is performed on the LDPC code obtained by performing the LDPC coding according to the parity check matrix along with the step parity matrix corresponding to the parity bits of the LDPC code so that the parity bits of the LDPC code are interleaved to different places of parity bits.

The data processing device may be an independent device, but may also be in the form of a block mounted in other devices.

A detailed explanation of an example bit interleaving unit

Figure 8 shows in more detail the parts of the transmitter shown in the Figure and the operation of the bit interleaving unit. In particular, the LDPC encoder 21 will be discussed here. The LDPC encoder 21 encodes the target data into the encoded LDPC data bits along with the information bits corresponding to the target data according to the parity check matrix in which the parity matrix corresponding to the parity bits of the LDPC code has a stepwise structure.

In particular, the LDPC encoder 21 encodes the target data into an LDPC code defined for example in accordance with the DVB-S.2 specification and generates the LDPC code.

- 17 The LDPC code defined in the DVB-S.2 specification is the IRA (Irregular Repeat Accumulate) type code, and the parity matrix in the LDPC code parity check matrix has a step structure. Details on the parity matrix and its step structure will be given below. An example of an IRA code is described in the publication of "Irregular RepeatAccumulate Codes" by H. Jin, A. Khandekar and RJ McEliece, during the Second International Symposium on Turbo Codes and Related Topics, p. 1-8, September 2000.

The LDPC code output from the 21 LDPC encoder is sent to a 22 bit interleaving unit.

The 22 bit interleaving unit is a data processing device that performs interleaving and is equipped with a parity interleaving unit 23, column interleaving unit 24 and demultiplexer 25.

The parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 21 to translate the parity bits of the LDPC code to different parity bit positions and generates the interleaved parity LDPC code for the column interleaving unit 24.

Column interleaving unit 24 performs interleaving of the column on the LDPC code derived from parity interleaving units 23, and then provides the LDPC code of the interleaved columns to demultiplexer 25.

Thus, the LDPC code is transmitted after two or more bits of the LDPC code and is mapped to one orthogonally modulated symbol thanks to the mapping unit 26 described below.

The column interleaving unit 24 performs permutation (e.g., the column interleaving described below) on the LDPC code bits obtained from the parity interleaving unit 23 in such a way that a plurality of LDPC code bits corresponding to "1" in any row of the parity check matrix used by the LDPC encoder 21, is not mapped to one symbol.

The demultiplexer 25 reorganizes the LDPC code obtained from the interleaving unit of columns 24 so that the positions of two or more bits of the LDPC code subject to mapping to one symbol are reorganized to form the LDPC code with increased resistance to AWGN, and then sends the received LDPC code to the mapping unit 26.

The mapping unit 26 maps two or more bits of LDPC codes from the multiplexer 25 to each signal point, which is determined according to a modulation scheme that is used by the orthogonal modulator 27 when performing orthogonal modulation (multi-valued modulation).

More specifically, the mapping unit 26 converts the LDPC code from the multiplexer 25 into symbols (symbol values) in the form of signal points determined according to a modulation scheme on the IQ plane (IQ constellation) defined thanks to axis I defining elements I of the same phases as carriers and the Q axis defining the elements of Q

- 18 orthogonal to carriers.

The modulation scheme that is used by the OFDM transmitter shown in Figure 1 to perform orthogonal modulation includes the modulation scheme defined in the DVB-T specification, which can be exemplified by Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (16QAM), 64QAM, 256QAM, 1024QAM and 4096QAM. One modulation scheme that is used by the orthogonal modulator 27 to perform orthogonal modulation is set, for example, by the operator operating the transmitter shown in Figure 1. Examples of other modulation schemes that the orthogonal modulator 27 may use include 4 pulse amplitude modulation ( 4 Pulse Amplitude Modulation - 4PAM).

The symbol received on the mapping unit 26 is sent to a time interleaving unit that can interleave different LDPC code words into different OFDM symbols. The output of the time interleaving unit 30 is then passed to the frame builder shown in Figure 1. The other parts of the transmitter shown in

Figure 1 performs orthogonal modulation of the OFDM symbol subcarrier signals received from the mapping unit 26 to generate the modulated signal and then send it.

Figure 9 shows the H parity check matrix that is used when encoding by the LDPC encoder 21 shown in Figure 8.

The H parity check matrix has a LowDensity Generation Matrix (LDGM) structure and can be expressed by the formula "H = [HA | HT]", where the HA information matrix is ​​the left element and the HT parity matrix is ​​the right element, where the information matrix HA corresponds to information bits from the LDPC code, and HT parity matrix corresponds to parity bits.

Here, the information bits and the parity bits among the bits of the LDPC code (one code word) are defined as the information length K and the parity length M, and the number of code bits is defined as the code length N = (K + M).

The length of information K and the parity length M of the LDPC code with the code length N result from the significance of the codes. Thus, the H parity check matrix is ​​the M x N matrix. In addition, the HA information matrix is ​​the M x K matrix, and the HT parity matrix is ​​the M x M matrix.

Figure 10 shows the parity matrix HT of the H parity check matrix LDPC defined in the DVB-S.2 specification.

The HT parity matrix H of the LDPC parity matrix H defined in the DVB-S.2 specification has a step structure such that the "1" elements of the HT parity matrix are arranged in a stepwise manner as shown in Figure 10. The first row of the H parity check matrix has a weighted value 1 and the remaining rows value 2. The last column of the H parity check matrix has a weighted value of 1 and the remaining columns a value of 2.

The LDPC parity matrix H code having the HT parity matrix with a step structure can easily be generated using the H parity matrix.

In more detail, let the order c vector represent the LDPC code (code word) and CT represent the column vector obtained by transposing the order vector. In addition, let the vector A represent the information bit of the part of the order c, which is the LDPC code, and let the vector of the order T represent the parity bit.

In this case, the vector of the order c can be expressed by the equation "c = [A | T]", where the vector of the order A is the left element and the vector of the order T the right element, where the vector of the order A corresponds to the information bits and the vector of the order T corresponds to the parity bits .

The H parity check matrix and a vector of c = [A | T], which corresponds to the LDPC code, requires the equation "HCT = 0" to be met. Thus, the value of each element of the order of the T row corresponding to the parity bits in the vector of the order c = [A | T] can be successively obtained by aligning the element of each order of the HCT column vector in the equation HCT = 0 to the value zero, in order starting from the first order when the HT parity matrix in the H = [HA | HT] parity matrix has a crotch structure as shown in Figure 10.

Figures 12A and 12B show the LDPC code H parity check matrix and weighted columns defined in the DVB-S.2 specification;

That is, Figure 11A shows the H parity check matrix LDPC of the DVB-S.2 specification.

First, the KX columns of the H parity check matrix have the value X, the next K3 columns have the value 3, the next M-1 value is 2, and the value in the last column is 1. Here, the sum of the number of columns "KX + K3 + M-1 + 1 "Equals the length of the N code.

In the DVB-2S.2 specification, the column numbers KX, K3 and M (parity length 15) and the X columns are given as shown in Figure 111B.

That is, Figure 111B shows the column numbers KX, K3 and M as well as the X value for each LDPC significance code defined in the DVB-S.2 specification.

Two LDPC codes from respective lengths N of 64800 bits and 16200 bits are defined in the DVB-S.2 specification.

In addition, 11 nominal eleven significance codes 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 were defined for the LDPC code 9/10, whose length N is 64,800 bits and 10 nominal significance codes 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9, whose length N is 16,200 bits, as shown in Figure 111B.

For LDPC codes, it is known that the code bit error rate decreases as the column value corresponding to the code bit in the H parity check matrix increases.

In the case of the H parity check matrix, as defined in the DVB-S.2 specification shown in Figures 12A and 12B, the value of the column increases as the number of the ordinal number of the column decreases (i.e. when the column is closer to the left side of the H parity check matrix), and therefore the code bit The LDPC corresponding to the parity H matrix is ​​more robust when the code bit number decreases (i.e. the first code bit is

- 20 most robust) and is more prone to errors when the code bit number increases (i.e. the last bit of code is the most vulnerable).

Figures 12A and 12B show the arrangement (signal points) of 16 symbols in the IQ plane in the case where 16QAM is implemented on an orthogonal modulator 27, Figure 8.

That is, Figure 13A shows the 16QAM symbols.

In 16 QAM one symbol represents 4 bits and 16 (= 24) symbols are given. In addition, 16 symbols are arranged in a 4 x 4 square in the I and Q directions, centered at the beginning of the IQ plane.

Here, when y0, y1, y2 and y3 represent 4 bits represented by one 16QAM symbol, sequentially starting from the most significant bit (MSB), the mapping unit 26 of Figure 8 maps 4 bits of LDPC code to the symbol 4 bits y0 to y3 corresponding to 4 bits of code when the modulation scheme is 16QAM.

Figure 13B shows the limits of the four bits y0 to y3 represented by the symbol 16QAM.

Here, the bit boundary bit yi (i = 0, 1, 2, 3, in Figures 12A and 12B) is the boundary between the bit symbols with the value "0" and the bit symbols with the value "1".

As shown in Figure 13B, the limit corresponding to the Q axis on the IQ plane is the only bit limit for the first bit (i.e. MSB) y0 of the four bits y0 to y3 represented by the 16 QAM symbol, and the limit corresponding to the I axis on the IQ plane is the only bit limit for the second bit (i.e. the second MSB), y1.

In addition, two boundaries, one between the first and second column of symbols (counting from the left) of the 4 x 4 symbols and the other between the third and fourth columns, are the limits of the third bit y2.

Further two boundaries, one between the first and second row of symbols (counting from above) among the 4 x 4 symbols and the second between the third and fourth row, are the limits of the fourth bit y3.

Each bit represented by a symbol is fault tolerant as the number of symbols distant from the bit boundary increases and is more prone to errors when the number of symbols near the bit boundary decreases.

When the error-resistant bit is called "strong bit" and the error-sensitive bit is called "weak bit", then the first bit (i.e. MSB) y0 and the second bit y1 are strong bits, and the third bit y2 and the fourth bit y3 are weak bits as shown in Figures 12A and 12B.

Figures 13 to 15 show the arrangement (signal points) of 64 symbols in the IQ plane in the case where 64QAM is implemented on an orthogonal modulator 27, Figure 8.

In 64 QAM one symbol represents 4 bits and 16 (= 26) symbols are given. In addition, 64 symbols are arranged in the form of a 8 x 8 square in the I and Q directions, centered

- 21 at the beginning of the IQ plane.

Here, when y0, y1, y2, y3, y4 and y5 represent 6 bits represented by one 64QAM symbol, sequentially starting with the most significant bit (MSB), the mapping unit 26 Figure 8 maps 6 bits of LDPC code to symbol 6 bits y0 to y5 corresponding to 6 code bits when the modulation scheme is 64QAM.

Figure 13 shows the border of the first and second bits y0 and y1 of bits y0 to y5 represented by the symbol 64 QAM, and Figure 14 shows the border of the third and fourth bits y2 and y3, while Figure 15 shows the border of the fifth and sixth bits y4 and y5.

One bit bound is present for each of the first and second bits y0 and y1 as shown in Figure 14. Two bit boundaries u are present for each third and fourth bit y2 and y3 as shown in Figure 14, and four bit boundaries are present for each fifth and sixth bit y4 and y5 as shown in Figure 15.

Accordingly, the first and second bits y0 and y1 of the 6 bits y0 to y5 represented by the 64QAM symbol are the strongest bits, and the third and fourth bits y2 and y3 are the second strongest bits, and the fifth and sixth bits y4 and y5 are the weak bits.

In Figures 12, 13 and 15 it can be seen that in the case of bits with orthogonally modulated symbols, the bits of greater importance are strong bits, and of lesser importance to weak bits.

The LDPC code output from the LDPC encoder 21 in Figure 8 includes error-prone code bits and error-resistant code bits as described above with reference to Figure 111.

Bits with orthogonal modulated symbols on orthogonal modulator 27 have strong bits and weak bits as described above with reference to Figures 12 to 15.

Accordingly, when the code bits susceptible to errors in the LDPC code are mapped to weak bits in orthogonally modulated symbols, the overall error resistance decreases.

Therefore, the invention suggests that the interleaving unit that interleaves the bits of the LDPC codes mapped the code bits of the error-prone LDPC codes to the strong bits of orthogonally modulated symbols.

The demultiplexer 25 in Figure 8 performs interleaving operation.

Figures 16A to 16D show the operation of the demultiplexer shown in Figure 8.

In particular, Figure 16A shows an example of the functional configuration of the demultiplexer 25.

The demultiplexer 25 has a memory 31 and a reorganization unit 32. The LDPC code is entered into memory 31. Memory 31 has a storage capacity of mb bits in a row (horizontal) and N / mb bits in a column (vertically). The LDPC code bits stored in memory 31 are stored in memory column 31 and read in the row direction from memory 31, and the read code bits are then sent to the reorganization unit 32.

- 22 Here, "M" denotes the number of bits of the LDPC code mapped to one symbol, and the symbol "b" denotes a specific integer (ie factor) by which "m" is multiplied to obtain the integer multiple of "m". As described above, "N" (= length of information K + parity length M) represents the length of the LDPC code.

Figure 16A shows an exemplary configuration of demultiplexer 25 in the case of a 64QAM modulation scheme. Accordingly, the number of "b" code bits in the LDPC code is mapped to one symbol 6.

In Figure 16A, the "b" factor is 1, therefore memory 31 has a capacity of N / (6x1) x (6x1) bits in columns and rows.

Then the memory area 31, which is one bit in the direction of the row and extends towards the column, is called the column. In the example shown in Figure 16A, the memory 31 has 6 (6x1) columns.

The demultiplexer 25 writes LDPC code bits to memory in the column direction from top to bottom of each column, sequentially starting from the column on the left to the right.

When the code bits have been completely written to the bottom of the rightmost column, the code bits are read from memory 31 in the row direction, successively starting from the first row of all columns in memory 31 in units of 6 bits (i.e. mb bits), and read code bits are sent to the reorganization unit 32.

The reorganization unit 32 changes the order of 6 bits of code received from memory 31 and transmits 6 reorganized bits as 6 bits y0, y1, y2, y3, y4 and y5 denoting the 64QAM symbol.

More specifically, when the 6 bits of code read from junctions 31 in the row direction are designated b0, b1, b2, b3, b4 and b5 sequentially starting from MSB, the code bits including and near the bit "b0" are error-resistant bits and the code bits including and adjacent to "b5" are error prone bits according to the relationship of column values ​​described with reference to Figure 111.

The reorganization unit 32 changes the order of the position 6 bits of code b0 to b5 in memory 31 so that the error-prone codes out of 6 bits of code b0 to b5 in memory are allocated to strong bits out of 6 bits y0 to y5 denoting the 64QAM symbol.

Different companies have suggested different ways to reorganize the 6 bits of code b0 to b5 in memory while allocating them to bits y0 to y5, denoting the symbol 64QAM.

Figure 16B shows the first reorganization method, Figure 16c shows the second reorganization method and Figure 16d shows the third method.

In Figures 16B to 16D, the line connecting the bi and yj bits means that the bit b is allocated to the symbol bit yj (i.e. the position of the code bit bi changes to the symbol bit yj) as in Figures 17A and 17B described above.

While the first reorganization method shown in Figure 16B suggests using

- 23 types of reorganization, the second method shown in Figure 16c suggests the use of two types of reorganization.

The third reorganization method shown in Figure 16D suggests another selection and use of 6 reorganization methods.

Figures 17A and 17B show an exemplary configuration of demultiplexer 25 and a fourth method of reorganization, in the case where the modulation method is 64QAM (so the number of code bits "m" in the LDPC code mapped to one symbol is 6 in Figure 16) and the factor "b" equals up 2.

When the "b" factor is 2, memory 31 has a capacity of N / (6x2) x (6x2) bits in columns and rows and has 12 = (6 x 2) columns.

Figure 17A shows the order in which the bits of the LDPC code are stored in memory 31.

The demultiplexer 25 writes LDPC code bits into memory towards the column from top to bottom of each column, sequentially starting from the leftmost column to the right side, as described above with reference to Figure 16A.

When the code bits have been completely written to the bottom of the rightmost column, the code bits are read from memory 31 in the direction of the row, starting sequentially from the first row of all columns in memory 31 in units of 12 bits (i.e. mb bits), and read code bits are sent to the reorganization unit 32.

The reorganization unit 32 changes the positions of 12 bits of code received from memory 31 according to the fourth reorganization method and generates 12 reorganized bits in the form of 12 bits representing two symbols (i.e. b symbols) of the 64QAM system, i.e. 6 bits y0, y1, y2, y3, y4 and y5 denoting the symbol 62QAM and 6 bits y0, y1, y2, y3, y4 and y5 denoting another symbol.

Figure 17B illustrates the fourth reorganization method implemented by the reorganization unit 32 shown in Figure 17a.

The optimal reorganization that minimizes the error rate in AWGN communication paths depends on the importance of the LDPC code and the like.

The manner in which the parity interleaving unit 23 shown in Figure 8 performs the parity interleaving will be described with reference to Figures 18 to 20.

Figure 18 is a Tanner plot (portion) of an LDPC code parity check matrix.

If an error, such as an erasure, appears simultaneously on two or more nodes connected (two or more bits of code) to the control node, the control node returns a "0" probability message that corresponds to a "1" probability to each variable node connected from the control node as shown in Figure 18. Therefore, decoding efficiency decreases when multiple variable nodes connected to the same control node are removed.

The LDPC code, defined in the DVB-S.2 specification, which is generated by the LDPC encoder 21 shown in Figure 8, is the IRA code and the HT parity matrix of the control matrix

- 24 parity H has a crotch structure as shown in Figure 11.

Figures 19A and 19B show an HT parity matrix having a crotch structure and a Tanner chart corresponding to an HT parity matrix.

This is significant, Figure 19A shows the HT parity matrix with crotch structure, and Figure 19B shows the Tanner chart, according to the HT parity matrix in Figure 19A.

When the HT parity matrix has a step structure, variable nodes whose messages are obtained using adjacent code bits (parity bits) in the LDPC code, corresponding to columns, including elements having the value "1" in the HT parity matrix, are connected to the same node control on the Tanner chart of the HT parity matrix.

Accordingly, if an error occurs, such as a serial error or an erase error, in adjacent parity bits, decoding efficiency drops because the control node connected to the variable nodes according to the wrong parity bits (i.e. variable nodes whose messages are obtained using parity bits) returns a message with a probability of "0" equal to the probability of "1", for each variable node connected to the control node. Decoding efficiency also decreases when the length of the series, which is the number of erroneous bits due to the series, is large.

Then, the parity interleaver 23 in Figure 8 performs the parity interleaving on the LDPC code from the LDPC encoder 21 to translate the parity bits of the LDPC code to different positions of the parity bits to prevent a decrease in decoding efficiency.

Figure 20 shows the parity matrix HT of the parity H matrix corresponding to the LDPC code after performing the parity interleaving on the PDPC code through the interleaving unit 23 shown in Figure 8.

Here, the HA information matrix in the H parity check matrix corresponding to the LDPC code defined in the DVB-S.2 specification generated by the LDPC encoder 21 has a cyclic structure.

The term "cyclic structure" refers to a structure in which a column, after a cyclic shift, corresponds to another column. Examples of a cyclic structure include a structure in which the position of the "1" element of each row of each column P corresponds to the position of the first column P that has been cyclically shifted towards the column by a value proportional to the value "q" obtained by dividing the parity length "M". Below, the number of "P" columns in a cyclic structure refers to the unit number of columns having the cyclic structure.

Examples of the LDPC code defined in the DVB-S.2 specification generated by the LDPC encoder 21 include two types of LDPC codes from 64800 and 16200 bits as described in Figure 12.

The following description will now focus on the type of LDPC codes having a length N of 64800 from two types of LDPC codes with lengths N 64800 and 16200 bits. For the LDPC code, whose length N is 64800 bits, 11 is defined

- 25 nominal significance codes as described above for Figure 12.

For any LDPC code having a length of N 64800 bits each of the 11 nominal significance codes, the unit number of columns P having a cyclic structure is "360", which is one of the dividers (except for 1 and M) of the parity length M in the DVB-S.2 specification .

For an LDPC code having a length N 64800 bits each of the 11 nominal bits of significance, the parity length M is calculated as a number different from the first, according to the equation M = qxP = qx360, where "q" changes depending on the significance of the code. Accordingly, as with the unit number of columns P having a cyclic structure, the value "q" is another divisor (except for 1 and M) of the parity length M and is calculated by dividing the parity length M by the number of units of the columns P having a cyclic structure (i.e. parity length M is the product of the dividers "P" and "q" parity length M).

When K is the information length, x is an integer equal to or greater than 0 and less than P, and y is an integer equal to or greater than 0 and less than q, the parity interleaving unit 23 interleaves on the LDPC code obtained from the LDPC encoder 21 to translate the code bit K + qx + y + I from the parity bit in which the code bits K + I to K + M (= N) -th in the LDPC code, to the position of the code bit K + Py + x + l -you.

According to this method of parity interleaving (parity bits), the variable nodes connected to this control node are located at a distance corresponding to the number of units of columns P having a cyclic structure (in this example 360 ​​bits), thus preventing errors in many variable nodes connected to the same node control. This allows you to increase fault tolerance.

The LDPC code that has been subjected to the even interleaving action such that the K + qx + y + I code bit is interleaved with the bit position of the K + Py + x + I code is identical to the LDPC code of the parity check matrix (hereinafter called the converted parity check matrix) obtained by permutating the columns on the original H parity check matrix to replace the K + Py + x + I column of the original H parity check column with the K + qx + y + I column.

The parity matrix of the converted parity check matrix has a pseudo-cyclic structure whose column number is "P" ("360" in Figure 20) as shown in Figure 20.

Here, the term "pseudo cyclic structure" refers to a structure in which part of the parity matrix, with the exception of a specific part of the parity matrix, has a cyclic structure. The converted parity check matrix obtained by performing the permutation of the parity interleaving column in the case of the LDPC parity check matrix defined in the DVB-S2.2 specification, has a right corner in the form of 360 x 360 (corresponding to the shifted matrix, which is described below), in which is only one element "1" less than in the cyclic structure (i.e. the position of the right corner 360 x 360 has the element "0" instead of "1", which is required in the case

- 26 cyclic structure). Because the converted parity check matrix has no (complete) cyclic structure, it is called a "pseudo cyclic structure".

In fact, the converted parity check matrix shown in Figure 20 is obtained by performing row permutation, including column permutation corresponding to parity interleaving, in the original parity check matrix H, so that the converted parity check matrix includes the elemental matrices described below.

The manner in which the twist interleaving unit 24 shown in Figure 8 performs interleaving of columns as a permutation process, will be described with reference to Figures 21 to 24.

The transmitter 11 shown in Figure 8 transmits two or more bits of LDPC code as one symbol as described above to improve frequency efficiency. For example, QPSK is used as the modulation method when two code bits are transmitted as one symbol and 16QAM is used as the modulation method when four code bits are transmitted as one symbol.

If an error, such as erasure, appears in the symbol, when two or more bits are transmitted as a symbol, as described above, all code bits of that symbol become erroneous (i.e., erased).

Accordingly, to improve decoding efficiency, in order to limit the likelihood (code bits) of simultaneously erasing variable nodes connected to the same control node, it is necessary to prevent the connection of variable nodes corresponding to the code bits of one symbol to the same control node.

On the other hand, in the case of the H parity check matrix of the LDPC code defined in the DVB-S.2 specification, derived from the LDPC encoder 21, the HA information matrix in the H parity check matrix has a cyclic structure, and the HT parity matrix has a step structure as above description. In the case of the converted parity check matrix, which is the parity check matrix of the LDPC code that has been interleaved parity, the parity matrix has a cyclic structure (in particular a pseudo-cyclic structure) as described above with reference to Figure 20.

Figures 21A and 21B show a converted parity check matrix.

In particular, Figure 21A shows the converted parity check matrix H of the parity check matrix H of the LDPC code having a length of N 64800 bits and code significance (r) ¾.

In Figure 21A, the position of each element having the value "1" in the converted parity check matrix is ​​shown as the dot "·".

Figure 21B illustrates the activity of the multiplexer 25 shown in Figure 25 on the LDPC code of the converted parity check matrix shown in Figure 21a, i.e. the LDPC code that has been parsed interleaved.

In Figure 21B, using 16QAM as the modulation method, the code bits of the evenly interleaved LDPC code are written towards the column in four columns, which constitute memory 31 of the demultiplexer 25.

The code bits, written in the direction of the columns in the four columns of memory 31, are read in the direction of the row in units of 4 bits as one symbol.

In this case, the four code bits B0, B1, B2 and B3 of one symbol may include multiple code bits corresponding to "1" in any row in the converted parity check matrix shown in Figure 21A. In this case, the variation nodes corresponding to the four bits of the code B0, B1, B2 and B3 are connected to the same control node.

Accordingly, if a symbol wiping occurs when the four code bits B0, B1, B2 and B3 of the symbol include code bits corresponding to "1" on any row of the converted parity check matrix, it is difficult to get the appropriate message for the same control node connected to a variable node corresponding to the code bits B0, B1, B2 and B3 respectively, which leads to a decrease in decoding efficiency.

When a significance code other than% is used, many code bits corresponding to different variable nodes connected to the same control node may be a symbol

16QAM.

Thus, the interleaving unit 24 performs the twisted passage of columns on the evenly interleaved LDPC codes originating from the 24 parity interleaving unit to translate the code bits of the evenly interleaved LDPC code so that many of the code bits corresponding to "1" in any row of the converted parity check matrix are not mapped to form one symbol.

Figure 22 shows the manner in which twisted interlacing is performed.

In particular, Figure 22 shows the memory 31 of the demultiplexer 25 shown in Figures 16 and 17.

Memory 31 has a storage capacity of mb bits in a row (horizontal) and N / mb bits in a column (vertically) and includes mb columns as described in reference to Figure 16. Twist interleaving unit 24 interleaves the columns by controlling the start position of the entries in each memory column 31, in which the recording of the column begins, when the bits of LDPC codes are written to memory in the direction of the column and read from memory 31 in the direction of the row.

More specifically, the twist interleaving unit 24 appropriately changes the start recording locations where the code bits begin to be written in each of the many columns so that many code bits read in the direction of the order constituting one symbol do not include multiple code bits corresponding to "1" in any row of converted parity check matrix. This means that the twist interleaving unit 24 permutes the bits of the LDPC code in such a way that many code bits

- 28 corresponding to "1" in any row of the parity check matrix are not included in the same symbol.

Figure 22 shows an exemplary memory configuration 31 when the 16QAM system is used as the modulation method and the "b" factor described in Figure 16 is "1". Accordingly, the number of code bits "m" in the LDPC code mapped to one symbol is 4, and the memory 31 includes 4 (= mb) columns.

The torsion interleaving unit 24 shown in Figure 22 (instead of the demultiplexer 25 shown in Figure 16) writes the LDPC code bits to the memory towards the column from top to bottom of each of the four columns belonging to memory 31, starting from the column to the left to the right side.

When the code bits are written in the entire rightmost column, the twist interleaving unit 24 reads the code bits in units of 4 bits (mb bits) in the row direction from the first row of all columns in memory 31 and transmits the read code bits in interlaced form a twisted column of LDPC code to the reorganization unit 32 of the demultiplexer 25 shown in Figures 16 and 17.

When the address of the first (top) position of each column is represented by "0" and the address of each position along the direction of the column is represented by a successively increasing integer, the twisting interleaving unit 24 shown in Figure 22 indicates that the start position of the write in the most column extended to the left is "0", the address of the starting position of the entry in the second column (from the left) is (2), the address of the starting position of the entry in the third column is "4", and the entry position of the entry in the fifth column is "7".

After writing the code bits to the column having the starting position, entries at an address other than "0" up to the bottom of the column, the twist interleaving unit 24 returns to the first position of the column at the address "0" and continues writing the code bits to the position immediately before the starting position recording. Then, twist interleaving unit 24 writes to the next right column.

The implementation of the torsional interleaving of columns, as described above, prevents the assignment of several code bits corresponding to several variable nodes connected to the same control node to the 16QAM symbol (i.e. before being included in the same symbol), in the case of the LDPC code of each significance code with the length N 64800, as specified in the DVB-S.2 specification. This improves the decoding efficiency on the communication path where the erasure occurs.

Figure 23 shows several memory columns 31 needed to perform column interleaving and write start position addresses in connection with each LDPC modulation method of each of the 11 significance codes N 64800 length as defined in the DVB-S.2 specification.

The number of "m" bits of one symbol is 2 and the "b" factor is 1 when one of three methods is used during the reorganization of the demultiplexer 25 in Figure 8

- 29 reorganization, shown in Figure 16, and QPSK is used as a modulation method.

In this case, memory 31 has 2 columns of 2x1 (= mb) bit writing in the direction of the row and writes 64800 / (2x1) bits in the direction of the column, as shown in Figure 23. The starting position of writing the first of the two columns of memory 31 is at the address " 0 "and the starting position of column 2 is next to the address" 2 ".

In addition, the number of "m" bits of one symbol is 2 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and QPSK is used as a modulation method.

In this case, memory 31 has 4 columns of 2x2 bits in the row direction and writes 64,800 / (2x2) bits in the column direction, as shown in Figure 23. The starting position of the first of four columns of memory 31 is located at address "0", position the initial entry of the second column is located at the address "2", the starting position of the third column is located at the address "4", and the initial position of the fourth column is located at the address "7".

In addition, the number of "m" bits of one symbol is 4 and the factor "b" is 1 when one of the three reorganization methods shown in Figure 16 is used during the reorganization of the demultiplexer 25 in Figure 8, and 16QAM is used as the modulation method.

In this case, memory 31 has 4 columns of 4x1 bit writing in the direction of the row and writes 64800 / (4x1) bits in the column direction, as shown in Figure 23. The starting position of writing the first of four columns of memory 31 is at address "0", and the starting position of the second column is at address "2", the starting position of the third column is at "4", and the starting position of the fourth column is at "7".

In addition, the number of "m" bits of one symbol is 4 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 16QAM is used as a modulation method.

In this case, the memory 31 has 8 columns of recording 4x2 bits in the direction of the row and writes 64,800 / (4x2) bits in the direction of the column, as shown in Figure 23. The starting position of the first of eight columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "2", the starting position of the fourth column is located at address "4", the starting position of the fifth column is located at the address "4", the starting position of the sixth column is at the address "5", the starting position of the seventh column is next to the address "7", and the starting position of the eighth column is the next to "7".

In addition, the number of "m" bits of one symbol is 6 and the "b" factor is 1 when one of the three reorganization methods used in Figure 16 is used during the reorganization of the demultiplexer 25 in Figure 8, and 64QAM is used as the modulation method.

In this case, memory 31 has 6 columns of 6x1 bit writing in the row direction and writes

- 30 64800 / (6x1) bits towards the column as shown in Figure 23. The starting position of saving the first of six columns of memory 31 is at address "0", the starting position of saving the second column is at address "2", the starting position of saving the third column is at address "5", the starting position of saving the fourth column is at address "9", the starting position of the fifth column is located at the address "10", and the starting position of the sixth column is at the address "13".

In addition, the number of "m" bits of one symbol is 6 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 64QAM is used as a modulation method.

In this case, memory 31 has 12 columns writing 6x2 bits in the direction of the row and writes 64800 / (6x2) bits in the direction of the column, as shown in Figure 23. The starting position of the first of the twelve columns of memory 31 is at the address "0", the starting position of the second column is at the address "0", the starting position of the third column is at the address "2", the starting position of the fourth column is at address "2", the starting position of the fifth column is next to the address "3", the starting position of the sixth column is next to the "4" address, the starting position of the seventh column is at the "4" address, the starting position of the eighth column is at the "5" address, the starting position of the ninth column is at the "5" address, the starting position of the tenth column is at the "7" ", The starting position of the eleventh column is at" 8 ", and the starting position of the twelfth column is at" 9 ".

In addition, the number of "m" bits of one symbol is 8 and the factor "b" is 1 when one of the three reorganization methods shown in Figure 16 is used during the reorganization of the demultiplexer 25 in Figure 8, and 256QAM is used as the modulation method.

In this case, the memory 31 has 8 columns writing 8x1 bits in the direction of the row and writes 64800 / (8x1) bits in the direction of the column, as shown in Figure 23. The starting position of the first of eight columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "2", the starting position of the fourth column is located at address "4", the starting position of the fifth column is located at the address "4", the starting position of the sixth column is at the address "5", the starting position of the seventh column is next to the address "7", and the starting position of the eighth column is the next to "7".

In addition, the number of "m" bits of one symbol is 8 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 256QAM is used as a modulation method.

In this case, memory 31 has 16 columns of 8x2 bits in the row direction and writes 64800 / (8x2) bits in the column direction, as shown in Figure 23. The starting position of the first of the sixteen memory columns 31 is at address "0", starting position

- the 31st entry of the second column is next to the "2" address, the start position of the third column is next to the "2" address, the starting position of the fourth column is next to the "2" address, the starting position of the fifth column is next to "2" ", The starting position of the sixth column is at the address" 3 ", the starting position of the seventh column is at the" 7 ", the starting position of the eighth column is at the" 15 ", the starting position of the ninth column is at the address "16", the starting position of the tenth column is at the address "20", the starting position of the eleventh column is at the address "22", the starting position of the twelfth column is at the address "22" ", The starting position of the thirteenth column entry is at the address" 27 ", the starting position of the fourteenth column is at the address" 27 ", the starting position of the fifteenth column is at the address "28", and the starting position of the sixteenth column is at the address "32"

In addition, the number of "m" bits of one symbol is 10 and the factor "b" is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 1024QAM is used as the modulation method.

In this case, the memory 31 has 10 columns write 10x1 bits in the direction of the row and stores 64800 / (10x1) bits in the direction of the column, as shown in Figure 23. The starting position of the first of ten columns of memory 31 is at the address "0", the starting position of writing the second column is at the address "3", the starting position of writing the third column is at the address "6", the starting position of writing the fourth column is at address "8", the starting position of the fifth column is located at the address "11", the starting position of the sixth column is at the address "13", the starting position of the seventh column is at the address "15", the starting position of the eighth column is at the address "17", the starting position of the ninth column is at the address "18", and the starting position of the tenth column is at the address " twenty".

In addition, the number of "m" bits of one symbol is 10 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 1024QAM is used as a modulation method.

In this case, the memory 31 has 20 columns write 10x2 bits in the direction of the row and stores 64800 / (10x2) bits in the direction of the column, as shown in Figure 23. The starting position of the first of twenty columns of memory 31 is at address "0", the starting position of writing the second column is at address "1", the starting position of writing the third column is at address "3", the starting position of writing the fourth column is at address "4", the starting position of the fifth column is located at the address "5", the starting position of the sixth column is at the address "6", the starting position of the seventh column is at the address "6", the starting position of the eighth column is at the "9", the starting position of the ninth column is at the "13", the starting position of the tenth

- 32 columns are located at address "14", the starting position of the eleventh column is located at address "14", the starting position of the twelfth column is located at address "16", the starting position of the thirteenth column is at address "21", the starting position of the fifteenth column entry is at the address "21", the starting position of the fifteenth column is at the address "23", the starting position of the sixteenth column is at the address "25", the starting position of the seventeenth column is at the address "25", the starting position of the eighteenth column is at the address "26", the starting position of the nineteenth column is at the address "28" "And the starting position of the twentieth column is at" 30 "

In addition, the number of "m" bits of one symbol is 12 and the "b" factor is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 4096QAM is used as the modulation method.

In this case, the memory 31 has 12 columns write 12x1 bits in the direction of the row and stores 64800 / (12x1) bits in the direction of the column, as shown in Figure 23. The starting position of the first of the twelve columns of memory 31 is at the address "0", the starting position of the second column is at the address "0", the starting position of the third column is at the address "2", the starting position of the fourth column is at address "2", the starting position of the fifth column is next to the address "3", the starting position of the sixth column is next to the "4" address, the starting position of the seventh column is at the "4" address, the starting position of the eighth column is at the "5" address, the starting position of the ninth column is at the "5" address, the starting position of the tenth column is at the "7" ", The starting position of the eleventh column is at" 8 ", and the starting position of the twelfth column is at" 9 ".

In addition, the number of "m" bits of one symbol is 12 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 4096QAM is used as a modulation method.

In this case, memory 31 has 24 columns of 12x2 bits writing in the row direction and writes

64800 / (12x2) bits towards the column as shown in Figure 23. The starting position of the first of twenty-four columns of memory 31 is at address "0", the starting position of writing the second column is at address "5", the starting position of writing the third column is at address "8", the starting position of writing the fourth column is at address "8", the starting position of the fifth column is located at the address "8", the starting position of the sixth column is at the address "8", the starting position of the seventh column is at the address "10", the starting position of the eighth column is at the "10", the starting position of the ninth column is at the "10", the starting position of the tenth column is at the "12" ", The entry position for the eleventh column

- 33 is at address "13", the starting position of the entry for the twelfth column is at the address "16", the starting position for entering the thirteenth column is at the address "17", the starting position for entering the fourteenth column is at the address "19", position the starting entry of the fifteenth column is located at the address "21", the starting position of the entry of the sixteenth column is at the address "22", the starting position of the entry of the seventeenth column is at the address "23", the starting position of the eighteenth column entry is at the address "26", the starting position of the nineteenth column is at the address "37", the starting position of the entry of the twentieth column is at the address "39", the starting position of the entry of the twenty-first column is at the address " 40 ", the entry position of the twenty-second column is at address" 41 ", the entry position of the twenty-third column is at address" 41 ", and the starting position of the twenty-fourth column entry is at address "41".

Figure 24 shows several columns of memory 31 necessary to perform column interleaving and write entry addresses for each LDPC modulation method of each of the 10 significance codes N 16200 length as defined in the DVB-S.2 specification.

The number of "m" bits of one symbol is 2 and the factor "b" is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and QPSK is used as the modulation method.

In this case, memory 31 has 2 columns of 2x1 bits in the row direction and writes 16,200 / (2x1) bits in the column direction, as shown in Figure 24. The starting position of the first of the two columns of memory 31 is located at address "0", and the start position of column 2 is located at the address "0".

In addition, the number of "m" bits of one symbol is 2 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and QPSK is used as a modulation method.

In this case, memory 31 has 4 columns of 2x2 bits in the row direction and writes 16,200 / (2x2) bits in the column direction, as shown in Figure 24. The starting position of the first of four columns of memory 31 is located at address "0", position the initial entry of the second column is located at the address "2", the starting position of the third column is located at the address "4", and the initial position of the fourth column is located at the address "3".

In addition, the number of "m" bits of one symbol is 4 and the factor "b" is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 16QAM is used as the modulation method.

In this case, memory 31 has 4 columns writing 4x1 bits in the direction of the row and writes 16,200 / (4x1) bits in the direction of the column, as shown in Figure 24. Initial position

- 34 entry of the first of four columns of memory 31 is located at the address "0", the initial position of the second column is located at the address "2", the initial position of the third column is located at the address "4", and the initial position of the fourth column is found at address "3".

In addition, the number of "m" bits of one symbol is 4 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 16QAM is used as a modulation method.

In this case, memory 31 has 8 columns to write 4x2 bits in the direction of the row and writes 16,200 / (4x2) bits in the direction of the column, as shown in Figure 24. The starting position of the first of eight columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "0", the starting position of the fourth column is located at address "1", the starting position of the fifth column is located at the address "7", the starting position of the sixth column is at the address "20", the starting position of the seventh column is located at the address "20", and the starting position of the eighth column is at the address "21".

In addition, the number of "m" bits of one symbol is 6 and the factor "b" is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 64QAM is used as the modulation method.

In this case, memory 31 has 6 columns of 6x1 bits in the row direction and writes 16,200 / (6x1) bits in the column direction as shown in Figure 24. The starting position of saving the first of six columns of memory 31 is at address "0", the starting position of saving the second column is at address "0", the starting position of saving the third column is at address "2", the starting position of saving the fourth column is at address "3", the starting position of the fifth column is located at the address "7", and the starting position of the sixth column is at the address "7".

In addition, the number of "m" bits of one symbol is 6 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 64QAM is used as a modulation method.

In this case, memory 31 has 12 columns writing 6x2 bits in the direction of the row and writes 16,200 / (6x2) bits in the direction of the column, as shown in Figure 24. The starting position of the first of the twelve columns of memory 31 is at the address "0", the starting position of the second column is at the address "0", the starting position of the third column is at the address "0", the starting position of the fourth column is at address "2", the starting position of the fifth column is next to the address "2", the starting position of the sixth column is next to the "2" address, the starting position of the seventh column is at the address "3", the starting position of the eighth column is at the "3" address, the starting position of the ninth column is at the "3" address, the starting position of the tenth

- the 35th column is at the address "6", the starting position of the eleventh column is at the "7" address, and the starting position of the 12th column is at the "7" address.

In addition, the number of "m" bits of one symbol is 8 and the factor "b" is 1 when one of the three reorganization methods shown in Figure 16 is used during the reorganization of the demultiplexer 25 in Figure 8, and 256QAM is used as the modulation method.

In this case, memory 31 has 8 columns of 8x1 bits in the row direction and writes 16,200 / (8x1) bits in the column direction as shown in Figure 24. The starting position of the first of eight columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "0", the starting position of the fourth column is located at address "1", the starting position of the fifth column is located at the address "7", the starting position of the sixth column is at the address "20", the starting position of the seventh column is located at the address "20", and the starting position of the eighth column is at the address "21".

In addition, the number of "m" bits of one symbol is 10 and the factor "b" is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 1024QAM is used as the modulation method.

In this case, the memory 31 has 10 columns to write 10x1 bits in the direction of the row and stores 16,200 / (10x1) bits in the direction of the column, as shown in Figure 24. The starting position of the first of ten columns of memory 31 is at the address "0", the starting position of writing the second column is at the address "1", the starting position of writing the third column is at the address "2", the starting position of writing the fourth column is at address "2", the starting position of the fifth column is next to the address "3", the starting position of the sixth column is next to the "3" address, the starting position of the seventh column is at the "4" address, the starting position of the eighth column is at the "4" address, the starting position of the ninth column is at the "5" address, and the starting position of the tenth column is at the " 7 ".

In addition, the number of "m" bits of one symbol is 10 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 1024QAM is used as a modulation method.

In this case, the memory 31 has 20 columns of recording 10x2 bits in the direction of the row and writes 16,200 / (10x2) bits in the direction of the column, as shown in Figure 24. The starting position of the first of twenty columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "0", the starting position of the fourth column is located at address "2", the starting position of the fifth column is next to the address "2", the starting position of the sixth column is next to the "2" address,

- the starting position of the seventh column is at the "2" address, the starting position of the eighth column is at the "2" address, the starting position of the ninth column is at the "5" address, the starting position of the tenth column is at the address "5", the starting position of the eleventh column is at address "5", the starting position of the twelfth column is at address "5", the starting position of the thirteenth column entry is at address "5", the starting position of the fourteenth column entry is at address "7", the starting position of the fifteenth column entry is at address "7", the starting position of the sixteenth column is at address "7" ", The starting position of the seventeenth column is at the address" 7 ", the starting position of the eighteenth column is at the address" 8 ", the starting position of the nineteenth column entry is at address "8", and the starting position of the twentieth column is at address "10".

In addition, the number of "m" bits of one symbol is 12 and the "b" factor is 1 when one of the first to third methods of reorganization, shown in Figure 16, is used during the reorganization of the demultiplexer 25 in Figure 8, and 4096QAM is used as the modulation method.

In this case, the memory 31 has 12 columns write 12x1 bits in the direction of the row and writes 16,200 / (12x1) bits in the direction of the column, as shown in Figure 24. The starting position of the first of the twelve columns of memory 31 is at the address "0", the starting position of the second column is at the address "0", the starting position of the third column is at the address "0", the starting position of the fourth column is at address "2", the starting position of the fifth column is next to the address "2", the starting position of the sixth column is next to the "2" address, the starting position of the seventh column is at the "3" address, the starting position of the eighth column is at the "3" address, the starting position of the ninth column is at the "3" address, the starting position of the tenth column is at the "6" address ", The starting position of the eleventh column is at" 7 ", and the starting position of the twelfth column is at" 7 ".

In addition, the number of "m" bits of one symbol is 12 and the factor "b" is 2 when the reorganization of the demultiplexer 25 in Figure 8 uses the fourth reorganization method shown in Figure 17 and 4096QAM is used as a modulation method.

In this case, memory 31 has 24 columns of 12x2 bits writing in the row direction and writes

16200 / (12x2) bits towards the column as shown in Figure 24. The starting position of the first of twenty-four columns of memory 31 is at the address "0", the starting position of the second column is located at the address "0", the starting position of the third column is located at the address "0", the starting position of the fourth column is at the address "0", the starting position of the fifth column is located at the address "0", the starting position of the sixth column is at the address "0", the starting position of the seventh column is next to the address "0", position

- the initial entry of the eighth column is located at the address "1", the starting position of the entry of the ninth column is at the address "1", the starting position of the entry of the tenth column is at the address "1", the starting position of the entry of the eleventh column is at the address " 2 ", the starting position of the entry for the twelfth column is at the" 2 "address, the starting position for the entry for the thirteenth column is at the" 2 "address, the starting position of the fourteenth column entry is at the address "3", the starting position of the fifteenth column is at the address "7", the starting position of the sixteenth column is at the address "9", the starting position of the seventeenth column is at the address "9" ", The starting position of the eighteenth column entry is at address" 9 ", the starting position of the nineteenth column entry is at address" 10 ", the starting position of the twenty-first column entry is at address "10", the starting position of the twenty-first column entry is at the address "10", the starting position of the twenty-second column entry is at the address "10", the starting position of the twenty-third column is at address '10' and the starting position of the twenty-fourth column is next to address '11'.

The transmission procedure implemented by the transmitter 11 in Figure 8 will now be described with reference to the diagram shown in Figure 25.

The LDPC encoder 21 waits for receiving the target data and codes the received target data to the LDPC code and passes this code to the interleaving unit 22 at step S101, and then the procedure goes to step S102.

In step S102, the bit interleaving unit 22 performs bit interleaving on the LDPC code transmitted by the LDPC encoder 21 and sends the LDPC code with the interleaved bits to the mapping unit 26, and then the procedure proceeds to step S103.

More specifically, in step S102, the parity interleaver 23 in the bit interleaver 22 performs parity interleaving on the LDPC code received from the LDPC encoder 21, and then sends the evenly interleaved LDPC code to the stranded column 24 interleaving unit.

The column interleaving unit 24 performs the column interleaving on the LDPC code received from the parity interleaving unit 23, and the demultiplexer 25 performs the reorganization process on the interlaced twisted LDPC code using the column interleaving unit 24. Then the demultiplexer 25 sends the reorganized LDPC code to the mapping unit 26.

In step S103, the mapping unit 26 maps the bits of the LDPC code received from the demultiplexer 25 to the symbol represented by a signal point determined according to the modulation scheme used by the orthogonal modulator 27 to perform orthogonal modulation and sends the mapped symbol to the orthogonal modulator 27, and then the procedure passes to step S104.

At step S104, the orthogonal modulator 27 performs orthogonal modulation of the carriers onto the symbol from the mapping unit 26, and then the procedure goes to step S105 and sends

- 38 orthogonally modulated signal and procedure is coming to an end.

The transmission procedure of Figure 25 is repeated.

Performing parity interleaving or column interleaving interleaving as described above can increase the resistance to erasure and series of errors when multiple bits of LDPC code are transmitted in one symbol.

The parity interleaving unit 23, which is a parity interleaving block and the twist interleaving unit 24, which is a twist interleaving block, can be integrated, although for ease of parity interleaving unit 23 and the column interleaving unit 24 are shown in Figure 8 as separate units.

More specifically, both the parity interleaving unit and the column twist interleaving unit can write and read code bits from memory and can be in the form of a matrix that converts the address (write address) at which the code bit is written to the address (reading address) at which the code bit is read.

Accordingly, it is possible to obtain an LDPC code that has been evenly interleaved and interleaved by twisting the columns by converting the code bits by matrix obtained by multiplying the matrix representing the parity interleaving and the matrix representing the twisted column passage.

The demultiplexer 25 may be integrated and have a parity interleaving unit 23 and a column twisting passage unit 24.

More specifically, the reorganization process carried out by the demultiplexer 25 can also be represented by a matrix that converts the write address of the memory 31 in which the LDPC code is stored to the read address.

Accordingly, it is possible to perform parity interleaving, column interleaving interleaving and the reorganization process jointly using a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing column interleaving and a matrix representing the reorganization process.

It is also possible to perform either parity interleaving only or only column interleaving interleaving.

The simulations for measuring the error rate that were carried out using the transmitter 11 of Figure 8 will now be described with reference to Figures 26 to 28.

The simulations were carried out using a communication path with 0dB tremor

D / U.

Figure 26A and 26B show the communication path model used during the simulation.

In particular, Figure 26A shows the tremor model used during the simulation.

Figure 26B shows a model of tremor communication path, the model of which is shown in Figure 26A.

- "H" in Figure 26B means the tremor model in Figure 26a. "N" means the ICI (Inter-Carrier Interference) interference shown in Figure 26b. During the simulation, the expected value E [N2] of the power of ICI was approximated by AWGN.

Figures 27 and 28 show the relationship between the Doppler frequencies fd of tremors and the error rate in simulations.

More specifically, Figure 27 shows the relationship between error rates and Doppler frequencies fd, when the modulation scheme is 16QAM, the significance of the code (r) is ³Ą and the method of reorganization is the first of those presented. Figure 28 shows the relationship between error rates and Doppler frequencies fd when the modulation scheme is 64QAM, the significance of the code (r) is 5/6, and the reorganization method is the first of these.

In Figures 27 and 28, the bold line shows the relationship between error rates and Doppler frequencies fd, after performing parity interleaving, column torsion interleaving and the reorganization process, and the thin line indicates the relationship between error rates and Doppler frequencies fd, when only the reorganization process was performed.

It can be seen in any of Figures 27 and 28 that error rates are improved (i.e., are lower) when parity interleaving, column interlacing and reorganization are performed, compared to the case in which only the reorganization was carried out.

Receiver

Figure 29 is an example illustration of a receiver that can be used to detect OFDM symbols and recover data bits from OFDM symbol subcarrier signals. As shown in Figure 29, the OFDM signal is received by the antenna 500 and detected by tuner 502, and then converted to digital by an analogue-digital converter 504. The 506 processor removing protective gaps removes them from the received OFDM symbol before data is recovered from it using the Fast Fourier Transform (FFT) 508 processor in combination with the channel estimator and correction 510 in cooperation with the built-in 511 signal decoding unit, according to known way. Demodulated data symbols are recovered on a reverse mapping device 512 and sent to a signal feedback interleaver 514, which is intended to reverse the mapping of received data symbols to regenerate the output symbol stream using reverse interleaved data symbols. The symbol 514 reverse interleaving unit described soon described in more detail. Interleaving unit and LDPC decoder

As shown in Figure 29, the receiver is also equipped with a reverse mapping unit 52, reverse interleaving unit 53 and an LDPC decoder 56. The reverse mapping unit 52 receives symbols (with respective values ​​of the axis direction I o and Q) from the symbol 514 interleaving and its the goal is to reverse the mapping

- 40 symbols to the encoded bits of the LDPC code and sends them to the bit interleaving unit 53. The reverse mapping of the received data symbols is accomplished by identifying the bits that are represented by the data symbol identified on the basis of the OFDM symbol subcarrier signal. The bit interleaving unit 53 is equipped with a demultiplexer 54 and a column twisting feedback interleaver 55 and performs interleaving on the LDPC code bits received from the reverse mapping unit 52.

More specifically, the demultiplexer 54 performs an inverted reorganization process, which is the inverse of the reorganization process carried out by the demultiplexer 25 shown in Figure 8 on the LDPC code obtained from the reverse mapping unit

52. In detail, the demultiplexer 54 performs an inverted reorganization process to recover the reorganized code bit positions to the original positions and sends the inversely reorganized LDPC code to the column twist reverse interleaving unit 55.

The column twisting back interleaving unit 55 performs the column twisting back interleaving process, which is the inverse of the column twisting interleaving in the form of the permutation process performed by the column twisting interleaving unit 24 shown in Figure 8, on the LDPC code obtained from the demultiplexer 54. In particular, the column twisting reverse interleaving unit 55 performs an inverted permutation process (e.g., column twisting reverse interleaving) to recover the original order of the LDPC code bits reorganized by the column twisting interleaving in the form of a code bit permutation process.

More specifically , the column twisting back interleaver 55 performs the column twisting back interleaving by writing and reading the LDPC code bits to and from the interleaving memory, which has a structure similar to that of memory 31 of Figure 22.

However, the reverse interleaving unit of the twisting columns 55 writes the code bit to the row interleaving memory by using the read address at which the code bit was read from memory 31 as the write address. In addition, the stranding reverse interleaver unit 55 reads the code bit from the column interleaving memory using the write address at which the code bit was stored in memory 31 as the read address.

The column twisting back interleaving unit 55 sends the de-interleaved LDPC code of the twisted column to the LDPC decoder 56.

Despite the fact that the parity interlacing, column twist interlacing and reorganization process were sequentially performed on the LDPC code provided from the reverse mapping unit 52 to the reverse interleaving unit 53, the reverse interleaving unit 53 only performs two processes, i.e. the reverse reorganization process corresponding to the reorganization process and interleaving reverse torsion column corresponds to the interleaving torsion of the column on the LDPC code. So the interleaving unit

- 41 reverse 53 does not perform parity reverse interleaving corresponding to parity interleaving (i.e., inverse parity interleaving). That is, reverse interleaver 53 does not perform back interleaving to recover the original order of the LDPC code bits reorganized by parity interleaving.

Accordingly, the LDPC code, in which the reverse reorganization and back-interleaving process of the stranding columns was performed and in the absence of parity back-interleaving, is transmitted from (column backscrewing unit 55) of the back interleaving unit 53 to decoder 56.

The LDPC decoder 56 decodes the LDPC code received from the back interleaving unit 53 by means of a converted parity check matrix obtained by at least permutating the column corresponding to the parity interleaving on the H parity check matrix, which the LDPC encoder 21 shown in Figure 8 used for LDPC coding, and then generates the resulting data in the form of decoded target data.

Figure 30 is a diagram illustrating the receiving procedure implemented on the receiver 12 shown in Figure 29.

The orthogonal modulator 51 receives the modulated signal from the transmitter 11 in step S111. The procedure then proceeds to step S112 to perform orthogonal demodulation on the modulated signal. The orthogonal demodulator 51 sends the symbol obtained by orthogonal demodulation to the feedback mapping unit 52 and the procedure proceeds from step S112 to S113.

At step S113, reverse mapping unit 52 performs reverse mapping of the symbol received from the orthogonal demodulator 51 to the LDPC code bits and forwards it to reverse interleaving unit 53. The procedure then proceeds to step S114.

At step S114, the reverse interleaver 53 performs interleaving on the LDPC code bits received from the reverse mapping unit 52 and the procedure proceeds to step S115.

More specifically, at step S114, the demultiplexer 54 in the reverse interleaver 53 performs reverse reorganization on the LDPC code received with the reverse mapping unit 52, and then sends the LDPC code to the reverse interleaving unit of the column 55.

The column twisting back interleaver 55 performs the column twisting back interleaving on the LDPC code sent from the demultiplexer 54 and sends the resulting LDPC code to the LDPC decoder 56.

At step S115, the LDPC decoder 56 performs decoding of the LDPC code received from the twisting column 55 reverse interleaving unit using a converted parity check matrix obtained at least by permutation of the column corresponding to the parity interleaving on the parity check matrix H, which the LDPC encoder 21 shown in Figure 8 used in LDPC encoding order, then

- 42 generates output data in the form of decoded target data. The procedure is coming to an end.

The reception procedure described in Figure 30 is repeated.

A demultiplexer 54 that performs a reverse reorganization process and a column twisting reverse interleaving unit 55 that performs column twisting reverse interleaving can be integrated into the demultiplexer 54, although the column twisting back interleaving unit 55 is shown in Figure 29 in the same way as in Figure 8 , for the purpose of greater transparency.

In the case where the transmitter 11 shown in Figure 8 does not perform column twisting back interleaving, there is no need to mount the column twisting back interleaving unit 55 at the receiver 12 shown in Figure 29.

It will now be described how the LDPC decoder 56 shown in Figure 29 performs the LDPC decoding process.

The LDPC decoder 56 shown in Figure 29 performs decoding of the LDPC code received from the column twisting reverse interleaving unit 55 on which the reorganization process and column twisting reverse interleaving in the absence of parity reverse interleaving, using a converted parity check matrix obtained by performing at least column permutation interleaved parity on the H parity check matrix, which the LDPC encoder 21 shown in Figure 8 used in the LDPC encoding.

Here, LDPC decoding, which is carried out using a converted parity matrix to reduce the size of the system and limit the operating frequency in a range that can be completely reachable, has already been suggested (for example Japanese Patent Application Publication No. 2004-343170).

First, LDPC decoding using the previously suggested converted parity check matrix will be described with reference to Figures 31 to 34.

Figure 31 shows an exemplary H parity check matrix LDPC code with 90 code length and 2/3 code significance.

In Figure 31, "0" is represented by a "", as in Figures 32 and 33 below.

The parity matrix in the parity H matrix shown in Figure 31 has a crotch structure.

Figure 32 shows the parity check matrix H 'obtained by performing the permutation of the Mathematical Expression order (8) and permutation of the Mathematical Expression column (9) on the parity check matrix H shown in Figure 31.

Permutation of the order: 6s + t + 1st row -&gt; 5t + s + 1st row ... (8)

Column permutation: 6x + y + 6th column 5y + x + 6th column ... (9)

- 43 Mathematical expressions (8) and (9), s, t, x and y are integers of which 0 &lt;s &lt;5, 0 &lt;t &lt;6, 0 &lt;x &lt;5 and 0 &lt;y &lt;6.

According to the permutation of the order of the mathematical expression (8), rows 1, 7, 13, 19 and 25, whose ordinal numbers are "1" as the remainder after dividing by 6, will be changed (and especially replaced) to 1, 2, 3, respectively, 4th and 5th rows, and 2nd, 8, 14, 20 and 24th rows, whose ordinal numbers are "2" as the remainder after dividing by 6, will be changed to rows 6, 7, 8, 9 and 10, respectively.

According to the permutation of the columns of mathematical expression (9), columns 61, 67, 73, 79 and 80 of the columns (parity) after column 60, whose order number is "1" as the remainder after dividing by 6, will be replaced by columns 61 , 62, 63, 64 and 65, and columns 62, 68, 74, 80 and 86, whose ordinal number is "2" as the remainder after dividing by 6, will be replaced by columns 66, 67, 68, 69 and 70, respectively.

The matrix obtained by permutation of the row and column on the H parity check matrix shown in Figure 31, is the H 'parity check matrix shown in Figure 32.

Here, performing permutation of the order for the H parity check matrix does not affect the bit order of the LDPC code.

The permutation of the column of the mathematical expression (9) corresponds to the parity interleaving, which is performed in order to interleave K + qx + y + 1st code bit on K + Py + x + 1st code bit, as described above, when the length of information K is "60", the unit number of columns P having a cyclic structure is "5", and the divider q (M / P) of the parity length M (in this example 30) is "6".

The zero vector is the result when the parity check matrix H 'shown in Figure 32, which will hereinafter be referred to as the "converted parity check matrix", is multiplied by the LDPC code obtained by carrying out the same permutation as the Mathematical Expression (9) on the LDPC code the parity check matrix H shown in Figure 31, which will hereinafter be referred to as the "original parity check matrix". More specifically, when "c" is the order vector obtained by permutating the Mathematical Expression column (9) on the "c" order vector as the LDPC code (code word) of the original H parity check matrix, HCT is a zero vector due to the nature of the parity check matrix and therefore H'C'T is also a zero vector.

Thus, the converted H 'parity check matrix shown in Figure 32 is the LDPC c' parity check matrix obtained by permutation of the Mathematical Expression column (9) on the LDPC c code of the original H parity check matrix.

Accordingly, the same LDPC code of the original H parity matrix that was obtained by decoding with the H parity check matrix can be obtained by decoding the LDPC code c 'of a permutated column, which was generated by permutation of a Mathematical Expression (9) on the LDPC code c

- the original H parity check matrix, using the converted H 'parity check matrix shown in Figure 32, followed by inverted permutation of the Mathematical Expression column (9) on the decoded LDPC c' code.

Figure 33 shows the converted H 'parity check matrix shown in

Figure 32, in which the elements are illustrated in the arrangement of 5 x 5 spaced matrices.

In Figure 33, the converted H 'parity matrix shown in the form of combined 5 x 5 unit matrices, each of which is generated by replacing one or more "1s" units of the 5 x 5 unit matrix with a "0s" unit (hereinafter referred to as "acid- matrices "), matrices generated by cyclic displacement of unit matrices or acid-unit matrices (hereinafter referred to as" shifted matrices "), matrices, each of which is the sum of two or more unit matrices, acid-unit matrices and shifted matrices (hereinafter referred to as the "sum of matrices") and zero 5 x 5 matrices.

This means that the converted H 'parity matrix shown in Figure 33 can be a matrix having 5 × 5 unit matrices, acid-unit matrices, shifted matrices, matrix sums and 5 × 5 zero matrices. Thus 5 × 5 matrices which are converted the H 'parity check matrix will be referred to as "element matrix".

The decoding of the LDPC code represented by the parity check matrix in the form of PxP element matrices can be performed using the architecture, which simultaneously performs calculations of the control node P and the calculation of the node of variables P.

Figure 34 is a block diagram showing an exemplary configuration of a decoding device that performs the above-described decoding process.

More specifically, Figure 34 shows an exemplary configuration of a decoding device that performs the LDPC code decoding process using the converted H 'parity matrix shown in Figure 33 obtained by at least permutating the Mathematical Expression column (9) on the original H parity matrix shown in Figure 31.

The decoding device shown in Figure 34 is equipped with an edge data storage memory 300 having 6 FIFO units 3001 to 3006, a selector 301 choosing one of the FIFO units 3001 to 3006, a control unit calculation unit 302, two cyclic shift systems 303 and 308, an edge storage memory 304 data having 18 FIFO units 3041 to 30418, a selector 305 selecting one of the FIFO units 3041 to 30418, memory of received data 306 for storing received information, unit of calculation of variable node 307, unit of calculation of decoded words 309, unit performing permutation of received data 310 and unit performing permutation of decoded data

- 45 311.

First, the method of saving data in the edge data storage memories 300 and 304 will be described.

The edge data storage memory 300 has the same number of FIFO units 3001 to 3006 as the number obtained by dividing the "30" rows of the converted H 'parity matrix shown in Figure 33 by the number of "5" rows of each element matrix. Each FIFO 300y unit (y = 1, 2, ... 6) has appropriate memory areas consisting of many levels, to which each message corresponding to the same edge number "5" as the number of rows and column number of each element matrix, can be simultaneously written or read. The number of memory area levels of each FIFO 300y unit is "9", which corresponds to a maximum number of 1s (Hamming weighted) towards the order of the converted parity check matrix shown in Figure 33.

Data (i.e., vi messages from variable nodes) corresponding to the "1" position of the first to fifth row of the converted H 'parity check matrix shown in Figure 33, are stored in the FIFO 3001 in the horizontal direction in each row while ignoring "0". In particular, when (j, i) specifies the elements of the jth order and ith column, data corresponding to the positions "1" of the 5x5 (1,1) to (5,5) unit matrix converted the parity check matrix H 'recorded are in the first level memory areas of the FIFO 3001 unit. Data corresponding to position "1" of the shifted matrix (1.21) to (5.25) of the converted H 'parity check matrix, which is obtained by cyclically shifting the 5 x 5 unit matrix to the right by 3 elements, is saved in the level memory area second. Similarly, data is recorded in levels 3 to 8 memory areas in relation to the converted H 'parity check matrix. Data corresponding to position '1' of the shifted matrix, (1.81) to (5.90) ​​the converted H 'parity check matrix, which is obtained by replacing' 1 'in the first row' 0 'in the 5 x 5 unit matrix and cyclic shift 5x5 unit matrix left by 1 element, are recorded in the memory area of ​​the ninth level.

Data corresponding to the "1" position of rows 6 to 10 of the converted H 'parity matrix shown in Figure 33 are recorded in FIFO 3002. In particular, the data corresponding to position "1" of the first shifted matrix included in the matrix total (6.1) to (10.5) of the converted parity check matrix H ', which is obtained by adding the first shifted matrix obtained by a cyclic shift of the 5x unit matrix 5 right by 1 element and the second shifted matrix obtained by cyclically shifting the 5 x 5 unit matrix to the right by 2 elements, are stored in the first-level memory area of ​​the FIFO 3002 unit. Data corresponding to position "1" of the second shifted matrix included in the matrix (6.1) to (10.5) of the converted H 'parity check matrix are stored in the second-level memory area of ​​the FIFO unit 3002.

More specifically, when an element matrix having a weighted value of 2 or more is represented by the sum of two or more PxP unit matrices with a value of

- 46 weighted "1", the acid-unit matrix generated by replacing one element "1s" of the unit matrix with the element "0s" and the shifted matrix generated by the cyclic shift of the unit matrix or the acid-unit matrix, data corresponding to position "1" of the unit matrix with the value weighted '1', unit acid matrix or shifted matrix (i.e. the message corresponding to the edge belonging to the unit matrix, acid-unit matrix or shifted matrix) is saved at the same address (the same FIFO unit from units 3001 to 3006).

Data is also saved in memory areas of levels 3 to 9 in connection with the converted H 'parity check matrix.

Similarly, data is recorded in units 3003 to 3006 in connection with the converted H 'parity check matrix.

The edge data storage 304 has the same number of 18 FIFO units 3041 to 30418 as the number obtained by dividing the "90" rows of the converted H 'parity check matrix by the number of "5" rows of each element matrix. Each FIFO 304x unit (x = 1, 2, ... 18) has appropriate memory areas consisting of many levels, to which each message corresponding to the same edge number "5" as the row number and column number of each converted H 'element matrix, can be simultaneously written or read.

Data (i.e., ui messages from the control nodes) corresponding to the "1" position of the first to fifth columns of the converted H 'parity matrix shown in Figure 33, are stored in FIFO 3041 in the vertical direction in each column while omitting "0". In particular, data corresponding to the "1" positions of the 5 × 5 (1.1) to (5.5) unit matrix converted the H 'parity check matrix are stored in the first level memory areas of FIFO 3041. Data corresponding to position '1' of the first shifted matrix included in the total of the matrix (6.1) to (10.5) of the converted parity check matrix H ', which is obtained by adding the first shifted matrix obtained by cyclic shift of the 5 x 5 unit matrix to the right by 1 element and the second shifted matrix obtained by cyclically shifting the 5 x 5 unit matrix to the right by 2 elements, are saved in the second-level memory area. Data corresponding to position "1" of the second shifted matrix included in the sum of the matrix (6.1) to (10.5) of the converted parity check matrix H 'are recorded in the third level memory area.

More specifically, when an elementary matrix having a weighted value of 2 or more is represented by the sum of two or more PxP unit matrices with a weighted value of "1", an acid-unit matrix generated by replacing one element "1s" of the unit matrix with an element "0s" and an offset matrix generated by the cyclic shift of the unit matrix or the acid-unit matrix, data corresponding to position '1' of the unit matrix with a weighted value '1', unit-acid matrix or shifted matrix (i.e. message corresponding to the edge belonging to a unit matrix, acid-matrix matrix or shifted matrix) are stored at the same address (same FIFO unit from units 3041 to 30418).

- 47 Data are also recorded in memory areas of levels 4 to 5 in relation to the converted H 'parity check matrix. The number of levels of memory areas for each FIFO 3041 unit is "5", which corresponds to a maximum of 1s (weighted)

Hamming) toward the first to fifth column of the converted H 'parity check matrix.

Similarly, data is recorded in FIFO units 3042 and 3043 in relation to the converted H 'parity check matrix, and the length (ie number of levels) of each FIFO unit is' 5'. Similarly, data is recorded in FIFO units 3044 to 30412 in relation to the converted H 'parity check matrix, and the length of each FIFO unit is' 3'. Similarly, data is recorded in FIFO units 30413 to 30418 with respect to the converted H 'parity check matrix, and the length of each FIFO unit is' 2'.

The operation of the decoding device shown in Figure 34 will now be described.

In the edge data storage memory 300 consisting of FIFO units 3001 to 3006, the FIFO data storage unit is selected from FIFO units

3001 up to 3006 according to information (matrix data) D312 indicating the row in the converted parity H 'matrix, which includes 5 D311 messages, received from the 308 cyclic shift system located in front of the edge data storage 300, and these 5 D311 messages are collected and saved to the selected FIFO unit in turn. When data is read from the edge data acquisition memory 300, first 5 messages D3001 are read sequentially from the FIFO 3001 unit, and then they are forwarded to selector 301 behind the edge data collection memory 300. After complete reading of messages from the FIFO 3001 unit, messages are sequentially read from FIFO units

3002 to 3006 in the edge data storage memory 300, and then are transferred to selector 301 in the same way.

The 301 selector selects 5 messages received from the FIFO unit from which data is currently being read from among the FIFO 3001 to 3006 units, according to the selection signal

D301 and sends selected messages in the form of D302 messages to the control unit 302 of the control node.

Control node calculation unit 302 has 5 control node calculators 3021 to 3025 and performs control node calculations according to Equation (7) using D302 messages (D3021 to D3025) (corresponding to vi messages in Equation (7)) received through selector 301 and generates 5 D303 messages (D3031 to D3035) (corresponding to ui messages in Equation (7)) received by calculations in the control node and sent to the 303 cyclic shift system.

The 303 cyclic shift system cyclically shifts 5 messages D3031 to D3035 received by the control node 302 calculation unit based on information (matrix data) D305 informing about the number of elements by which the original unit matrix has been cyclically shifted to get each corresponding edge in the converted

- 48 parity check matrices H 'and generate cyclically shifted messages in the form of D304 messages sent to the edge data storage memory 304.

In an edge storage data storage 304 consisting of 18 FIFO units 3041 to 30418, the FIFO unit for data storage is selected from FIFO units 3041 to 30418 according to the information D305 indicating the row in the converted H 'parity control matrix, which includes 5 D304 messages , received from cyclic shift system 303 located in front of the edge data storage memory 304, and these 5 D304 messages are collected and saved to the selected FIFO unit in turn. When data is read from the edge data collection memory 304, first 5 messages D3061 are read sequentially from the FIFO 3041 unit, and then they are forwarded to selector 305 behind the edge data collection memory 304. After complete reading of the data from the FIFO 3041 unit, the messages are sequentially read from the FIFO 3042 to 30418 units in the edge data storage memory 304, and then are transmitted in the same way to the selector 301.

The 305 selector selects 5 messages received from the FIFO unit, from which data is currently being read from among the FIFO units 3041 to 30418, according to the D307 selection signal and sends selected messages in the form of D308 messages to both the 307 control node calculation unit and the decoded owl calculator 309.

On the other hand, the permutation unit of the received data 310 performs the permutation of the Mathematical Expression column (9) to permute the LDPC code D313 obtained by the communication path and sends the resulting data in the form of the received data D314 in the data memory received 306. The received data memory 306 calculates and stores the receiving Probability Ratio Register (LLR) contained in the D314 data received from the permutation unit of the received data 310 and sends the LLR in groups of 5 as received values ​​D309 to both the 307 variable node calculation unit and the 309 decoded owl calculation unit .

The 307 variable node calculation unit has 5 variable node calculators 3071 to 3075 and performs the control node calculations in accordance with Equation (1) using messages D308 (D3081 to D3085) (corresponding to messages u and in Equation (1)) received via the 305 selector and 5 received values D309 (corresponding to received uoi values ​​in Equation (1)) received by the data unit received 306 and generates 5 D310 messages (D3101 to D3105) (corresponding to messages vi in ​​Equation (1)) obtained by calculations in the variable node and sent to the 308 cyclic shift system.

The 308 cyclic shift system cyclically shifts 5 messages D3101 to D3105 calculated by the calculation unit of the variable node 307 based on information about the number of elements by which the original unit matrix has been cyclically shifted to get each appropriate edge in the converted H 'parity control matrix and generates cyclically shifted messages in the form of D311 messages sent to the edge data storage memory 300.

- 49 The LDPC code may be decoded once by carrying out the above operations once. After decoding the LDPC code a predetermined number of times, the decoding device shown in Figure 34 receives and transmits the final decoded data via the decoded word calculation unit 309 and the decoded data permutation unit 311.

More specifically, the decoded word processing unit 309 has 5 decoded word calculators 3091 to 3095 and performs, as the last process of many decoding procedures, calculating decoded data (i.e. decoded word) based on Equation (5) using messages D308 (D3081 to D3085) (corresponding to messages in Equation (5)) sent through selector 305 and 5 received values ​​D309 (corresponding to received values ​​in Equation (5)) received from received data memory 306 and forward the calculated decoded D315 data to the decoded data permutation unit 311.

The decoded data permutation unit 311 performs the reverse permutation of the Mathematical Expression column (9) on the decoded D315 data obtained from the decoded word processing unit 309 to change the order of the decoded D315 data and transmits the resulting data as finally decoded D316 data.

As described above, one or both of the order permutations and column permutations are implemented on the parity check matrix (i.e., the original parity check matrix) to convert the parity check matrix (i.e., the converted parity check matrix), which can be represented by a combination of the matrix elementary i.e. combination of the P x ​​P unit matrix, the acid-unit matrix generated by replacing one or more "1s" elements of the unit matrix with the "0s" element, the shifted matrix generated by the cyclic shift of the unit matrix or the acid-unit matrix, the sum of the matrix generated by a positive two or more unit matrices, acid-unit matrices or shifted matrices and zero matrices P x P. This conversion of the parity check matrix allows the use of an LDPC architecture when decoding, which simultaneously calculates the P control node and calculates the P variable node.

Simultaneous calculations of the P node limits the operating frequency in the range that can be completely achievable, which allows decoding to be carried out several times.

Similar to the decoding device shown in Figure 34, the LDPC decoder 56 located at the receiver 12 shown in Figure 29 was designed to decode the LDPC code while performing the calculations of the control node P and the calculations of the variable node P.

More specifically, when for ease of explanation it is assumed that the parity check matrix of the output LDPC code from the encoder 21 located in the transmitter 11 shown in Figure 11 is the parity check matrix H, in which the parity matrix has a crotch structure, for example as shown in Figure 31, interleaving unit

- 50 parity 23 located in transmitter 11 interleaves the parity to interleave the code bit Fqx + y + I-th into K + Py + x + 1-th code bit, where the length of information K is "60", the number of columns P having a cyclic structure is "5" and the divisor of q (= M / P) parity length M is "6".

Because the parity interleaving corresponds to the permutation of the Mathematical Expression column (9) as mentioned above, the LDPC encoder 56 does not need to perform the permutation of the Mathematical Expression column (9).

Therefore, at receiver 12 in Figure 29, the LDPC code that has not been parred is significant, the LDPC code after the permutation of the Mathematical Expression column (9) is sent through the reverse interleaving unit of the column 55 to the LDPC 56 encoder, as described above. The LDPC encoder 56 performs the same processes that are performed in the decoding device in Figure 34, except that the permutation of the Mathematical Expression column (9) is not carried out by the LDPC 56 decoder.

More specifically, Figure 35 shows an example of the configuration of the LDPC decoder 56 shown in Figure 29.

The LDPC decoder 56 shown in Figure 35 has the same configuration as the decoding device shown in Figure 34, except that the received data permutation unit 310 shown in Figure 34 is not mounted here and performs the same processes as the decoding device shown in Figure 34 after except that the permutation of the Mathematical Expression column (9) is not implemented in the LDPC 56 decoder, so the description of the same configuration and processes will be omitted.

The LDPC decoder 56 may have a smaller size compared to the decoding device in Figure 34, because the LDPC decoder 56 can be built without the data permutation unit 310 obtained, as said above.

Despite this, for ease of explanation, Figures 31 to 35 are described with reference to an example in which the length N of the LDPC code is 90, the length of information K is 60, the unit number of columns P having a cyclic structure (i.e. the number of rows and the number of columns of the element matrix) ) is 5, and the divisor of q (= M / P) parity length M is 6, the length of the code N, the length of information K, the number of columns P having a cyclic structure and the divider q (= M / P) are not limited to the above values.

Thus while the LDPC encoder 21 located in the transmitter 11 in Figure 8 transmits the LDPC code, e.g. having the code length N 64800, the information length K equal to N-Pq (= NM), the unit number of columns P having a cyclic structure is 360, and the divider q M / P, the LDPC decoder 56 shown in Figure 35 can be used to decode the LDPC code while performing the calculations of the control node P and the calculation of the variable node P.

The above series of actions can be performed not only in terms of hardware, but also software. When a number of processes are implemented in software, it is software

- 51 can be installed on any general purpose computer.

Figure 36 shows an example configuration of a computer having a program implementing a number of the above-mentioned processes.

The program can be previously saved to a 405 hard drive or ROM 403 as a built-in storage medium in the computer.

The program can also be saved temporarily or permanently on removable media 411 for example on a diskette, CD-ROM, magnetic optical discs (MOD), DVDs, magnetic disks or in semiconductor memory. These removable storage media 411 can be provided in so-called program packages.

Instead of installing the program from a removable 411 storage medium, as described above, the program can be sent wirelessly from the appropriate page to the computer via a satellite connection for digital information transfer or via a cable connector from the local LAN or the Internet, and the computer can receive the program thanks to the 408 communication unit and can install the received program on the 405 internal hard drive.

The computer may be equipped with a processor (CPU - Central Processing Unit) 402. CPU 402 is connected to interface 410 input / output (10) via bus 401. CPU 402 executes the program stored in ROM 403 after entering a command by the user, for example after connecting the 407 input unit in the form of a keyboard, mouse, microphone and the like to the 410 interface. Alternatively, CPU 402 writes to RAM 404 and executes the program saved on hard disk 405; program saved on hard disk 405 after receiving from satellite or via network by communication unit 408 or program installed on hard disk 405 after reading from removable storage medium 411 inserted into drive 409. By executing the program in this way, CPU 402 carries out the processes described above in accordance with the diagrams or processes implemented by the elements described above, with respect to block diagrams. Then, if needed, the CPU 402 generates process results, e.g., via an output unit 406 equipped with an LCD screen, a loudspeaker and the like I / O 410 interfaces, or sends process results via communication unit 408 and stores the results on hard disk 405.

In the above description, it should be noted that the stages describing the program forcing the computer to perform various activities are not necessarily given in chronological order and can be implemented in parallel or individually (for example, by means of parallel or object-oriented processing).

The program can be implemented on one computer or on several in a distributed manner. The program can also be transferred to a remote computer to be used there.

Persons skilled in the subject will recognize that the examples of the invention are not limited to those described above, and various modifications may be made without departing from the scope of the invention as set forth in the appended claims.

- 52 More specifically, despite the fact that the LDPC code defined in the DVB-S.2 specification performs parity or column interlacing, which is a permutation process, the parity interleaving can be used on the LDCP code of the parity matrix in which the matrix information has no cyclic structure, provided that the parity matrix in the parity matrix has a step structure, and the column interlacing as a permutation process can be applied, for example, to the LDPC code of a parity check matrix, which is converted into a pseudo-cyclic structure by conducting at least column permutation or to the LDPC code of a quicyclic (QC) matrix parity check, having a completely cyclic structure.

This is a significant, LDPC parity check matrix that is subject to interlaced parity only requires the recognition of a parity matrix having a step structure and does not need to include a cyclic structure information matrix.

The LDPC code parity check matrix, which is subject to column twisting as a permutation process, is not limited to any particular structure.

In addition, the permutation process must be able to permutate bits of LDPC code so that many code bits corresponding to the value '1' in any row of the parity check matrix are not included in the same symbol and can be performed differently from the interlacing of the twisting columns. More specifically, the permutation process can be performed by controlling read and write addresses, for example using memory in which data is stored in only one direction instead of memory 31 in which data is stored in column and row directions.

Symbol interleaving unit

It has been proposed that the number of modes that are available in the DVB-T2 standard should be extended to include 1k, 16k and 32k modes. The following description is provided to show how the symbol interleaving unit operates according to the state of the art, but it can be seen that the symbol interleaving unit can be used in other modes and other DVB standards.

To create new modes, various elements must be defined, among which is the symbol interleaving unit 33. The bit for constellation mapping unit 26, symbol interleaving unit 33 and frame builder 32 are shown in more detail in Figure 37.

As described above, the prior art provides a device for performing acid-optimal mapping of data symbols to OFDM subcarrier symbols. According to an exemplary technique, the symbol interleaving unit is designed to perform optimal mapping of input data symbols to OFDM subcarrier symbols in accordance with the permutation code and generator polynomial that has been checked based on simulation analysis. The symbol interleaving unit is therefore combined with a bit interleaving unit and LDPC coding to improve the efficiency of data transmission via communication channels as proposed for DVB.

Figure 37 shows a more detailed shot of a bit belonging to the symbol constellation of the mapping unit 26 and the frame builder 32 to more accurately depict an embodiment of the present method. Data bits received from bit interleaving unit 26 via channel 62 are grouped into sets of bits mapped to data cells according to the number of bits per symbol determined by the modulation scheme. Groups of bits that are data words are fed in parallel via data channels 64 to the mapping processor 66. The mapping processor 66 then selects one of the data symbols according to a predefined mapping method. The constellation point is represented as a real and imaginary element and sent to the output channel 29 as one of the set of input data to the frame builder 32.

The frame builder 32 receives data cells from the bit to the constellation mapping unit 28 via channel 29 together with data cells from other channels 31. After building the frame of multiple OFDM cell sequences, the cells of each OFDM symbol are then written to the memory of the interleaving unit 100 and read from to of the interleaving unit 100 according to the write and read addresses generated by the address generator 102. According to the order of read and write, interleaving of data cells is accomplished by generating appropriate addresses. Operation of the address generator 102 and the memory of the interleaver 100 will be described shortly with reference to Figures 38, 39 and 40. The interleaved data cells are then combined with pilot and synchronization symbols received from the signal generator 36 in the OFDM symbol builder 37 to generate the OFDM symbol which is sent to the OFDM modulator 38, as explained above.

Figure 38 shows an example of a part of the symbol interleaving unit 33 which illustrates the state of the art in the field of symbol interleaving. In Figure 38, the input data cells of the frame builder 32 are stored in the interleaving unit 100's memory. Data cells are written to the memory of the interleaver 100 according to the write address sent from the address generator 102 through channel 104 and read from the memory of interleaver 100 according to the read address sent by the address generator through channel 106. Address generator 102 generates a write address and a read address as described above, depending on whether the OFDM symbol is odd or even, which is identified based on the signal sent through channel 108 and depending on the selected mode, which is defined based on the signal sent through the channel 110. As described, the modes that can be used are 1k, 2k, 4k, 8k, 16k and 32k. As described below, the write address and the read address are generated differently for the odd and even symbols, as explained in reference to Figure 39, which gives an example of the possibility of implementing the interleaving unit memory 100.

In the example shown in Figure 39, the interleaving unit memory consists of an upper part 100 representing the operation of the interleaving unit memory in the transmitter and a lower part 340 that shows the operation of the memory of the interleaver in the receiver. Interleaving unit 100 and reverse interleaving unit 340 are shown in Figure 39 to facilitate understanding of operation. As shown in Figure 39,

- 54 depicting the communication between interleaving unit 100 and reverse interleaving unit 340 through other devices and transmission channels, has been simplified and represented in the form of segment 140 between interleaving unit 100 and reverse interleaving unit 340. Operation of interleaver 100 is described in the following paragraphs:

Although Figure 39 illustrates only four input cells and four PFDM symbol subcarrier signals, it can be seen that the technique shown in Figure 39 can be developed into more subcarrier signals, e.g. 756 in 1k mode, 1512 in 2k mode, 3024 in 4k mode, 6048 in 8k mode, 12096 in 16k mode and 24192 in 32k mode.

The input and output addressing of the memory of the interleaver 100 shown in Figure 39 refers to odd and even symbols. For an OFDM symbol, data cells are received through an input channel 120 and stored in the interleaving unit 124.1 memory according to the address sequence 120 generated for each OFDM symbol by the address generator 102. Write addresses are used for positive symbols so that interleaving can be performed by shuffling save addresses. Therefore, for each interleaved symbol y (h (q)) = y '(q).

For odd symbols, the same interleaving unit memory 124.2 is used. However, as shown in Figure 39 regarding the odd symbol, the writing order 132 is in the same address sequence that was used to read the previous positive symbol 126. This function allows items introduced by the odd and even symbol interleaving units to use the same memory of the interleaving unit 100, provided that the address is read before writing. The data cells stored in the interleaving unit 124 for odd symbols are then read in the order 134 generated by the address generator 102 for the next OFDM even symbol and so on. Thus, only one address is generated for one symbol, with current writing and reading for odd / even OFDM symbols.

In summary, as shown in Figure 39, after calculating the set of H (q) addresses for all subcarrier signals, the input vector Y '= (y0', y1 ', y2', ... yNmax_1 ') is processed to generate the interleaved vector Y = (y0, y1, y2, ... yNmax_1) and defined by:

yH (q) = y'q for even symbols q = 0, ..., Nmax-1 yq = Y'H (q) for odd symbols q = 0, ..., Nmax-1

In other words, in the case of OFDM even symbols, input words are stored in memory in a permutated manner and read in a sequential manner, while odd symbols are written in a sequential manner and read in a permutated manner. In the above case, H (q) permutation is defined in the following table:

- 55 q 0 1 2 3

H (q) 13 0 2

Table 1: permutation for a simple case in which Nmax = 4

As shown in Figure 39, reverse interleaving unit 340 operates to reverse interleaving performed by interleaver 100 by using the same set of addresses generated by the equivalent address generator, but using the write and read addresses in the reverse order. In this case, regarding even symbols, the write addresses 342 are given in sequential order, while the read addresses 344 are generated by the address generator. Accordingly, in the case of odd symbols, the order of writing 346 is determined based on the set of addresses generated by the address generator, while reading 348 is in sequential order.

Address generation for operating modes

A block diagram showing the algorithm used to generate the permutation function H (q) is shown in Figure 40 for the 32k mode. However, as can be seen, the 32k mode interleaving unit shown in Figure 40 can be adapted to operate in 1k, 2k, 4k, 8k or 16k mode by performing the adaptation of the generator polynomial and permutation code as explained below.

In Figure 40, the linear reverse shift registers are formed by thirteen register levels 200 and a gate type XOR 202, which is connected to the levels register levels 200 according to the generator polynomial. For this reason, according to the contents of the shift register 200, the next bit of shift registers is generated by the XOR 202 gate type by performing an operation of the exclusion alternative type (xoring) on ​​the contents of the shift registers R [0], R [1], R [2], R [12] according to the generator polynomial:

<img file="PL2403147T3_D0005.tif" />

According to the generator polynomial, a sequence of pseudo-random bits is generated on the content of the shift register 200. To generate the address in 32k mode as shown, a permutation system 210 has been developed that effectively permutes the order of bits in the shift register 200.1 from the order R'i [n] in the order of Ri [n] at the output of the permutation system 210. The fourteen bits at the output of the permutation circuit 210 are sent via a conventional channel 212, to which the most significant bit is input through channel 214 through the switching circuit 218. Therefore, a fifteen bit address is generated on channel 212. However, to ensure the address's authenticity, the address control system 216 analyzes the generated address to determine if it exceeds a certain maximum value. The specified maximum value may correspond to the maximum number of subcarrier signals that are available for data symbols in an OFDM symbol available in the mode that is used. However, the 32k mode interleaving unit can also be used for other modes so that the address generator 102 can operate in the 2k, 4k, 8k, 16k and 32k modes, before adjusting the number of maximum valid addresses.

- 56 If the generated address exceeds the specified maximum value, the address control unit 216 controls the signal and sends it through channel 220 to the control unit 224. If the generated address exceeds the specified maximum value, this address is rejected and a new address is generated for the symbol.

For mode 32, a bit word (Nr-1) R'i is defined, where Nr = log2 Mmax, where Mmax = 32768 using LFSR (reverse shift register).

The polynomials used to generate this sequence are:

32k mode:

where i varies from 0 to Mmax-1

After generating one word, the word R'i undergoes a permutation process to generate another bit word (No.-1) called Ri. Ri results from R'i, due to the permutation carried out:

<td>Position of R'i bits</td><td> 13</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions Ri</td><td> 6</td><td> 5</td><td> 0</td><td> 10</td><td> 8</td><td> 1</td><td> 11</td><td> 12</td><td> 2</td><td> 9</td><td> 4</td><td> 3</td><td> 13</td><td> 7</td>

Bit permutation for 32k mode.

This means that in 32k mode, bit number 12 in R'i is sent to position 5 in Ri. The address H (q) results from Ri after satisfying the following equation:

<img file="PL2403147T3_D0006.tif" />

The element (imod2) 2N, -1 of the above equation is shown in Figure 20 by means of the switching block T218.

Address control is performed on H (q) to check whether the generated address is within the allowable limits: if (H (q) &lt;Nmax), where Nmax = 24192, for example, in 32k mode, the address is valid If the address is not is important, the control unit is informed and will try to generate a new H (q) by increasing the factor i.

The role of the switching block is to ensure that no address exceeding Nmax is generated twice in a row. As a result, if an exceeding value has been generated, it means that the MSB (i.e. switch bit) of address H (q) is one. Thus, the next value generated will have MSB set to zero to ensure that a valid address is generated. The additional bit reduces the likelihood that if the address exceeds the specified maximum value of the address, the next address will be a valid address. In one example, the additional bit is the most significant bit.

The following equations summarize the general behavior and help understand the loop structure of this algorithm:

- 57 q = 0;

for (i '= t); and &lt;M_max; L = i ⁺ 1)

N_r-a {H (q) - (i mt&gt; d2) -2^No. r * ifCHepper ^ mas) q-ąf-h Ϊ

Analysis supporting the address generator

The selection of the polynomial generator and permutation code discussed above for the address generator 102 of each of the operating modes, e.g., 32k mode, has been identified based on simulation analysis of the relative efficiency of the interleaving unit. The relative efficiency of the interleaving unit was evaluated using the relative compatibility of the interleaving unit to separate consecutive symbols or "interleaving quality". Accordingly, to use a single memory, the interleaving unit must efficiently perform the interleaving of odd and even symbols. The relative quality measure of interleaving unit is determined by defining the distance D (in the number of subcarrier signals). Criterion C was chosen to determine the number of subcarrier signals constituting the distance &lt;D at the output of the interleaving unit that was at the distance &lt;D at the entrance to the interleaving unit; the number of subcarrier signals for each distance D is then weighted relative to a relative distance. Criterion C is rated for both odd and even OFDM symbols. Minimizing C generates a quality interleaving unit.

<img file="PL2403147T3_D0007.tif" />

where: Nparz (d) and Nnieparz (d) is the number of even and subcarrier subcarrier signals at the output of the interleaving unit, respectively, which contain each subcarrier signal space.

The analysis of the interleaving unit identified for the 32k mode for the value D = 5 is shown in Figure 41 (a) for even OFDM symbols and in Figure 41 (b) for odd OFDM symbols. According to the above analysis, the C value of the permutation code identified above for the 32k mode generated a value of C = 21.75, the weighted number of subcarrier signals with symbols that are separated by a value of five or less at the output according to the above equation is 21.75.

The corresponding analysis was carried out for the alternative permutation code for the even OFDM symbols in Figure 41 (c) and the odd OFDM symbols in Figure 41 (d). As seen from the comparison with the results shown in Figures 41 (a) and 41 (b), more elements are present that represent symbols separated by small distances such as D = 1 and D = 2, after reference to the results given in Figures 41 (a ) and 41 (b), showing that when the permutation code is identified for the 32k mode, the symbol interleaving unit generates a superior quality interleaving unit. Alternate permutation codes

- 58 The following fifteen alternative possible codes (bit positions [n] Ri, where n = 1 to 15) generate a good quality symbol interleaving unit as specified in criterion C.

<td>Bit position R'i</td><td> 13</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td>L</td><td> 0</td>

<td>Bit position Ri [1]</td><td> 0</td><td> 6</td><td> 1</td><td> 7</td><td> 2</td><td> 11</td><td> 12</td><td> 5</td><td> 9</td><td> 8</td><td> 3</td><td> 10</td><td> 4</td><td> 13</td>

<td>Bit position Ri [2]</td><td> 9</td><td> 5</td><td> 0</td><td> 7</td><td> 2</td><td> 8</td><td> 3</td><td> 6</td><td> 12</td><td> 11</td><td> 4</td><td> 1</td><td> 10</td><td> 13</td>

<td>Bit position Ri [3]</td><td> 9</td><td> 12</td><td> 0</td><td> 1</td><td> 2</td><td> 13</td><td> 5</td><td> 8</td><td> 6</td><td> 3</td><td> 7</td><td> 4</td><td> 10</td><td> 11</td>

<td>Bit position Ri [4]</td><td> 13</td><td> 8</td><td> 1</td><td> 12</td><td> 11</td><td> 0</td><td> 9</td><td> 5</td><td> 3</td><td> 7</td><td> 6</td><td> 2</td><td> 10</td><td> 4</td>

<td>Bit position Ri [5]</td><td> 5</td><td> 8</td><td> 7</td><td> 0</td><td> 3</td><td> 2</td><td> 11</td><td> 4</td><td> 13</td><td> 6</td><td> 1</td><td> 10</td><td> 12</td><td> 9</td>

<td>Bit position Ri [6]</td><td> 8</td><td> 9</td><td> 5</td><td> 13</td><td> 0</td><td> 10</td><td> 7</td><td> 1</td><td> 12</td><td> 3</td><td> 2</td><td> 4</td><td> 11</td><td> 6</td>

<td>Bit position Ri [7]</td><td> 11</td><td> 10</td><td> 0</td><td> 7</td><td> 2</td><td> 9</td><td> 8</td><td> 1</td><td> 5</td><td> 3</td><td> 6</td><td> 4</td><td> 12</td><td> 13</td>

<td>Bit position Ri [8]</td><td> 11</td><td> 4</td><td> 0</td><td> 13</td><td> 10</td><td> 12</td><td> 5</td><td> 7</td><td> 2</td><td> 8</td><td> 3</td><td> 1</td><td> 6</td><td> 9</td>

<td>Bit position Ri [9]</td><td> 4</td><td> 0</td><td> 5</td><td> 1</td><td> 12</td><td> 2</td><td> 10</td><td> 3</td><td> 13</td><td> 9</td><td> 6</td><td> 11</td><td> 8</td><td> 7</td>

<td>Bit position Ri [10]</td><td> 4</td><td> 7</td><td> 0</td><td> 8</td><td> 10</td><td> 1</td><td> 6</td><td> 3</td><td> 2</td><td> 9</td><td> 11</td><td> 12</td><td> 13</td><td> 5</td>

<td>Bit position Ri [11]</td><td> 4</td><td> 6</td><td> 0</td><td> 13</td><td> 12</td><td> 1</td><td> 11</td><td> 2</td><td> 8</td><td> 3</td><td> 10</td><td> 7</td><td> 9</td><td> 5</td>

<td>Bit position Ri [12]</td><td> 0</td><td> 5</td><td> 1</td><td> 9</td><td> 2</td><td> 12</td><td> 3</td><td> 6</td><td> 8</td><td> 7</td><td> 4</td><td> 10</td><td> 11</td><td> 13</td>

<td>Bit position Ri [13]</td><td> 12</td><td> 4</td><td> 2</td><td> 11</td><td> 10</td><td> 1</td><td> 13</td><td> 6</td><td> 0</td><td> 9</td><td> 3</td><td> 8</td><td> 5</td><td> 7</td>

<td>Bit position Ri [14]</td><td> 10</td><td> 6</td><td> 0</td><td> 13</td><td> 12</td><td> 11</td><td> 8</td><td> 5</td><td> 2</td><td> 4</td><td> 3</td><td> 1</td><td> 9</td><td> 7</td>

<td>Bit position Ri [15]</td><td> 7</td><td> 6</td><td> 0</td><td> 1</td><td> 10</td><td> 3</td><td> 9</td><td> 4</td><td> 2</td><td> 5</td><td> 8</td><td> 11</td><td> 12</td><td> 13</td>

Bit permutation for 32k mode.

Adaptation of the symbol interleaving unit and address generator to other modes

Accordingly, the symbol interleaving unit shown in Figure 40 can be adapted to symbols in other modes simply by changing the maximum valid address, number of levels in the linear return signal register and permutation code. In particular, according to the above analysis, the following values ​​were determined for the 1k, 2k, 4k, 8k and 16k modes:

1k mode

Maximum valid address: about one thousand

Number of levels in the linear feedback register: nine

Generator polynomial: ^{= Λ&gt;}Permutation Code:

<td>R'i bit positions</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions Ri</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td><td> 5</td><td> 6</td><td> 7</td><td> 8</td>

2k mode

Maximum valid address: approximately two thousand. Number of levels in the linear feedback register: ten

Generator polynomial: Permutation code:

<img file="PL2403147T3_D0008.tif" />

<td>Bit positions R'i [n]</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions Ri [n]</td><td> 0</td><td> 7</td><td> 5</td><td> 1</td><td> 8</td><td> 2</td><td> 6</td><td> 9</td><td> 3</td><td> 4</td>

4k mode

Maximum valid address: approximately four thousand. Number of levels in the linear feedback register: eleven

Generator polynomial:

Permutation Code:

<td>R'i [n] for n =</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Ri [n] for n =</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

8k mode

Maximum valid address: approximately eight thousand. Number of levels in the linear feedback register: twelve

Generator polynomial: # · ilś-Ή ¹ -'Μ

Permutation Code:

<td>R'i bit positions</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions Ri</td><td> 5</td><td> 11</td><td> 3</td><td> 0</td><td> 10</td><td> 8</td><td> 6</td><td> 9</td><td> 2</td><td> 4</td><td> 1</td><td> 7</td>

16k mode

Maximum valid address: approximately sixteen thousand Number of levels in a linear feedback register: thirteen Polynomial generator:

<img file="PL2403147T3_D0009.tif" />

Permutation Code:

<td>R'i bit positions</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit position Ri</td><td> 8</td><td> 4</td><td> 3</td><td> 2</td><td> 0</td><td> 11</td><td> 1</td><td> 5</td><td> 12</td><td> 10</td><td> 6</td><td> 7</td><td> 9</td>

Further description of the symbol interleaving unit at the receiver

Returning to the interleaving unit shown in Figure 29, the symbol interleaving unit 514 is based on the data processing device shown in Figure 42 equipped with the memory of interleaving unit 540 and address generator 542. The memory of interleaving unit 540 is shown in Figure 39 and works as described above by performing interleaving by using address sets generated by address generator 542. The address generator 542 has the form shown in Figure 40 and its purpose is to generate appropriate addresses to map data symbols recovered from each OFDM subcarrier signal to an output data stream.

The remaining parts of the OFDM receiver shown in Figure 29 are used to perform error correction decoding of 518 bits of data encoded into LDPC to remove errors and recover the estimated value of the source data.

One of the advantages of the state of the art for both the receiver and the transmitter is that the symbol interleaving unit and the symbol back interleaving unit working in the receivers and the transmitter can be switched between 1k, 2k, 4k, 8k, 16k and 32k modes by changing generator polynomials and the permutation order. Hence, address generator 542 shown in Figure 42 has input data 544 providing mode information and input data 546 indicating whether OFDM odd / even symbols are present. Thus, flexible implementation is provided because the symbol interleaving unit and the back interleaving unit can be made as shown in Figures 38 and 42 with the address generator shown in any of Figures 40. The address generator can therefore be adapted to different modes by changing the polynomials and the permutation order specified for each mode. For example, this can be done by changing the software. Alternatively, in other embodiments, the receiver of the embedded signal processing unit 511 may have an embedded signal indicative of the DVB-T2 transmission mode and used to automatically configure the symbol reverse interleaving unit according to the detected mode.

Alternatively, as described above, different interleaving units can be used for different modes by simply adapting the maximum valid address to the mode used.

Optimal use of odd interleaving units

As shown in Figure 39, two symbol interleaving processes, one for even OFDM symbols and the other for odd, allow limiting the amount of memory used during interleaving. In the example shown in Figure 39, the order of writing for the odd symbol is the same as the order of reading for

- even symbol, therefore when reading the odd symbol from memory, the even symbol can be written from the position which has just been read; then, when the even symbol is read from the memory, the next odd symbol can be saved to the location just read.

As above, during an experimental analysis of the efficiency of interleaving units (using criterion C above) and as shown in Figure 43 (A) and Figure 43 (B), it was found that interleaving schemes designed for 2k symbol interleaving units and 8k for DVB-T2 and 4k symbol interleaving units for DVB-H, work better on odd symbols than even symbols. Thus, the results of the evaluation of the efficiency of the interleaving units, for example shown in Figures 43 (A) and 43 (B), showed that the odd interleaving units work better than the even interleaving units. This can be seen by comparing Figure 43 (A), which shows the results of the even interleaving unit with Figure 43 (B), which shows the results of the odd symbols: it can be seen that the average distance at the output of the subcarrier interleaving unit which was adjacent to the interleaving unit is greater for the odd symbol interleaving unit than for the even symbol interleaving unit.

It is understood that the memory capacity of the interleaver required to implement the symbol interleaver depends on the number of data symbols mapped to OFDM subcarrier symbols. Thus, the symbol interleaving unit in the 16k mode requires half the memory required for the 32k mode, and similarly the memory capacity required for the 8k mode is half that of the 16k mode. Thus, a transmitter or receiver that is equipped with a symbol interleaving unit of a given mode that has the maximum number of data symbols that can be carried by an OFDM symbol, the receiver or transmitter will be equipped with an appropriate memory capacity to perform two odd interleaving processes for any of modes that generate half or less than half the subcarrier signals per OFDM symbol in this maximum mode. For example, a receiver or transmitter having a flight unit for 32k mode will have adequate memory capacity to perform two 16k odd interleaving processes, each on a separate 16k memory.

Thus, to take advantage of the efficiency of odd interleaving processes, a symbol interleaving unit that is capable of using multiple modulation modes can be set such that only the odd interleaving process is used when it is in a mode that includes half or less than half of the signals maximum mode subcarriers, which reflects the maximum number of OFDM symbol subcarrier signals. This maximum mode therefore determines the maximum amount of memory. For example, a transmitter / receiver capable of operating in 32k mode, when operating with a smaller number of subcarrier signals (i.e. 16k, 8k, 4k or 1k), instead of using separate odd and even symbol interleaving processes, will use two odd interleaving units.

Illustration of the adaptation of the symbol interleaving unit 33, which is shown in Figure 38

- 62 is shown in Figure 44 for the interleaving of input data symbols into OFDM symbol subcarrier signals in an odd pattern. The symbol interleaving unit 33.1 exactly corresponds to the symbol interleaving unit 33 shown in Figure 38, except that the address generator 102.1 is adapted only to perform the odd interleaving process. In the example shown in Figure 44, the symbol interleaving unit 33.1 operates in a mode in which the number of data symbols that can be carried in an OFDM symbol is less than half the maximum number that can be carried by an OFDM symbol in the operating mode with the largest number of subcarrier symbols per OFDM symbol. In such form, the symbol interleaving unit 33.1 is configured to divide the memory of interleaver 100. In Figure 44, the memory of the interleaver 100 is divided into two parts 601, 602. To illustrate the symbol interleaving 33.1 operating in a mode in which data symbols are mapped to OFDM symbols using an odd passage process, the Figure shows an exploded view of each half of the memory 601 interlaced units

602. This view is an illustration of the odd interleaving mode on the transmitter side for the four symbols A, B, C, D reproduced from Figure 39. Thus, as shown in Figure 44, for the next sets of first and second data symbols, the data symbols are stored in the unit's memory. interleaving 601, 602 in a sequential manner and read according to the addresses generated by the address generator 102 in the permutated order according to the addresses generated by the generator. Thus, as shown in Figure 44, because the odd interleaving process is performed for successive sets of first and second sets of data symbols, the interleaving unit memory must be divided into two parts. Symbols from the first set of data symbols are recorded in the first half of the memory of the interleaver 601, and symbols from the second set of data symbols are written in the second part of the memory of interleaver 602 because the symbol interleaving unit cannot use the same parts of the symbol interleaver memory that can be used when working in odd and even interleaving modes.

A suitable example of an interleaving unit in a receiver is shown in

Figure 42, but is adapted exclusively to the odd process, is shown in Figure 45. As shown in Figure 45, the interleaving unit memory 540 is divided into two halves 710, 712, and address generator 542 has been adapted to write data symbols to the interleaving unit memory and reading data symbols from the memory in respective memory parts 710, 712 for subsequent sets of data symbols to perform only odd interleaving. Thus, in response to the arrangement shown in Figure 44, Figure 45 shows the interleaving mapping that is implemented at the receiver and shown in Figure 39, in exploded view, for the first and second memory half of the interleaving unit 710, 712. Thus, the first set of symbols data is written to the first part of the memory of the interleaver 710 in the permutated order defined according to the addresses generated by the address generator

542, as shown by the order in which the data symbols were written in the permutated recording sequence 1, 3, 0, 2. According to the above, the data symbols are read from

- 63 the first part of the memory of the interleaver 710 in order, thus recovering the original order of A, B, C, D.

Accordingly, the second successive set of data symbols that have been recovered from the next PFDM symbol are written to the second half of the memory of interleaver 712 according to addresses generated by address generator 542 in permutated order and read to the output stream in order.

In one example, the addresses generated for the first set of data symbols recorded in the first half of the memory of the interleaver 710 can be reused to write the second subsequent set of data symbols in the memory of interleaver 712. Accordingly, the transmitter may reuse the addresses generated for one half of the interleaving unit for the first set of data symbols to read the second set of data symbols that have been stored in the second half of the memory in order.

Application of permutation sequences

In one example, the address generator may use different permutation codes from a set of permutation codes for subsequent OFDM symbols. By using the permutation sequence in the address of the memory unit, the generator limits the likelihood that any bit of data input into the interleaving unit will not always modulate the same number of OFDM symbol subcarrier signals. In another example, two address generators may be used; one generating addresses for the first set of data symbols and for the first half of the memory, and the other generating a different sequence of addresses for the second set of data symbols and the second half of the memory. The two address generators may differ in terms of the permutation code chosen from the above permutation table.

For example, a cyclic sequence may be used in such a way that the permutation code in the set of sequential permutation codes will be used for subsequent OFDM symbols and then repeated. The cyclic sequence may, for example, be two or four lengths. For example, in the case of the 16k symbol interleaving unit, the sequence of two permutation codes that will be used cyclically in an OFDM symbol may be, for example:

8432011151210679

7953111402121086 while the sequence of four permutation codes might look like this:

8432011151210679

7953111402121086

6117523011081294

5129031024678111

Switching the permutation code to another one can be done in response to

- 64 the change of the odd / parity signal detected by the control channel 108. In response to this, the control unit 224 changes the permutation code in the permutation code system 210 using control line 111.

For example, in a 1k symbol interleaving unit, two permutation codes can be:

432105678

325014786 while the four codes can be:

432105678

325014786

753826140

168253407

In other combinations of sequences it is possible to use 2k, 4k and 8k or modes

0.5k. For example, the following permutation codes for each of the 0.5k, 2k, 4k and 8k modes provide good symbol de-correlation and can be used cyclically to generate an address error generated by the address generator for each of the respective modes:

2k mode:

0751826934*

4832901567

8390215746

7048369152

4k mode:

710581249036**

627108034195

954231010687

141039726508

8k mode:

51130108692417*

10854291067311

1169847210,1053

83117915640210

For the above permutation codes, the first two may be used in

- 65 two-sequential cycles, while all four can be used in a four-sequential cycle. In addition, the following sequences of four permutation codes, which are used to provide an error in the address generator, to determine good de-correlation of interleaved symbols (some are the same as above):

0.5k mode:

37461205

42573016

53604127

61052743

2k mode:

0751826934*

3270158496

4832901567

7395210648

4k mode:

710581249036**

627108034195

103412706859

089510463217

8k mode:

51130108692417*

81076052139411

11369274105108

10817560114293 * permutations used in the DVB-T standard ** permutations used in the DVB-H standard

Examples of address generators and their corresponding interleaving units for 2k, 4k and 8k modes are described in European Patent Application No. 04251667.4. The address generator for the 0.5k mode is described in our filed UK patent application number 0722553.5.

As can be seen, the transmitter and receiver shown in Figures 1 and 7 respectively are illustrated for information purposes only and are not limited to these systems. For example, as can be seen, the position of the symbol interleaving units and units

- 66 interleaving with respect to, for example, bit interleaving units and mapping and reverse mapping units may vary. It can be seen that the interleaving and reverse interleaving effect does not change after changing position, despite the fact that the interleaving unit can interleave I / O symbols instead of bit vectors v. The same change can be performed at the receiver. Accordingly, the interleaving unit and the back interleaving unit can operate on different types of data and can be differently positioned relative to the items given in the preferred embodiments.

As described above, the permutation codes and polynomial of the interleaving unit generator which has been described in relation to the implementation of a specific mode can be successfully used in other modes by changing the specified maximum allowed address according to the number of subcarrier signals in that mode.

According to one embodiment of the receiver, a data processing device is described to map data symbols received from a specified number of OFDM symbol subcarrier signals (orthogonal frequency multiplication) to the form of an output data stream.

As mentioned above, preferred embodiments of the invention find use in DVB standards such as, for example, DVB-T, DVB-T2 and DVB-H, which are incorporated herein by reference. For example, preferred embodiments of the invention may be used in a transmitter or receiver operating in accordance with the DVB-T2 standard as described in the ETSI EN 302 755 standard, although it can be seen that the invention is not limited to DVB and can be used in other broadcasting standards or reception, both in stationary and mobile systems. In addition, preferred embodiments of the invention find use with cable transmission standards known as DVB-C2.

In addition to the above examples, as well as the embodiments and features of the invention described in the following claims, other solutions may relate to a data processing device mapping input symbols transmitted to a specified number of OFDM symbol subcarrier signals (orthogonal frequency reproduction). The specified number of subcarrier signals corresponding to the modulation mode and the input symbols may include odd data symbols and even data symbols. The data processing apparatus consists of an interleaving unit carrying out the first interleaving process that interleaves the odd input data symbols into subcarriers and the even interleaving process which interleaves the even input data symbols into subcarriers, the first odd interleaving process and the even interleaving process, which reads and reads data symbols to map to OFDM subcarrier signals to the interleaving unit memory, the reading occurs in a different order to that of loading in such a way that when the odd symbol is read from a given location in the memory, the even symbol can be written to the location in the memory just read, and after reading the even symbol from a given place in the memory, the next odd symbol can become

- 67 places saved; an odd interleaving process that reads and reads the odd data symbols from the interleaving unit memory according to the odd interleaving scheme, and an even interleaving process that loads and reads even data symbols from the memory of the interleaving unit according to the parity interleaving scheme. When the modulation is in a mode that includes half or less than half the subcarrier signals relative to the total number of subcarrier signals that may be in the interleaving unit's memory, the data processing device assigns a portion of the interleaving memory to the first odd interleaving process and a second portion of memory interleaving for the second odd interleaving process according to the first, a second odd interleaving process by interleaving even input symbols.

According to another embodiment of the invention, the data processing device maps the input symbols transmitted on a specific number of subcarrier signals of Orthogonal Frequency Division Multiplexed (OFDM). The specified number of subcarrier signals corresponds to the modulation mode, and the input symbols include first data symbols to map to the first OFDM symbol and second data symbols to map to the second OFDM symbol. The data processing apparatus consists of an interleaving unit performing an odd interleaving process that interleaves the first input data symbols into subcarriers and an even interleaving process which interleaves the second input data symbols into subcarriers, the odd interleaving process storing the first input data symbols in the interleaving unit memory in accordance with the ordering order of the first input data symbols and reading the first data symbols from the interleaving unit memory for signals in a sequence defined by the permutation code; an even interleaving process that writes the second input data symbols to the interleaving unit memory in the order defined by the permutation code and reads the second data symbols from the memory into subcarrier signals in order, in such a way that when the first input data symbol is read from interleaving unit memory, a second symbol can be written in this place, and when the second symbol is read from the memory of the interleaver, the next first symbol can be written here. When the modulation is in a mode that includes half or fewer subcarrier signals relative to the total number that can be accommodated in the interleaver memory, the data processing device interleaves the first and second input symbols according to the odd interleaving process.

In another embodiment of the invention, there is provided a method of mapping input symbols transmitted on a certain number of subcarrier signals of Orthogonal Frequency Division Multiplexed (OFDM). The method consists of mapping the first data symbols to the first OFDM symbol and mapping the second data symbols to the second OFDM symbol.