Data processing apparatus and method

[0001] The invention relates to a data processing device capable of mapping input symbols to signals of the subcarrier symbols of orthogonal frequency division multiplication (OFDM).

[0002] An embodiment of the invention may be an OFDM transmitter.

Background of the Invention [0003] The digital terrestrial broadcast television (DVB-T) standard uses orthogonal frequency division multiplexing (OFDM) to transmit video and sound image data to receivers by broadcasting a radio signal. There are two known DVB-T modes that are known as 2k and 8k modes. The 2k mode provides 2048 subcarriers, while the 8k mode provides 8192 subcarriers. Similarly, for the digital television standard for portable devices (DVB-H) there is a 4k mode in which the number of subcarriers is 4096.

[0004] Correction code schemes, such as LDPC / BCH coding, that have been proposed for DVB-T2 work better when the noise and degradation of the symbol values ​​resulting from communication are uncorrelated. Terrestrial broadcasting channels may be susceptible to correlated signal loss in both time and frequency domains. In this way, by separating the encoded symbols as much as possible into different OFDM symbol subcarrier signals, the efficiency of correction code schemes can be increased. Accordingly, in order to improve the integrity of data transmitted using DVB-T or DVB-H, a symbol interleaver is provided to interleave the input data symbols as the symbols are mapped to OFDM symbol subcarrier signals. Such symbol interleaver includes the memory of the interleaver and the address generator. The interleaver is organized to read data symbols into the interleaver memory to map to OFDM subcarrier signals and to read from the data symbol memory for OFDM subcarriers, the reading occurs in a different order than loading and is determined based on the set of addresses that are generated through the address generator. The layout for 2k mode and 8k mode has been disclosed in the DVB-T standard for generating addresses that affect mapping. Similarly, for the 4k mode of the DVB-H standard, a system is provided for generating addresses for mapping, and an address generator for implementing this mapping is disclosed in European Patent Application 04251667.4. The address generator has a linear feedback shift register that can generate a pseudo-random bit sequence and permutation system. The permutation system permutes the order of the contents of the shift register with linear feedback to generate the address. This address provides an indication of the location of the interleaver memory for recording the input data symbol or reading the input data symbol from the interleaver memory for mapping the OFDM symbol to one of the subcarrier signals. Similarly, the address generator in the receiver is

- 2 prepared to generate interleaving device memory addresses for writing received data symbols to the interleaving device memory or reading data symbols from it to create an output data stream.

[0005] According to a further development of the terrestrial digital television standard, known as DVB-T2, there is a desire to improve data transmission and in particular to provide an improved data symbol interleaving system on OFDM symbol subcarrier signals.

Summary of the Invention [0006] According to an embodiment of the invention, there is provided a data processing device capable of mapping input data symbols transmitted on a predetermined number of subcarrier signals of orthogonal frequency division multiplexing (OFDM) symbols. The data processing device includes an interleaving device capable of reading into a predetermined memory a number of data symbols to map to signals of OFDM subcarriers, and to read from the memory of data symbols for OFDM subcarriers in order to carry out the mapping, the reading being in a different order than loading, and the order is determined based on the set of addresses, with the result that the data symbols are interleaved on the subcarrier signals. The data processing apparatus includes an address generator capable of generating a set of addresses, the address being generated for each of the input data symbols for mapping the input data symbols to subcarrier signals. The address generator includes a linear feed shift register containing a predetermined number of register stages that are capable of generating a pseudo random sequence of bits according to the generator polynomial, a permutation system prepared to receive the contents of the shift register stages and permutate the order of the bits present in the register stages according to permutation code to create the address of one of the OFDM subcarriers, and the control unit, which, acting in conjunction with the address checking system, can regenerate the address when the generated address exceeds the pre-set maximum valid address. The maximum correct address given in advance is approximately two thousand, the linear feedback shift register has ten degrees of register with the generator polynomial for the linear feedback shift register, the permutation row forms, along with the additional bit, an eleven-bit address. The data processing device is characterized in that the permutation system is prepared to change the permutation code, which permutes the order of the bits of the register degrees to create a set of addresses from one OFDM symbol to another.

[0007] Embodiments of the invention may provide a data processing device operating as a symbol interleaver for mapping data symbols transmitted to an OFDM symbol, having generally two thousand subcarrier signals that can provide improved integrity of transmitted data. The improvement is provided by changing the permutation code that is used to change the order of the bits in the feedback shift register from one OFDM symbol to another.

For example, the permutation code used may be one of the sequences of cyclically switched different permutation codes for each of a plurality of OFDM symbols. As a result, an improvement is provided by limiting the possibility of an event that subsequent or such data bits that are close in the input data stream will be mapped to the same OFDM symbol subcarrier, so that correction coding can work with greater efficiency.

[0008] In one embodiment, the number of subcarrier signals may be between substantially eight hundred and two thousand and forty-eight. In addition, the OFDM symbol may include pilot subcarriers that are prepared to carry known symbols, and the predetermined maximum valid address may depend on the number of pilot subcarrier symbols present in the OFDM symbol. In this way, the 2k mode can be equipped with effective symbol interleavers, for example for a DVB standard such as DVB-T2, DVB-T or DVB-H.

[0009] In one example, the sequence of different permutation codes creates an 11-bit · * · './ · address. for the i-th data symbol from the bit in the n-th stage of the register -Ϋ. according to the permutation code specified by the table:

<td>fij for n =</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>fi; for n =</td><td> 0</td><td> 7</td><td> 5</td><td> 1</td><td> 8</td><td> 2</td><td> 6</td><td> 9</td><td> 3</td><td> 4</td>

[0010] Although the permutation code sequence may comprise any number of codes

<img file="PL2333964T3_D0001.tif" />

and

<td>fli for n =</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>fi; for n =</td><td> 3</td><td> 2</td><td> 7</td><td> 0</td><td> 1</td><td> 5</td><td> 8</td><td> 4</td><td> 9</td><td> 6</td>

[0011] For example, approximately two thousand subcarriers may be provided as one of many operating modes, with approximately two thousand subcarriers providing half or less than half the maximum number of subcarriers in the OFDM symbols of any of the operating modes. Input data symbols may be formed as first sets of input data symbols or treated as such for mapping to the first OFDM symbols, and second sets of input data symbols for mapping to the second OFDM symbols. The data processing apparatus can be used to interleave the input data symbols from both the first and second sets

- 4 according to the odd interlacing process. The odd interleaving process includes writing the first set of input data symbols to the first part of the interleaver memory in accordance with the sequential order of the first set of input data symbols, reading the first sets of input data symbols from the first part of the interleaver memory on the subcarrier signals of the first OFDM symbols in order defined by one from sequence permutation codes, writing the second set of input data symbols to the second part of the interleaver memory according to the sequential order of the second sets of input data symbols and reading the second set of input data symbols from the second part of the interleaving device memory on the subcarrier signals of the second OFDM symbols in the order defined by other sequence permutation codes.

[0012] The first OFDM symbols may be odd OFDM symbols and the second OFDM symbols may be even OFDM symbols.

[0013] In some conventional OFDM transmitters and receivers that operate in accordance with 2k or 8k modes for DVB-T and 4k mode for DVB-H, two symbol interleaving processes are used in the transmitter and receiver, one for even OFDM symbols and one for odd OFDM symbols. However, the analysis showed that the interleaving schemes designed for 2k and 8k interleavers for DVB-T and 4k symbol interleavers for DVB-H work better for odd symbols than for even symbols. Embodiments of the invention are arranged so that only the odd symbol interleaving process is used, as long as the transmitter / receiver is not in the maximum number of subcarriers mode. Therefore, when the number of data symbols that can be carried by OFDM symbol subcarriers in one of many operating modes is less than half the number of data symbols that can be carried in an operating mode that works as transferring the largest number of subcarrier signals to an OFDM symbol then the OFDM symbol interleaver in the transmitter and receiver is set to interleave the data symbols of both the first and second sets, using the odd interlacing process. Because the interleaver interleaves the data symbols of both the first and second sets of data symbols into OFDM symbols by using the odd interleaver process, the interleaver uses different parts of the memory of the interleaver to write and read the data symbols. Therefore, compared to the example where the interleaver uses the odd interleaver process and the even interleaver process to interleave the first and second sets of data symbols into the next first and second OFDM symbols, which consumes available memory, the amount of memory capacity used is twice the number of data symbols that can be carried by the OFDM symbol for the odd interleaving only. This is comparable to the required memory size of one time the number of data symbols that can be transferred in the OFDM symbol in the mode with the highest number of data symbols to the OFDM symbol using both the odd and even interleaving processes. However, the number of subcarriers per OFDM symbol for this maximum operating mode is twice the next capacity of the number of subcarriers per OFDM symbol for any other operating mode with the next

- 5 largest subcarriers per OFDM symbol.

[0014] According to several examples, therefore, a minimum memory size of the interleaver can be provided according to the maximum number of input data symbols that can be transferred to OFDM symbol subcarriers that are available to carry input data symbols in any of the operating modes.

[0015] In some embodiments, the operating mode that provides the maximum number of subcarriers per OFDM symbol is the 32K mode. Other modes may include one or more of 1K, 2K, 4K, 8K and 16K modes. Therefore, as will become clear from the above explanation, in 32K mode, the odd and even interleavers are used to interleave data symbols, so that the amount of memory of the interleaver can be only sufficient to include 32K data symbols. However, for 16K mode and any of the other modes, only the odd interleaving process is used, so that 16K mode memory equivalent to 32K symbols is required, 4K mode requires 8K symbols equivalent to memory, and 2K mode requires memory size equivalent to 4K symbols.

[0016] According to another embodiment of the invention, a data processing device is provided capable of mapping input data symbols transmitted on a predetermined number of subcarrier signals of orthogonal frequency division multiplication symbols OFDM, wherein the predetermined number of subcarrier signals is determined in accordance with one mode of many operating modes, and the input data symbols comprise first sets of input data symbols to map to the first OFDM symbols and second sets of input data symbols to map to the second OFDM symbols. The data processing equipment includes:

an interleaver capable of loading into a preset memory the number of data symbols to map to OFDM subcarrier signals, and to read from the data symbol memory for OFDM subcarriers to perform mapping, the reading being in a different order than loading, and the order is determined on based on the address set, with the effect that the data symbols are interleaved on the subcarrier signals, an address generator capable of generating the address set, wherein the address is generated for each of the input symbols to map the input data symbols to one of the subcarrier signals, and the address generator includes a linear feedback shift register containing a predetermined number of register stages and capable of generating a pseudo-random bit sequence according to the generator polynomial, a permutation system capable of receiving the contents of the shift register stages and permuting the order of bits present in the register stages, according to the permutation code to create the address of one of the OFDM subcarriers, and a control unit capable of, in conjunction with the address checking system, to regenerate the address when generated the address exceeds the maximum valid valid address given in advance, one of the many operating modes provides approximately two thousand subcarriers per OFDM symbol, approximately two thousand subcarriers provides

- 6 half or less than half the maximum number of subcarriers in the OFDM symbols of any of the operating modes, the maximum correct address given in advance is approximately two thousand, the linear feedback shift register has ten register degrees with the polynomial generator for the linear feedback shift register

ΰ.Λ - A., and the permutation code forms, along with the additional bit, an 11-bit address, and the data processing device is adapted to interleave the input data symbols of both the first and second sets according to the odd interleaving process. The odd interleaving process includes writing the first sets of input data symbols to the first part of the interleaver memory according to the sequential order of the first input data symbol sets, reading the first sets of input data symbols from the first part of the interleaving device memory on the subcarrier signals of the first OFDM symbols according to the order defined by the set addresses writing the second set of input data symbols to the second part of the interleaver memory according to the sequential order of the second set of input data symbols and reading the second set of input data symbols from the second part of the interleaving device memory on the subcarrier signals of the second OFDM symbols in accordance with the order defined by the set of addresses.

[0017] Various objects and features of the invention are defined in the appended claims. Further objects of the invention include a method of mapping input symbols transmitted on a predetermined number of subcarrier signals of orthogonal frequency division multiplexing (OFDM) symbols, and a transmitter.

Brief description of the drawings [0018] Embodiments of the invention will be described only by way of example with reference to the accompanying drawings, in which similar parts are marked with corresponding reference numbers, and in which:

Figure 1 is a schematic block diagram of an encoded OFDM transmitter that can be used, for example, in the DVB-T2 standard;

Figure 2 is a schematic block diagram of the transmitter parts shown in Fig. 1, wherein the symbol mapping device and the frame builder illustrate the operation of the interleaver;

Figure 3 is a schematic block diagram of the symbol interleaver shown in Figure 2;

Figure 4 is a schematic block diagram of the memory of the interleaver shown in Fig. 3 and the corresponding deinterleaver at the receiver;

Figure 5 is a schematic block diagram of the address generator shown in Figure 3 for the 2k mode;

Figure 6 is a schematic block diagram of an encoded OFDM receiver that it can

- 7 be used, for example, in the DVB-T2 standard;

Figure 7 is a schematic block diagram of the symbol deinterleaver device shown in Figure 6;

Figure 8 (a) is a diagram illustrating results for an interleaver for even OFDM symbols, and Figure 8 (b) is a diagram illustrating results for odd OFDM symbols; Figures 8 (a) and 8 (b) show distance plots at the output of the interleaver for subcarriers that were adjacent to the input of the interleaver;

Figure 9 is a schematic block diagram of the symbol interleaver shown in Fig. 3, illustrating an operating mode in which interleaving is performed only in accordance with the odd interleaving mode and

Fig. 10 is a schematic block diagram of the symbol deinterleaver device shown in Fig. 7, illustrating an operating mode in which interleaving is performed only according to the odd interleaving mode.

Description of Preferred Embodiments [0019] The following description is provided to illustrate the operation of the symbol interleaver according to the prior art, although it will be appreciated that the symbol interleaver can be used in other modes, other DVB standards and other OFDM systems.

[0020] Figure 1 is an example of a block diagram of an encoded OFDM transmitter that can be used, for example, to transmit video images and audio signals according to the DVB-T2 standard. In Fig. 1, the source program generates data to be transmitted by the COFDM transmitter. The video encoder 2 and audio encoder 4 and data encoder 6 generate video, audio and other data to be transmitted and are entered into the multiplexer 10 program. Exiting the multiplexer 10 program creates a multiplexed stream with other information required to transfer video, audio and other data. Multiplexer 10 provides a stream on the connecting channel 12. There may be many such multiplied streams that are fed to different branches A, B etc. For simplicity, only branch A will be described.

[0021] As shown in Fig. 1, the COFDM transmitter 20 receives the stream on the multiplexer adaptation and energy dissipation block 22. The multiplexer 22 energy adjustment and dissipation randomizes the data and feeds the appropriate data to the correction coder 24, which performs stream correction coding. A bit interleaver 26 for interleaving coded data bits is shown, which for example DVB-T2 is the output of the LDPC / BCH encoder. The output from the bit interleaver 26 is fed to a bit mapper to constellation 28 that maps bit groups to the constellation point to be used for transmitting the coded data bits. The outputs from the bit mapping device to constellation 28 are constellation point labels that represent real and imaginary components. Constellation point labels represent data symbols formed of two or more bits, depending on the modulation scheme used. They will be referred to as data cells. These cells

8 data is passed through a time interleaver 30, the effect of which is interleaving of data cells arising from multiple LDPC code words.

[0022] Data cells are received by the frame builder 32, with data cells formed by the branch B etc. in Fig. 1, through other channels 31. The frame builder 32 then forms a plurality of data cells into sequences for transmission on COFDM symbols, the symbol COFDM contains a number of data cells, and each data cell is mapped to one of the subcarriers. The number of subcarriers will depend on the mode of operation of the system, which may include one of the 1k, 2k, 4k, 8kl, 16k or 32k modes, each of which provides a different number of subcarriers, for example according to the following table:

<td>Mode</td><td>subcarriers</td>

<td>1K</td><td> 756</td>

<td>2K</td><td> 1512</td>

<td>4K</td><td> 3024</td>

<td>8K</td><td> 6048</td>

<td>16K</td><td> 12096</td>

<td>32K</td><td> 24192</td>

Number of subcarriers taken from DVB-T / H [0023] Therefore, in one example, the number of subcarriers for the 2k mode is one thousand five hundred twelve. For a DVB-T2 system, the number of subcarriers per OFDM symbol may vary depending on the number of pilot carriers and other reserved ones. Therefore, in DVB-T2, unlike DVB-T, the number of subcarriers for data transfer is not fixed. Broadcasters can choose one of the operating modes from 1k, 2k, 4k, 8k, 16k, 32k, each of which provides a range of subcarriers for data on the OFDM symbol, with the maximum available for each of these modes being 1024, 2048, 4096, 8192, respectively , 16384, 32768. In DVB-T2, the physical layer frame consists of multiple OFDM symbols. Typically, a frame begins with one or more OFDM preamble or P2 symbols followed by a series of OFDM symbols carrying useful data. The end of the physical layer frame is marked with symbols that close the frame. For each operating mode, the number of subcarriers may be different for each type of symbol. In addition, this may vary for each of them depending on whether the bandwidth extension is selected, or tone reservation is activated, and according to the pilot subcarrier pattern that has been selected. In this state of affairs, it is difficult to generalize a specific number of subcarriers per OFDM symbol. However, the frequency interleaver for each mode can interleave any symbol for which the number of subcarriers is smaller or the same as the maximum number of subcarriers allowed for a given mode. For example, in 1k mode, the interleaver would work for symbols with subcarrier numbers less than or equal to 1024, and for 16k mode with subcarrier numbers less than or equal to 16384.

[0024] The sequence of data cells to be carried in each COFDM symbol is then sent to the symbol interleaver 33. Symbol

- 9 COFDM is in turn generated by the 37 COFDM symbol builder block, which introduces the pilot and synchronization signal supplied from the pilot forming device and the embedded 36. In turn, the OFDM modulator 38 creates a time domain OFDM symbol, which is fed to the guard insertion processor 40 to generate a guard interval between the symbols, then to the digital-to-analog converter 42, and finally to the RF amplifier within the RF front end devices 44 to the final transmitting by the COFDM transmitter from the antenna 46.

[0025] As explained above, the invention provides an installation for providing quasi-optimal mapping of data symbols to signals of the OFDM symbol subcarriers. According to an embodiment, an interleaver is provided to obtain an optimal mapping of the input data symbols to COFDM subcarrier signals according to the permutation code and generator polynomial that has been verified by simulation analysis.

[0026] As shown in Fig. 2, a more detailed exemplary illustration of a bit mapping device for constellation symbol 28 and frame builder 32 is provided to illustrate an embodiment. The data bits received from the bit interleaver 26 via channel 62 are grouped into bit sets for mapping to data cell according to the number of bits per symbol provided by the modulation scheme. The bit groups that make up the data word are fed in parallel through the data channels 64 to the mapping processor 66. The mapping processor 66 then selects one of the data symbols according to the pre-assigned mapping. The constellation point is represented by the real and imaginary component that is provided to the output channel 29 as one of the set of input signals to the frame builder 32.

[0027] The frame builder 32 receives data cells from the bit mapping device into constellations 28 via channel 29, along with data cells from other channels 31. After building a frame from multiple COFDM cell sequences, the cells of each COFDM symbol are then stored in the interleaver memory 100 and read from the interleaver memory 100 according to the write addresses and read addresses generated by the address generator 102. The interleaving of data cells is achieved in accordance with the writing order and reading order by generating the appropriate addresses. Operation of the address generator 102 and the memory 100 of the interleaver will be described in more detail soon with reference to Figs. 3, 4 and 5. The interleaved data cells are then combined with pilot and synchronization symbols received from the pilot signal forming and in-signaling device 36 to the OFDM symbol builder 37 to form the COFDM symbol which is fed to the OFDM modulator 38 as explained above.

The interleaver [0028] Figure 3 shows an example of a part of the symbol interleaver 33, which illustrates the symbol interleaving technique. In Fig. 3, the input data cells of the frame builder 32 are stored in the memory 100 of the interleaver. cells

- 10 data is written to the memory 100 of the interleaver according to the write address provided from the address generator 102 on channel 104, and read from the memory 100 of the interleaver according to the read address supplied from the address generator 102 on channel 106. The address generator 102 generates a write address and a read address as explained below, depending on whether the COFDM symbol is odd or even, which is identified based on the signal from channel 108 and depending on the selected mode, which is identified based on the signal given from channel 110. As explained, the mode can be one of the 1k, 2k, 4k, 8kl, 16k or 32k modes. As explained below, the write address and read address are generated differently for the odd and even symbols, as explained with reference to Fig. 4, which shows an embodiment of the memory 100 of the interleaver.

[0029] In the example shown in Fig. 4, the interleaver memory is shown to include an upper part 100 illustrating the operation of the interleaver memory in the transmitter and a lower part 340, which illustrates the operation of the memory of the deinterleaver in the receiver. Interleaver 100 and deinterleaver 340 are shown together in Fig. 4 to facilitate understanding of their operation. As shown in fig. 4, the communication between interleaver 100 and de-interleaver 340 through other devices and through the transmission channel has been simplified and mapped as segment 140 between interleaver 100 and de-interleaver 340. Operation of interleaver 100 is described in the following paragraphs.

[0030] Although Fig. 4 is an illustration for only four input data cells exemplified by four COFDM symbol subcarrier signals, it will be appreciated that the embodiment illustrated in Fig. 4 can be extended to more subcarriers, such as 756 for mode 1k, 1512 for 2k mode, 3024 for 4k mode and 6048 for 8k mode, 12096 for 16k mode and 24192 for 32k mode.

[0031] The memory input and output addressing 100 of the interleaver shown in Fig. 4 is shown for odd and even symbols. For the even COFDM symbol, data cells are taken from the input channel 77 and stored in the memory of the interleaver 124.1 according to the address sequence 120 generated for each COFDM symbol by the address generator 102. Recording addresses are applied to even symbols such that, as illustrated, interleaving is performed by shuffling the recording addresses. Therefore, for each interleaved symbol y (h (q)) = y '(q), [0032] For odd symbols, the memory of interleaver 124.2 is used. However, as shown in Figure 4 for odd symbols, the order of record 132 is in the same address sequence used to read the previous even symbol 126. This property allows, for the implementation of the odd and even symbols interleaver, to use only the memory 100 of the interleaver, provided that the read operation for the given address is performed before the write operation. Data cells written to the memory of the interleaver 124 during the odd symbols are then read in sequence 134 generated by the address generator 102 for

- 11 next even COFDM symbol, and so on. In this way, only one address is generated per symbol, with simultaneous loading and saving of odd / even COFDM symbols.

[0033] In summary, as shown in Fig. 4, once the set of addresses H (q) has been calculated for all active subcarriers, the input vector Y '= (y₀', y₁', y₂',. .y_Nmax-1') is processed to produce interleaved vector Y = (y₀, y₁, y₂, y_{N MA}x-₁) defined by:

s_H(q) = y'q for even symbols, for q = 0, ..., N_max-ly_q = y '_H(q) for odd symbols, for q = 0, ..., N_max[0034] In other words, for even OFDM symbols, input words are written in a permutated manner in memory and read back in a sequential manner, while for odd symbols they are written sequentially and read back as permutated. In the above case, the permutation H (q) is defined by the following table:

<td>Q</td><td>U 1 2</td><td> 3</td>

<td>H (q)</td><td> 1 3 0</td><td> 2</td>

Table 1: Permutation for the simple case when Nmax = 4 [0035] As shown in Fig. 4, the deinterleaver 340 operates to reverse the interlace introduced by the interleaver 100, by using the same set of addresses as generated by the equivalent address generator, but using reverse write and read addresses. As such, for even symbols, write addresses 342 are in sequential order, while read addresses 344 are provided by the address generator. Accordingly, for odd symbols, the order of writing 346 is determined based on the set of addresses generated by the address generator, while reading 348 occurs in sequential order.

Generating addresses for the 2k mode [0036] A schematic block diagram of the algorithm used to generate the permutation function H (q) is shown in Fig. 5 for the 2K mode. In Fig. 5, the linear feedback shift register is formed by twelve degrees of shift register 200 to generate an address from 0 to two thousand forty eight, and gate xor 202, which is connected to shift register degrees 200 according to the generator polynomial. Therefore, according to the contents of the shift register 200, the next bit of the shift register is provided from the gate output xor 202 by the operation xor on the contents of shift register R [0] and register stage R [3]. According to the generator polynomial, a pseudo random bit sequence is generated from the contents of shift register 200. However, in order to generate the address for the 2k mode, a permutation circuit 210 is provided which illustrates the bit order within the shift register 200 from the order R'i [n] to the order Rfn efficiently at the output of the permutation circuit 210. Ten bits from the output 210 is permutation

12 are then fed to the connecting channel 212, to which the most significant bit is added, through the channel 214, which is provided by the switching circuit 218. Therefore, the eleven-bit address is generated on the channel 212. To ensure the authenticity of the address, the address checking system 216 analyzes the generated address to determine if it exceeds the maximum number of subcarrier signals. If this is the case, then a control signal is generated, fed through the connecting channel 220 to the control unit 224. If the generated address exceeds the maximum number of carrier signals, then this address is rejected and a new address is generated again for the specific symbol.

In summary, the word (N_r - 1) bit R'i, where N_r = log2 M_maxand M_max = 2048 in 2K mode, using LFSR (linear feedback shift register).

[0038] The polynomials used to generate this sequence are as follows:

2K mode: &amp; ί C &amp; l = Φ where i changes from 0 to M_max - [0039] As soon as the word R 'is generated_and it goes through permutation to form another word (N_r - 1) bit, called R_and. R_and is derived from R '_and by bit permutations given in the table below.

<td>R 'bit positions_and [N]</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>R bit positions_and [N]</td><td> 0</td><td> 7</td><td> 5</td><td> 1</td><td> 8</td><td> 2</td><td> 6</td><td> 9</td><td> 3</td><td> 4</td>

Table: Bit permutation for 2K mode [0040] As an example, for the permutation code above it means that for 2K mode, bit number 9 with R '_and is sent at bit position number 0 R_and.

[0041] The address H (q) is then derived from R_and by the following equation:

<img file="PL2333964T3_D0002.tif" />

[0042] (and mod2) 2^{No. 1} part of the above equation is represented in Figure 5 by T218 switching block.

[0043] Next, an address check is performed on H (q) to verify that the generated address falls within the range of allowable addresses: if (H (q) &lt;N_max), where in one example N_max = 1512 in 2K mode, then the address is correct. If the address is not correct, the control unit is informed and will attempt to generate a new H (q) by increasing the i indicator.

[0044] The task of the switching block is to make sure that we do not generate an address exceeding N_max twice in a row. As a result, if an exceeding value is generated, it means that the MSB (i.e. switch bit) of address H (q) was one. Therefore, the next value generated will have MSB (most significant bit) set to zero, ensuring that the correct address is created.

[0045] The following equations summarize the overall operation and help understand the structure

- 13 loops of this algorithm:

q = 0;

for (i = 0; i &lt;M_max; i = i + 1)

<img file="PL2333964T3_D0003.tif" />

j ^ O and f (H (q) &lt;N_max) q = q + l; } [0046] As will be explained briefly, in one example of the address generator, the above-mentioned permutation code is used to generate addresses for all OFDM symbols. In another example, permutation codes may be changed between symbols, with the result that the set of permutation codes is cyclically changed for subsequent OFDM symbols. To this end, control lines 108, 110 provide an indication of whether the OFDM symbol is odd or even and the current mode is used to select the permutation code. This example mode, in which many permutation codes are cyclically changed, is particularly suitable for the example in which only the odd interleaver is used, which will be explained later. A signal indicating that another permutation code should be used is provided by control channel 111. In one example, possible permutation codes are pre-stored in permutation system 210. In another example, control unit 224 provides a new permutation code to be used for the OFDM symbol.

Receiver [0047] Figure 6 is an exemplary illustration of a receiver that can be used as part of an embodiment. As shown in Fig. 6, the COFDM signal is received by the antenna 300 and detected by tuner 302 and converted to digital by an analog-to-digital converter 304. The guard clearance removal processor removes the guard clearance from the received COFDM symbol before data is recovered from the COFDM symbol using a Fast Fourier Transform (FFT) processor 308 in combination with an estimator and channel correction 310 in cooperation with the embedded signaling assembly - decoding 311, according to known techniques . Demodulated data is recovered from the mapping device 312 and fed to the symbol deinterleaver 314 that operates to perform a demapping of the received data symbol to regenerate the output interleaved data stream.

[0048] Deinterleaver 314 is formed of a data processing device as shown in Fig. 6 with interleaver memory 540 and address generator 542. Interleaver memory is as shown in Fig. 4 and functions as explained already above to deinterlace by using the address sets generated by the address generator 542. The address generator 542 is built as shown in Fig. 7 and prepared to generate the appropriate addresses for mapping data symbols recovered from each COFDM subcarrier signals to the output data stream.

[0049] The remaining parts of the COFDM receiver shown in Fig. 6 are intended to perform decoding operations in the correction coding process 318 to correct errors and recover the source data estimate.

[0050] One of the advantages provided by the embodiment for both the receiver and the transmitter is that the symbol interleaver and the symbol deinterlacing device operating in the receivers and transmitters can be switched between 1k, 2k, 4k, 8k, 16k and 32k modes by changing generator polynomials and permutation order. Hence the address generator 542 shown in Fig. 7 includes an input signal 544 providing mode indications and an input signal 546 indicating whether there are odd / even COFDM symbols. In this way, flexible execution is ensured because the symbol interleaver and deinterleaver can be formed as shown in Figs. 3 and 7, with the address generator illustrated in Fig. 5. The address generator can therefore be adapted to different modes by changing the generator polynomials and the permutation order indicated for each mode. For example, this can be done using a program change. Alternatively, in other embodiments, the embedded signal indicating the DVB-T2 transmission mode may be detected at the receiver in the embedded signaling processing unit 311 and used to automatically configure the symbol deinterlacing device according to the detected mode. Optimal use of odd interleavers [0051] As shown in Fig. 4, two symbol interleaving processes, one for even COFDM symbols and one for odd COFDM symbols allow limiting the amount of memory used during interleaving. In the example shown in Fig. 4, the order in which the odd symbols are written is the same as the order in which the even symbols are read, therefore, while the odd symbol is being read from memory, the even symbol may be written in the location just read; on the other hand, when this even symbol is read from memory, the following odd symbol can be saved in the location just read.

[0052] The choice of the polynomial generator and permutation codes explained above was identified after simulation analysis of the relative efficiency of the interleaver. The relative performance of the interleaver was evaluated using the relative ability of the interleaver to separate successive symbols or "interleaving quality". The relative quality measure of the interleaver is determined by defining the distance D (in a number of subcarriers). Criterion C is selected to identify the number of subcarriers that are at a distance &lt;D at the output of the interleaver, which were at a distance &lt;D at the input of the interleaver, where the number of subcarriers for each distance D is then weighted relative to the relative distance. Criterion C is evaluated for both odd and even COFDM symbols. Minimizing C produces a higher quality interleaving device.

C _ £ d) / ci + £ (ci) / ci ri

- 15 where N_even(d) and N_nieparzysthese (d) are the numbers of subcarriers in the even and odd symbols at the output of the interleaver respectively, which remain within the distance d of the subcarriers.

[0053] As mentioned above, during the experimental analysis of the efficiency of the interleaving devices (using criterion C as defined above) and for the example shown in Fig. 8 (a) and Fig. 8 (b), it was found that interleaving schemes designed for interleaving devices 2k and 8k data for DVB-T and 4k symbol interleaver for DVB-H work better for odd symbols than for even symbols. Therefore, based on the results of the evaluation of the efficiency of the interleaving devices, e.g. for 16K, as illustrated in Figs. 8 (a) and 8 (b), it was found that the interleavers oddly perform better than the even interleavers. This can be seen by comparing Fig. 8 (a), which shows the results for the even symbol interleaver and Fig. 8 (b), illustrating the results for odd symbols: it can be seen that the average distance of the subcarriers at the output of the interleaver that were adjacent to the input of the interleaver is greater for the odd symbol interleaver than for the even symbol interleaver.

[0054] As will be appreciated, the amount of memory of the interleaver required to implement the symbol interleaver is dependent on the number of data symbols to be mapped to COFDM carrier symbols. Hence, the 16k symbol interleaver requires half the memory that is needed to implement the 32k symbol interleaver, and similarly, the amount of memory required to implement the 8k symbol interleaver is half the amount of memory required to implement the 16k interleaver. Therefore, a transmitter or receiver that is prepared to implement a mode symbol interleaver that sets the maximum number of data symbols that can be transferred to an OFDM symbol, then such a receiver or transmitter will contain sufficient memory to implement two odd interleaving processes for any other mode which provides half or less than half the number of subcarriers per OFDM symbol in this given maximum mode. For example, a receiver or transmitter containing 32K interleavers will have sufficient memory to accept two odd 16K interleavers, each with their own 16K memory.

[0055] Therefore, in order to apply better performance of odd interleaving processes, a symbol interleaver capable of adopting multiple modulation modes can be prepared such that only an odd interleaving process is used if it operates in a mode that contains half or less than half the number of subcarriers in maximum mode, which represents the maximum number of subcarriers per OFDM symbol. Therefore, this maximum mode sets the maximum amount of memory. For example, in a transmitter / receiver capable of operating in 32k mode, when operating in a smaller number of carriers mode (i.e. 16K, 8K, 4K or 1K), instead of using separate odd and even symbol interleaving processes, two interleaving devices may be used odd-.

[0056] Fig. 9 is an adaptation of a symbol interleaver 33, which is shown in Fig. 3 when interleaving the input data symbols with OFDM symbol subcarriers only in the odd interleaving mode. The symbol interleaver 33.1 corresponds exactly to the symbol interleaver 33 shown in Fig. 3, except that the address generator 102.1 is adapted to perform only the odd interleaving process. In the example shown in Fig. 9, the 33.1 symbol interleaver operates in a mode in which the number of data symbols that can be transferred on an OFDM symbol is less than half of the maximum number that can be transferred by an OFDM symbol in the mode with the highest number of subcarriers to the OFDM symbol. As such, the 33.1 symbol interleaver was arranged to divide the memory 100 of the interleaver. For the illustration shown in fig. 9, this interleaver memory 100 is divided into two parts 401, 402. As an illustration of 33.1 symbol interleaver operating in a mode in which data symbols are mapped to OFDM symbols using an odd interleaving process, Fig. 9 shows an expanded view of each half 401, 402 interleaver memory. The extended view is an illustration of the odd interleaving mode, as shown for the transmitter side for the four symbols A, B, C, D reproduced in Fig. 4. Therefore, as shown in Fig. 9, for successive sets of first and second data symbols, symbols data is written to the memory of the interleaver 401, 402 in sequential order and read in permutated order according to the addresses generated by the address generator 102, as previously explained. Thus, as illustrated in Fig. 9, as the odd interleaving process is performed for successive sets of first and second sets of data symbols, the memory of the interleaver must be divided into two parts. Symbols from the first set of data symbols are recorded in the first half of the memory of the interleaver 401, and symbols from the second set of data symbols are recorded in the second part of the memory of the interleaver 402. This is because the symbol interleaver is no longer able to reuse the same parts of the symbol interleaver memory, which can be assumed when working in odd and even interleaving modes.

[0057] A suitable example of a receiver interleaving device that appears in Fig. 7, but adapted to operate only with the odd interleaving process, is shown in Fig. 10. As shown in Fig. 10, the memory of the interleaver 540 is divided into two halves 410, 412, and the address generator 542 is adapted to write data symbols to the interleaver memory and read data symbols from the interleaver memory to the relevant parts of memory 410, 402 for subsequent sets of data symbols, to implement only the odd interleaving process. Therefore, according to the representation shown in Fig. 9, Fig. 10 shows a mapping of the interleaving process that is performed at the receiver and illustrated in Fig. 4 as an expanded view functioning for both the first and second halves of the interleaving memory 410, 412. In this way, the first set of data symbols is stored in the first part of the memory of the interleaver 410 in permutated order defined according to addresses generated by the 542 address generator, as

- 17 is illustrated by a data symbol write order that provides a write sequence of 1, 3, 0, 2. As illustrated, the data symbols are then read from the first part of the memory of the interleaver 410 in sequential order, thus recovering the original sequence A, B, C, D.

[0058] Accordingly, a second successive set of data symbols that are recovered from the next OFDM symbol is recorded in the second half of the memory of the interleaver 412 according to the addresses generated by the address generator 542 in permutated order and read into the output data stream in sequential order.

[0059] In one example, the addresses generated for the first set of data symbols to be recorded in the first half of the memory of the interleaver 410 can be used again to write the second subsequent set of data symbols to the memory of the interleaver 412. Accordingly, the transmitter can also reuse addresses generated for one half of the interleaver for the first set of data symbols to read the second set of data symbols that has been written to the other half of the memory in sequential order.

Odd interleaver interleaving [0060] The performance of an interleaver that uses two odd interleavers can be further improved by using a sequence of only odd interleaver only than a single odd odd interleaver only, so any bit of data input into interleaving does not always modulate the same carrier in the OFDM symbol.

[0061] The sequence of only odd interleavers can be performed by:

adding an offset to the address of the modul interleaver number of data carriers or using permutation sequences in the interleaver.

Adding an offset [0062] Adding an offset to the modulo interleaver address of the number of data carriers effectively shifts and wraps the OFDM symbol cyclically so that any bit of data input into the interleaver does not always modulate the same carrier in the OFDM symbol. Thus, the address generator may optionally include an offset generator that generates an offset in the address generated by the address generator on the output channel H (q).

[0063] The offset would change every symbol. For example, this offset can provide a cyclic sequence. Such a cyclic sequence may for example be 4 and may consist of, for example, prime numbers. For example, such a sequence could be:

0, 41, 97, 157 [0064] Furthermore, the offset can be a random sequence that can be generated by

- 18 another address generator from a similar OFDM symbol interleaver or may be generated by some other means.

Using the permutation sequence [0065] As shown in Fig. 5, control line 111 extends from the address generator control unit to the permutation system. As mentioned above, in one example, the address generator may use a different permutation code from the set of permutation codes for successively the following OFDM symbols. The use of permutation sequences in the interleaver address generator limits the likelihood that any bit of data input into the interleaver does not always modulate the same subcarrier in the OFDM symbol.

[0066] For example, it may be a cyclic sequence, such that another permutation code in the set of permutation codes in the sequence is used for successively OFDM symbols in succession and then repeated. Such a cyclic sequence may for example be two or four lengths. For example, for an 8K symbol interleaver, the sequence of two permutation codes that are cyclically changed to an OFDM symbol can be:

0751826934*

3270158496 [0067] While the sequence of four permutation codes can be:

0751826934*

3270158496 4837901567 7395210648 [0068] Switching one permutation code to another can be implemented in response to the odd / even signal change indicated on control channel 108. In response, control unit 224 changes permutation code in circuit of permutation code 210 via control line 111.

[0069] For an example of a 1k interleaver, two permutation codes can be:

3 2 1 0 5 6 7 8

2 5 0 1 4 7 8 6 while four permutation codes can have the form:

3 2 1 0 5 6 7 8 3 2 5 0 1 4 7 8 6 7 5 3 8 2 6 1 4 0 1 6 8 2 5 3 4 0 7 [0070] Other sequence combinations for 2k, 4k and 16k modes may be possible carrier or

- even the 0.5k carrier mode. For example, the following permutation codes for each of the 0.5k, 2k, 4k and 16k modes provide good symbol correlation removal and can be used cyclically to generate the address offset generated by the address generator for each of the relevant modes:

4k mode:

10 5 8 1 2 4 9 0 3 6** 6 2 7 10 8 0 3 4 1 9 5 9 5 4 2 3 10 1 0 6 8 7

I 4 10 3 9 7 2 6 5 0 8 8k mode:

51130 10 869241 7 * 8107605 2 1 394 11

II 3 69 274 105 1 0 8 108 1 75 60 II 429 3

16k mode:

4 3 2 0 11 1 5 12 10 6 7 9

9 5 3 11 1 4 0 2 12 10 8 6

11 7 5 2 3 0 1 10 8 12 9 4

12 9 0 3 10 2 4 6 7 8 11 1 [0071] For the permutation codes indicated above, the first two can be used in a cycle of two sequences, while all four can be used in a cycle of four sequences. In addition, the following are several sequences of four permutation codes that are cyclically changed to provide offset in the address generator for good correlation removal in interleaved symbols (some are common to the above):

0.5k mode:

7 4 6 1 2 0 5

2 5 7 3 0 1 6

3 6 0 4 1 2 7

1 0 5 2 7 4 3

2k mode:

0751826934*

4832901567

8390215746

704 8369 1 5 2

4k mode:

10 5 8 1 2 4 9 0 3 6**

2 7 10 8 0 3 4 1 9 5

- 20 10 3 4 1 2 7 0 6 8 5 9

8 9 5 10 4 6 3 2 1 7

8k mode:

11 3 0 10 8 6 9 2 4 1 7*

8 5 4 2 9 1 0 6 7 3 11

6 9 8 4 7 2 1 0 10 5 3

3 11 7 9 1 5 6 4 0 2 10 * these are permutations in the DVB-T standard ** these are permutations in the DVB-H standard [0072] Examples of address generators and corresponding interleaving devices for 2k, 4k and 8k modes are disclosed in European Patent Application No. 04251667.4. The address generator for the 0.5k mode is disclosed in our concurrently filed British patent application number 0722553.5.

[0073] As will be appreciated, the transmitter and receiver shown in Figures 1 and 6, respectively, are shown as illustrations only and are not intended to be limiting. For example, it will be appreciated that the position of the symbol interleaver and the deinterleaver in relation to, for example, the interleaver and the bit mapping device can be changed. As you will realize, the effect of the interleaver and deinterleaver does not change due to their relative position, although the interleaver can interleave I / Q symbols instead of v-bit vectors. Appropriate changes can be made at the receiver. Accordingly, the interleaver and deinterleaver can operate on different types of data, and can be positioned differently with respect to the items described in the embodiments.

[0074] According to one embodiment of the receiver, there is provided a data processing device for mapping symbols received from a predetermined number of orthogonal frequency division multiplex (OFDM) symbol subcarrier signals to the output symbol stream.

[0075] As explained above, the permutation codes and polynomial generator of the interleaver, which have been described in relation to the implementation of a particular mode, can equally well be applied to other modes, by changing the predetermined maximum allowable address according to the number of subcarriers for that mode .

[0076] As mentioned above, embodiments of the invention find use in DVB standards such as DVB-T, DVB-T2 and DVB-H. For example, embodiments of the invention may be used in a transmitter or receiver operating in accordance with the DVB-H standard, in handheld portable terminals. Portable terminals can be built into mobile phones (be they of the second, third or higher generation) or, for example, electronic notebooks (PDAs) or tablets. Such mobile terminals may be able to receive DVB-H or DVB-T / T2 compatible signals indoors or in traffic, for example in cars or trains, even at high speeds.

- 21 Mobile terminals can for example be powered by batteries, mains electricity, low voltage direct current (DC) source or powered by car battery. Services that can be provided by DVB-H may include voice services, communications, internet browsing, radio, still and / or moving video, television services, interactive services, video on demand or almost on demand video, and options. These services may work in conjunction with each other. In other embodiments, the invention finds use with the DVB-T2 standard defined in accordance with ETSI EN 302 755. In other embodiments, the invention finds use in the cable broadcasting standard known as DVB-C2. However, it may be realized that the invention is not limited to use with DVB and may be extended to other broadcasting or receiving standards, both stationary and movable.

Anna Stenzel

Patent Attorney