Interleaver for mapping symbols on the carriers of an OFDM system

ES 2 310 883 T3

DESCRIPTION

Interleaver for mapping symbols on the carriers of an OFDM system.

Field of the invention

The present invention relates to a data processing apparatus that functions to correlate input symbols to signals carrying an Orthogonal Frequency Division Multiplexed (OFDM) symbol.

The present invention also relates to a data processing apparatus that functions to de-correlate symbols received from a predetermined number of signals carrying an OFDM symbol, into a stream of output symbols.

Background of the invention

The digital terrestrial video transmission standard (DVB-T = Digital Video Broadcasting-Terrestrial) (reference [1]) uses orthogonal frequency division multiplexing (OFDM) to communicate, to receivers, data representing video images and sound, by means of a radio communication transmission signal. It is known that there are two modes for the DVB-T standard which are known as the 2k mode and the 8k mode. The 2k mode provides 2,048 subcarriers, while the 8k mode provides 8,192 subcarriers.

To improve the integrity of the data communicated by the 2k mode or by the 8k mode, a symbol interleaver is provided to interleave input data symbols when these symbols are mapped onto the carrier signals of an OFDM symbol. Said symbol interleaver comprises an interleaver memory in combination with an address generator. The address generator generates an address for each of the input symbols, each address indicating one of the carrier signals of the OFDM symbol, into which the data symbol is to be mapped. An arrangement for the 2k mode and for the 8k mode has been described in the DVB-T standard, which generates the addresses for correlation. The address generator is known to comprise a feedback linear shift register which functions to generate a pseudo-random sequence of bits, and a permutation circuit. The permutation circuit permutes the order of the contents of the linear shift register with feedback to generate an address. The address provides an indication of one of the OFDM carriers to carry an input data symbol stored in the interleaver memory, in order to map the input symbols to the OFDM symbol carrier signals.

Like 2k mode and 8k mode, it has also been proposed to provide a 4k mode. The 4k mode has been used in the Japanese standard for digital television transmission, which is the Integrated Service Digital Broadcasting (ISDB) system.

Compendium of the invention

According to one aspect of the present invention, a transmitter is provided for transmitting data using orthogonal frequency division multiplexed (OFDM) symbols, the transmitter includes a data processing apparatus that functions to correlate input symbols to be communicated in a predetermined number of carrier signals, of an orthogonal frequency division multiplexed (OFDM) symbol according to a plurality of different operating modes, each of which provides a different number of OFDM carriers. The data processing apparatus comprises an interleaver memory which functions to input into it the predetermined number of data symbols in order to correlate them to the OFDM carrier signals, and to read the data symbols for the OFDM carriers in order to effect the correlation. Reading is done in a different order than input, the order being determined by a set of addresses, with the effect that the data symbols are interleaved in the carrier signals. The set of addresses is determined by an address generator, an address being generated for each of the input symbols, in order to indicate one of the carrier signals to which the data symbol is to be mapped.

The address generator comprises a feedback linear shift register that includes a predetermined number of register stages, and that operates to generate a pseudo-random sequence of bits in accordance with a generator polynomial, and a permutation circuit and a control unit. The permutation circuit functions to receive the contents of the shift register stages and to permute the bits present in the register stages according to a permutation order, in order to form an address of one of the OFDM carriers. The control unit works in combination with an address check circuit, to regenerate an address when a generated address exceeds the maximum number of carriers. The transmitter is characterized in that the transmitter can be switched between the 2k, 4k and 8k operating modes, and that for the 4k mode the predetermined number of OFDM carrier signals is substantially four thousand, and the feedback linear shift register has eleven stages Register with a generator polynomial for the feedback linear shift register, from R'¡ [10] = R ',, [0] ® R',, [2]. The permutation order forms an eleven-bit address R, [n] for the i-order data symbol of the bit present in the nth register stage R ', | n |, according to the following table:

ES 2 310 883 T3

<td>R'i [0] for n =</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>R¡ [n] for n =</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

Although, within the DVB-T standard, it is known to provide 2k mode and 8k mode, there are advantages to providing 4k mode. While the 8k mode provides an arrangement to establish a single frequency network with sufficient guard periods to accommodate greater propagation delays between DVB transmitters, the 2k mode is known to provide an advantage in mobile applications. This is because the 2k symbol period is only a quarter of the 8k symbol period, allowing the channel estimate (based on scattered pilots embedded in each symbol) to be updated more frequently, so that the receiver more accurately track channel timing drift due to Doppler and other effects. Therefore, the 2k mode is advantageous for mobile applications. However, the 2k mode requires a multi-frequency network thereby complicating the arrangement of transmitters to provide a transmission system. A 4k mode provides the advantage of reasonably good reception for mobile users, even at high conduction speeds that thereby cause higher Doppler shifts, without the need for a costly carrier-to-carrier interference cancellation scheme. A practical realization of a reasonably inexpensive transmission network can also be created. However, to provide 4k mode, a symbol interleaver must be provided to map the input data symbols into the OFDM symbol carrier signals.

Embodiments of the present invention can provide a data processing apparatus that functions as a symbol interleaver to correlate symbols of data to be communicated into an OFDM symbol having substantially four thousand carrier signals. In one embodiment, the number of carrier signals is three thousand twenty-four. Therefore, a 4k mode can be provided, for example for a DVB standard, such as DVBT or DVB-H. The DVB-H standard (Digital Video Broadcasting-Handheld = portable digital video transmission) is related to the DVB-T standard. The DVB-H standard was formerly known as DVB-X. DVB-H signals are suitable for reception by portable devices such as pocket mobile terminals.

The correlation of data symbols to be transmitted in signals carrying an OFDM symbol, where the number of carrier signals is substantially four thousand, represents a substantial technical problem that requires analysis and simulation tests to establish an appropriate generator polynomial for the linear shift register with feedback and the order of permutation. This is because the correlation requires that the symbols be interleaved in the carrier signals with the effect that successive symbols of the input data stream are separated in frequency as much as possible, in order to optimize the performance of the control schemes. coding error correction.

Error correction coding schemes, such as Reed-Solomon coding and convolutional coding, perform best when noise and degradation of symbol values ​​resulting from communication are uncorrelated. Some radio channels, such as those used for the DVB-T standard, may suffer from correlated fading in both time and frequency domains. Therefore, by separating the encoded symbols into different signals carrying the OFDM symbol as much as possible, the performance of error correction coding schemes can be improved.

Through performance simulation analysis, it has been discovered that the generator polynomial for the feedback linear shift register, in combination with the order permutation circuit noted above, provides good performance in the presence of typical noise and fading conditions. channel. Also, by providing an arrangement that can create address generation, for both 2k mode and 8k mode, as well as 4k mode, changing the middle taps of the generator polynomial for the linear shift register with feedback and the order of permutation. , an inexpensive practical implementation of the symbol interleaver is obtained for the 4k mode. Additionally, a transmitter and receiver can be switched between 2k mode, 4k mode, and 8k mode, by changing the generator polynomial and the permutation orders. This can be done by programming (or by the transmission parameter signaling channel (TPS = Transmission Parameter Signaling) incorporated in the receiver), whereby a flexible practical implementation is provided.

Various aspects and features of the present invention are defined in the appended claims. Other aspects of the present invention include a receiver that functions to de-map symbols received from a predetermined number of carrier signals of an orthogonal frequency division multiplexed (OFDM) symbol, into a stream of output symbols.

Brief description of the drawings

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which like parts are provided with corresponding reference numerals, and in which:

Figure 1 is a schematic block diagram of a Coded OFDM transmitter, which can be used, for example, with the DVB-T standard;

Figure 2 is a schematic block diagram of an inner symbol interleaver and a correlation processor shown in Figure 1;

Figure 3 is a schematic block diagram of the symbol interleaver shown in Figure 2;

Figure 4 is a schematic block diagram of an interleaver memory shown in Figure 3, and the corresponding symbol deinterleaver of the receiver;

Figure 5 is a schematic block diagram of an address generator shown in Figure 3 for the 2k mode;

Figure 6 is a schematic block diagram of an address generator as shown in Figure 3, in the 8k mode;

Figure 7 is a schematic block diagram of an address generator shown in Figure 3, in 4k mode;

Figure 8 is a schematic block diagram of a Coded OFDM receiver, which can be used, for example, with the DVB-T standard; and Figure 9 is a schematic block diagram of an inner symbol deinterleaver shown in Figure 8.

Description of preferred embodiments

The existing DVB-T standard, based on OFDM, is composed of a 2k mode and an 8k mode, which means that the bandwidth used to transmit the signal is divided into 2,048 subcarriers (2k mode) or 8,192 subcarriers (2k mode). 8k). The 2k mode presents some interesting features regarding mobility. Indeed, the short symbol time in this mode allows good Doppler performance in mobile environments. On the other hand, the 8k mode provides network planners with the possibility of building a sparse, and therefore inexpensive, single-frequency network (SFN = Single Frequency Network). Research carried out on the subject showed that the introduction of a 4k mode would be a good compromise between these two modes. This would provide reasonably good reception for mobile users, even at high driving speeds, without the need for a complicated and costly Inter Carrier Interference Cancellation (ICI) scheme. This would also help keep the cost of the network at a reasonable level. This document describes a new symbol interleaver for this 4k mode.

Figure 1 provides an exemplary block diagram of a Coded OFDM transmitter (COFDM) that can be used, for example, to transmit video images and audio signals in accordance with the DVB-T standard. In Figure 1, a program source generates data to be transmitted by the COFDM transmitter. A video encoder 2, an audio encoder 4 and a data encoder 6 generate video, audio and other data to be transmitted, which are supplied to a program multiplexer 8. An output from the program multiplexer 8 is supplied to a transport multiplexer 10 which forms a multiplexed transport stream with other information necessary to communicate the video, audio and other data. The transport multiplexer 10 provides a transport stream on a connecting channel 12, to a divider 14. The divider divides the transport stream into different branches A and B, which provide different forward error correction and interleaving coding. For the sake of simplicity, only branch A.

As shown in Figure 1, a COFDM transmitter 20 receives the data transport stream in an energy dispersal and adaptation multiplexer block 22. The energy dispersion and adaptation multiplexer block 22 randomizes the transport stream data and supplies the appropriate data to an outer encoder 24 which performs a first outer encoding of the transport data. An outer interleaver 26 is arranged to interleave the encoded data symbols which, for the example of the DVB-T standard, is the Reed-Solomon (RS) code, so that the outer interleaver interleaves RS symbols. An inner encoder 28 is arranged to convolutionally encode the outer interleaver data using a convolutional encoder, the encoded data being supplied to an inner interleaver 30. The inner interleaver 30 can also receive encoded data from the second encoder branch B.

An output of the inner interleaver is a set of data symbols that are then mapped into constellation points of a modulation scheme. For the DVB-T example shown, the modulation scheme is QPSK (Quadrature Phase Shift Keying = Quadrature Phase Shift Keying) (DVB-T can have quadrature amplitude modulation (QAM = Quadrature Amplitude Modulation) 16QAM 4-bit / carrier or 64QAM 6-bit / carrier, as well as QPSK). Each data symbol in inner interleaver 30 is then mapped to one of the COFDM carrier signals by a mapping processor 32. The COFDM symbol is then generated by a frame adaptation processor 34, which inputs pilot and timing signals supplied from a signal former 36. Then, an OFDM generator 38 forms the OFDM symbol in the time domain, which is supplied to a guard insert processor 40 to generate an interval of

ES 2 310 883 T3 stores between symbols and then a digital-to-analog converter 42 and finally an RF amplifier within an RF front end 44 for eventual transmission by the COFDM transmitter from an antenna 46.

To create a new 4k mode, several elements have to be defined, but the main one is the 4k symbol interleaver, which is part of the inner interleaver shown in Figure 1.

The inner interleaver itself is made up of a bit interleaver and a symbol interleaver, as shown in Figure 2.

As explained above, the present invention provides a device for providing near optimal correlation of input data symbols on OFDM carrier signals. According to the exemplary technique, the inner interleaver is arranged to effect optimal mapping of input data symbols on COFDM carrier signals. The inner interleaver 30 and the correlation processor 32 are shown in greater detail in Figure 2. In Figure 2, the inner interleaver 30 comprises a demultiplexer processor 60 that receives convolutionally coded bits from an input channel 62. The demultiplexer then splits the bits into two input bit streams that are supplied to interleavers 68 and 70 of bits via patch channels 64 and 66. The bit interleavers interleaves the bits which are then formed into two connecting channels 72.1, 72.2 to connect the bits from each of the bit interleavers 68 and 70 to a symbol interleaver 76. The symbol interleaver forms the input symbols of the connecting channels 72.1, 72.2 into symbols to be mapped onto the COFDM carrier signals. For the exemplary technique shown in Figure 2, interleaved symbols from symbol interleaver 76 are mapped into constellation points of a QPSK carrier signal for each of the COFDM symbol signals.

The existing DVB-T specification already defines a symbol interleaver for 2k and 8k modes. The purpose of the symbol interleaver is to map v-bit words (depending on the chosen modulation scheme) on the 1,512 (2k mode) or 6,048 (8k mode) active carriers per OFDM symbol. The symbol interleaver acts on blocks of 1,512 (2k mode) or 6,048 (8k mode) symbols of data. Exemplary embodiments of the present invention utilize the symbol interleaver 76 to provide an optimized mapping of the input data symbols supplied from the connection channels 72.1, 72.2, on the COFDM carrier signals. An example of the symbol interleaver 76 for mapping the input data symbols on the COFDM carrier signals is shown in Figure 3.

Interleaver RAM

In Figure 3, the input data symbols of the connecting channel 72 are supplied to an interleaver memory 100. The interleaver memory 100 maps the input data symbols into the COFDM carrier signals according to correlation addresses provided by the generator. 102 addresses. An exemplary practical embodiment of interleaver memory 100 is shown in Figure 4.

Figure 4 comprises an upper portion 100 illustrating the interleaver memory operation in the transmitter, and a lower portion 340 illustrating the deinterleaver memory operation in the receiver. Interleaver 100 and deinterleaver 340 are shown together in Figure 4 to facilitate understanding of their operation. As shown in Figure 4, a representation of the communication between interleaver 100 and deinterleaver 340, through other services and through a transmission channel, has been simplified and represented as a section 140 between interleaver 100 and the deinterleaver 340. The operation of interleaver 100 is described in the following paragraphs:

Although Figure 4 provides an illustration of only four input data symbols in an example of four signals carrying a COFDM symbol, it will be appreciated that the technique illustrated in Figure 4 can be extended to a larger number of carriers, such as 1,512 for 2k mode, 3,024 for 4k mode and 6,048 for 8k mode.

The input and output address assignment of interleaver memory 100 presented in Figure 4 is shown for odd and even symbols. For an even COFDM symbol, data symbols are taken from input channel 72 and written to interleaver RAM 124.1 according to an address sequence 120 generated for each COFDM symbol by address generator 102. The write addresses are applied for the even symbol so that, as illustrated, the interleaving is effected by the redistribution of the write addresses. Hence, for each interleaved symbol y (h (q)) = y '(q).

For odd symbols the same interleaver RAM 124.2 is used. However, as shown in Figure 4, for the odd symbol, the writing order 132 is in the same address sequence as that used to read the previous even symbols 126. This feature allows practical implementations of odd and even symbol interleavers to use only one RAM memory, as long as the read operation for a given address is performed before the write operation. Data symbols written to interleaver RAM 124 during odd symbols are then read in a sequence 134 generated by address generator 102 for the next even COFDM symbol, and so on.

ES 2 310 883 T3

In summary, as represented in Figure 4, once the set of addresses H (q) has been calculated for all active carriers, the input vector Y '= (y₀', Y_i', Y₂', Y_Nmax-1') to produce the interleaved vector Y = (y₀, Y_i, Y₂,... Y_Nmax-i) defined by:

yH (q) = y '_what for even symbols, for q = 0, ..., N_max-1 and_what = y '_{H (q)} for odd symbols, for q = 0, ..., N_max-1

In other words, for even OFDM symbols, the input words are written in a permuted manner into a memory, and reread in a sequential manner, while for odd symbols, they are sequentially written and reread permuted. In the previous case, the permutation H (q) is defined by the following table:

TABLE 1

Permutation for simple case where Nmax = 4

<td>what</td><td> 12 3 4</td>

<td>H (q)</td><td> 13 0 2</td>

As shown in Figure 4, deinterleaver 340 functions to reverse the interleaver applied by interleaver 100, applying the same set of addresses as generated by an equivalent address generator, but applying the read and write addresses in reverse. Thus, for even symbols, the write addresses 342 are in sequential order, while the read addresses 344 are provided by the address generator. Correspondingly, for odd symbols, the writing order 346 is determined by the set of addresses generated by the address generator, while the reading 348 is done in sequential order.

Address Generation

Figure 5 represents a schematic block diagram of the algorithm used to generate the permutation function H (q) for the 2k mode, and in Figure 6 for the 8k mode.

Figure 5 shows a practical embodiment of the address generator 102.1 for the 2k mode. In Figure 5, a feedback linear shift register is made up of ten register stages 200.1 and an Exclusive-OR (XOR) gate 202.1, which is connected to the shift register stages 200.1 according to a generator polynomial. Therefore, according to the content of the shift register 200.1, a next bit of the shift register is provided from the output of the Exclusive-OR gate 202.1, performing a logical Exclusive-OR operation between the contents of the shift register R [ 0] and the registration stage R [3]. According to the generator polynomial, a pseudo-random sequence of bits is generated from the contents of the shift register 200.1. However, to generate an address for the illustrated 2k mode, a permutation circuit 210.1 is provided that effectively permutes the order of the bits within shift register 200.1, from an order R '[n] to an order R, | n | at the output of the permutation circuit 210.1. Then, ten bits of the output of the permutation circuit 210.1 are supplied in a connection channel 212.1, to which a more significant bit is added, through a channel 214.1, which is provided by a switching circuit 218.1. Therefore, on channel 212.1 an eleven-bit address is generated. However, to ensure the authenticity of an address, an address check circuit 216.1 analyzes the generated address to determine if it exceeds the maximum number of bearer signals. If so, a control signal is generated and supplied to a control unit 224.1 through a connection channel 220.1. If the generated address exceeds the maximum number of bearer signals, this address is rejected and a new address is generated for the particular symbol.

An address generator 102.2 for the 8k mode is shown in Figure 6. The parts of the address generator for the 8k mode, shown in Figure 6, correspond to those shown for the 2k mode and therefore, to avoid repetition, only the essential differences between Figure 6 and Figure 5 will be described. Essentially, the difference between Figure 6 and Figure 5 is that the feedback linear shift register 200.2 has twelve shift register stages to generate an address between 0 and 8.191. Again , the shift register is formed by the logical Exclusive-OR operation between the shift register stages selected according to the generator polynomial. The address is then formed by permuting the order of the bits within shift register 200.2, which is determined according to a predetermined order. Again, the generator polynomial and the order of permutation are provided for the 8k mode, which differ from the 2k mode.

ES 2 310 883 T3

In summary, for the 2k and 8k modes a word R 'is defined_i of (N_r - 1) bits, with N_r = log₂ M_max, where M_max = 2,048 in 2k mode, and M_max = 8,192 in 8k mode, using an LFSR (Linear Feedback Shift Register = linear feedback shift register).

The polynomials used to generate this sequence are the following:

2k mode: R'i [9] = R '_i-1[0] ® R '^ [3]

8k mode: R '_i[11] = R '_i-1[0] ® R '_i-1[1] ® R '_i-1[4] © R '_i-1[6] where i varies from 0 to M_max -1.

Once an R 'word has been generated_i, it goes through a permutation to produce another word of (N_r - 1) bits, called R_i. R_i is derived from R '_i using the bit permutations given in Tables 1 and 2.

TABLE 2

Bit permutation for 2k mode

<td>Bit positions of R'¡</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions of R,</td><td> 0</td><td> 7</td><td> 5</td><td> 1</td><td> 8</td><td> 2</td><td> 6</td><td> 9</td><td> 3</td><td> 4</td>

TABLE 3

Bit permutation for 8k mode

<td>Bit positions of R'¡</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions of R,</td><td> 5</td><td> 11</td><td> 3</td><td> 0</td><td> 10</td><td> 8</td><td> 6</td><td> 9</td><td> 2</td><td> 4</td><td> 1</td><td> 7</td>

For example, this means that for 2k mode, bit number 9 of R '_i is sent in bit position number 0 of R_i.

Then the direction H (q) is derived from R_i using the following equation:

N_r-2

H (q) = (i mode2) .2^Nr^-1 + £ R_i(j) .2^j.

j = 0

The part (i mode2). 2^{Nr 1} of the above equation is represented in Figure 5 and Figure 6 by the T218 switching block.

An address check is then performed on H (q) to verify that the generated address is within the acceptable range of addresses: if (H (q) &lt;N_max), where_max = 1,512 in 2k mode and 6,048 in 8k mode, so the address is valid. If the address is not valid, the control unit is informed and it will try to generate a new H (q) by incrementing the index i.

The role of the switch block is to ensure that an address exceeding N is not generated_max twice in a row. Indeed, if an excessive value had been generated, this means that the most significant bit (that is, the switch bit) of the address H (q) was one. Thus, the next generated value will have a most significant bit set to zero, which ensures the production of a valid address.

ES 2 310 883 T3

The following equations summarize the overall behavior and help to understand the loop structure of this algorithm:

q = 0 for (i = 0; i &lt;N_max; i = i + 1)

N_r-2 {H (q) = (imod2). 2^Nr-1 + £ Ri (j) .2^j;

j = 0 if (H (q) &lt;Nmax) q = q + 1;}

Symbol interleaver for 4k mode

Figure 7 shows an address generator 102.3 for 4k mode, according to the present technique. Again, the address generator of Figure 7 corresponds to the address generator shown in Figures 5 and 6 and therefore only differences with these Figures will be discussed and explained. As shown in Figure 7, the feedback linear shift register 200.3 has eleven shift register stages. Again, an Exclusive-OR gate 202.3 is arranged to generate the pseudo-random sequence of bits. The permutation of the contents of the shift register to form the address of an input data symbol, which is to be mapped into one of the COFDM carrier signals, is provided by the permutation circuit 210.3.

The symbol interleaver acts on blocks of N_max = 3,024 data symbols. (M_max = 4.096).

The polynomial used to generate the sequence R 'is:

R '_i[10] = R '_i-₁[0] ® R '_i-₁[2]

From vector R '_i a vector R is derived_i using the bit permutation given in Table 4:

TABLE 4

Bit permutation for 4k mode

<td>Bit positions of R'¡</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Bit positions of R,</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

The input of the interleaver is defined as the vector Y '= (y₀', Y₁', Y₂',..., Y_Nmax-1').

The interleaved vector Y = (y₀, Y₁, Y₂,..., Y_Nmax-1) is defined by:

Y_{H (q)} = y '_what for even symbols, for q = 0, ..., N_max-1 and_what = y '_{H (q)} for odd symbols, for q = 0, ..., N_max-1

Receiver

Figure 8 provides an exemplary illustration of a receiver that can be used with the present technique. As shown in Figure 8, a COFDM signal is received by an antenna 300 and detected by a tuner 302, and converted to digital form by an analog-to-digital converter 304. A guard interval suppression processor 306 suppresses the guard interval of a received COFDM symbol, before the data is retrieved from the COFDM symbol, using a Fast Fourier Transform (FFT = Fast Fourier Transform) processor 308 in combination with a channel estimation and correction circuit 310, in cooperation with a transmission parameter signaling decoder unit 311 (TPS = Transmission Parameter Signaling), according to known techniques. The demodulated data is retrieved from a de-correlator 312 and supplied to an inner symbol de-interleaver 314, which functions to reverse-correlate the received data symbol in order to regenerate an output data stream with the de-interleaved data.

The symbol deinterleaver 314 is formed by a data processing apparatus as shown in Figure 9, with an interleaver memory 340 and an address generator 342. The interleaver memory is as shown in Figure 4, and works as previously explained to effect deinterleaving using address sets generated by the address generator 342. The address generator 342 is formed as shown in Figure 7, and is arranged to generate corresponding addresses in order to correlate the recovered data symbols from each COFDM subcarrier signal, into an output data stream.

ES 2 310 883 T3

The remaining parts of the COFDM receiver shown in Figure 8 are arranged to perform error correction decoding and deinterleaving in order to correct errors and retrieve an estimate of the data from the source. In particular, an inner code deinterleaver 316 and an inner decoder 318 function to effect decoding of the inner convolutional code input by the inner interleaver 30 and inner encoder 28 of the transmitter shown in Figure 1. An outer deinterleaver 320 and an outer encoder 322 function to decode the Reed-Solomon code to retrieve an estimate of the data from source 1, after the random conversion has been recovered by a random conversion retriever 324. .

An advantage provided by the present technique, for both the receiver and the transmitter, is that a symbol interleaver and a symbol de-interleaver, operating in the receivers and transmitters, can be switched between 2k, 8k and 4k mode. changing the generating polynomials and the order of permutation. Therefore, a flexible practical embodiment is provided in that the symbol interleaver and deinterleaver may be formed as shown in Figures 4 and 9, with an address generator as illustrated in any of Figures 5, 6 or 7. Therefore, the address generator can be adapted to the different modes by changing the generator polynomials and the permutation orders indicated for each of the 2k, 4k and 8k modes. For example, this can be done using a scheduling change. Alternatively, in other embodiments, a built-in TPS signal, indicating the mode of the DVB-T transmission (digital terrestrial video transmission), can be detected at the receiver, in the TPS channel processing unit 311, and used to configure symbol deinterleaver automatically based on detected mode.

Various modifications may be made to the embodiments described above without departing from the scope of the present invention. In particular, the exemplary representation of the generator polynomial and the order of permutation, which have been used to represent aspects of the invention, are not intended to be limiting, and extend to equivalent forms of the generator polynomial and the order of permutation.

As will be appreciated, the transmitter and receiver shown in Figures 1 and 8, respectively, are provided as illustrations only, and are not intended to be limiting. For example, it will be appreciated that the position of the symbol interleaver and the symbol de-interleaver can be changed with respect to, for example, the bit interleaver and the mapper and de-mapper. As will be seen, the effect of the interleaver and deinterleaver is unchanged by their relative position, although the interleaver may be interleaving I / Q (in-phase / quadrature) symbols instead of v-bit vectors. A corresponding change can be made at the receiver. Accordingly, the interleaver and deinterleaver may be working on different types of data, and may be located differently than the position described in the exemplary embodiments.

As mentioned above, embodiments of the present invention find application with DVB standards, such as DVB-T and DVB-H. For example, embodiments of the present invention can be used in a transmitter or receiver operating in accordance with the DVB-H standard in portable mobile terminals. Mobile terminals can be integrated with mobile phones (either second, third or higher generation) or personal digital assistants, or whiteboard personal computers, for example. Such mobile terminals may be capable of receiving DVB-H or DVB-T compatible signals inside buildings or on the move, for example in cars or trains, even at high speeds. Mobile terminals can be powered, for example, by batteries, electricity grids or low-voltage DC power sources, or powered by a car battery. The services that can be provided by the DVB-H standard may include voice, messaging, Internet search, radio, still and / or moving video images, television services, interactive services, video or immediate video on demand. The services could work in combination with each other. It will be noted that the present invention is not limited to application with the DVB standard, and can be extended to other standards for transmission or reception, both fixed and mobile.

References

[1] EN 300 744, “Framing structure, channel coding and modulation for digital terrestrial television”, ETSI (European Telecommunication Standard Institute).