Interleaver for mapping symbols on the carriers of an OFDM system

[0001] The present invention relates to a data processing device adapted to map inserted symbols to symbol carrier signals in an Orthogonal Frequency Division Multiplexed (OFDM) system.

[0002] The present invention also relates to a data processing device adapted to inverse map the symbols obtained from a predetermined number of OFDM symbol carrier signals to the output symbol stream.

Background Art [0003] Digital Terrestrial Digital Broadcasting (DVB-T) standard EN 300 744, "Framing structure, channel coding and modulation for digital terrestrial television" ("Frame structure, channel coding and modulation for digital television terrestrial ") ETSL uses orthogonal frequency division multiplexing (OFDM) to transfer data representing video and audio to receivers via a broadcast radio signal. For the DVB-T standard, there are two modes that are known as 2k mode and 8k mode. The 2k mode provides for 2048 subcarriers, while the 8k mode provides 8192 subcarriers.

[0004] When mapping to OFDM symbol carrier signals of these symbols transmitted in both 2k and 8k modes, a symbol interleaver is used to improve data integrity to interleave the input data symbols. Such a symbol interleaver contains an interleaver memory connected to an address generator. The address generator generates an address for each of the symbols entered, with each address pointing to one of the OFDM symbol carrier signals to which the data symbol is to be mapped. The structure for generating addresses for mapping for 2k and 8k modes is described in the DVB-T standard. An address generator containing a linear feedback shift register that is adapted to generate a pseudo-random bit sequence and a permutation system is known. The permutation system permutes the order of the content of the linear feedback shift register to generate the address. The address is an indication of one of the OFDM carriers for carrying the symbol of the entered data stored in the interleaver memory to map input symbols to the OFDM symbol carrier signals.

[0005] In addition to the 2k mode and the 8k mode, it has also been proposed to use the 4k mode. The 4k mode was used in the Japanese digital television standard, which is an integrated digital television system (ISDB Integrated Service Digital Broadcasting system).

SUMMARY OF THE INVENTION [0006] According to one aspect of the present invention, a transmitter is proposed for transmitting data using symbols in an Orthogonal Frequency Division Multiplexed system, which transmitter includes a data processing device adapted to map input symbols to a certain number Carrier signals of an Orthogonal Frequency Division Multiplexing (OFDM) symbol. Data processing device

V2O75PI_OO / L 2 EP 1 662 739 includes an interleaver memory adapted to read a predetermined number of symbols for mapping onto OFDM carriers, and to read data symbols for OFDM carriers when performing mapping. Reading takes place in a different order than loading, with the order being determined by the set of addresses, which means that the data symbols on the carrier signals are interleaved. The address set is determined by the address generator, the address being generated for each of the input symbols, indicating one of the carrier signals to which the data symbol is to be mapped. [0007] The address generator includes a linear feedback shift register that includes a predetermined number of register stages and is adapted to generate a pseudo-random bit sequence according to the generating polynomial, and a permutation system and control unit. The permutation system is functionally adapted to receive the contents of register stages and perform permutations with shaping the address of one of the OFDM carriers. The control unit is able, together with the address checking system, to regenerate the address when the generated address exceeds the maximum number of carriers. The transmitter is characterized in that the predetermined number of OFDM carrier signals is approximately four thousand, and the linear feedback shift register has eleven degrees with a polynomial generating for the linear feedback shift register, in the form R; [10] = Rh [0] ® Rh [2] · The permutation order is the 11-bit address R, {n] for the i-th data symbol from the bit in the n-th stage R'i [n] of the register, according to the table :

<td>R] [n]</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>Ri [n] for n =</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

[0008] Although it is known to use the 2k mode and the 8k mode based on the DVB-T standard, it is preferred to use the 4k mode. However, the 8k mode is the setting for setting up a single frequency network with sufficient protection intervals taking into account the higher propagation delays between DVB transmitters, it is known that the 2k mode is advantageous for mobile applications. This is because the 2k symbol period is only a quarter of the 8k symbol period, which allows channel estimation (based on distributed pilots embedded in each symbol) with more frequent updating, enabling the receiver to track time changes more accurately as a result of Doppler and other effects. The 2k mode is therefore advantageous for mobile applications. However, the 2k mode requires a multi-frequency network, which complicates the structure of the transmitters when setting up the transmission system. 4k mode has the advantage of moderately good reception for mobile users, even at high speeds, resulting in a larger Doppler shift, without the need for an expensive system to reduce interference between carriers. It is also possible to effectively implement a broadcasting network at acceptable costs. However, in order to implement the 4k mode, it is necessary to use a symbol interleaver to map input data symbols to OFDM symbol carrier signals.

[0009] Embodiments of the present invention provide a data processing device operably capable of acting as a symbol interleaver, for mapping the data symbols to be transmitted to an OFDM symbol having approximately four thousand carrier signals. In one embodiment, the number of carrier signals is three thousand twenty four. The 4k mode as such can be adapted, for example, to the DVB standard as

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DVB-T or DVB-H. The DVB-H (Digital Video Broadcasting - Handheld Digital Handheld Television) standard has a reference to DVB-T. The DVB-H standard was formerly known as DVB-X. DVB-H signals are adapted to be picked up by hand-held devices, e.g. portable mobile terminals.

[0010] Mapping of data symbols to be transmitted to carrier signals of OFDM symbols, with the number of carrier signals being essentially four thousand, is a serious technical problem requiring simulation analysis and testing to determine the appropriate generator polynomial for linear feedback register and permutation order. This is because mapping requires symbols to be interleaved on the carrier signals, as a result of which subsequent symbols from the input data stream would be frequency-separated by the highest possible value in order to ensure optimal performance of the error correction coding methods.

[0011] Error correction coding methods, such as Reed-Solomon coding and convolutional coding, for example, work better when noise and symbol degradation resulting from transmission are uncorrelated. Some radio channels, such as those used in DVB-T, may experience the detrimental effects of correlated loss in both time and frequency domains. Just separating the encoded symbols into different OFDM symbol signals as efficiently as possible can give an increase in the efficiency of the error correction coding methods.

[0012] By means of a simulation performance analysis, it has been found that the generating polynomial for a linear feedback shift register in combination with the permutation circuit order mentioned above provides good efficiency in the presence of typical channel noise and decay conditions. In addition, by using a structure that can provide implementation of address generation for both 2k mode, 8k mode and 4k mode by changing polynomial branches for linear feedback shift register and permutation order, an economically efficient implementation of the symbol interleaver is obtained for the mode 4k. In addition, the transmitter and receiver can be switched between 2k mode, 4k mode and 8k mode by changing the generating polynomial and permutation orders. This can be done programmatically (or via the transmission parameter signaling (TPS) channel built into the receiver), as a result of which flexibility of implementation is ensured.

[0013] Various aspects and characteristics of the invention are defined in the appended claims. Other aspects of the invention include a receiver capable of inverse mapping symbols derived from a designated number of symbol carrier signals with orthogonal frequency division multiplication (OFDM), onto a stream of output symbols.

List of drawing figures [0014] Variations of the invention are described below, by way of example only, with reference to the accompanying drawing figures, in which similar parts are designated by identical reference numbers, wherein:

Fig. 1 shows a block diagram of an OFDM coded modulation transmitter that can be used, for example, in the DVB-T standard;

Fig. 2 is a block diagram of the internal symbol interleaver and the mapping processor of Fig. 1;

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Fig. 3 is a block diagram of the interleaver of Fig. 2;

Fig. 4 is a block diagram of the interleaver memory of Fig. 3 and the corresponding symbol de-interleaver at the receiver;

Fig. 5 is a block diagram of the address generator shown in Fig. 3 for the 2k mode;

Fig. 6 is a block diagram of the address generator shown in Fig. 3 in the 8k mode;

Fig. 7 is a block diagram of the generator of Fig. 3 in the 4k mode;

Fig. 8 shows a block diagram of an OFDM coding receiver that can be used, for example, in the DVB-T standard; and

Fig. 9 is a block diagram of the inner character interleaver of Fig. 8.

Description of Preferred Embodiments [0015] The existing OFDM-based DVB-T standard includes 2K and 8K mode, which means that the bandwidth used for signal transmission is divided into either 2048 (2K mode) or 8192 (8K mode) subcarriers. 2K mode has some interesting features about mobility. In fact, the low symbol duration in this mode ensures good Doppler parameters in mobile environments. On the other hand, the 8K mode gives network designers the opportunity to build SFN (Single Frequency NetWork) networks with low density, and therefore cheap. Research in this topic has shown that the introduction of 4K mode would be a good compromise between the two modes. It would provide fairly good reception for mobile users even at high speeds, without the need for a complicated and expensive ICI (inter-carrier) interference reduction method. It would also help maintain the cost of the network at an acceptable level. This document describes the new symbol interleaver for this 4K mode.

[0016] Fig. 1 includes an exemplary block diagram of an OFDM code transmitter that can be used, for example, to transmit video images and audio signals in accordance with the DVB-T standard. In Fig. 1, the program source generates data to be transmitted by the COFDM transmitter. The video encoder 2 and audio encoder 4 and data encoder 6 generate video, audio and other broadcast data that is fed to the program multiplexer 8. The output signal of the program multiplexer 8 is fed to the transport multiplexer 10, which, with other information needed for the transmission of video, audio and other data, forms the multiplexed transport stream. The transport multiplexer 10 feeds the transport stream through a connection channel 12 to the splitter 14. The splitter divides the transport stream into different branches A and B, which provide different coding with direct error correction and interlacing. For simplicity, only branch A is described below.

[0017] As shown in Fig. 1, the COFDM transmitter 20 receives a transport data stream at block 22 of a multiplexer with adaptation and energy dissipation. The multiplexer 22 with energy dissipation and adaptation randomizes the transport stream data and feeds the relevant data to the external encoder 24, which performs the first external coding of the transport data. The external interleaver 26 is used to interleave coded data symbols, which in the DVB-T example are Reed-Solomon code (RS), so that the external interleaver interleaves the symbols

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RS. Internal encoder 28 is adapted to encode data from an external interleaver using a convolutional encoder, wherein the encoded data is fed to the internal interleaver 30. The internal interleaver 30 can receive the encoded data from the second encoding branch B.

[0018] The output of the internal interleaver is a set of data symbols that are then mapped to the constellation points of the modulation. In the DVB-T example shown, the modulation method is QPSK (DVB-T can have 4 bits on a 16QAM carrier or 6 bits on a 64OAM carrier as well as QPSK). Each data symbol from the internal interleaver 30 is then mapped to one of the COFDM carrier signals by the mapping processor 32. Then through the frame adaptation processor 34, which introduces pilot and synchronization signals fed from the signal forming system 36. The OFDM generator 38 then forms the time domain OFDM symbol that is fed to the protection input processor 40, to generate the protection period between the symbols, then to the DAC 42, and finally to the RF amplifier. in the RF head 44 for final transmission by the COFDM transmitter from the 46 antenna.

[0019] To create a new 4K mode, several elements need to be specified, but the main one is the 4K symbol interleaver, which is part of the internal interleaver shown in Fig. 1.

[0020] The internal interleaver itself consists of a bit interleaver and a symbol interleaver, as shown in Fig. 2.

[0021] As explained above, the invention provides the ability to implement quasi-optimal mapping of input data symbols to OFDM carrier signals. According to an exemplary method, an internal interleaver is used to obtain the optimal mapping of input data symbols to COFDM carrier signals. Internal interleaver 30 and mapping processor 32 are shown in more detail in Fig. 2. In Fig. 2 internal interleaver 30 includes a demultiplexing processor 60 that receives the convolutional encoded bits from input channel 62. The demultiplexer divides the bits into two input bit streams that are fed through connection channels 64 and 66 to bit interleavers 68 and 70. The bit interleavers 68 and 70 interleave the bits, which are then formed in two connection channels 72.1, 72.2 to feed the input bits from each of the bit interleavers 68 and 70 to the character interleaver 76. In the example method shown in Fig. 2, the interleaved symbols from character interleaver 76 is mapped to constellation points of the QPSK carrier signal for each of the signals in the COFDM symbol.

[0022] The existing DVB-T standard already includes requirements for character interleavers for 2K and 8K modes. The task of the character interleaver is to map v-bit words (where v depends on the modulation method chosen) to 1512 (in 2K mode) or 6048 (in 8K mode) of active carriers to the OFDM symbol. The character interleaver works on blocks of 1512 (in 2K mode) or 6048 (in 8K mode) data symbols. Embodiments of the invention utilize character interleavers 76 to provide optimized mapping of input data symbols fed from connection channels 72.1, 72.2. on COFDM carrier signals. An example of the character interleaver 76 for performing the mapping of input data symbols to COFDM carrier signals is shown in Fig. 3.

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RAM of the interleaver

[0023] In Fig. 3, the input data symbols from the attachment channel 72 are fed to the memory 100 of the interleaver. The interleaver memory 100 maps the input data symbols onto COFDM carrier signals according to the mapping addresses provided by the address generator 102. An exemplary implementation of the interleaver memory 100 is shown in Fig. 4.

[0024] Fig. 4 includes an upper portion 100 showing the operation of the interleaver memory at the transmitter and a lower portion 340 that shows the operation of the de-interleaving memory at the receiver. Interleaver 100 and de-interleaver 340 are shown together in Fig. 4 to facilitate understanding of their operation. As can be seen in fig. 4, the representation of the transmission between interleaver 100 and de-interleaver 340 via other devices and via a transmission channel is simplified and shown as section 140 between interleaver 100 and de-interleaver 340. The operation of the interleaver 100 is described in the following paragraphs:

Although Fig. 4 only shows four COFDM symbol carrier signals, it is obvious that the method of Fig. 4 can be extended to more carriers, e.g. 1512 in the 3k mode, 3024 in the 4k mode, and 6048 in the case of 8k mode.

[0025] Input and output addressing of the interleaver memory 100 shown in Fig. 4 is shown for odd and even symbols. For the even COFDM symbol, data symbols are taken from input channel 72 and written to RAM 124.1 of the interleaver according to the address sequence 120 generated for each COFDM symbol by the address generator 102. The write addresses are applied to the even symbol so that, as shown, interleaving is accomplished by shuffling the entry addresses. Thus, for each interleaved symbol y (h (q)) = y '(q).

[0026] For odd symbols, the same interleaver RAM 124.2 is used. However, as shown in Fig. 4 for the odd symbol, the write order 132 in the same address sequence serves to read the previous even symbol 126. This option allows the implementation of odd and even symbols interleaving using only one RAM, assuming that the read operation for a given address is performed before the write operation. The data symbols stored in the interleaver RAM 124 during the odd symbols duration are then read in some sequence 134 generated by the address generator 102 for the next even COFDM, and so on.

In summary, as shown in Fig. 4, after calculating the set of addresses H (q) for all active carriers, the input vector Y '= (yo', yl, yi ... yNmax-i ') is processed from creating an interlaced vector Y = (y₀, y_1t s₂... y_nmax-i) determined by:

yH (q) = y'q for even symbols, for q = 0, ... N_max-1 yq = y'H (qs for odd symbols, for q = 0, ... N_max[0028] In other words, for even OFDM symbols, input words are written with permutation to memory and read back sequentially, while odd symbols are written sequentially and read with permutation. In the above case, permutation is given by the following table:

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Table 1: permutation for a simple case in which Nmax = 4

<td>Q</td><td> 1</td><td> 2</td><td> 3</td><td> 4</td>

<td>H (q)</td><td> 1</td><td> 3</td><td> 0</td><td> 2</td>

[0029] As shown in Fig. 4, the de-interleaver 340 operates to reverse the interlace introduced by the interleaver 100, by using the same set of addresses as the one generated by the corresponding address generator, but with the reverse application of read and write addresses. Write addresses 342 for even symbols appear in sequential order, while read addresses 344 are provided by the address generator. Accordingly, in the case of odd symbols, write order 346 is determined from the set of addresses generated by the address generator, while read order 348 is sequential.

Address generation [0030] A block diagram of the algorithm used to generate the permutation function H (q) is shown in Figure 5 for the 2K mode and in Figure 6 for the 8K mode.

[0031] The implementation of the address generator 102.1 for the 2k mode is shown in Figure 5. In Figure 5, the linear feedback shift register is formed by ten register stages 200.1 and the gate XOR 202.1, which is connected to the shift register stages 200.1, according to generating polynomial. Thus, according to the contents of shift register 200.1, the next bit of shift register is given from the gate output XOR 202.1 when performing XOR operations on the contents of shift register R [0] and stage R [3] of the register. According to the generation polynomial, the pseudo-random bit sequence is generated from the content of the shift register 200.1. However, to generate the address for the presented 2k mode, a 210.1 permutation circuit is used, which effectively permutes the bit order in the shift register 200.1 from the order Rj / nj to the order R, [n] at the output of the permutation circuit 210.1. The ten bits from the output of the permutation circuit 210.1 are fed to the connection channel 212.1, to which the most significant bit transmitted via the 218.1 trigger system is added via channel 214.1. An eleven-bit address is therefore generated on channel 212.1. However, to make sure the address is authentic, address control system 216.1 analyzes the generated address, checking if it exceeds the maximum number of carrier signals. If so, a control signal is generated via connection channel 220.1 to control unit 224.1. If the generated address exceeds the maximum number of carrier signals, this address is rejected and a new address is generated for this particular symbol.

[0032] Fig. 6 shows an address generator 102.2 for 8k mode. The parts of the address generator for the 8k mode shown in Fig. 6 correspond to the parts shown for the 2k mode, so in order to avoid repetition only the essential differences between Figs. 6 and 5 are described below. In principle, the difference between Figs. 6 and 5 is in that the feedback linear shift register 200.2 has twelve shift register stages to generate an address between 0 and 8191. Also in this case, the shift register is shaped by subjecting the XOR operation to the shift register stages selected according to the generating polynomial. The address is shaped by the permutation of the order of the bits in shift register 200.2, which are determined according to a predetermined order. Also in this case, the generator polynomial and permutation order are used for the 8k mode, which are different than in the 2k mode.

V2O75PI_OO / L 8 EP 1 662 739 In summary, the word (N is defined for 2k and 8k modes_r-1) -bit R ', wherein N_r= log₂M_max, Where's m_{It has}x = 2048 in 2K and M mode_max= 8192 in 8K mode, using LFSR (Linear Feedback Shift Register).

[0034] The polynomials used to generate this sequence are as follows:

Mode2K: 7?, '[9j = R [0] Φ Ąf, [3]

8K mode: 7?, '[11] = R' ^ [0] Φ R [1 jΦ R ', __t [4] Φ R'__} [6] where i varies from 0 to M_max-1.

[0035] After generating one word R'i, it undergoes permutation to form another 10 (bit-1) -bit word designated R_b R, is derived from Rj by bit permutations, given in Tables 1 and 2.

Table 2: Permission for bits for 2K mode

<td>R'i bit positions</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>R bit positions</td><td> 0</td><td> 7</td><td> 5</td><td> 1</td><td> 8</td><td> 2</td><td> 6</td><td> 9</td><td> 3</td><td> 4</td>

Table 3: Bit permutation for 8K mode

<td>R 'bit positions_f</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>R bit positions</td><td> 5</td><td> 11</td><td> 3</td><td> 0</td><td> 10</td><td> 8</td><td> 6</td><td> 9</td><td> 2</td><td> 4</td><td> 1</td><td> 7</td>

[0036] For example, this means that for the 2K mode bit number 9 R 'is transmitted at the bit position number 0 R ,.

[0037] The address H (q) is then derived from R, by the following equation:

N_r-2

H (q) = (and mod2) · 2^Nr-¹ + · 2Ϊ j = 0 [0038] Part (and mod2) -2N^r"1 in the above equation is represented in Fig. 5 and in Fig. 6 by the T218 flip-flop.

[0039] At H (q), an address check is then performed to confirm that the generated address is within the range of allowable addresses: if (H (q) &lt;Nmax), where N_max= 1512 in 2K mode and 6048 in 8K mode, this address is valid. If the address is not valid, the control unit is informed and it tries to generate a new address H (q) by incrementally increasing the index i.

[0040] The task of the flip-flop block is to make sure twice that in a row that we do not generate an address exceeding the value of N_max. As a result, if a value exceeding it was generated, it means that the MSB of the address H (q) (i.e. flip bit) was set to one. Yes

V2075PI_00 / L 9 EP 1 662 739 so the next value generated will have the MSB bit set to zero, which will ensure the generation of a valid address.

[0041] The following equations summarize the overall operation and help in understanding the loop structure of this algorithm:

q = O;

for (i = 0; i &lt;M_max; i = i + 1) {H (q) = (i mod2) · 2^Nr-1 + XR, (j) · 2j;

j = 0 and f (H (q) &lt;N_max) q = q + 1;}

Character interleaver for the 4k mode [0042] Fig. 7 shows an address generator 102.3 for the 4k mode according to the present method. Also in this case, the address generator of Fig. 7 corresponds to the address generator shown in Figs. 5 and 6, so that only the differences between these figures are also described and explained below. As shown in Fig. 7, the linear feedback shift register 200.3 has eleven degrees of shift register. Also here, the XOR 202.3 gate is used to generate a pseudo-random bit sequence. The permutation of the contents of the shift register to create the address of the input data symbol for mapping onto one of the COFDM carrier signals is carried out in permutation system 210.3.

[0043] The character interleaver works on blocks after N_max= 3024 data symbols. (M_max= 4096). [0044] The polynomial used to generate the R 'sequence is as follows:

Ri [10] = RU [0] Φ Rh [2] [0045] The vector R, is derived from the vector R ', by the permutation given in Table 4:

Table 4: Bit permutation for 4K mode

<td>R'i bit positions</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td>R bit positions</td><td> 7</td><td> 10</td><td> 5</td><td> 8</td><td> 1</td><td> 2</td><td> 4</td><td> 9</td><td> 0</td><td> 3</td><td> 6</td>

[0046] The input data of the interlace system is defined as the vector Y '= (yo', yl, y and yNmax-i ') · [0047] Interlaced vector, Y = (y₀, y-ι, y₂... yNmax-i). is determined by:

yH (q) = y'q for even symbols, for q = 0, ..., N_max-1 yq⁼y'H (q) for odd symbols, for q = 0, ..., N_max-1

Receiver [0048] Fig. 8 is an example diagram of a receiver that can be used in the present method. As shown in Fig. 8, the COFDM signal is received from the antenna 300, detected in the tuner 302 and converted to digital form by an analog-to-digital converter 304.

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The guard period removal processor 306 removes the guard period from the received COFDM symbol, before recovering data from the COFDM symbol using a Fast Fourier Transform (FFT) processor 308 in conjunction with a channel estimation and correction system 310, in cooperation with the Decoding Transmission Signaling Unit 311 ), according to known methods. Demodulated data is obtained from the inverse mapping system 312 and fed to an internal character interleaver eliminator 314 that operates by inverse mapping the received data symbol at the regeneration of the non-interlaced output data stream.

[0049] The character interleaver 314 is a data processing system as shown in Fig. 9, with the interleaver RAM memory and address generator 342. The interleaver memory is as shown in Fig. 4, and works as explained above, performing interleaving elimination using the address sets generated by the address generator 342. The address generator 342 is shaped as shown in Fig. 7, and is structurally adapted to generate the appropriate addresses when mapping data symbols recovered from the signals of each COFDM subcarrier to the output data stream.

[0050] The remaining parts of the COFDM receiver shown in Fig. 8 serve to perform decoding and to eliminate error correction interleaving to correct errors and determine the source data. In particular, the internal convolutional code introduced by the internal interleaver 30 and the internal coder 28 of the transmitter shown in Fig. 1 decode the internal code deinterleaver 316 and internal decoder 318. The external de-interleaver 320 and the external decoder 322 operate by performing Reed-Solomon code decoding with data determination from source 1, after decryption by the 324 decoder.

[0051] One of the advantages that this method provides for both the receiver and the transmitter is that the character interleaver and the character interleaver, working in the receivers and transmitters can be switched between 2k, 4k and 8k modes by changing polynomials generating and permutation orders shown for each of the 2k, 4k and 8k modes. This can be achieved, for example, using a software change. Optionally, in other embodiments, a built-in TPS signal indicating the DVB-T transmission mode used for automatically configuring the de-interlacing circuitry according to the detected mode may be detected at the receiver in the TPS channel processing unit 311.

[0052] Without departing from the scope of the present invention, various modifications can be made. In particular, the exemplary representations of the generator polynomial and permutation order that were used to represent aspects of the invention are not intended to be limiting and extend to forms equivalent to the generator polynomial and permutation order.

[0053] Of course, the transmitter and receiver, shown in Figs. 1 and 8, respectively, are provided for illustration only and not for limitation. For example, it is clear that the position of the character interleaver and the deinterlacing system relative to, for example, the bit interleaver and the mapping and inverse mapping systems can change. Of course, the operation of the interleaver and the interleaver elimination system does not change depending on their relative position, although the interleaver can perform I / Q symbol interleaving instead of v-bit vectors. The corresponding change can be made at the receiver. Accordingly, the interleaver and deinterlacing system can be operated with other types of data, and can be placed in positions other than those described in the exemplary embodiments.

[0054] As already mentioned, embodiments of the invention find use in DVB standards, for example DVB-T and DVB-H. V2O75PI_OO / L ii EP 1 662 739. Embodiments of the invention can be used in a transmitter or receiver operating in accordance with the DVB-H standard in portable mobile terminals. Mobile terminals can be integrated, for example, with mobile phones (second, third or newer generation) or palmtops or tablet PCs. Such mobile terminals may be able to receive DVB-H or DVB-T compatible signals indoors or in traffic, for example in cars or trains, even at high speeds. For example, mobile terminals can be powered by a battery, a mains power supply or a low-voltage direct current source, or by a car battery. Services provided by DVB-H may include voice services, messaging, internet browsing, radio, still and / or moving video images, television services, interactive services, full / simplified video on demand service. Services may work in combination with one another. Of course, the invention is not limited to use with DVB and can be extended to other standards for broadcasting or reception, both landline and mobile.