Interleaver for mapping symbols on the carriers of an OFDM system

A transmitter for transmitting data using multiplexing by orthogonal frequency division, OFDM, including the transmitter apparatus data processing operable to map input symbols to be communicated in a predetermined number of carrier signals of a multiplexed symbol division number an interleaver memory operable to read it: orthogonal frequency OFDM (orthogonal frequency Division Multiplexed) according to a plurality of different operating modes, each of which provides a different number of OFDM carriers, the processing apparatus data comprising the default data symbols to be mapped in the OFDM carrier signals, and to read the data symbols for the OFDM carriers to effect the mapping, carrying out the reading in a different introduction order, number being determined It orders through a set of addresses, with the effect that the data symbols are interleaved on the carrier signals; an address generator is operable to generate the set of addresses, an address being generated for each of the input symbols, in order to indicate one of the carrier signals onto which has to correlate the data symbol, comprising address generator: a log linear feedback shift includes a predetermined number of register stages, and operable to generate a pseudo random bit sequence according to a generator polynomial; a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form a direction of one of the OFDM carriers; and a control unit that operates in combination with an address check circuit to regenerate an address when a generated address exceeds the predetermined number of carriers; characterized in that the transmitter can be switched between operating modes 2k, 4k and 8k and 4k because for the default mode OFDM carrier signals is three thousand and twenty-four recording linear feedback shift register has eleven stages of a generator polynomial for recording linear feedback shift of R''i [10] = R''i-1 [0] Phi-1 R''i [2], and the permutation order forms an address R i [n] for eleven bit data symbol i'th bit present in the n-th register stage, R''i [n], according to the table: (See table)