Down-conversion of an electromagnetic signal with feedback control

0001This application is a continuation of pending U.S. patent application Ser. No. 12/976,477, titled, “Down-Conversion of an Electromagnetic Signal with Feedback Control,” filed on Dec. 22, 2010, which is a continuation of U.S. Pat. No. 7,894,789, titled, “Down-Conversion of an Electromagnetic Signal with Feedback Control,” filed on Apr. 7, 2009, which is a continuation of U.S. Pat. No. 7,539,474, filed Feb. 17, 2005, which is a continuation of U.S. Pat. No. 6,879,817, filed Mar. 14, 2000, which claims the benefit of U.S. Provisional Application, No. 60/171,502, filed Dec. 22, 1999, U.S. Provisional Application No. 60/177,705, filed Jan. 24, 2000, U.S. Provisional Application No. 60/129,839, filed Apr. 16, 1999, U.S. Provisional Application No. 60/158,047, filed Oct. 7, 1999, U.S. Provisional Application No. 60/171,349, filed Dec. 21, 1999, U.S. Provisional Application No. 60/177,702, filed Jan. 24, 2000, U.S. Provisional Application No. 60/180,667, filed Feb. 7, 2000, and U.S. Provisional Application No. 60/171,496, filed Dec. 22, 1999, all of which are incorporated by reference herein in their entireties.

CROSS-REFERENCE TO OTHER APPLICATIONS

0002The following applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0003">“Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998.</li><li id="ul0001-0002" num="0004">“Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998.</li><li id="ul0001-0003" num="0005">“Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998.</li><li id="ul0001-0004" num="0006">“Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998.</li><li id="ul0001-0005" num="0007">“Applications of Universal Frequency Translation,” Ser. No. 09/261,129, filed Mar. 3, 1999.</li><li id="ul0001-0006" num="0008">“Method and System for Down-Converting Electromagnetic Signals Having Optimized Switch Structures,” Ser. No. 09/293,095, filed Apr. 16, 1999.</li><li id="ul0001-0007" num="0009">“Method and System for Down-Converting Electromagnetic Signals Including Resonant Structures for Enhanced Energy Transfer,” Ser. No. 09/293,342, filed Apr. 16, 1999.</li><li id="ul0001-0008" num="0010">“Method and System for Frequency Up-Conversion with a Variety of Transmitter Configurations,” Ser. No. 09/293,580, filed Apr. 16, 1999.</li><li id="ul0001-0009" num="0011">“Integrated Frequency Translation and Selectivity with a Variety of Filter Embodiments,” Ser. No. 09/293,283, filed Apr. 16, 1999.</li><li id="ul0001-0010" num="0012">“Matched Filter Characterization and Implementation of Universal Frequency Translation Method and Apparatus,” Ser. No. (to be assigned), Atty. Docket No. 1744.0920000, filed Mar. 9, 2000.</li></ul>

BACKGROUND OF THE INVENTION

00131. Field of the Invention

0014The present invention relates to down-conversion and up-conversion of electromagnetic (EM) signals. More particularly, the present invention relates to reducing or eliminating DC offset voltages and re-radiation that occurs during down-conversion of EM signals to intermediate frequency or baseband signals.

00152. Related Art

0016Electromagnetic (EM) information signals (baseband signals) include, but are not limited to, video baseband signals, voice baseband signals, computer baseband signals, etc. Baseband signals include analog baseband signals and digital baseband signals.

0017It is often beneficial to propagate EM signals at higher frequencies. This is generally true regardless of whether the propagation medium is wire, optic fiber, space, air, liquid, etc. To enhance efficiency and practicality, such as improved ability to radiate and added ability for multiple channels of baseband signals, up-conversion to a higher frequency is utilized. Conventional up-conversion processes modulate higher frequency carrier signals with baseband signals. Modulation refers to a variety of techniques for impressing information from the baseband signals onto the higher frequency carrier signals. The resultant signals are referred to herein as modulated carrier signals. For example, the amplitude of an AM carrier signal varies in relation to changes in the baseband signal, the frequency of an FM carrier signal varies in relation to changes in the baseband signal, and the phase of a PM carrier signal varies in relation to changes in the baseband signal.

0018In order to process the information that was in the baseband signal, the information must be extracted, or demodulated, from the modulated carrier signal. However, because conventional signal processing technology is limited in operational speed, conventional signal processing technology cannot easily demodulate a baseband signal from higher frequency modulated carrier signal directly. Instead, higher frequency modulated carrier signals must be down-converted to an intermediate frequency (IF), from where a conventional demodulator can demodulate the baseband signal.

0019Conventional down-converters include electrical components whose properties are frequency dependent. As a result, conventional down-converters are designed around specific frequencies or frequency ranges and do not work well outside their designed frequency range.

0020Conventional down-converters generate unwanted image signals and thus must include filters for filtering the unwanted image signals. However, such filters reduce the power level of the modulated carrier signals. As a result, conventional down-converters include power amplifiers, which require external energy sources.

0021When a received modulated carrier signal is relatively weak, as in, for example, a radio receiver, conventional down-converters include additional power amplifiers, which require additional external energy.

SUMMARY OF THE INVENTION

0022Briefly stated, the present invention is directed to methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof. The present invention is further directed to reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal. The present invention is still further directed to improving receiver dynamic range.

0023Generally, the invention operates by receiving an EM signal. The invention also receives an aliasing signal having an aliasing rate. The invention aliases the EM signal according to the aliasing signal to down-convert the EM signal.

0024In an embodiment, the invention down-converts the EM signal to an intermediate frequency (IF) signal.

0025In another embodiment, the invention down-converts the EM signal to a demodulated baseband information signal.

0026In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

0027In another embodiment, the EM signal is an I/Q modulated signal, which is down-converted to an in-phase information signal and a quadrature-phase information signal.

0028The invention is applicable to any type of EM signal, including but not limited to, modulated carrier signals (the invention is applicable to any modulation scheme or combination thereof) and unmodulated carrier signals.

0029Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is generally indicated by the left-most digit(s) in the corresponding reference number.

BRIEF DESCRIPTION OF THE FIGURES

0030The invention shall be described with reference to the accompanying figures, wherein:

0031<figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.

0032<figref idref="DRAWINGS">FIG. 1B</figref> is a more detailed diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.

0033<figref idref="DRAWINGS">FIG. 1C</figref> illustrates a UFT module used in a universal frequency down-conversion (UFD) module according to an embodiment of the invention.

0034<figref idref="DRAWINGS">FIG. 1D</figref> illustrates a UFT module used in a universal frequency up-conversion (UFU) module according to an embodiment of the invention.

0035<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a universal frequency translation (UFT) module according to an alternative embodiment of the invention.

0036<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.

0037<figref idref="DRAWINGS">FIG. 4</figref> is a more detailed diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.

0038<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram of a universal frequency up-conversion (UFU) module according to an alternative embodiment of the invention.

0039<figref idref="DRAWINGS">FIGS. 6A-6I</figref> illustrate example waveforms used to describe the operation of the UFU module.

0040<figref idref="DRAWINGS">FIG. 7</figref> illustrates a UFT module used in a receiver according to an embodiment of the invention.

0041<figref idref="DRAWINGS">FIG. 8</figref> illustrates a UFT module used in a transmitter according to an embodiment of the invention.

0042<figref idref="DRAWINGS">FIG. 9</figref> illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using a UFT module of the invention.

0043<figref idref="DRAWINGS">FIG. 10</figref> illustrates a transceiver according to an embodiment of the invention.

0044<figref idref="DRAWINGS">FIG. 11</figref> illustrates a transceiver according to an alternative embodiment of the invention.

0045<figref idref="DRAWINGS">FIG. 12</figref> illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using enhanced signal reception (ESR) components of the invention.

0046<figref idref="DRAWINGS">FIG. 13</figref> illustrates a UFT module used in a unified down-conversion and filtering (UDF) module according to an embodiment of the invention.

0047<figref idref="DRAWINGS">FIG. 14</figref> illustrates an example receiver implemented using a UDF module according to an embodiment of the invention.

0048<figref idref="DRAWINGS">FIGS. 15A-15F</figref> illustrate example applications of the UDF module according to embodiments of the invention.

0049<figref idref="DRAWINGS">FIG. 16</figref> illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using enhanced signal reception (ESR) components of the invention, wherein the receiver may be further implemented using one or more UFD modules of the invention.

0050<figref idref="DRAWINGS">FIG. 17</figref> illustrates a unified down-converting and filtering (UDF) module according to an embodiment of the invention.

0051<figref idref="DRAWINGS">FIG. 18</figref> is a table of example values at nodes in the UDF module of <figref idref="DRAWINGS">FIG. 17</figref>.

0052<figref idref="DRAWINGS">FIGS. 19A and 19B</figref> together provide a detailed diagram of an example UDF module according to an embodiment of the invention.

0053<figref idref="DRAWINGS">FIGS. 20A and 20G</figref> are example aliasing modules according to embodiments of the invention.

0054<figref idref="DRAWINGS">FIGS. 20B-20F</figref> are example waveforms used to describe the operation of the aliasing modules of <figref idref="DRAWINGS">FIGS. 20A and 20G</figref>.

0055<figref idref="DRAWINGS">FIG. 21</figref> illustrates an enhanced signal reception system according to an embodiment of the invention.

0056<figref idref="DRAWINGS">FIGS. 22A-22F</figref> are example waveforms used to describe the system of <figref idref="DRAWINGS">FIG. 21</figref>.

0057<figref idref="DRAWINGS">FIG. 23A</figref> illustrates an example transmitter in an enhanced signal reception system according to an embodiment of the invention.

0058<figref idref="DRAWINGS">FIGS. 23B and 23C</figref> are example waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention.

0059<figref idref="DRAWINGS">FIG. 23D</figref> illustrates another example transmitter in an enhanced signal reception system according to an embodiment of the invention.

0060<figref idref="DRAWINGS">FIGS. 23E and 23F</figref> are example waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention.

0061<figref idref="DRAWINGS">FIG. 24A</figref> illustrates an example receiver in an enhanced signal reception system according to an embodiment of the invention.

0062<figref idref="DRAWINGS">FIGS. 24B-24J</figref> are example waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention.

0063<figref idref="DRAWINGS">FIG. 25</figref> illustrates an exemplary I/Q modulation receiver, according to an embodiment of the present invention.

0064<figref idref="DRAWINGS">FIG. 26</figref> illustrates a I/Q modulation control signal generator, according to an embodiment of the present invention.

0065<figref idref="DRAWINGS">FIG. 27</figref> illustrates example waveforms related to the I/Q modulation control signal generator of <figref idref="DRAWINGS">FIG. 26</figref>.

0066<figref idref="DRAWINGS">FIG. 28</figref> illustrates example control signal waveforms overlaid upon an input RF signal.

0067<figref idref="DRAWINGS">FIG. 29</figref> illustrates a I/Q modulation receiver circuit diagram, according to an embodiment of the present invention.

0068<figref idref="DRAWINGS">FIGS. 30-40</figref> illustrate example waveforms related to the receiver of <figref idref="DRAWINGS">FIG. 29</figref>.

0069<figref idref="DRAWINGS">FIG. 41</figref> illustrates a single channel receiver, according to an embodiment of the present invention.

0070<figref idref="DRAWINGS">FIG. 42</figref> illustrates an alternative I/Q modulation receiver, according to an embodiment of the present invention.

0071<figref idref="DRAWINGS">FIG. 43</figref> illustrates an I/Q modulation transmitter, according to an embodiment of the present invention.

0072<figref idref="DRAWINGS">FIG. 44A</figref> illustrates an example antenna that transmits re-radiation.

0073<figref idref="DRAWINGS">FIGS. 44B-D</figref> illustrates example signals and frequency spectrums related to re-radiation effects.

0074<figref idref="DRAWINGS">FIGS. 45A-D</figref> illustrate example implementations of a switch module according to embodiments of the invention.

0075<figref idref="DRAWINGS">FIGS. 46A-D</figref> illustrate example aperture generators.

0076<figref idref="DRAWINGS">FIG. 46E</figref> illustrates an oscillator according to an embodiment of the present invention.

0077<figref idref="DRAWINGS">FIG. 47</figref> illustrates an energy transfer system with an optional energy transfer signal module according to an embodiment of the invention.

0078<figref idref="DRAWINGS">FIG. 48</figref> illustrates an aliasing module with input and output impedance match according to an embodiment of the invention.

0079<figref idref="DRAWINGS">FIG. 49A</figref> illustrates an example pulse generator.

0080<figref idref="DRAWINGS">FIGS. 49B</figref> and C illustrate example waveforms related to the pulse generator of <figref idref="DRAWINGS">FIG. 49A</figref>.

0081<figref idref="DRAWINGS">FIG. 50</figref> illustrates an example energy transfer module with a switch module and a reactive storage module according to an embodiment of the invention.

0082<figref idref="DRAWINGS">FIGS. 51A-B</figref> illustrate example energy transfer systems according to embodiments of the invention.

0083<figref idref="DRAWINGS">FIG. 52A</figref> illustrates an example energy transfer signal module according to an embodiment of the present invention.

0084<figref idref="DRAWINGS">FIG. 52B</figref> illustrates a flowchart of state machine operation according to an embodiment of the present invention.

0085<figref idref="DRAWINGS">FIG. 52C</figref> is an example energy transfer signal module.

0086<figref idref="DRAWINGS">FIG. 53</figref> is a schematic diagram of a circuit to down-convert a 915 MHZ signal to a 5 MHZ signal using a 101.1 MHZ clock according to an embodiment of the present invention.

0087<figref idref="DRAWINGS">FIG. 54</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 53</figref> according to embodiments of the present invention.

0088<figref idref="DRAWINGS">FIG. 55</figref> is a schematic diagram of a circuit to down-convert a 915 MHZ signal to a 5 MHZ signal using a 101 MHZ clock according to an embodiment of the present invention.

0089<figref idref="DRAWINGS">FIG. 56</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 55</figref> according to embodiments of the present invention.

0090<figref idref="DRAWINGS">FIG. 57</figref> is a schematic diagram of a circuit to down-convert a 915 MHZ signal to a 5 MHZ signal using a 101.1 MHZ clock according to an embodiment of the present invention.

0091<figref idref="DRAWINGS">FIG. 58</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 57</figref> according to an embodiment of the present invention.

0092<figref idref="DRAWINGS">FIG. 59</figref> shows a schematic of the circuit in <figref idref="DRAWINGS">FIG. 53</figref> connected to an FSK source that alternates between 913 and 917 MHZ at a baud rate of 500 Kbaud according to an embodiment of the present invention.

0093<figref idref="DRAWINGS">FIG. 60A</figref> illustrates an example energy transfer system according to an embodiment of the invention.

0094<figref idref="DRAWINGS">FIGS. 60B-C</figref> illustrate example timing diagrams for the example system of <figref idref="DRAWINGS">FIG. 60A</figref>.

0095<figref idref="DRAWINGS">FIG. 61</figref> illustrates an example bypass network according to an embodiment of the invention.

0096<figref idref="DRAWINGS">FIG. 62</figref> illustrates an example bypass network according to an embodiment of the invention.

0097<figref idref="DRAWINGS">FIG. 63</figref> illustrates an example embodiment of the invention.

0098<figref idref="DRAWINGS">FIG. 64A</figref> illustrates an example real time aperture control circuit according to an embodiment of the invention.

0099<figref idref="DRAWINGS">FIG. 64B</figref> illustrates a timing diagram of an example clock signal for real time aperture control, according to an embodiment of the invention.

0100<figref idref="DRAWINGS">FIG. 64C</figref> illustrates a timing diagram of an example optional enable signal for real time aperture control, according to an embodiment of the invention.

0101<figref idref="DRAWINGS">FIG. 64D</figref> illustrates a timing diagram of an inverted clock signal for real time aperture control, according to an embodiment of the invention.

0102<figref idref="DRAWINGS">FIG. 64E</figref> illustrates a timing diagram of an example delayed clock signal for real time aperture control, according to an embodiment of the invention.

0103<figref idref="DRAWINGS">FIG. 64F</figref> illustrates a timing diagram of an example energy transfer including pulses having apertures that are controlled in real time, according to an embodiment of the invention.

0104<figref idref="DRAWINGS">FIG. 65</figref> illustrates an example embodiment of the invention.

0105<figref idref="DRAWINGS">FIG. 66</figref> illustrates an example embodiment of the invention.

0106<figref idref="DRAWINGS">FIG. 67</figref> illustrates an example embodiment of the invention.

0107<figref idref="DRAWINGS">FIG. 68</figref> illustrates an example embodiment of the invention.

0108<figref idref="DRAWINGS">FIG. 69A</figref> is a timing diagram for the example embodiment of <figref idref="DRAWINGS">FIG. 65</figref>.

0109<figref idref="DRAWINGS">FIG. 69B</figref> is a timing diagram for the example embodiment of <figref idref="DRAWINGS">FIG. 66</figref>.

0110<figref idref="DRAWINGS">FIG. 70A</figref> is a timing diagram for the example embodiment of <figref idref="DRAWINGS">FIG. 67</figref>.

0111<figref idref="DRAWINGS">FIG. 70B</figref> is a timing diagram for the example embodiment of <figref idref="DRAWINGS">FIG. 68</figref>.

0112<figref idref="DRAWINGS">FIG. 71A</figref> illustrates and example embodiment of the invention.

0113<figref idref="DRAWINGS">FIG. 71B</figref> illustrates example equations for determining charge transfer, in accordance with the present invention.

0114<figref idref="DRAWINGS">FIG. 71C</figref> illustrates relationships between capacitor charging and aperture, in accordance with an embodiment of the present invention.

0115<figref idref="DRAWINGS">FIG. 71D</figref> illustrates relationships between capacitor charging and aperture, in accordance with an embodiment of the present invention.

0116<figref idref="DRAWINGS">FIG. 71E</figref> illustrates power-charge relationship equations, in accordance with an embodiment of the present invention.

0117<figref idref="DRAWINGS">FIG. 71F</figref> illustrates insertion loss equations, in accordance with an embodiment of the present invention.

0118<figref idref="DRAWINGS">FIG. 72</figref> shows the original FSK waveform <b>5902</b> and the down-converted waveform <b>5904</b>.

0119<figref idref="DRAWINGS">FIG. 73</figref> illustrates a down-converter according to an embodiment of the present invention, showing some DC offset contributions.

0120<figref idref="DRAWINGS">FIG. 74</figref> illustrates a down-converter according to an embodiment of the present invention, that removes at least some DC offset contributions.

0121<figref idref="DRAWINGS">FIGS. 75 and 76</figref> illustrate circuit diagrams according to embodiments of the present invention.

0122<figref idref="DRAWINGS">FIG. 77A</figref> illustrates an example clock pulse train.

0123<figref idref="DRAWINGS">FIG. 77B</figref> illustrates an example clock frequency spectrum.

0124<figref idref="DRAWINGS">FIG. 78</figref> illustrates a circuit diagram according to an embodiment of the present invention, which may be used to measure DC offsets.

0125<figref idref="DRAWINGS">FIGS. 79 and 80</figref> illustrate example output offset plots for the circuit diagram of <figref idref="DRAWINGS">FIG. 78</figref>, for a variety of clock signals.

0126<figref idref="DRAWINGS">FIGS. 81 and 82</figref> show example output offset plots obtained for the circuit model of <figref idref="DRAWINGS">FIG. 78</figref>, with variations in the bond wire inductance.

0127<figref idref="DRAWINGS">FIG. 83</figref> illustrates example V_OCIresponse for a variety of clock signal rise and fall times.

0128<figref idref="DRAWINGS">FIGS. 84A</figref>, <b>84</b>B, <b>85</b>A and <b>85</b>B show the results on an I port of an I/Q receiver according to an embodiment of the present invention, for a variety of LO drive levels and 3 operating channels, for two different assemblies.

0129<figref idref="DRAWINGS">FIG. 86A</figref> illustrates example complimentary architecture output offset for a variety of clock signal pulse widths.

0130<figref idref="DRAWINGS">FIG. 86B</figref> shows an example spectral plot of a carrier tone at RF, corresponding to LO re-radiation at a UFD module.

0131<figref idref="DRAWINGS">FIG. 86C</figref> illustrates the LO re-radiation spectrum shown in <figref idref="DRAWINGS">FIG. 86B</figref> after modulation by an example modified maximal length linear PN sequence.

0132<figref idref="DRAWINGS">FIG. 86D</figref> shows an example PN modulated output of a UFD module.

0133<figref idref="DRAWINGS">FIG. 86E</figref> illustrates the result of <figref idref="DRAWINGS">FIG. 86D</figref> after PN rectification or correlation.

0134<figref idref="DRAWINGS">FIG. 86F</figref> illustrates the result of <figref idref="DRAWINGS">FIG. 86E</figref> after low pass filtering to recover the baseband beat note.

0135<figref idref="DRAWINGS">FIG. 86G</figref> illustrates an exemplary signal input harmonic spectrum and conversion clock harmonic spectrum.

0136<figref idref="DRAWINGS">FIG. 86H</figref> illustrates an exemplary power series.

0137<figref idref="DRAWINGS">FIG. 86I</figref> illustrates an exemplary system block diagram, according to an embodiment of the present invention.

0138<figref idref="DRAWINGS">FIG. 87</figref> shows a conventional wireless communications down-conversion system.

0139<figref idref="DRAWINGS">FIG. 88A</figref> shows an exemplary down-conversion system that reduces output DC offset, according to an embodiment of the present invention.

0140<figref idref="DRAWINGS">FIGS. 88B-H</figref> show example waveforms related to the system of <figref idref="DRAWINGS">FIG. 88A</figref>, according to an embodiment of the present invention.

0141<figref idref="DRAWINGS">FIG. 89</figref> shows an exemplary down-conversion system that reduces output DC offset, according to an embodiment of the present invention.

0142<figref idref="DRAWINGS">FIG. 90</figref> illustrates some aspects of charge injection related to the present invention.

0143<figref idref="DRAWINGS">FIG. 91</figref> illustrates an exemplary circuit configuration for reducing DC offset voltage caused by charge injection, according to an embodiment of the present invention.

0144<figref idref="DRAWINGS">FIG. 92A</figref> illustrates an exemplary down-conversion system, according to an embodiment of the present invention, that may be used to indicate potential points in a signal path where DC offset voltages may be injected.

0145<figref idref="DRAWINGS">FIG. 92B</figref> illustrates an exemplary auto-zero compensation circuit for reducing or eliminating DC offset inserted by circuit components, according to an embodiment of the present invention.

0146<figref idref="DRAWINGS">FIG. 93</figref> illustrates an exemplary differential DC offset voltage cancellation circuit, according to an embodiment of the present invention.

0147<figref idref="DRAWINGS">FIG. 94A</figref> illustrates a second exemplary differential DC offset voltage cancellation circuit, according to an embodiment of the present invention.

0148<figref idref="DRAWINGS">FIGS. 94B-H</figref> illustrate example waveforms related to the circuit of <figref idref="DRAWINGS">FIG. 94A</figref>, according to an embodiment of the present invention.

0149<figref idref="DRAWINGS">FIG. 95</figref> illustrates an exemplary differential receiver circuit, according to an embodiment of the present invention.

0150<figref idref="DRAWINGS">FIG. 96</figref> illustrates an exemplary input RF signal and exemplary control signal waveforms, according to embodiments of the present invention.

0151<figref idref="DRAWINGS">FIG. 97</figref> illustrates an exemplary I/Q modulation receiver circuit, according to an embodiment of the present invention.

0152<figref idref="DRAWINGS">FIGS. 98A-98I</figref> show an exemplary input RF I/Q signal, and several exemplary control signal waveforms.

0153<figref idref="DRAWINGS">FIG. 99</figref> illustrates an exemplary buffered I/Q modulation receiver circuit, according to an embodiment of the present invention.

0154<figref idref="DRAWINGS">FIG. 100</figref> illustrates an exemplary receiver with a placebo circuit, according to an embodiment of the present invention.

0155<figref idref="DRAWINGS">FIG. 101</figref> shows an exemplary control signal waveform, and a corresponding exemplary placebo control signal waveform.

0156<figref idref="DRAWINGS">FIG. 102</figref> illustrates a receiver with adjacent apertures circuit, according to an embodiment of the present invention.

0157<figref idref="DRAWINGS">FIG. 103</figref> shows an exemplary control signal waveform, and a corresponding π-shifted control signal waveform.

0158<figref idref="DRAWINGS">FIG. 104</figref> illustrates an exemplary receiver with adjacent apertures circuit, according to an embodiment of the present invention.

0159<figref idref="DRAWINGS">FIG. 105</figref> illustrates an exemplary circuit for improving dynamic range, according to an embodiment of the present invention.

0160<figref idref="DRAWINGS">FIGS. 106A-C</figref> illustrate exemplary waveforms related to improving dynamic range.

0161<figref idref="DRAWINGS">FIG. 107</figref> illustrates an exemplary bias circuit, according to an embodiment of the present invention.

0162<figref idref="DRAWINGS">FIG. 108</figref> depicts a flowchart that illustrates operational steps for down-converting and spectrally spreading an input signal, according to an embodiment of the present invention.

0163<figref idref="DRAWINGS">FIG. 109</figref> depicts a flowchart that illustrates operational steps for down-converting an input signal and reducing a DC offset voltage, according to an embodiment of the present invention.

0164<figref idref="DRAWINGS">FIG. 110</figref> depicts a flowchart that illustrates operational steps for reducing DC offset in a signal path, according to an embodiment of the present invention.

0165<figref idref="DRAWINGS">FIG. 111</figref> depicts a flowchart that illustrates operational steps for down-converting an input signal and canceling DC offset voltages, according to an embodiment of the present invention.

0166<figref idref="DRAWINGS">FIG. 112</figref> depicts a flowchart that illustrates operational steps for down-converting an input signal and canceling DC offset voltages, according to an embodiment of the present invention.

0167<figref idref="DRAWINGS">FIG. 113</figref> depicts a flowchart that illustrates operational steps for differentially down-converting an input signal, according to an embodiment of the present invention.

0168<figref idref="DRAWINGS">FIG. 114</figref> depicts a flowchart that illustrates operational steps for down-converting an input signal with a variety of control signal pulse widths, according to an embodiment of the present invention.

0169<figref idref="DRAWINGS">FIG. 115</figref> depicts a flowchart that illustrates operational steps for down-converting an RF I/Q modulated input signal, according to an embodiment of the present invention.

0170<figref idref="DRAWINGS">FIG. 116</figref> depicts a flowchart that illustrates operational steps for down-converting an RF I/Q modulated input signal, according to an embodiment of the present invention.

0171<figref idref="DRAWINGS">FIG. 117</figref> depicts a flowchart that illustrates operational steps for down-converting an input signal and altering circuit re-radiation, according to an embodiment of the present invention.

0172<figref idref="DRAWINGS">FIGS. 118A-B</figref> depict flowcharts that illustrate operational steps for down-converting an input signal and altering circuit re-radiation, according to an embodiment of the present invention.

0173<figref idref="DRAWINGS">FIG. 119</figref> depicts a flowchart that illustrates operational steps for improving dynamic range, according to an embodiment of the present invention.

0174<figref idref="DRAWINGS">FIG. 120</figref> depicts a flowchart that illustrates operational steps for down-converting a RF I/Q modulated signal and reducing DC offset voltages, according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Table of Contents

1. Overview of the Invention

2. Universal Frequency Translation

3. Frequency Down-conversion

0000<ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0000"><ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0175">3.1 Optional Energy Transfer Signal Module</li><li id="ul0003-0002" num="0176">3.2 Smoothing the Down-Converted Signal</li><li id="ul0003-0003" num="0177">3.3 Impedance Matching</li><li id="ul0003-0004" num="0178">3.4 Tanks and Resonant Structures</li><li id="ul0003-0005" num="0179">3.5 Charge and Power Transfer Concepts</li><li id="ul0003-0006" num="0180">3.6 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration <ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0181">3.6.1 Varying Input and Output Impedances</li><li id="ul0004-0002" num="0182">3.6.2 Real Time Aperture Control</li></ul></li><li id="ul0003-0007" num="0183">3.7 Adding a Bypass Network</li><li id="ul0003-0008" num="0184">3.8 Modifying the Energy Transfer Signal Utilizing Feedback</li><li id="ul0003-0009" num="0185">3.9 Other Implementations</li><li id="ul0003-0010" num="0186">3.10 Example Energy Transfer Down-Converters</li></ul></li></ul>

4. Frequency Up-conversion

5. Enhanced Signal Reception

6. Unified Down-conversion and Filtering

7. Example Application Embodiments of the Invention

7.0 DC Offset, Re-radiation, and Dynamic Range Considerations and Corrections

0000<ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0187">7.1 Overview of DC Offset and Re-radiation <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0188">7.1.1 Introduction</li><li id="ul0007-0002" num="0189">7.1.2 A Basic DC Offset Model</li><li id="ul0007-0003" num="0190">7.1.3 Clock Modulation via PN Code <ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0191">7.1.3.1 Interpretation of R_xx(T) and Required Leakage</li><li id="ul0008-0002" num="0192">7.1.3.2 Charge Injected DC Offset</li><li id="ul0008-0003" num="0193">7.1.3.3 Clock Waveform Impact on CI Induced Offsets</li><li id="ul0008-0004" num="0194">7.1.3.4 Bench Example</li><li id="ul0008-0005" num="0195">7.1.3.5 Complementary Architecture</li><li id="ul0008-0006" num="0196">7.1.3.6 Spreading Code Results</li></ul></li><li id="ul0007-0004" num="0197">7.1.4 UFD Module DC Offsets from Non-Linearities</li></ul></li><li id="ul0006-0002" num="0198">7.2 Example Embodiments to Address DC Offset and Re-radiation Problems <ul id="ul0009" list-style="none"><li id="ul0009-0001" num="0199">7.2.1 DC Offset <ul id="ul0010" list-style="none"><li id="ul0010-0001" num="0200">7.2.1.1 Reducing DC Offset by Spectral Spreading and De-spreading <ul id="ul0011" list-style="none"><li id="ul0011-0001" num="0201">7.2.1.1.1 Conventional Wireless Communications Receiver</li><li id="ul0011-0002" num="0202">7.2.1.1.2 Spread/De-spread Receiver Embodiment of the Present Invention</li></ul></li><li id="ul0010-0002" num="0203">7.2.1.3 Charge Injection Reduction Embodiment</li><li id="ul0010-0003" num="0204">7.2.1.4 Auto-Zero Compensation</li><li id="ul0010-0004" num="0205">7.2.1.5 Reducing DC Offset with Differential Configurations</li><li id="ul0010-0005" num="0206">7.2.1.6 Reducing DC Offset with Differential Outputs</li></ul></li><li id="ul0009-0002" num="0207">7.2.2 Re-radiation <ul id="ul0012" list-style="none"><li id="ul0012-0001" num="0208">7.2.2.1 Reducing Re-radiation by Adjusting Control Signal Attributes <ul id="ul0013" list-style="none"><li id="ul0013-0001" num="0209">7.2.2.1.1 I/Q Modulation Receiver Control Signal Considerations and Embodiments</li><li id="ul0013-0002" num="0000"> 7.2.2.1.1.1 Non-overlapping I/Q Control Signal Pulses Embodiments</li><li id="ul0013-0003" num="0000"> 7.2.2.1.1.2 Buffered I/Q Modulation Receiver Embodiment</li></ul></li><li id="ul0012-0002" num="0210">7.2.2.2 Reducing Re-radiation with Placebo Down-conversion Modules</li><li id="ul0012-0003" num="0211">7.2.2.3 Reducing Re-radiation with Adjacent Apertures</li></ul></li><li id="ul0009-0003" num="0212">7.2.3 Additional DC Offset and Re-radiation Reduction Embodiments</li></ul></li><li id="ul0006-0003" num="0213">7.3 Example Embodiments to Improve Dynamic Range <ul id="ul0014" list-style="none"><li id="ul0014-0001" num="0214">7.3.1 Adjusting Down-conversion Module Dynamic Range</li><li id="ul0014-0002" num="0215">7.4 Example Receiver and Transmitter Embodiments for Addressing DC Offset and Re-radiation <ul id="ul0015" list-style="none"><li id="ul0015-0001" num="0216">7.4.1 Example I/Q Modulation Receiver Embodiments <ul id="ul0016" list-style="none"><li id="ul0016-0001" num="0217">7.4.1.1 Example I/Q Modulation Control Signal Generator Embodiments</li></ul></li><li id="ul0015-0002" num="0218">7.4.1.2 Detailed Example I/Q Modulation Receiver Embodiment with Exemplary Waveforms</li><li id="ul0015-0003" num="0219">7.4.1.3 Example Single Channel Receiver Embodiment</li><li id="ul0015-0004" num="0220">7.4.1.4 Alternative Example I/Q Modulation Receiver Embodiment</li><li id="ul0015-0005" num="0221">7.4.1.5 Example Transmitter Embodiment</li></ul></li></ul></li></ul></li></ul>

8. Conclusion

1. OVERVIEW OF THE INVENTION

0222The present invention is directed to receivers implemented using universal frequency translation (UFT) modules. The UFT modules perform frequency translation operations. Embodiments of the present invention incorporating various applications of the UFT module are described below.

0223Receivers exhibit multiple advantages by using UFT modules. These advantages include, but are not limited to, lower power consumption, longer power source life, fewer parts, lower required package size, lower package weight, lower cost, less tuning, and more effective signal transmission and reception. The receivers of the present invention can receive and transmit signals across a broad frequency range. Furthermore, the DC offset voltages and re-radiation generated by receivers are the present invention are reduced or eliminated in embodiments. The structure and operation of embodiments of the UFT module, and various applications of the same, utilizing DC offset/re-radiation reduction, are described in detail in the following sections.

2. UNIVERSAL FREQUENCY TRANSLATION

0224The present invention is related to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.

0225<figref idref="DRAWINGS">FIG. 1A</figref> illustrates a universal frequency translation (UFT) module <b>102</b> according to embodiments of the invention. (The UFT module is also sometimes called a universal frequency translator, or a universal translator.)

0226As indicated by the example of <figref idref="DRAWINGS">FIG. 1A</figref>, some embodiments of the UFT module <b>102</b> include three ports (nodes), designated in <figref idref="DRAWINGS">FIG. 1A</figref> as Port <b>1</b>, Port <b>2</b>, and Port <b>3</b>. Other UFT embodiments include other than three ports.

0227Generally, the UFT module <b>102</b> (perhaps in combination with other components) operates to generate an output signal from an input signal, where the frequency of the output signal differs from the frequency of the input signal. In other words, the UFT module <b>102</b> (and perhaps other components) operates to generate the output signal from the input signal by translating the frequency (and perhaps other characteristics) of the input signal to the frequency (and perhaps other characteristics) of the output signal.

0228An example embodiment of the UFT module <b>103</b> is generally illustrated in <figref idref="DRAWINGS">FIG. 1B</figref>. Generally, the UFT module <b>103</b> includes a switch <b>106</b> controlled by a control signal <b>108</b>. The switch <b>106</b> is said to be a controlled switch.

0229As noted above, some UFT embodiments include other than three ports. For example, and without limitation, <figref idref="DRAWINGS">FIG. 2</figref> illustrates an example UFT module <b>202</b>. The example UFT module <b>202</b> includes a diode <b>204</b> having two ports, designated as Port <b>1</b> and Port <b>2</b>/<b>3</b>. This embodiment does not include a third port, as indicated by the dotted line around the “Port <b>3</b>” label.

0230The UFT module is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.

0231For example, a UFT module <b>115</b> can be used in a universal frequency down-conversion (UFD) module <b>114</b>, an example of which is shown in <figref idref="DRAWINGS">FIG. 1C</figref>. In this capacity, the UFT module <b>115</b> frequency down-converts an input signal to an output signal.

0232As another example, as shown in <figref idref="DRAWINGS">FIG. 1D</figref>, a UFT module <b>117</b> can be used in a universal frequency up-conversion (UFU) module <b>116</b>. In this capacity, the UFT module <b>117</b> frequency up-converts an input signal to an output signal.

0233These and other applications of the UFT module are described below. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. In some applications, the UFT module is a required component. In other applications, the UFT module is an optional component.

3. FREQUENCY DOWN-CONVERSION

0234The present invention is directed to systems and methods of universal frequency down-conversion, and applications of same.

0235In particular, the following discussion describes down-converting using a Universal Frequency Translation Module. The down-conversion of an EM signal by aliasing the EM signal at an aliasing rate is fully described in co-pending U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference. A relevant portion of the above mentioned patent application is summarized below to describe down-converting an input signal to produce a down-converted signal that exists at a lower frequency or a baseband signal.

0236<figref idref="DRAWINGS">FIG. 20A</figref> illustrates an aliasing module <b>2000</b> for down-conversion using a universal frequency translation (UFT) module <b>2002</b> which down-converts an EM input signal <b>2004</b>. In particular embodiments, aliasing module <b>2000</b> includes a switch <b>2008</b> and a capacitor <b>2010</b>. The electronic alignment of the circuit components is flexible. That is, in one implementation, the switch <b>2008</b> is in series with input signal <b>2004</b> and capacitor <b>2010</b> is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation (see <figref idref="DRAWINGS">FIG. 20G</figref>), the capacitor <b>2010</b> is in series with the input signal <b>2004</b> and the switch <b>2008</b> is shunted to ground (although it may be other than ground in configurations such as differential mode). Aliasing module <b>2000</b> with UFT module <b>2002</b> can be easily tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of the EM input signal <b>2004</b>.

0237In one implementation, aliasing module <b>2000</b> down-converts the input signal <b>2004</b> to an intermediate frequency (IF) signal. In another implementation, the aliasing module <b>2000</b> down-converts the input signal <b>2004</b> to a demodulated baseband signal. In yet another implementation, the input signal <b>2004</b> is a frequency modulated (FM) signal, and the aliasing module <b>2000</b> down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below.

0238In an embodiment, the control signal <b>2006</b> includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal <b>2004</b>. In this embodiment, the control signal <b>2006</b> is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal <b>2004</b>. Preferably, the frequency of control signal <b>2006</b> is much less than the input signal <b>2004</b>.

0239A train of pulses <b>2018</b> as shown in <figref idref="DRAWINGS">FIG. 20D</figref> controls the switch <b>2008</b> to alias the input signal <b>2004</b> with the control signal <b>2006</b> to generate a down-converted output signal <b>2012</b>. More specifically, in an embodiment, switch <b>2008</b> closes on a first edge of each pulse <b>2020</b> of <figref idref="DRAWINGS">FIG. 20D</figref> and opens on a second edge of each pulse. When the switch <b>2008</b> is closed, the input signal <b>2004</b> is coupled to the capacitor <b>2010</b>, and charge is transferred from the input signal to the capacitor <b>2010</b>. The charge stored during successive pulses forms down-converted output signal <b>2012</b>.

0240Exemplary waveforms are shown in <figref idref="DRAWINGS">FIGS. 20B-20F</figref>.

0241<figref idref="DRAWINGS">FIG. 20B</figref> illustrates an analog amplitude modulated (AM) carrier signal <b>2014</b> that is an example of input signal <b>2004</b>. For illustrative purposes, in <figref idref="DRAWINGS">FIG. 20C</figref>, an analog AM carrier signal portion <b>2016</b> illustrates a portion of the analog AM carrier signal <b>2014</b> on an expanded time scale. The analog AM carrier signal portion <b>2016</b> illustrates the analog AM carrier signal <b>2014</b> from time t₀to time t₁.

0242<figref idref="DRAWINGS">FIG. 20D</figref> illustrates an exemplary aliasing signal <b>2018</b> that is an example of control signal <b>2006</b>. Aliasing signal <b>2018</b> is on approximately the same time scale as the analog AM carrier signal portion <b>2016</b>. In the example shown in <figref idref="DRAWINGS">FIG. 20D</figref>, the aliasing signal <b>2018</b> includes a train of pulses <b>2020</b> having negligible apertures that tend towards zero (the invention is not limited to this embodiment, as discussed below). The pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s). The pulses <b>2020</b> repeat at an aliasing rate, or pulse repetition rate of aliasing signal <b>2018</b>. The aliasing rate is determined as described below, and further described in co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0243As noted above, the train of pulses <b>2020</b> (i.e., control signal <b>2006</b>) control the switch <b>2008</b> to alias the analog AM carrier signal <b>2016</b> (i.e., input signal <b>2004</b>) at the aliasing rate of the aliasing signal <b>2018</b>. Specifically, in this embodiment, the switch <b>2008</b> closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch <b>2008</b> is closed, input signal <b>2004</b> is coupled to the capacitor <b>2010</b>, and charge is transferred from the input signal <b>2004</b> to the capacitor <b>2010</b>. The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples <b>2022</b> form down-converted signal portion <b>2024</b> (<figref idref="DRAWINGS">FIG. 20E</figref>) that corresponds to the analog AM carrier signal portion <b>2016</b> (<figref idref="DRAWINGS">FIG. 20C</figref>) and the train of pulses <b>2020</b> (<figref idref="DRAWINGS">FIG. 20D</figref>). The charge stored during successive under-samples of AM carrier signal <b>2014</b> form the down-converted signal <b>2024</b> (<figref idref="DRAWINGS">FIG. 20E</figref>) that is an example of down-converted output signal <b>2012</b> (<figref idref="DRAWINGS">FIG. 20A</figref>). In <figref idref="DRAWINGS">FIG. 20F</figref>, a demodulated baseband signal <b>2026</b> represents the demodulated baseband signal <b>2024</b> after filtering on a compressed time scale. As illustrated, down-converted signal <b>2026</b> has substantially the same “amplitude envelope” as AM carrier signal <b>2014</b>. Therefore, <figref idref="DRAWINGS">FIGS. 20B-20F</figref> illustrate down-conversion of AM carrier signal <b>2014</b>.

0244The waveforms shown in <figref idref="DRAWINGS">FIGS. 20B-20F</figref> are discussed herein for illustrative purposes only, and are not limiting. Additional exemplary time domain and frequency domain drawings, and exemplary methods and systems of the invention relating thereto, are disclosed in co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0245The aliasing rate of control signal <b>2006</b> determines whether the input signal <b>2004</b> is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or an AM signal. Generally, relationships between the input signal <b>2004</b>, the aliasing rate of the control signal <b>2006</b>, and the down-converted output signal <b>2012</b> are illustrated below:

0000<br />(Freq. of input signal 2004)=<i>n</i>·(Freq. of control signal 2006)±(Freq. of down-converted output signal 2012)

0000For the examples contained herein, only the “+” condition will be discussed. The value of n represents a harmonic or sub-harmonic of input signal <b>2004</b> (e.g., n=0.5, 1, 2, 3, . . . ).

0246When the aliasing rate of control signal <b>2006</b> is off-set from the frequency of input signal <b>2004</b>, or off-set from a harmonic or sub-harmonic thereof, input signal <b>2004</b> is down-converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of input signal <b>2004</b>. As a result, the under-samples form a lower frequency oscillating pattern. If the input signal <b>2004</b> includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHZ input signal to a 1 MHZ IF signal, the frequency of the control signal <b>2006</b> would be calculated as follows:

0000<br />(Freq_input−Freq_IF)/<i>n</i>=Freq_control

0000<br />(901 MHZ−1 MHZ)/<i>n=</i>900<i>/n </i>

0000For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal <b>2006</b> would be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

0247Exemplary time domain and frequency domain drawings, illustrating down-conversion of analog and digital AM, PM and FM signals to IF signals, and exemplary methods and systems thereof, are disclosed in co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0248Alternatively, when the aliasing rate of the control signal <b>2006</b> is substantially equal to the frequency of the input signal <b>2004</b>, or substantially equal to a harmonic or sub-harmonic thereof, input signal <b>2004</b> is directly down-converted to a demodulated baseband signal. This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of the input signal <b>2004</b>. As a result, the under-samples form a constant output baseband signal. If the input signal <b>2004</b> includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHZ input signal to a demodulated baseband signal (i.e., zero IF), the frequency of the control signal <b>2006</b> would be calculated as follows:

0000<br />(Freq_input−Freq_IF)/<i>n</i>=Freq_control

0000<br />(900 MHZ−0 MHZ)/<i>n=</i>900 MHZ/<i>n </i>

0000For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal <b>2006</b> should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

0249Exemplary time domain and frequency domain drawings, illustrating direct down-conversion of analog and digital AM and PM signals to demodulated baseband signals, and exemplary methods and systems thereof, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0250Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F₁and an upper frequency F₂(that is, [(F₁+F₂)÷2]) of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F₁equal to 899 MHZ and F₂equal to 901 MHZ, to a PSK signal, the aliasing rate of the control signal <b>2006</b> would be calculated as follows:

0000<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>Frequency</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>of</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>the</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>input</mi></mrow><mo>=</mo><mrow><mrow><mo>(</mo><mrow><msub><mi>F</mi><mn>1</mn></msub><mo>+</mo><msub><mi>F</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mo>÷</mo><mn>2</mn></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mrow><mrow><mo>(</mo><mrow><mrow><mn>899</mn><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>MHZ</mi></mrow><mo>+</mo><mrow><mn>901</mn><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>MHZ</mi></mrow></mrow><mo>)</mo></mrow><mo>÷</mo><mn>2</mn></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mrow><mn>900</mn><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>MHZ</mi></mrow></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0001.tif" />

0000Frequency of the down-converted signal=0 (i.e., baseband)

0000<br />(Freq_input−Freq_IF)/<i>n</i>=Freq_control

0000<br />(900 MHZ−0 MHZ)/<i>n=</i>900 MHZ/<i>n </i>

0000For n=0.5, 1, 2, 3, etc., the frequency of the control signal <b>2006</b> should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F₁and the upper frequency F₂.

0251As another example, to down-convert a FSK signal to an amplitude shift keying (ASK) signal (a subset of AM), either the lower frequency F₁or the upper frequency F₂of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F₁equal to 900 MHZ and F₂equal to 901 MHZ, to an ASK signal, the aliasing rate of the control signal <b>2006</b> should be substantially equal to:

0000<br />(900 MHZ−0 MHZ)/<i>n=</i>900 MHZ/<i>n</i>, or

0000<br />(901 MHZ−0 MHZ)/<i>n=</i>901 MHZ/<i>n. </i>

0000For the former case of 900 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal <b>2006</b> should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. For the latter case of 901 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal <b>2006</b> should be substantially equal to 1.802 GHz, 901 MHZ, 450.5 MHZ, 300.333 MHZ, 225.25 MHZ, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F₁and the upper frequency F₂(i.e., 1 MHZ).

0252Exemplary time domain and frequency domain drawings, illustrating down-conversion of FM signals to non-FM signals, and exemplary methods and systems thereof, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0253In an embodiment, the pulses of the control signal <b>2006</b> have negligible apertures that tend towards zero. This makes the UFT module <b>2002</b> a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired.

0254In another embodiment, the pulses of the control signal <b>2006</b> have non-negligible apertures that tend away from zero. This makes the UFT module <b>2002</b> a lower input impedance device. This allows the lower input impedance of the UFT module <b>2002</b> to be substantially matched with a source impedance of the input signal <b>2004</b>. This also improves the energy transfer from the input signal <b>2004</b> to the down-converted output signal <b>2012</b>, and hence the efficiency and signal to noise (s/n) ratio of UFT module <b>2002</b>.

0255Exemplary systems and methods for generating and optimizing the control signal <b>2006</b>, and for otherwise improving energy transfer and s/n ratio, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.

0256When the pulses of the control signal <b>2006</b> have non-negligible apertures, the aliasing module <b>2000</b> is referred to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal <b>2006</b> is referred to as an energy transfer signal. Exemplary systems and methods for generating and optimizing the control signal <b>2006</b> and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.

02573.1. Optional Energy Transfer Signal Module

0258<figref idref="DRAWINGS">FIG. 47</figref> illustrates an energy transfer system <b>4701</b> that includes an optional energy transfer signal module <b>4702</b>, which can perform any of a variety of functions or combinations of functions including, but not limited to, generating the energy transfer signal <b>4506</b>.

0259In an embodiment, the optional energy transfer signal module <b>4702</b> includes an aperture generator, an example of which is illustrated in <figref idref="DRAWINGS">FIG. 46C</figref> as an aperture generator <b>4620</b>. The aperture generator <b>4620</b> generates non-negligible aperture pulses <b>4626</b> from an input signal <b>4624</b>. The input signal <b>4624</b> can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating the input signal <b>4624</b> are described below.

0260The width or aperture of the pulses <b>4626</b> is determined by delay through the branch <b>4622</b> of the aperture generator <b>4620</b>. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator <b>4620</b> decrease. In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components utilized in the example aperture generator <b>4620</b> do not require as fast reaction times as those that are required in an under-sampling system operating with the same EM input frequency.

0261The example logic and implementation shown in the aperture generator <b>4620</b> are provided for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. The example aperture generator <b>4620</b> includes an optional inverter <b>4628</b>, which is shown for polarity consistency with other examples provided herein.

0262An example implementation of the aperture generator <b>4620</b> is illustrated in <figref idref="DRAWINGS">FIG. 46D</figref>. Additional examples of aperture generation logic are provided in <figref idref="DRAWINGS">FIGS. 46A and 46B</figref>. <figref idref="DRAWINGS">FIG. 46A</figref> illustrates a rising edge pulse generator <b>4640</b>, which generates pulses <b>4626</b> on rising edges of the input signal <b>4624</b>. <figref idref="DRAWINGS">FIG. 46B</figref> illustrates a falling edge pulse generator <b>4650</b>, which generates pulses <b>4626</b> on falling edges of the input signal <b>4624</b>.

0263In an embodiment, the input signal <b>4624</b> is generated externally of the energy transfer signal module <b>4702</b>, as illustrated in <figref idref="DRAWINGS">FIG. 47</figref>. Alternatively, the input signal <b>4724</b> is generated internally by the energy transfer signal module <b>4702</b>. The input signal <b>4624</b> can be generated by an oscillator, as illustrated in <figref idref="DRAWINGS">FIG. 46E</figref> by an oscillator <b>4630</b>. The oscillator <b>4630</b> can be internal to the energy transfer signal module <b>4702</b> or external to the energy transfer signal module <b>4702</b>. The oscillator <b>4630</b> can be external to the energy transfer system <b>4701</b>. The output of the oscillator <b>4630</b> may be any periodic waveform.

0264The type of down-conversion performed by the energy transfer system <b>4701</b> depends upon the aliasing rate of the energy transfer signal <b>4506</b>, which is determined by the frequency of the pulses <b>4626</b>. The frequency of the pulses <b>4626</b> is determined by the frequency of the input signal <b>4624</b>. For example, when the frequency of the input signal <b>4624</b> is substantially equal to a harmonic or a sub-harmonic of the EM signal <b>4504</b>, the EM signal <b>4504</b> is directly down-converted to baseband (e.g. when the EM signal is an AM signal or a PM signal), or converted from FM to a non-FM signal. When the frequency of the input signal <b>4624</b> is substantially equal to a harmonic or a sub-harmonic of a difference frequency, the EM signal <b>4504</b> is down-converted to an intermediate signal.

0265The optional energy transfer signal module <b>4702</b> can be implemented in hardware, software, firmware, or any combination thereof.

02663.2 Smoothing the Down-Converted Signal

0267Referring back to <figref idref="DRAWINGS">FIG. 20A</figref>, the down-converted output signal <b>2012</b> may be smoothed by filtering as desired.

02683.3. Impedance Matching

0269The energy transfer module <b>2000</b> has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., UFT <b>2002</b>), and (2) the impedance of the storage module (e.g., capacitor <b>2010</b>), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies).

0270Starting with an aperture width of approximately ½ the period of the EM signal being down-converted as a preferred embodiment, this aperture width (e.g. the “closed time”) can be decreased. As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from ½ the period of the EM signal being down-converted, the impedance of the energy transfer module decreases.

0271One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module's characteristic input impedance is 300 ohms. An impedance matching circuit can be utilized to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below.

0272Referring to <figref idref="DRAWINGS">FIG. 48</figref>, a specific embodiment using an RF signal as an input, assuming that the impedance <b>4812</b> is a relatively low impedance of approximately 50 Ohms, for example, and the input impedance <b>4816</b> is approximately 300 Ohms, an initial configuration for the input impedance match module <b>4806</b> can include an inductor <b>5006</b> and a capacitor <b>5008</b>, configured as shown in <figref idref="DRAWINGS">FIG. 50</figref>. The configuration of the inductor <b>5006</b> and the capacitor <b>5008</b> is a possible configuration when going from a low impedance to a high impedance. Inductor <b>5006</b> and the capacitor <b>5008</b> constitute an L match, the calculation of the values which is well known to those skilled in the relevant arts.

0273The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1 MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.

0274In an embodiment, the energy transfer module's characteristic output impedance is 2K ohms. An impedance matching circuit can be utilized to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.

0275When matching from a high impedance to a low impedance, a capacitor <b>5014</b> and an inductor <b>5016</b> can be configured as shown in <figref idref="DRAWINGS">FIG. 50</figref>. The capacitor <b>5014</b> and the inductor <b>5016</b> constitute an L match, the calculation of the component values being well known to those skilled in the relevant arts.

0276The configuration of the input impedance match module <b>4806</b> and the output impedance match module <b>4808</b> are considered to be initial starting points for impedance matching, in accordance with the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be optimized in accordance with other various design criteria and considerations.

0277As other optional optimizing structures and/or components are utilized, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria.

02783.4 Tanks and Resonant Structures

0279Resonant tank and other resonant structures can be used to further optimize the energy transfer characteristics of the invention. For example, resonant structures, resonant about the input frequency, can be used to store energy from the input signal when the switch is open, a period during which one may conclude that the architecture would otherwise be limited in its maximum possible efficiency. Resonant tank and other resonant structures can include, but are not limited to, surface acoustic wave (SAW) filters, dielectric resonators, diplexers, capacitors, inductors, etc.

0280An example embodiment is shown in <figref idref="DRAWINGS">FIG. 60A</figref>. Two additional embodiments are shown in <figref idref="DRAWINGS">FIG. 55</figref> and <figref idref="DRAWINGS">FIG. 63</figref>. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. These implementations take advantage of properties of series and parallel (tank) resonant circuits.

0281<figref idref="DRAWINGS">FIG. 60A</figref> illustrates parallel tank circuits in a differential implementation. A first parallel resonant or tank circuit consists of a capacitor <b>6038</b> and an inductor <b>6020</b> (tank<b>1</b>). A second tank circuit consists of a capacitor <b>6034</b> and an inductor <b>6036</b> (tank<b>2</b>).

0282As is apparent to one skilled in the relevant art(s), parallel tank circuits provide: <ul id="ul0017" list-style="none"><li id="ul0017-0001" num="0000"><ul id="ul0018" list-style="none"><li id="ul0018-0001" num="0283">low impedance to frequencies below resonance;</li><li id="ul0018-0002" num="0284">low impedance to frequencies above resonance; and</li><li id="ul0018-0003" num="0285">high impedance to frequencies at and near resonance.</li></ul></li></ul>

0286In the illustrated example of <figref idref="DRAWINGS">FIG. 60A</figref>, the first and second tank circuits resonate at approximately 920 MHz. At and near resonance, the impedance of these circuits is relatively high. Therefore, in the circuit configuration shown in <figref idref="DRAWINGS">FIG. 60A</figref>, both tank circuits appear as relatively high impedance to the input frequency of 950 MHz, while simultaneously appearing as relatively low impedance to frequencies in the desired output range of 50 MHz.

0287An energy transfer signal <b>6042</b> controls a switch <b>6014</b>. When the energy transfer signal <b>6042</b> controls the switch <b>6014</b> to open and close, high frequency signal components are not allowed to pass through tank<b>1</b> or tank<b>2</b>. However, the lower signal components (50 Mhz in this embodiment) generated by the system are allowed to pass through tank<b>1</b> and tank<b>2</b> with little attenuation. The effect of tank<b>1</b> and tank<b>2</b> is to further separate the input and output signals from the same node thereby producing a more stable input and output impedance. Capacitors <b>6018</b> and <b>6040</b> act to store the 50 MHz output signal energy between energy transfer pulses.

0288Further energy transfer optimization is provided by placing an inductor <b>6010</b> in series with a storage capacitor <b>6012</b> as shown. In the illustrated example, the series resonant frequency of this circuit arrangement is approximately 1 GHz. This circuit increases the energy transfer characteristic of the system. The ratio of the impedance of inductor <b>6010</b> and the impedance of the storage capacitor <b>6012</b> is preferably kept relatively small so that the majority of the energy available will be transferred to storage capacitor <b>6012</b> during operation. Exemplary output signals A and B are illustrated in <figref idref="DRAWINGS">FIGS. 60B and 60C</figref>, respectively.

0289In <figref idref="DRAWINGS">FIG. 60A</figref>, circuit components <b>6004</b> and <b>6006</b> form an input impedance match. Circuit components <b>6032</b> and <b>6030</b> form an output impedance match into a 50 ohm resistor <b>6028</b>. Circuit components <b>6022</b> and <b>6024</b> form a second output impedance match into a 50 ohm resistor <b>6026</b>. Capacitors <b>6008</b> and <b>6012</b> act as storage capacitors for the embodiment. Voltage source <b>6046</b> and resistor <b>6002</b> generate a 950 MHz signal with a 50 ohm output impedance, which are used as the input to the circuit. Circuit element <b>6016</b> includes a 150 MHz oscillator and a pulse generator, which are used to generate the energy transfer signal <b>6042</b>.

0290<figref idref="DRAWINGS">FIG. 55</figref> illustrates a shunt tank circuit <b>5510</b> in a single-ended to-single-ended system <b>5512</b>. Similarly, <figref idref="DRAWINGS">FIG. 63</figref> illustrates a shunt tank circuit <b>6310</b> in a system <b>6312</b>. The tank circuits <b>5510</b> and <b>6310</b> lower driving source impedance, which improves transient response. The tank circuits <b>5510</b> and <b>6310</b> are able store the energy from the input signal and provide a low driving source impedance to transfer that energy throughout the aperture of the closed switch. The transient nature of the switch aperture can be viewed as having a response that, in addition to including the input frequency, has large component frequencies above the input frequency, (i.e. higher frequencies than the input frequency are also able to effectively pass through the aperture). Resonant circuits or structures, for example resonant tanks <b>5510</b> or <b>6310</b>, can take advantage of this by being able to transfer energy throughout the switch's transient frequency response (i.e. the capacitor in the resonant tank appears as a low driving source impedance during the transient period of the aperture).

0291The example tank and resonant structures described above are for illustrative purposes and are not limiting. Alternate configurations can be utilized. The various resonant tanks and structures discussed can be combined or utilized independently as is now apparent.

02923.5 Charge and Power Transfer Concepts

0293Concepts of charge transfer are now described with reference to <figref idref="DRAWINGS">FIGS. 71A-F</figref>. <figref idref="DRAWINGS">FIG. 71A</figref> illustrates a circuit <b>7102</b>, including a switch S and a capacitor <b>7106</b> having a capacitance C. The switch S is controlled by a control signal <b>7108</b>, which includes pulses <b>19010</b> having apertures T.

0294In <figref idref="DRAWINGS">FIG. 71B</figref>, Equation 10 illustrates that the charge q on a capacitor having a capacitance C, such as the capacitor <b>7106</b>, is proportional to the voltage V across the capacitor, where: <ul id="ul0019" list-style="none"><li id="ul0019-0001" num="0000"><ul id="ul0020" list-style="none"><li id="ul0020-0001" num="0295">q=Charge in Coulombs</li><li id="ul0020-0002" num="0296">C=Capacitance in Farads</li><li id="ul0020-0003" num="0297">V=Voltage in Volts</li><li id="ul0020-0004" num="0298">A=Input Signal Amplitude</li></ul></li></ul>

0299Where the voltage V is represented by Equation 11, Equation 10 can be rewritten as Equation 12. The change in charge Δq over time t is illustrated as in Equation 13 as Δq(t), which can be rewritten as Equation 14. Using the sum-to-product trigonometric identity of Equation 15, Equation 14 can be rewritten as Equation 16, which can be rewritten as equation 17.

0300Note that the sin term in Equation 11 is a function of the aperture T only. Thus, Δq(t) is at a maximum when T is equal to an odd multiple of π (i.e., π, 3π, 5π, . . . ). Therefore, the capacitor <b>7106</b> experiences the greatest change in charge when the aperture T has a value of π or a time interval representative of 180 degrees of the input sinusoid. Conversely, when T is equal to 2π, 4π, 6π, . . . , minimal charge is transferred.

0301Equations 18, 19, and 20 solve for q(t) by integrating Equation 10, allowing the charge on the capacitor <b>7106</b> with respect to time to be graphed on the same axis as the input sinusoid sin(t), as illustrated in the graph of <figref idref="DRAWINGS">FIG. 71C</figref>. As the aperture T decreases in value or tends toward an impulse, the phase between the charge on the capacitor C or q(t) and sin(t) tend toward zero. This is illustrated in the graph of <figref idref="DRAWINGS">FIG. 71D</figref>, which indicates that the maximum impulse charge transfer occurs near the input voltage maxima. As this graph indicates, considerably less charge is transferred as the value of T decreases.

0302Power/charge relationships are illustrated in Equations 21-26 of <figref idref="DRAWINGS">FIG. 71E</figref>, where it is shown that power is proportional to charge, and transferred charge is inversely proportional to insertion loss.

0303Concepts of insertion loss are illustrated in <figref idref="DRAWINGS">FIG. 71F</figref>. Generally, the noise figure of a lossy passive device is numerically equal to the device insertion loss. Alternatively, the noise figure for any device cannot be less that its insertion loss. Insertion loss can be expressed by Equation 27 or 28. From the above discussion, it is observed that as the aperture T increases, more charge is transferred from the input to the capacitor <b>7106</b>, which increases power transfer from the input to the output. It has been observed that it is not necessary to accurately reproduce the input voltage at the output because relative modulated amplitude and phase information is retained in the transferred power.

03043.6 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration

03053.6.1 Varying Input and Output Impedances

0306In an embodiment of the invention, the energy transfer signal (i.e., control signal <b>2006</b> in <figref idref="DRAWINGS">FIG. 20A</figref>), is used to vary the input impedance seen by the EM Signal <b>2004</b> and to vary the output impedance driving a load. An example of this embodiment is described below using a gated transfer module <b>5101</b> shown in <figref idref="DRAWINGS">FIG. 51A</figref>. The method described below is not limited to the gated transfer module <b>5101</b>.

0307In <figref idref="DRAWINGS">FIG. 51A</figref>, when switch <b>5106</b> is closed, the impedance looking into circuit <b>5102</b> is substantially the impedance of a storage module, illustrated here as a storage capacitance <b>5108</b>, in parallel with the impedance of a load <b>5112</b>. When the switch <b>5106</b> is open, the impedance at point <b>5114</b> approaches infinity. It follows that the average impedance at point <b>5114</b> can be varied from the impedance of the storage module illustrated in parallel with the load <b>5112</b>, to the highest obtainable impedance when switch <b>5106</b> is open, by varying the ratio of the time that switch <b>5106</b> is open to the time switch <b>5106</b> is closed. The switch <b>5106</b> is controlled by an energy transfer signal <b>5110</b>. Thus the impedance at point <b>5114</b> can be varied by controlling the aperture width of the energy transfer signal in conjunction with the aliasing rate.

0308An example method of altering the energy transfer signal <b>5106</b> of <figref idref="DRAWINGS">FIG. 51A</figref> is now described with reference to <figref idref="DRAWINGS">FIG. 49A</figref>, where a circuit <b>4902</b> receives an input oscillating signal <b>4906</b> and outputs a pulse train shown as doubler output signal <b>4904</b>. The circuit <b>4902</b> can be used to generate the energy transfer signal <b>5106</b>. Example waveforms of <b>4904</b> are shown on <figref idref="DRAWINGS">FIG. 49C</figref>.

0309It can be shown that by varying the delay of the signal propagated by the inverter <b>4908</b>, the width of the pulses in the doubler output signal <b>4904</b> can be varied. Increasing the delay of the signal propagated by inverter <b>4908</b>, increases the width of the pulses. The signal propagated by inverter <b>4908</b> can be delayed by introducing a R/C low pass network in the output of inverter <b>4908</b>. Other means of altering the delay of the signal propagated by inverter <b>4908</b> will be well known to those skilled in the art.

03103.6.2 Real Time Aperture Control

0311In an embodiment, the aperture width/duration is adjusted in real time. For example, referring to the timing diagrams in <figref idref="DRAWINGS">FIGS. 64B-F</figref>, a clock signal <b>6414</b> (FIG. <b>64</b>B) is utilized to generate an energy transfer signal <b>6416</b> (<figref idref="DRAWINGS">FIG. 64F</figref>), which includes energy transfer pluses <b>6418</b>, having variable apertures <b>6420</b>. In an embodiment, the clock signal <b>6414</b> is inverted as illustrated by inverted clock signal <b>6422</b> (<figref idref="DRAWINGS">FIG. 64D</figref>). The clock signal <b>6414</b> is also delayed, as illustrated by delayed clock signal <b>6424</b> (<figref idref="DRAWINGS">FIG. 64E</figref>). The inverted clock signal <b>6414</b> and the delayed clock signal <b>6424</b> are then ANDed together, generating an energy transfer signal <b>6416</b>, which is active—energy transfer pulses <b>6418</b>—when the delayed clock signal <b>6424</b> and the inverted clock signal <b>6422</b> are both active. The amount of delay imparted to the delayed clock signal <b>6424</b> substantially determines the width or duration of the apertures <b>6420</b>. By varying the delay in real time, the apertures are adjusted in real time.

0312In an alternative implementation, the inverted clock signal <b>6422</b> is delayed relative to the original clock signal <b>6414</b>, and then ANDed with the original clock signal <b>6414</b>. Alternatively, the original clock signal <b>6414</b> is delayed then inverted, and the result ANDed with the original clock signal <b>6414</b>.

0313<figref idref="DRAWINGS">FIG. 64A</figref> illustrates an exemplary real time aperture control system <b>6402</b> that can be utilized to adjust apertures in real time. The example real time aperture control system <b>6402</b> includes an RC circuit <b>6404</b>, which includes a voltage variable capacitor <b>6412</b> and a resistor <b>6426</b>. The real time aperture control system <b>6402</b> also includes an inverter <b>6406</b> and an AND gate <b>6408</b>. The AND gate <b>6408</b> optionally includes an enable input <b>6410</b> for enabling/disabling the AND gate <b>6408</b>. The RC circuit <b>6404</b>. The real time aperture control system <b>6402</b> optionally includes an amplifier <b>6428</b>.

0314Operation of the real time aperture control circuit is described with reference to the timing diagrams of <figref idref="DRAWINGS">FIGS. 64B-F</figref>. The real time control system <b>6402</b> receives the input clock signal <b>6414</b>, which is provided to both the inverter <b>6406</b> and to the RC circuit <b>6404</b>. The inverter <b>6406</b> outputs the inverted clock signal <b>6422</b> and presents it to the AND gate <b>6408</b>. The RC circuit <b>6404</b> delays the clock signal <b>6414</b> and outputs the delayed clock signal <b>6424</b>. The delay is determined primarily by the capacitance of the voltage variable capacitor <b>6412</b>. Generally, as the capacitance decreases, the delay decreases.

0315The delayed clock signal <b>6424</b> is optionally amplified by the optional amplifier <b>6428</b>, before being presented to the AND gate <b>6408</b>. Amplification is desired, for example, where the RC constant of the RC circuit <b>6404</b> attenuates the signal below the threshold of the AND gate <b>6408</b>.

0316The AND gate <b>6408</b> ANDs the delayed clock signal <b>6424</b>, the inverted clock signal <b>6422</b>, and the optional Enable signal <b>6410</b>, to generate the energy transfer signal <b>6416</b>. The apertures <b>6420</b> are adjusted in real time by varying the voltage to the voltage variable capacitor <b>6412</b>.

0317In an embodiment, the apertures <b>6420</b> are controlled to optimize power transfer. For example, in an embodiment, the apertures <b>6420</b> are controlled to maximize power transfer. Alternatively, the apertures <b>6420</b> are controlled for variable gain control (e.g. automatic gain control—AGC). In this embodiment, power transfer is reduced by reducing the apertures <b>6420</b>.

0318As can now be readily seen from this disclosure, many of the aperture circuits presented, and others, can be modified as in circuits illustrated in <figref idref="DRAWINGS">FIGS. 46</figref> H-K. Modification or selection of the aperture can be done at the design level to remain a fixed value in the circuit, or in an alternative embodiment, may be dynamically adjusted to compensate for, or address, various design goals such as receiving RF signals with enhanced efficiency that are in distinctively different bands of operation, e.g. RF signals at 900 MHZ and 1.8 GHz.

03193.7 Adding a Bypass Network

0320In an embodiment of the invention, a bypass network is added to improve the efficiency of the energy transfer module. Such a bypass network can be viewed as a means of synthetic aperture widening. Components for a bypass network are selected so that the bypass network appears substantially lower impedance to transients of the switch module (i.e., frequencies greater than the received EM signal) and appears as a moderate to high impedance to the input EM signal (e.g., greater that 100 Ohms at the RF frequency).

0321The time that the input signal is now connected to the opposite side of the switch module is lengthened due to the shaping caused by this network, which in simple realizations may be a capacitor or series resonant inductor-capacitor. A network that is series resonant above the input frequency would be a typical implementation. This shaping improves the conversion efficiency of an input signal that would otherwise, if one considered the aperture of the energy transfer signal only, be relatively low in frequency to be optimal.

0322For example, referring to <figref idref="DRAWINGS">FIG. 61</figref> a bypass network <b>6102</b> (shown in this instance as capacitor <b>6112</b>), is shown bypassing switch module <b>6104</b>. In this embodiment the bypass network increases the efficiency of the energy transfer module when, for example, less than optimal aperture widths were chosen for a given input frequency on the energy transfer signal <b>6106</b>. The bypass network <b>6102</b> could be of different configurations than shown in <figref idref="DRAWINGS">FIG. 61</figref>. Such an alternate is illustrated in <figref idref="DRAWINGS">FIG. 57</figref>. Similarly, <figref idref="DRAWINGS">FIG. 62</figref> illustrates another example bypass network <b>6202</b>, including a capacitor <b>6204</b>.

0323The following discussion will demonstrate the effects of a minimized aperture and the benefit provided by a bypassing network. Beginning with an initial circuit having a 550 ps aperture in <figref idref="DRAWINGS">FIG. 65</figref>, its output is seen to be 2.8 mVpp applied to a 50 ohm load in <figref idref="DRAWINGS">FIG. 69A</figref>. Changing the aperture to 270 ps as shown in <figref idref="DRAWINGS">FIG. 66</figref> results in a diminished output of 2.5 Vpp applied to a 50 ohm load as shown in <figref idref="DRAWINGS">FIG. 69B</figref>. To compensate for this loss, a bypass network may be added, a specific implementation is provided in <figref idref="DRAWINGS">FIG. 67</figref>. The result of this addition is that 3.2 Vpp can now be applied to the 50 ohm load as shown in <figref idref="DRAWINGS">FIG. 70A</figref>. The circuit with the bypass network in <figref idref="DRAWINGS">FIG. 67</figref> also had three values adjusted in the surrounding circuit to compensate for the impedance changes introduced by the bypass network and narrowed aperture. <figref idref="DRAWINGS">FIG. 68</figref> verifies that those changes added to the circuit, but without the bypass network, did not themselves bring about the increased efficiency demonstrated by the embodiment in <figref idref="DRAWINGS">FIG. 67</figref> with the bypass network. <figref idref="DRAWINGS">FIG. 70B</figref> shows the result of using the circuit in <figref idref="DRAWINGS">FIG. 68</figref> in which only 1.88 Vpp was able to be applied to a 50 ohm load.

03243.8 Modifying the Energy Transfer Signal Utilizing Feedback

0325<figref idref="DRAWINGS">FIG. 47</figref> shows an embodiment of a system <b>4701</b> which uses down-converted Signal <b>4708</b>B as feedback <b>4706</b> to control various characteristics of the energy transfer module <b>4704</b> to modify the down-converted signal <b>4708</b>B.

0326Generally, the amplitude of the down-converted signal <b>4708</b>B varies as a function of the frequency and phase differences between the EM signal <b>4504</b> and the energy transfer signal <b>4506</b>. In an embodiment, the down-converted signal <b>4708</b>B is used as the feedback <b>4706</b> to control the frequency and phase relationship between the EM signal <b>4504</b> and the energy transfer signal <b>4506</b>. This can be accomplished using the example logic in <figref idref="DRAWINGS">FIG. 52A</figref>. The example circuit in <figref idref="DRAWINGS">FIG. 52A</figref> can be included in the energy transfer signal module <b>4702</b>. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. In this embodiment a state-machine is used as an example.

0327In the example of <figref idref="DRAWINGS">FIG. 52A</figref>, a state machine <b>5204</b> reads an analog to digital converter, A/D <b>5202</b>, and controls a digital to analog converter, DAC <b>5206</b>. In an embodiment, the state machine <b>5204</b> includes 2 memory locations, Previous and Current, to store and recall the results of reading A/D <b>5202</b>. In an embodiment, the state machine <b>5204</b> utilizes at least one memory flag.

0328The DAC <b>5206</b> controls an input to a voltage controlled oscillator, VCO <b>5208</b>. VCO <b>5208</b> controls a frequency input of a pulse generator <b>5210</b>, which, in an embodiment, is substantially similar to the pulse generator shown in <figref idref="DRAWINGS">FIG. 46C</figref>. The pulse generator <b>5210</b> generates energy transfer signal <b>4506</b>.

0329In an embodiment, the state machine <b>5204</b> operates in accordance with a state machine flowchart <b>5219</b> in <figref idref="DRAWINGS">FIG. 52B</figref>. The result of this operation is to modify the frequency and phase relationship between the energy transfer signal <b>4506</b> and the EM signal <b>4504</b>, to substantially maintain the amplitude of the down-converted signal <b>4708</b>B at an optimum level.

0330The amplitude of the down-converted signal <b>4708</b>B can be made to vary with the amplitude of the energy transfer signal <b>4506</b>. In an embodiment where the switch module <b>6502</b> is a FET as shown in <figref idref="DRAWINGS">FIG. 45A</figref>, wherein the gate <b>4518</b> receives the energy transfer signal <b>4506</b>, the amplitude of the energy transfer signal <b>4506</b> can determine the “on” resistance of the FET, which affects the amplitude of the down-converted signal <b>4708</b>B. The energy transfer signal module <b>4702</b>, as shown in <figref idref="DRAWINGS">FIG. 52C</figref>, can be an analog circuit that enables an automatic gain control function. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention.

03313.9 Other Implementations

0332The implementations described above are provided for purposes of illustration. These implementations are not intended to limit the invention. Alternate implementations, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate implementations fall within the scope and spirit of the present invention.

03333.10 Example Energy Transfer Down-Converters

0334Example implementations are described below for illustrative purposes. The invention is not limited to these examples.

0335<figref idref="DRAWINGS">FIG. 53</figref> is a schematic diagram of an exemplary circuit to down convert a 915 MHZ signal to a 5 MHZ signal using a 101.1 MHZ clock.

0336<figref idref="DRAWINGS">FIG. 54</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 53</figref>. Waveform <b>5302</b> is the input to the circuit showing the distortions caused by the switch closure. Waveform <b>5304</b> is the unfiltered output at the storage unit. Waveform <b>5306</b> is the impedance matched output of the down-converter on a different time scale.

0337<figref idref="DRAWINGS">FIG. 55</figref> is a schematic diagram of an exemplary circuit to down-convert a 915 MHZ signal to a 5 MHZ signal using a 101.1 MHZ clock. The circuit has additional tank circuitry to improve conversion efficiency.

0338<figref idref="DRAWINGS">FIG. 56</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 55</figref>. Waveform <b>5502</b> is the input to the circuit showing the distortions caused by the switch closure. Waveform <b>5504</b> is the unfiltered output at the storage unit. Waveform <b>5506</b> is the output of the down-converter after the impedance match circuit.

0339<figref idref="DRAWINGS">FIG. 57</figref> is a schematic diagram of an exemplary circuit to down-convert a 915 MHZ signal to a 5 MHZ signal using a 101.1 MHZ clock. The circuit has switch bypass circuitry to improve conversion efficiency.

0340<figref idref="DRAWINGS">FIG. 58</figref> shows example simulation waveforms for the circuit of <figref idref="DRAWINGS">FIG. 57</figref>. Waveform <b>5702</b> is the input to the circuit showing the distortions caused by the switch closure. Waveform <b>5704</b> is the unfiltered output at the storage unit. Waveform <b>5706</b> is the output of the down-converter after the impedance match circuit.

0341<figref idref="DRAWINGS">FIG. 59</figref> shows a schematic of the example circuit in <figref idref="DRAWINGS">FIG. 53</figref> connected to an FSK source that alternates between 913 and 917 MHZ, at a baud rate of 500 Kbaud. <figref idref="DRAWINGS">FIG. 72</figref> shows the original FSK waveform <b>5902</b> and the down-converted waveform <b>5904</b> at the output of the load impedance match circuit.

4. FREQUENCY UP-CONVERSION

0342The present invention is directed to systems and methods of frequency up-conversion, and applications of same.

0343An example frequency up-conversion system <b>300</b> is illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. The frequency up-conversion system <b>300</b> is now described.

0344An input signal <b>302</b> (designated as “Control Signal” in <figref idref="DRAWINGS">FIG. 3</figref>) is accepted by a switch module <b>304</b>. For purposes of example only, assume that the input signal <b>302</b> is a FM input signal <b>606</b>, an example of which is shown in <figref idref="DRAWINGS">FIG. 6C</figref>. FM input signal <b>606</b> may have been generated by modulating information signal <b>602</b> onto oscillating signal <b>604</b> (<figref idref="DRAWINGS">FIGS. 6A and 6B</figref>). It should be understood that the invention is not limited to this embodiment. The information signal <b>602</b> can be analog, digital, or any combination thereof, and any modulation scheme can be used.

0345The output of switch module <b>304</b> is a harmonically rich signal <b>306</b>, shown for example in <figref idref="DRAWINGS">FIG. 6D</figref> as a harmonically rich signal <b>608</b>. The harmonically rich signal <b>608</b> has a continuous and periodic waveform.

0346<figref idref="DRAWINGS">FIG. 6E</figref> is an expanded view of two sections of harmonically rich signal <b>608</b>, section <b>610</b> and section <b>612</b>. The harmonically rich signal <b>608</b> may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment). For ease of discussion, the term “rectangular waveform” is used to refer to waveforms that are substantially rectangular. In a similar manner, the term “square wave” refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed.

0347Harmonically rich signal <b>608</b> is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal <b>608</b>. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is referred to as the first harmonic. <figref idref="DRAWINGS">FIG. 6F</figref> and <figref idref="DRAWINGS">FIG. 6G</figref> show separately the sinusoidal components making up the first, third, and fifth harmonics of section <b>610</b> and section <b>612</b>. (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal <b>608</b> is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in <figref idref="DRAWINGS">FIG. 6H</figref>.

0348The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal <b>306</b> and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal <b>306</b>. According to an embodiment of the invention, the input signal <b>606</b> may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).

0349A filter <b>308</b> filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal <b>310</b>, shown for example as a filtered output signal <b>614</b> in <figref idref="DRAWINGS">FIG. 6I</figref>.

0350<figref idref="DRAWINGS">FIG. 4</figref> illustrates an example universal frequency up-conversion (UFU) module <b>401</b>. The UFU module <b>401</b> includes an example switch module <b>304</b>, which comprises a bias signal <b>402</b>, a resistor or impedance <b>404</b>, a universal frequency translator (UFT) <b>450</b>, and a ground <b>408</b>. The UFT <b>450</b> includes a switch <b>406</b>. The input signal <b>302</b> (designated as “Control Signal” in <figref idref="DRAWINGS">FIG. 4</figref>) controls the switch <b>406</b> in the UFT <b>450</b>, and causes it to close and open. Harmonically rich signal <b>306</b> is generated at anode <b>405</b> located between the resistor or impedance <b>404</b> and the switch <b>406</b>.

0351Also in <figref idref="DRAWINGS">FIG. 4</figref>, it can be seen that an example filter <b>308</b> is comprised of a capacitor <b>410</b> and an inductor <b>412</b> shunted to a ground <b>414</b>. The filter is designed to filter out the undesired harmonics of harmonically rich signal <b>306</b>.

0352The invention is not limited to the UFU embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0353For example, in an alternate embodiment shown in <figref idref="DRAWINGS">FIG. 5</figref>, an unshaped input signal <b>501</b> is routed to a pulse shaping module <b>502</b>. The pulse shaping module <b>502</b> modifies the unshaped input signal <b>501</b> to generate a (modified) input signal <b>302</b> (designated as the “Control Signal” in <figref idref="DRAWINGS">FIG. 5</figref>). The input signal <b>302</b> is routed to the switch module <b>304</b>, which operates in the manner described above. Also, the filter <b>308</b> of <figref idref="DRAWINGS">FIG. 5</figref> operates in the manner described above.

0354The purpose of the pulse shaping module <b>502</b> is to define the pulse width of the input signal <b>302</b>. Recall that the input signal <b>302</b> controls the opening and closing of the switch <b>406</b> in switch module <b>304</b>. During such operation, the pulse width of the input signal <b>302</b> establishes the pulse width of the harmonically rich signal <b>306</b>. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal <b>306</b> are a function of at least the pulse width of the harmonically rich signal <b>306</b>. As such, the pulse width of the input signal <b>302</b> contributes to setting the relative amplitudes of the harmonics of harmonically rich signal <b>306</b>.

0355Further details of up-conversion as described in this section are presented in pending U.S. application “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998, incorporated herein by reference in its entirety.

5. ENHANCED SIGNAL RECEPTION

0356The present invention is directed to systems and methods of enhanced signal reception (ESR), and applications of same.

0357Referring to <figref idref="DRAWINGS">FIG. 21</figref>, transmitter <b>2104</b> accepts a modulating baseband signal <b>2102</b> and generates (transmitted) redundant spectrums <b>2106</b><i>a</i>-<i>n</i>, which are sent over communications medium <b>2108</b>. Receiver <b>2112</b> recovers a demodulated baseband signal <b>2114</b> from (received) redundant spectrums <b>2110</b><i>a</i>-<i>n</i>. Demodulated baseband signal <b>2114</b> is representative of the modulating baseband signal <b>2102</b>, where the level of similarity between the modulating baseband signal <b>2114</b> and the modulating baseband signal <b>2102</b> is application dependent.

0358Modulating baseband signal <b>2102</b> is preferably any information signal desired for transmission and/or reception. An example modulating baseband signal <b>2202</b> is illustrated in <figref idref="DRAWINGS">FIG. 22A</figref>, and has an associated modulating baseband spectrum <b>2204</b> and image spectrum <b>2203</b> that are illustrated in <figref idref="DRAWINGS">FIG. 22B</figref>. Modulating baseband signal <b>2202</b> is illustrated as an analog signal in <figref idref="DRAWINGS">FIG. 22</figref><i>a</i>, but could also be a digital signal, or combination thereof. Modulating baseband signal <b>2202</b> could be a voltage (or current) characterization of any number of real world occurrences, including for example and without limitation, the voltage (or current) representation for a voice signal.

0359Each transmitted redundant spectrum <b>2106</b><i>a</i>-<i>n </i>contains the necessary information to substantially reconstruct the modulating baseband signal <b>2102</b>. In other words, each redundant spectrum <b>2106</b><i>a</i>-<i>n </i>contains the necessary amplitude, phase, and frequency information to reconstruct the modulating baseband signal <b>2102</b>.

0360<figref idref="DRAWINGS">FIG. 22C</figref> illustrates example transmitted redundant spectrums <b>2206</b><i>b</i>-<i>d</i>. Transmitted redundant spectrums <b>2206</b><i>b</i>-<i>d </i>are illustrated to contain three redundant spectrums for illustration purposes only. Any number of redundant spectrums could be generated and transmitted as will be explained in following discussions.

0361Transmitted redundant spectrums <b>2206</b><i>b</i>-<i>d </i>are centered at f₁, with a frequency spacing f₂between adjacent spectrums. Frequencies f₁and f₂are dynamically adjustable in real-time as will be shown below. <figref idref="DRAWINGS">FIG. 22D</figref> illustrates an alternate embodiment, where redundant spectrums <b>2208</b><i>c,d </i>are centered on unmodulated oscillating signal <b>2209</b> at f₁(Hz). Oscillating signal <b>2209</b> may be suppressed if desired using, for example, phasing techniques or filtering techniques. Transmitted redundant spectrums are preferably above baseband frequencies as is represented by break <b>2205</b> in the frequency axis of <figref idref="DRAWINGS">FIGS. 22C and 22D</figref>.

0362Received redundant spectrums <b>2110</b><i>a</i>-<i>n </i>are substantially similar to transmitted redundant spectrums <b>2106</b><i>a</i>-<i>n</i>, except for the changes introduced by the communications medium <b>2108</b>. Such changes can include but are not limited to signal attenuation, and signal interference. <figref idref="DRAWINGS">FIG. 22E</figref> illustrates example received redundant spectrums <b>2210</b><i>b</i>-<i>d</i>. Received redundant spectrums <b>2210</b><i>b</i>-<i>d </i>are substantially similar to transmitted redundant spectrums <b>2206</b><i>b</i>-<i>d</i>, except that redundant spectrum <b>2210</b><i>c </i>includes an undesired jamming signal spectrum <b>2211</b> in order to illustrate some advantages of the present invention. Jamming signal spectrum <b>2211</b> is a frequency spectrum associated with a jamming signal. For purposes of this invention, a “jamming signal” refers to any unwanted signal, regardless of origin, that may interfere with the proper reception and reconstruction of an intended signal. Furthermore, the jamming signal is not limited to tones as depicted by spectrum <b>2211</b>, and can have any spectral shape, as will be understood by those skilled in the art(s).

0363As stated above, demodulated baseband signal <b>2114</b> is extracted from one or more of received redundant spectrums <b>2210</b><i>b</i>-<i>d</i>. <figref idref="DRAWINGS">FIG. 22F</figref> illustrates example demodulated baseband signal <b>2212</b> that is, in this example, substantially similar to modulating baseband signal <b>2202</b> (<figref idref="DRAWINGS">FIG. 22A</figref>); where in practice, the degree of similarity is application dependent.

0364An advantage of the present invention should now be apparent. The recovery of modulating baseband signal <b>2202</b> can be accomplished by receiver <b>2112</b> in spite of the fact that high strength jamming signal(s) (e.g. jamming signal spectrum <b>2211</b>) exist on the communications medium. The intended baseband signal can be recovered because multiple redundant spectrums are transmitted, where each redundant spectrum carries the necessary information to reconstruct the baseband signal. At the destination, the redundant spectrums are isolated from each other so that the baseband signal can be recovered even if one or more of the redundant spectrums are corrupted by a jamming signal.

0365Transmitter <b>2104</b> will now be explored in greater detail. <figref idref="DRAWINGS">FIG. 23A</figref> illustrates transmitter <b>2301</b>, which is one embodiment of transmitter <b>2104</b> that generates redundant spectrums configured similar to redundant spectrums <b>2206</b><i>b</i>-<i>d</i>. Transmitter <b>2301</b> includes generator <b>2303</b>, optional spectrum processing module <b>2304</b>, and optional medium interface module <b>2320</b>. Generator <b>2303</b> includes: first oscillator <b>2302</b>, second oscillator <b>2309</b>, first stage modulator <b>2306</b>, and second stage modulator <b>2310</b>.

0366Transmitter <b>2301</b> operates as follows. First oscillator <b>2302</b> and second oscillator <b>2309</b> generate a first oscillating signal <b>2305</b> and second oscillating signal <b>2312</b>, respectively. First stage modulator <b>2306</b> modulates first oscillating signal <b>2305</b> with modulating baseband signal <b>2202</b>, resulting in modulated signal <b>2308</b>. First stage modulator <b>2306</b> may implement any type of modulation including but not limited to: amplitude modulation, frequency modulation, phase modulation, combinations thereof, or any other type of modulation. Second stage modulator <b>2310</b> modulates modulated signal <b>2308</b> with second oscillating signal <b>2312</b>, resulting in multiple redundant spectrums <b>2206</b><i>a</i>-<i>n </i>shown in <figref idref="DRAWINGS">FIG. 23B</figref>. Second stage modulator <b>2310</b> is preferably a phase modulator, or a frequency modulator, although other types of modulation may be implemented including but not limited to amplitude modulation. Each redundant spectrum <b>2206</b><i>a</i>-<i>n </i>contains the necessary amplitude, phase, and frequency information to substantially reconstruct the modulating baseband signal <b>2202</b>.

0367Redundant spectrums <b>2206</b><i>a</i>-<i>n </i>are substantially centered around f₁, which is the characteristic frequency of first oscillating signal <b>2305</b>. Also, each redundant spectrum <b>2206</b><i>a</i>-<i>n </i>(except for <b>2206</b><i>c</i>) is offset from f₁by approximately a multiple of f₂(Hz), where f₂is the frequency of the second oscillating signal <b>2312</b>. Thus, each redundant spectrum <b>2206</b><i>a</i>-<i>n </i>is offset from an adjacent redundant spectrum by f₂(Hz). This allows the spacing between adjacent redundant spectrums to be adjusted (or tuned) by changing f₂that is associated with second oscillator <b>2309</b>. Adjusting the spacing between adjacent redundant spectrums allows for dynamic real-time tuning of the bandwidth occupied by redundant spectrums <b>2206</b><i>a</i>-<i>n. </i>

0368In one embodiment, the number of redundant spectrums <b>2206</b><i>a</i>-<i>n </i>generated by transmitter <b>2301</b> is arbitrary and may be unlimited as indicated by the “a-n” designation for redundant spectrums <b>2206</b><i>a</i>-<i>n</i>. However, a typical communications medium will have a physical and/or administrative limitations (i.e. FCC regulations) that restrict the number of redundant spectrums that can be practically transmitted over the communications medium. Also, there may be other reasons to limit the number of redundant spectrums transmitted. Therefore, preferably, the transmitter <b>2301</b> will include an optional spectrum processing module <b>2304</b> to process the redundant spectrums <b>2206</b><i>a</i>-<i>n </i>prior to transmission over communications medium <b>2108</b>.

0369In one embodiment, spectrum processing module <b>2304</b> includes a filter with a passband <b>2207</b> (<figref idref="DRAWINGS">FIG. 23C</figref>) to select redundant spectrums <b>2206</b><i>b</i>-<i>d </i>for transmission. This will substantially limit the frequency bandwidth occupied by the redundant spectrums to the passband <b>2207</b>. In one embodiment, spectrum processing module <b>2304</b> also up converts redundant spectrums and/or amplifies redundant spectrums prior to transmission over the communications medium <b>2108</b>. Finally, medium interface module <b>2320</b> transmits redundant spectrums over the communications medium <b>2108</b>. In one embodiment, communications medium <b>2108</b> is an over-the-air link and medium interface module <b>2320</b> is an antenna. Other embodiments for communications medium <b>2108</b> and medium interface module <b>2320</b> will be understood based on the teachings contained herein.

0370<figref idref="DRAWINGS">FIG. 23D</figref> illustrates transmitter <b>2321</b>, which is one embodiment of transmitter <b>2104</b> that generates redundant spectrums configured similar to redundant spectrums <b>2208</b><i>c</i>-<i>d </i>and unmodulated spectrum <b>2209</b>. Transmitter <b>2321</b> includes generator <b>2311</b>, spectrum processing module <b>2304</b>, and (optional) medium interface module <b>2320</b>. Generator <b>2311</b> includes: first oscillator <b>2302</b>, second oscillator <b>2309</b>, first stage modulator <b>2306</b>, and second stage modulator <b>2310</b>.

0371As shown in <figref idref="DRAWINGS">FIG. 23D</figref>, many of the components in transmitter <b>2321</b> are similar to those in transmitter <b>2301</b>. However, in this embodiment, modulating baseband signal <b>2202</b> modulates second oscillating signal <b>2312</b>. Transmitter <b>2321</b> operates as follows. First stage modulator <b>2306</b> modulates second oscillating signal <b>2312</b> with modulating baseband signal <b>2202</b>, resulting in modulated signal <b>2322</b>. As described earlier, first stage modulator <b>2306</b> can effect any type of modulation including but not limited to: amplitude modulation frequency modulation, combinations thereof, or any other type of modulation. Second stage modulator <b>2310</b> modulates first oscillating signal <b>2304</b> with modulated signal <b>2322</b>, resulting in redundant spectrums <b>2208</b><i>a</i>-<i>n</i>, as shown in <figref idref="DRAWINGS">FIG. 23E</figref>. Second stage modulator <b>2310</b> is preferably a phase or frequency modulator, although other modulators could used including but not limited to an amplitude modulator.

0372Redundant spectrums <b>2208</b><i>a</i>-<i>n </i>are centered on unmodulated spectrum <b>2209</b> (at f₁Hz), and adjacent spectrums are separated by f₂Hz. The number of redundant spectrums <b>2208</b><i>a</i>-<i>n </i>generated by generator <b>2311</b> is arbitrary and unlimited, similar to spectrums <b>2206</b><i>a</i>-<i>n </i>discussed above. Therefore, optional spectrum processing module <b>2304</b> may also include a filter with passband <b>2325</b> to select, for example, spectrums <b>2208</b><i>c,d </i>for transmission over communications medium <b>2108</b>. In addition, optional spectrum processing module <b>2304</b> may also include a filter (such as a bands top filter) to attenuate unmodulated spectrum <b>2209</b>. Alternatively, unmodulated spectrum <b>2209</b> may be attenuated by using phasing techniques during redundant spectrum generation. Finally, (optional) medium interface module <b>2320</b> transmits redundant spectrums <b>2208</b><i>c,d </i>over communications medium <b>2108</b>.

0373Receiver <b>2112</b> will now be explored in greater detail to illustrate recovery of a demodulated baseband signal from received redundant spectrums. <figref idref="DRAWINGS">FIG. 24A</figref> illustrates receiver <b>2430</b>, which is one embodiment of receiver <b>2112</b>. Receiver <b>2430</b> includes optional medium interface module <b>2402</b>, down-converter <b>2404</b>, spectrum isolation module <b>2408</b>, and data extraction module <b>2414</b>. Spectrum isolation module <b>2408</b> includes filters <b>2410</b><i>a</i>-<i>c</i>. Data extraction module <b>2414</b> includes demodulators <b>2416</b><i>a</i>-<i>c</i>, error check modules <b>2420</b><i>a</i>-<i>c</i>, and arbitration module <b>2424</b>. Receiver <b>2430</b> will be discussed in relation to the signal diagrams in <figref idref="DRAWINGS">FIGS. 24B-24J</figref>.

0374In one embodiment, optional medium interface module <b>2402</b> receives redundant spectrums <b>2210</b><i>b</i>-<i>d </i>(<figref idref="DRAWINGS">FIG. 22E</figref>, and <figref idref="DRAWINGS">FIG. 24B</figref>). Each redundant spectrum <b>2210</b><i>b</i>-<i>d </i>includes the necessary amplitude, phase, and frequency information to substantially reconstruct the modulating baseband signal used to generated the redundant spectrums. However, in the present example, spectrum <b>2210</b><i>c </i>also contains jamming signal <b>2211</b>, which may interfere with the recovery of a baseband signal from spectrum <b>2210</b><i>c</i>. Down-converter <b>2404</b> down-converts received redundant spectrums <b>2210</b><i>b</i>-<i>d </i>to lower intermediate frequencies, resulting in redundant spectrums <b>2406</b><i>a</i>-<i>c </i>(<figref idref="DRAWINGS">FIG. 24C</figref>). Jamming signal <b>2211</b> is also down-converted to jamming signal <b>2407</b>, as it is contained within redundant spectrum <b>2406</b><i>b</i>. Spectrum isolation module <b>2408</b> includes filters <b>2410</b><i>a</i>-<i>c </i>that isolate redundant spectrums <b>2406</b><i>a</i>-<i>c </i>from each other (<figref idref="DRAWINGS">FIGS. 24D-24F</figref>, respectively). Demodulators <b>2416</b><i>a</i>-<i>c </i>independently demodulate spectrums <b>2406</b><i>a</i>-<i>c</i>, resulting in demodulated baseband signals <b>2418</b><i>a</i>-<i>c</i>, respectively (<figref idref="DRAWINGS">FIGS. 24G-24I</figref>). Error check modules <b>2420</b><i>a</i>-<i>c </i>analyze demodulate baseband signal <b>2418</b><i>a</i>-<i>c </i>to detect any errors. In one embodiment, each error check module <b>2420</b><i>a</i>-<i>c </i>sets an error flag <b>2422</b><i>a</i>-<i>c </i>whenever an error is detected in a demodulated baseband signal. Arbitration module <b>2424</b> accepts the demodulated baseband signals and associated error flags, and selects a substantially error-free demodulated baseband signal (<figref idref="DRAWINGS">FIG. 24J</figref>). In one embodiment, the substantially error-free demodulated baseband signal will be substantially similar to the modulating baseband signal used to generate the received redundant spectrums, where the degree of similarity is application dependent.

0375Referring to <figref idref="DRAWINGS">FIGS. 24G-I</figref>, arbitration module <b>2424</b> will select either demodulated baseband signal <b>2418</b><i>a </i>or <b>2418</b><i>c</i>, because error check module <b>2420</b><i>b </i>will set the error flag <b>2422</b><i>b </i>that is associated with demodulated baseband signal <b>2418</b><i>b. </i>

0376The error detection schemes implemented by the error detection modules include but are not limited to: cyclic redundancy check (CAC) and parity check for digital signals, and various error detections schemes for analog signal.

0377Further details of enhanced signal reception as described in this section are presented in pending U.S. application “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998, incorporated herein by reference in its entirety.

6. UNIFIED DOWN-CONVERSION AND FILTERING

0378The present invention is directed to systems and methods of unified down-conversion and filtering (UDF), and applications of same.

0379In particular, the present invention includes a unified down-converting and filtering (UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.

0380<figref idref="DRAWINGS">FIG. 17</figref> is a conceptual block diagram of a UDF module <b>1702</b> according to an embodiment of the present invention. The UDF module <b>1702</b> performs at least frequency translation and frequency selectivity.

0381The effect achieved by the UDF module <b>1702</b> is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, the UDF module <b>1702</b> effectively performs input filtering.

0382According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.

0383In embodiments of the invention, input signals <b>1704</b> received by the UDF module <b>1702</b> are at radio frequencies. The UDF module <b>1702</b> effectively operates to input filter these RF input signals <b>1704</b>. Specifically, in these embodiments, the UDF module <b>1702</b> effectively performs input, channel select filtering of the RF input signal <b>1704</b>. Accordingly, the invention achieves high selectivity at high frequencies.

0384The UDF module <b>1702</b> effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.

0385Conceptually, the UDF module <b>1702</b> includes a frequency translator <b>1708</b>. The frequency translator <b>1708</b> conceptually represents that portion of the UDF module <b>1702</b> that performs frequency translation (down conversion).

0386The UDF module <b>1702</b> also conceptually includes an apparent input filter <b>1706</b> (also sometimes called an input filtering emulator). Conceptually, the apparent input filter <b>1706</b> represents that portion of the UDF module <b>1702</b> that performs input filtering.

0387In practice, the input filtering operation performed by the UDF module <b>1702</b> is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concurrently with the frequency translation operation. This is a reason why the input filter <b>1706</b> is herein referred to as an “apparent” input filter <b>1706</b>.

0388The UDF module <b>1702</b> of the present invention includes a number of advantages. For example, high selectivity at high frequencies is realizable using the UDF module <b>1702</b>. This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, the UDF module <b>1702</b> can be designed with a filter center frequency f_Con the order of 900 MHZ, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth).

0389It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable.

0390The invention exhibits additional advantages. For example, the filtering center frequency f_Cof the UDF module <b>1702</b> can be electrically adjusted, either statically or dynamically.

0391Also, the UDF module <b>1702</b> can be designed to amplify input signals.

0392Further, the UDF module <b>1702</b> can be implemented without large resistors, capacitors, or inductors. Also, the UDF module <b>1702</b> does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module <b>1702</b> is friendly to integrated circuit design techniques and processes.

0393The features and advantages exhibited by the UDF module <b>1702</b> are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, the UDF module <b>1702</b> performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa.

0394According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and samples/instances of the output signal.

0395More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.

0396As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (IF) or baseband.

0397Next, the input sample is held (that is, delayed).

0398Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.

0399Thus, according to a preferred embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, current samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.). By operating in this manner, the UDF module preferably performs input filtering and frequency down-conversion in a unified manner.

0400<figref idref="DRAWINGS">FIGS. 19A and 19B</figref> together illustrate an example implementation of the unified down-converting and filtering (UDF) module <b>1922</b>. The UDF module <b>1922</b> performs the frequency translation operation and the frequency selectivity operation in an integrated, unified manner as described above, and as further described below.

0401In the example provided by <figref idref="DRAWINGS">FIGS. 19A and 19B</figref>, the frequency selectivity operation performed by the UDF module <b>1922</b> comprises a band-pass filtering operation according to EQ. 1, below, which is an example representation of a band-pass filtering transfer function.

0000<br /><i>VO=α</i>₁<i>z</i>⁻¹<i>VI−β</i>₁<i>z</i>⁻¹<i>VO−β</i>₀<i>z</i>⁻²<i>VO</i>  EQ. 1

0402It should be noted, however, that the invention is not limited to band-pass filtering. Instead, the invention effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof. As will be appreciated, there are many representations of any given filter type. The invention is applicable to these filter representations. Thus, EQ. 1 is referred to herein for illustrative purposes only, and is not limiting.

0403The UDF module <b>1922</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref> and <figref idref="DRAWINGS">FIG. 19B</figref>) includes a down-convert and delay module <b>1924</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>), first and second delay modules <b>1928</b> and <b>1930</b> (both shown in <figref idref="DRAWINGS">FIG. 19B</figref>), first and second scaling modules <b>1932</b> and <b>1934</b> (both shown in <figref idref="DRAWINGS">FIG. 19B</figref>), an output sample and hold module <b>1936</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>), and an (optional) output smoothing module <b>1938</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>. The down-convert and delay module <b>1924</b> and the control signal (sampling signal) together form a frequency translator <b>1708</b>. Other embodiments of the UDF module will have these components in different configurations, and/or a subset of these components, and/or additional components. For example, and without limitation, in the configuration shown in <figref idref="DRAWINGS">FIG. 19B</figref>, the output smoothing module <b>1938</b> is optional.

0404As further described below, in the example provided by <figref idref="DRAWINGS">FIGS. 19A and 19B</figref>, the down-convert and delay module <b>1924</b> and the first and second delay modules <b>1928</b> and <b>1930</b> include switches that are controlled by a clock having two phases, φ₁and φ₂. φ₁and φ₂preferably have the same frequency, and are non-overlapping (alternatively, a plurality such as two clock signals having these characteristics could be used). As used herein, the term “non-overlapping” is defined as two or more signals where only one of the signals is active at any given time. In some embodiments, signals are “active” when they are high. In other embodiments, signals are active when they are low.

0405Preferably, each of these switches closes on a rising edge of φ₁or φ₂, and opens on the next corresponding falling edge of φ₂or φ₂. However, the invention is not limited to this example. As will be apparent to persons skilled in the relevant art(s), other clock conventions can be used to control the switches.

0406In the example provided by <figref idref="DRAWINGS">FIGS. 19A and 19B</figref>, it is assumed that α₁is equal to one. Thus, the output of the down-convert and delay module <b>1924</b> is not scaled. As evident from the embodiments described above, however, the invention is not limited to this example.

0407The example UDF module <b>1922</b> has a filter center frequency of 900.2 MHZ and a filter bandwidth of 570 KHz. The pass band of the UDF module <b>1922</b> is on the order of 899.915 MHZ to 900.485 MHZ. The Q factor of the UDF module <b>1922</b> is approximately 1879 (i.e., 900.2 MHZ divided by 570 KHz).

0408The operation of the UDF module <b>1922</b> shall now be described with reference to a Table <b>1802</b> (<figref idref="DRAWINGS">FIG. 18</figref>) that indicates example values at nodes in the UDF module <b>1922</b> at a number of consecutive time increments. It is assumed in Table <b>1802</b> that the UDF module <b>1922</b> begins operating at time t−1. As indicated below, the UDF module <b>1922</b> reaches steady state a few time units after operation begins. The number of time units necessary for a given UDF module to reach steady state depends on the configuration of the UDF module, and will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

0409At the rising edge of φ₁at time t−1, a switch <b>1950</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) in the down-convert and delay module <b>1924</b> closes. This allows a capacitor <b>1952</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) to charge to the current value of an input signal, VI_t−1, such that node <b>1902</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) is at VI_t−1. This is indicated by cell <b>1804</b> in <figref idref="DRAWINGS">FIG. 18</figref>. In effect, the combination of the switch <b>1950</b> and the capacitor <b>1952</b> in the down-convert and delay module <b>1924</b> operates to translate the frequency of the input signal VI to a desired lower frequency, such as IF or baseband. Thus, the value stored in the capacitor <b>1952</b> represents an instance of a down-converted image of the input signal VI.

0410The manner in which the down-convert and delay module <b>1924</b> performs frequency down-conversion is further described elsewhere in this application, and is additionally described in pending U.S. application “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, which is herein incorporated by reference in its entirety.

0411Also at the rising edge of φ₁at time t−1, a switch <b>1958</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) in the first delay module <b>1928</b> closes, allowing a capacitor <b>1960</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) to charge to VO_t−1, such that node <b>1906</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) is at VO_t−1. This is indicated by cell <b>1806</b> in Table <b>1802</b>. (In practice, VO_t−1is undefined at this point. However, for ease of understanding, VO_t−1shall continue to be used for purposes of explanation.)

0412Also at the rising edge of φ₁at time t−1, a switch <b>1966</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) in the second delay module <b>1930</b> closes, allowing a capacitor <b>1968</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) to charge to a value stored in a capacitor <b>1964</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>). At this time, however, the value in capacitor <b>1964</b> is undefined, so the value in capacitor <b>1968</b> is undefined. This is indicated by cell <b>1807</b> in table <b>1802</b>.

0413At the rising edge of φ₂at time t−1, a switch <b>1954</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) in the down-convert and delay module <b>1924</b> closes, allowing a capacitor <b>1956</b> to charge to the level of the capacitor <b>1952</b>. Accordingly, the capacitor <b>1956</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) charges to VI_t−1, such that node <b>1904</b> (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) is at VI_t−1. This is indicated by cell <b>1810</b> in Table <b>1802</b>.

0414The UDF module <b>1922</b> may optionally include a unity gain module <b>1990</b>A (shown in <figref idref="DRAWINGS">FIG. 19A</figref>) between capacitors <b>1952</b> and <b>1956</b>. The unity gain module <b>1990</b>A operates as a current source to enable capacitor <b>1956</b> to charge without draining the charge from capacitor <b>1952</b>. For a similar reason, the UDF module <b>1922</b> may include other unity gain modules <b>1990</b>B (shown in <figref idref="DRAWINGS">FIG. 19A) through 1990G</figref> (<b>1990</b>C-<b>1990</b>G shown in <figref idref="DRAWINGS">FIG. 19B</figref>). It should be understood that, for many embodiments and applications of the invention, these unity gain modules <b>1990</b>A-<b>1990</b>G are optional. The structure and operation of the unity gain modules <b>1990</b> will be apparent to persons skilled in the relevant art(s).

0415Also at the rising edge of φ₂at time t−1, a switch <b>1962</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) in the first delay module <b>1928</b> closes, allowing a capacitor <b>1964</b> to charge to the level of the capacitor <b>1960</b>. Accordingly, the capacitor <b>1964</b> charges to VO_t−1, such that node <b>1908</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) is at VO_t−1. This is indicated by cell <b>1814</b> in Table <b>1802</b>.

0416Also at the rising edge of φ₂at time t−1, a switch <b>1970</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) in the second delay module <b>1930</b> closes, allowing a capacitor <b>1972</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) to charge to a value stored in a capacitor <b>1968</b>. At this time, however, the value in capacitor <b>1968</b> is undefined, so the value in capacitor <b>1972</b> is undefined. This is indicated by cell <b>1815</b> in table <b>1802</b>.

0417At time t, at the rising edge of φ₁, the switch <b>1950</b> in the down-convert and delay module <b>1924</b> closes. This allows the capacitor <b>1952</b> to charge to VI_t, such that node <b>1902</b> is at VI_t. This is indicated in cell <b>1816</b> of Table <b>1802</b>.

0418Also at the rising edge of φ₁at time t, the switch <b>1958</b> in the first delay module <b>1928</b> closes, thereby allowing the capacitor <b>1960</b> to charge to VO_t. Accordingly, node <b>1906</b> is at VO_t. This is indicated in cell <b>1820</b> in Table <b>1802</b>.

0419Further at the rising edge of φ₁at time t, the switch <b>1966</b> in the second delay module <b>1930</b> closes, allowing a capacitor <b>1968</b> to charge to the level of the capacitor <b>1964</b>. Therefore, the capacitor <b>1968</b> charges to VO_t−1, such that node <b>1910</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) is at VO_t−1. This is indicated by cell <b>1824</b> in Table <b>1802</b>.

0420At the rising edge of φ₂at time t, the switch <b>1954</b> in the down-convert and delay module <b>1924</b> closes, allowing the capacitor <b>1956</b> to charge to the level of the capacitor <b>1952</b>. Accordingly, the capacitor <b>1956</b> charges to VI_t, such that node <b>1904</b> is at VI_t. This is indicated by cell <b>1828</b> in Table <b>1802</b>.

0421Also at the rising edge of φ₂at time t, the switch <b>1962</b> in the first delay module <b>1928</b> closes, allowing the capacitor <b>1964</b> to charge to the level in the capacitor <b>1960</b>. Therefore, the capacitor <b>1964</b> charges to VO_t, such that node <b>1908</b> is at VO_t. This is indicated by cell <b>1832</b> in Table <b>1802</b>.

0422Further at the rising edge of φ₂at time t, the switch <b>1970</b> in the second delay module <b>1930</b> closes, allowing the capacitor <b>1972</b> in the second delay module <b>1930</b> to charge to the level of the capacitor <b>1968</b> in the second delay module <b>1930</b>. Therefore, the capacitor <b>1972</b> charges to VO_t−1, such that node <b>1912</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) is at VO_t−1. This is indicated in cell <b>1836</b> of <figref idref="DRAWINGS">FIG. 18</figref>.

0423At time t+1, at the rising edge of φ₁, the switch <b>1950</b> in the down-convert and delay module <b>1924</b> closes, allowing the capacitor <b>1952</b> to charge to VI_t+1. Therefore, node <b>1902</b> is at V_t+2, as indicated by cell <b>1838</b> of Table <b>1802</b>.

0424Also at the rising edge of φ₁at time t+1, the switch <b>1958</b> in the first delay module <b>1928</b> closes, allowing the capacitor <b>1960</b> to charge to VO_t+1. Accordingly, node <b>1906</b> is at VO_t+1, as indicated by cell <b>1842</b> in Table <b>1802</b>.

0425Further at the rising edge of φ₁at time t+1, the switch <b>1966</b> in the second delay module <b>1930</b> closes, allowing the capacitor <b>1968</b> to charge to the level of the capacitor <b>1964</b>. Accordingly, the capacitor <b>1968</b> charges to VO_t, as indicated by cell <b>1846</b> of Table <b>1802</b>.

0426In the example provided by <figref idref="DRAWINGS">FIGS. 19</figref> A and <b>19</b>B, the first scaling module <b>1932</b> scales the value at node <b>1908</b> (i.e., the output of the first delay module <b>1928</b>) by a scaling factor of −0.1. Accordingly, the value present at node <b>1914</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) at time t+1 is −0.1*VO_t. Similarly, the second scaling module <b>1934</b> scales the value present at node <b>1912</b> (i.e., the output of the second scaling module <b>1930</b>) by a scaling factor of −0.8. Accordingly, the value present at node <b>1916</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) is −0.8*VO_t−1at time t+1.

0427At time t+1, the values at the inputs of the summer <b>1926</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) are: VI_tat node <b>1904</b>, −0.1*VO_tat node <b>1914</b>, and −0.8*VO_t−1at node <b>1916</b> (in the example provided by <figref idref="DRAWINGS">FIGS. 19A and 19B</figref>, the values at nodes <b>1914</b> and <b>1916</b> are summed by a second summer <b>1925</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>), and this sum is presented to the summer <b>1926</b>). Accordingly, at time t+1, the summer <b>1926</b> generates a signal equal to VI_t−0.1*VO_t−0.8*VO_t−1.

0428At the rising edge of φ₁at time t+1, a switch <b>1991</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) in the output sample and hold module <b>1936</b> closes, thereby allowing a capacitor <b>1992</b> (shown in <figref idref="DRAWINGS">FIG. 19B</figref>) to charge to VO_t−1. Accordingly, the capacitor <b>1992</b> charges to VO_t+1, which is equal to the sum generated by the adder <b>1926</b>. As just noted, this value is equal to: VI_t−0.1*VO_t−0.8*VO_t−1. This is indicated in cell <b>1850</b> of Table <b>1802</b>. This value is presented to the optional output smoothing module <b>1938</b>, which smoothes the signal to thereby generate the instance of the output signal VO_t+1. That is, the output signal at node <b>1920</b> is a low pass filtered version of the value at node <b>1918</b>. It is apparent from inspection that this value of VO_t+1is consistent with the band pass filter transfer function of EQ. 1.

0429Further details of unified down-conversion and filtering as described in this section are presented in pending U.S. application “Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998, incorporated herein by reference in its entirety.

7. EXAMPLE APPLICATION EMBODIMENTS OF THE INVENTION

0430As noted above, the UFT module of the present invention is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.

0431Example applications of the UFT module were described above. In particular, frequency down-conversion, frequency up-conversion, enhanced signal reception, and unified down-conversion and filtering applications of the UFT module were summarized above, and are further described below. These applications of the UFT module are discussed herein for illustrative purposes. The invention is not limited to these example applications. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s), based on the teachings contained herein.

0432For example, the present invention can be used in applications that involve frequency down-conversion. This is shown in <figref idref="DRAWINGS">FIG. 1C</figref>, for example, where an example UFT module <b>115</b> is used in a down-conversion module <b>114</b>. In this capacity, the UFT module <b>115</b> frequency down-converts an input signal to an output signal. This is also shown in <figref idref="DRAWINGS">FIG. 7</figref>, for example, where an example UFT module <b>706</b> is part of a down-conversion module <b>704</b>, which is part of a receiver <b>702</b>.

0433The present invention can be used in applications that involve frequency up-conversion. This is shown in <figref idref="DRAWINGS">FIG. 1D</figref>, for example, where an example UFT module <b>117</b> is used in a frequency up-conversion module <b>116</b>. In this capacity, the UFT module <b>117</b> frequency up-converts an input signal to an output signal. This is also shown in <figref idref="DRAWINGS">FIG. 8</figref>, for example, where an example UFT module <b>806</b> is part of up-conversion module <b>804</b>, which is part of a transmitter <b>802</b>.

0434The present invention can be used in environments having one or more transmitters <b>902</b> and one or more receivers <b>906</b>, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>. In such environments, one or more of the transmitters <b>902</b> may be implemented using a UFT module, as shown for example in <figref idref="DRAWINGS">FIG. 8</figref>. Also, one or more of the receivers <b>906</b> may be implemented using a UFT module, as shown for example in <figref idref="DRAWINGS">FIG. 7</figref>.

0435The invention can be used to implement a transceiver. An example transceiver <b>1002</b> is illustrated in <figref idref="DRAWINGS">FIG. 10</figref>. The transceiver <b>1002</b> includes a transmitter <b>1004</b> and a receiver <b>1008</b>. Either the transmitter <b>1004</b> or the receiver <b>1008</b> can be implemented using a UFT module. Alternatively, the transmitter <b>1004</b> can be implemented using a UFT module <b>1006</b>, and the receiver <b>1008</b> can be implemented using a UFT module <b>1010</b>. This embodiment is shown in <figref idref="DRAWINGS">FIG. 10</figref>.

0436Another transceiver embodiment according to the invention is shown in <figref idref="DRAWINGS">FIG. 11</figref>. In this transceiver <b>1102</b>, the transmitter <b>1104</b> and the receiver <b>1108</b> are implemented using a single UFT module <b>1106</b>. In other words, the transmitter <b>1104</b> and the receiver <b>1108</b> share a UFT module <b>1106</b>.

0437As described elsewhere in this application, the invention is directed to methods and systems for enhanced signal reception (ESR). Various ESR embodiments include an ESR module (transmit) in a transmitter <b>1202</b>, and an ESR module (receive) in a receiver <b>1210</b>. An example ESR embodiment configured in this manner is illustrated in <figref idref="DRAWINGS">FIG. 12</figref>.

0438The ESR module (transmit) <b>1204</b> includes a frequency up-conversion module <b>1206</b>. Some embodiments of this frequency up-conversion module <b>1206</b> may be implemented using a UFT module, such as that shown in <figref idref="DRAWINGS">FIG. 1D</figref>.

0439The ESR module (receive) <b>1212</b> includes a frequency down-conversion module <b>1214</b>. Some embodiments of this frequency down-conversion module <b>1214</b> may be implemented using a UFT module, such as that shown in <figref idref="DRAWINGS">FIG. 1C</figref>.

0440As described elsewhere in this application, the invention is directed to methods and systems for unified down-conversion and filtering (UDF). An example unified down-conversion and filtering module <b>1302</b> is illustrated in <figref idref="DRAWINGS">FIG. 13</figref>. The unified down-conversion and filtering module <b>1302</b> includes a frequency down-conversion module <b>1304</b> and a filtering module <b>1306</b>. According to the invention, the frequency down-conversion module <b>1304</b> and the filtering module <b>1306</b> are implemented using a UFT module <b>1308</b>, as indicated in <figref idref="DRAWINGS">FIG. 13</figref>.

0441Unified down-conversion and filtering according to the invention is useful in applications involving filtering and/or frequency down-conversion. This is depicted, for example, in <figref idref="DRAWINGS">FIGS. 15A-15F</figref>. <figref idref="DRAWINGS">FIGS. 15A-15C</figref> indicate that unified down-conversion and filtering according to the invention is useful in applications where filtering precedes, follows, or both precedes and follows frequency down-conversion. <figref idref="DRAWINGS">FIG. 15D</figref> indicates that a unified down-conversion and filtering module <b>1524</b> according to the invention can be utilized as a filter <b>1522</b> (i.e., where the extent of frequency down-conversion by the down-converter in the unified down-conversion and filtering module <b>1524</b> is minimized). <figref idref="DRAWINGS">FIG. 15E</figref> indicates that a unified down-conversion and filtering module <b>1528</b> according to the invention can be utilized as a down-converter <b>1526</b> (i.e., where the filter in the unified down-conversion and filtering module <b>1528</b> passes substantially all frequencies). <figref idref="DRAWINGS">FIG. 15F</figref> illustrates that the unified down-conversion and filtering module <b>1532</b> can be used as an amplifier. It is noted that one or more UDF modules can be used in applications that involve at least one or more of filtering, frequency translation, and amplification.

0442For example, receivers, which typically perform filtering, down-conversion, and filtering operations, can be implemented using one or more unified down-conversion and filtering modules. This is illustrated, for example, in <figref idref="DRAWINGS">FIG. 14</figref>.

0443The methods and systems of unified down-conversion and filtering of the invention have many other applications. For example, as discussed herein, the enhanced signal reception (ESR) module (receive) operates to down-convert a signal containing a plurality of spectrums. The ESR module (receive) also operates to isolate the spectrums in the down-converted signal, where such isolation is implemented via filtering in some embodiments. According to embodiments of the invention, the ESR module (receive) is implemented using one or more unified down-conversion and filtering (UDF) modules. This is illustrated, for example, in <figref idref="DRAWINGS">FIG. 16</figref>. In the example of <figref idref="DRAWINGS">FIG. 16</figref>, one or more of the UDF modules <b>1610</b>, <b>1612</b>, <b>1614</b> operates to down-convert a received signal. The UDF modules <b>1610</b>, <b>1612</b>, <b>1614</b> also operate to filter the down-converted signal so as to isolate the spectrum(s) contained therein. As noted above, the UDF modules <b>1610</b>, <b>1612</b>, <b>1614</b> are implemented using the universal frequency translation (UFT) modules of the invention.

0444The invention is not limited to the applications of the UFT module described above. For example, and without limitation, subsets of the applications (methods and/or structures) described herein (and others that would be apparent to persons skilled in the relevant art(s) based on the herein teachings) can be associated to form useful combinations.

0445For example, transmitters and receivers are two applications of the UFT module. <figref idref="DRAWINGS">FIG. 10</figref> illustrates a transceiver <b>1002</b> that is formed by combining these two applications of the UFT module, i.e., by combining a transmitter <b>1004</b> with a receiver <b>1008</b>.

0446Also, ESR (enhanced signal reception) and unified down-conversion and filtering are two other applications of the UFT module. <figref idref="DRAWINGS">FIG. 16</figref> illustrates an example where ESR and unified down-conversion and filtering are combined to form a modified enhanced signal reception system.

0447The invention is not limited to the example applications of the UFT module discussed herein. Also, the invention is not limited to the example combinations of applications of the UFT module discussed herein. These examples were provided for illustrative purposes only, and are not limiting. Other applications and combinations of such applications will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such applications and combinations include, for example and without limitation, applications/combinations comprising and/or involving one or more of: (1) frequency translation; (2) frequency down-conversion; (3) frequency up-conversion; (4) receiving; (5) transmitting; (6) filtering; and/or (7) signal transmission and reception in environments containing potentially jamming signals.

0448Additional examples are set forth below describing applications of the UFT module with circuits that reduce or eliminate unwanted DC offset and re-radiation, and improve dynamic range.

04497.0 DC Offset, Re-Radiation, and Dynamic Range Considerations and Corrections

0450Various embodiments related to the method(s) and structure(s) described herein are presented in this section (and its subsections). Problems related to DC offset, re-radiation, and dynamic range are described below. Applications of the UFT module are provided in relation to circuits used to reduce or eliminate problems of DC offset and re-radiation, and to improve dynamic range.

0451These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

04527.1 Overview of DC Offset and Re-Radiation

0453Receivers, and other electronic circuits, may suffer from problems of DC offset and re-radiation. Generally, “DC offset” refers to a DC voltage level that is added to a signal of interest by related circuitry. The related circuitry creates the DC offset voltage through a variety of mechanisms that are well known. Some of these mechanisms are discussed in further detail below. If a DC offset voltage value is significant, it can degrade the quality of the signal of interest. In a receiver, for example, the signal of interest may be a down-converted signal. Unless reduced or eliminated, the added DC offset voltage level may undesirably change the voltage value of the down-converted signal. As a result, the actual voltage value of the down-converted signal may be difficult to ascertain by down-stream processing.

0454Generally, “re-radiation” is an undesired phenomenon where a signal comprising one or more frequency components generated by receiving circuitry is transmitted by an antenna. For example, the frequency components may be generated by a local oscillator of the receiving circuitry. When transmitted, these frequency components may undesirably interfere with nearby receivers, or may be received back by the same antenna that transmitted them. When the frequency components are received back by the same antenna that transmitted them, this may be referred to “re-radiation recapture”. The phenomenon of re-radiation recapture may further impair signals that are down-converted, and/or may cause undesirable DC offset voltages that may impair the down-converted signals. For instance, the re-radiated and recaptured signal may appear to the receiver as unwanted noise, within or without the frequency band(s) of interest, or may combine with local signals to create an undesired DC offset voltage. The phenomenon of creating a DC offset voltage by re-radiation recapture is described further below. Solutions provided herein for eliminating unwanted DC offset voltages apply to eliminating DC offset voltages produced from re-radiation recapture.

0455Furthermore, signals in a receiver circuit may travel or radiate to other receiver circuit sections, causing problems similar to those of re-radiation recapture described above, including problems of noise and DC offset voltages. For instance, local oscillator signals may undesirably transmit through the circuit substrate, through the air, or through other paths, to other receiver circuit sections, causing unwanted noise problems and problems with unwanted DC offset voltages being generated. Circuits provided herein for solving problems with DC offsets, re-radiation, and re-radiation recapture also apply to solving problems of noise and unwanted DC offset voltages caused by this phenomenon.

0456The concepts of DC offset and re-radiation are further described in the following sub-sections. Furthermore, example methods and systems are provided in subsequent sections below for reducing or eliminating unwanted DC offset and re-radiation. Such methods and systems can be used alone, or in combination with each other, to address offset issues.

04577.1.1 Introduction

0458Embodiments of the UFT module may be used in many communications applications. For some of these applications, the signal space may include waveforms with near DC content. Such waveforms exist, for example, in signals transmitted at radio frequencies. Hence, it may be advantageous to limit the amount of artificial DC insertion or DC offsets contributed by the UFT module or its complimentary demodulation architecture.

0459This section presents an overview of DC offset contributions of the UFT module, and related circuitry, relevant for zero IF implementation. In addition, embodiments of the present invention are presented for reducing the adverse impacts of the DC offsets.

04607.1.2 DC Offset Model Overview

0461<figref idref="DRAWINGS">FIG. 73</figref> illustrates a down-conversion circuit <b>7300</b> according to an embodiment of the present invention. The down-conversion circuit <b>7300</b> of <figref idref="DRAWINGS">FIG. 73</figref> provides a model that indicates possible DC offset contributions. Down-conversion circuit <b>7300</b> comprises a UFD module <b>7302</b>. UFD module <b>7302</b> comprises a UFT module (not shown).

0462There are at least three significant categories of offsets.

04631. Clock Excitation or Charge Injected

04642. Re-radiation Offsets

04653. Intermodulation Distortion

0466Each category possesses its own mechanisms.

0467The following definitions in Table 1 set the backdrop for analysis and understanding of the offset phenomena from a high level model. At least some of the phenomena relevant to the discussion in terms of device physics may be lumped into one or more of the following model parameters.

0000<br /><i>R</i>(<i>t</i>)=[<i>r</i>(<i>t</i>)+<i>k</i>₁<i>k</i>₂<i>C</i>_A(<i>t′</i>_A)+<i>k</i>₂<i>k</i>_B<i>C</i>_B(<i>t′</i>_B))+<i>k</i>_LNA<i>+k</i>_A<i>C</i>_A(<i>t′</i>_A)+<i>k</i>_B<i>C</i>_B(<i>T′B</i>)<i>C</i>(<i>t</i>)+<|{tilde over (<i>C</i>)}(<i>t</i>)|><i>k</i>_cλ  Eq. 29

0000(*The charge injection path associated with k_ffhas been ignored in Eq. 29. This component will be addressed separately in a subsequent section.)

0000<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="168pt" align="left" /><thead><row><entry namest="1" nameend="2" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>r(t) = s(t) +</entry><entry>r(t) is the received signal of interest which consists of a</entry></row><row><entry>n(t);.</entry><entry>modulated carrier s(t) and a noise component n(t).</entry></row><row><entry>k₁k_AC(t′_A1) or</entry><entry>This signal is a conditioned clock 7304 or transient</entry></row><row><entry>k_AC(t′_A)</entry><entry>waveform, which leaks to the core input of UFD module</entry></row><row><entry /><entry>7302 across free-space, substrate, etc.</entry></row><row><entry /><entry>t′_A1is a delayed time variable.</entry></row><row><entry /><entry>t_AI= t − t_A− t₁where t_Ais the delay of the specific (A)</entry></row><row><entry /><entry>path, and t₁is the additional delay through the (1) path.</entry></row><row><entry>k₂k_BC_B(t′_B2) or</entry><entry>This signal is similar to the one described above except</entry></row><row><entry>k_BC_B(t′_B)</entry><entry>that the leakage paths and delays are different and the</entry></row><row><entry /><entry>leakage signal is a raw clock 7306 rather than a</entry></row><row><entry /><entry>conditioned clock 7304.</entry></row><row><entry><|{tilde over (C)}(t)|>k_cλ</entry><entry>This is a signal which is self-generating at UFD 7302</entry></row><row><entry /><entry>module, and is derived from the charge injection</entry></row><row><entry /><entry>phenomena at UFD 7302 module when the conditioned</entry></row><row><entry /><entry>clock 7304 or control is active. Essentially, the</entry></row><row><entry /><entry>conditioned clock C(t) is modified by a</entry></row><row><entry /><entry>nonlinear operation (in this case an abs function)</entry></row><row><entry /><entry>averaged or integrated over some interval and scaled by a</entry></row><row><entry /><entry>gain constant k_cλ,and delayed by t_cλ.</entry></row><row><entry /><entry>When C(t) is not active, then <|{tilde over (C)}(t)|> · k_cλ,→ 0. This</entry></row><row><entry /><entry>offset term is summed effectively at the output of UFD</entry></row><row><entry /><entry>module 7302.</entry></row><row><entry /><entry>< > denotes the expectation operation.</entry></row><row><entry>* k_ff</entry><entry>Gain constant associated with feed forward charge</entry></row><row><entry /><entry>injection path. This path is typically of interest when</entry></row><row><entry /><entry>interferences are present. Usually, offsets will not be</entry></row><row><entry /><entry>significant unless the S/I (Signal to Interference power) is</entry></row><row><entry /><entry>very low and I is very large.</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0468There may be additional leakage terms, which are not illustrated in the model.

04697.1.3 Clock Modulation Via PN Code

0470A system and method for addressing DC offset, according to an embodiment of the present invention, involves modifying the LO (local oscillator) in such a manner that the offsets are randomized and spectrally spread. After some amount of amplification the randomized signal may be de-spread coherently. At least some of the offset, particularly that offset which is due to LO re-radiation, may be removed. <figref idref="DRAWINGS">FIG. 74</figref> illustrates a down-conversion circuit <b>7400</b>, according to an embodiment of the present invention, that removes at least some offset. Down-conversion circuit <b>7400</b> comprises a UFD module <b>7402</b>. UFD module <b>7402</b> comprises a UFT module (not shown).

0471Although only a single down-conversion channel is illustrated in <figref idref="DRAWINGS">FIG. 74</figref>, in alternative embodiments the architecture may be extended to include both I and Q, especially if two uncorrelated PN (Pseudo-random Noise) sequences are utilized. Other dual or multiple channel embodiments are also within the scope and spirit of the present invention. In an embodiment, the PN code or similar sequence is formed by a maximal length linear feed back shift register (or other logic) and is modulated onto the clock and pulse conditioned to form C(t). C_PN(t′) is the baseband PN sequence waveform. C_PN(t′) is virtually identical to C_PN(t) except for a very small time shift. R′(t) may be given by:

0000<br /><i>R</i>′(<i>t</i>)=<i>k</i>_BB<i>R</i>(<i>t−t</i>_BB)(<i>C</i>_PN(<i>t</i>′))  Eq. 30

0000<br />Which may be expanded to:

0000<br /><i>R</i>′(<i>t</i>)<i>k</i>_BB[(<i>r</i>(<i>t−t</i>_BB)<i>C</i>(<i>t′</i>)+<img file="US2013122846A1_D0002.tif" />(<i>t−t</i>_BB))<i>k</i>_LNA<i>+X</i>(<i>t−t</i>_BB)]<i>C</i>_PN(<i>t</i>)+(>|<i>{tilde over (C)}</i>(<i>t−t</i>_BB)|><i>k</i>_cλ<i>k</i>_BB)<i>C</i>_PN(<i>t</i>′)  Eq. 31

0000<br />where:

0000<br /><img file="US2013122846A1_D0003.tif" />(<i>t</i>)=(<i>k</i>₁<i>k</i>_A<i>C</i>(<i>t′</i>_1A)+<i>k</i>₂<i>k</i>_B<i>C</i>_B(<i>t′</i>_2B))<i>C</i>(<i>t</i>)

0000<br /><i>X</i>(<i>t</i>)=(<i>k</i>_A<i>C</i>(<i>t′</i>_A)+<i>k</i>_B<i>C</i>_B(<i>t′</i>_B))<i>C</i>(<i>t</i>)

0000<br /><i>t′</i>_X<u style="single">Δ</u>(<i>t−t</i>_X)

0000<br /><i>C</i>(<i>t</i>){tilde over (−)}<i>C</i>_A(<i>t′</i>)  Eq. 32

0472It will be apparent to persons skilled in the relevant art(s) from the teaching herein that examination of these equations, combined with the knowledge that C(t) can be a pseudo random sequence, will reveal interesting cross correlations for the math provided above.

0473For the moment, delays on the order of sub-carrier cycle times and carrier cycle times may be ignored, thereby considering many of the delay terms to be zero. While this may not actually be the case, this does provide a substantially worst case bounding view of cross-correlation properties of the described signal in one dimension. The general result would apply to the I/Q complex signal representation. However, the first step for a single dimension is instructive and therefore provided. The cross-correlation R_XXis calculated as follows:

0000<br /><i>R</i>_XX(<i>t</i>)<u style="single">Δ</u><<i>k</i>_BB<i>R</i>(<i>t</i>)<i>C</i>_PN(<i>t</i>)>≈<<i>k</i>_BB<i>R</i>(<i>t−t</i>_BB)<i>C</i>_PN(<i>t′</i>)>  Eq. 33

0000<br />The result is:

0000<br /><i>R</i>_XX(<i>t</i>){tilde over (−)}<[<i>k</i>_BB<i>k</i>_LNA<i>r</i>(<i>t</i>)+<i>k</i>_1A<i>k</i>_LNA<i>k</i>_BB<i>C</i>(<i>t</i>)<i>C</i>_A(<i>t</i>)<i>C</i>_PN(<i>t′</i>)+<i>k</i>_2B<i>k</i>_LNA<i>k</i>_BB<i>C</i>(<i>t</i>)<i>C</i>_B(<i>t</i>)<i>C</i>_PN(<i>t</i>′)+<i>k</i>_BB<i>k</i>_A<i>C</i>_A(<i>t</i>′)<i>C</i>(<i>t</i>)+<i>k</i>_BB<i>k</i>_B<i>C</i>_B(<i>t</i>)<i>C</i>_PN(<i>t′</i>)+<|{tilde over (<i>C</i>)}(<i>t</i>)|><i>k</i>_cλ<i>·k</i>_BB<i>C</i>_PN(<i>t</i>′)[>  Eq. 34

0000C_PN(t), C_A(t), r(t), and C_B(t) average to zero over a long term, if C_PN(t) is augmented. Even if r(t) does not average to zero, r(t) is not considered because it is the signal of interest. (NOTE: An “augmented” sequence refers to the process of chip stuffing as required to provide ideal code balance.)

0474It will be known to persons skilled in the relevant art(s) that C(t) and C_B(t) are uncorrelated. It is also known that |{tilde over (C)}(t)| and C_PN(t) are uncorrelated when C_PN(t) is bipolar. If the cross-correlations indicated above are in fact indicative of the process, then R_XX(t) would approximately reduce to:

0000<br /><i>R</i>_XX(<i>t</i>)≈→0  Eq. 35

0000R_XX(t) represents the DC offset that exists due to LO re-radiation leaking into the front end of UFD module <b>7402</b> by some ancillary path, such that it is converted into band at the output of UFD module <b>7402</b> for the case where the leakage is synchronous in part or whole to the UFD module transform, plus charge injected offset. This synchronicity is actually rare for cases where k_1Aor k_Ais large. Typically those gains would be much less than 1.

0475What the above equation reveals is that little or no DC offset effects remain if C_PN(t) and C(t) are balanced, bipolar sequences.

0476In this case, a spreading sequence, spreading rate, and sequence length are selected. This selection typically requires careful examination of the signaling scheme, data rate, etc. Also, the Cl path involving k_ffhas not been accounted for in this analysis.

04777.1.3.1 Interpretation of R_xx(t) and Required Leakage

0478It may be desirable that R_xx(t) be 3.16×10⁻⁶volts peak in a 50Ω system for a number of applications. For a system design where the UFD module possesses an output impedance of 1KΩ, a signal level of 63.2 μV peak may be tolerated (−100 dBm).

0479In embodiments, clock port or control port signals may swing as much as 2V peak internal to the UFD module. If 2 volts must be reduced to 63.2 μV at the UFD module output, then:

0000<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mrow><mi>V</mi><mo>·</mo><msub><mi>k</mi><mrow><mi>c</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>λ</mi></mrow></msub></mrow></mrow><mo>&lt;</mo><mrow><mn>63.2</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>-</mo><mn>6</mn></mrow></msup><mo></mo><msub><mi>V</mi><mi>peak</mi></msub></mrow></mrow><mo>∴</mo><mrow><msub><mi>k</mi><mrow><mi>c</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>λ</mi></mrow></msub><mo>&lt;</mo><mfrac><mrow><mn>63.2</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>-</mo><mn>6</mn></mrow></msup></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>36</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0004.tif" />

0480Hence:

0000<br /><i>k</i>_cλ&lt;31.6×10⁻⁶{tilde over (&lt;)}−90 dB(power)  Eq. 37

0000Eq. 37 implies that the effective isolation from charge injected DC must be on the order of 90 dB (power) or greater at the UFD module in various embodiments.

0481In embodiments, it is unlikely that 90 dB of chip isolation would be achieved in a system-on-a-chip design. It may be more difficult to maintain isolations over temperature and production lots. In an embodiment, the suppression is such that the LO re-radiation in band @ 2450 MHZ for a n=5 system is −20 dBm.

0482A similar calculation for the aggregate LO re-radiation components reveals the requirement of approximately 100 dB suppression, effectively.

04837.1.3.2 Charge Injected DC Offset

0484The charge injected DC offset phenomena may be modeled as some rectification of the clock or control port energy weighted by some gain constant, k_cλ. The amount of DC offset introduced at the output of the UFD module may be given as:

0000<br /><i>CI</i>_UFDDC<u style="single">Δ</u>(<|<i>{tilde over (C)}</i>(<i>t</i>)|>)<i>k</i>_cλ  Eq. 38

0485However, it may also be of value to construct a picture more closely associated with how this term arises. Consider a down-conversion circuit <b>7500</b> shown in <figref idref="DRAWINGS">FIG. 75</figref>, configured according to an embodiment of the present invention. Down-conversion circuit <b>7500</b> comprises a UFD module <b>7502</b>. UFD module <b>7502</b> comprises a UFT module (not shown). An equation can be written to describe the voltage at the output due to C(t). The complex domain equation is:

0000<maths id="MATH-US-00003" num="00003"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><msub><mi>V</mi><mi>OCI</mi></msub><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><msub><mi>V</mi><mi>C</mi></msub><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow><mo></mo><mrow><mo>(</mo><mfrac><mrow><mrow><msub><mi>Z</mi><mi>L</mi></msub><mo>·</mo><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup></mrow><mo></mo><mrow><msub><mi>C</mi><mi>OLeff</mi></msub><mo>·</mo><mi>s</mi></mrow></mrow><mrow><mrow><mrow><mrow><mrow><msub><mi>Z</mi><mi>L</mi></msub><mo></mo><msub><mi>Z</mi><mi>C</mi></msub></mrow><mo>+</mo><mrow><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><msub><mi>Z</mi><mi>C</mi></msub></mrow><mo>+</mo><mrow><msub><mi>Z</mi><mi>L</mi></msub><mo>·</mo><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup></mrow></mrow><mo>)</mo></mrow><mo></mo><mrow><msub><mi>C</mi><mi>OLeff</mi></msub><mo>·</mo><mi>S</mi></mrow></mrow><mo>+</mo><mrow><mo>(</mo><mrow><msub><mi>Z</mi><mi>L</mi></msub><mo>+</mo><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup></mrow></mrow></mrow></mfrac><mo>)</mo></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mstyle><mspace width="4.4em" height="4.4ex" /></mstyle><mo></mo><mrow><mi>Z</mi><mo></mo><msub><mo>-</mo><mi>L</mi></msub><mo></mo><mrow><munder><mi>Δ</mi><mi>_</mi></munder><mo></mo><mstyle><mspace width="1.7em" height="1.7ex" /></mstyle><mo></mo><mi>Complex</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>Load</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>Impedance</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mrow><mo>(</mo><mfrac><msub><mi>R</mi><mi>L</mi></msub><mrow><mrow><msub><mi>R</mi><mi>L</mi></msub><mo></mo><mrow><mi>C</mi><mo>·</mo><mi>S</mi></mrow></mrow><mo>+</mo><mn>1</mn></mrow></mfrac><mo>)</mo></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><munder><mi>Δ</mi><mi>_</mi></munder><mo></mo><mstyle><mspace width="3.6em" height="3.6ex" /></mstyle><mo></mo><mi>Complex</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>Source</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mi>Impedance</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mrow><mo>(</mo><mrow><mi>Z</mi><mo></mo><msub><mo>-</mo><mrow><mi>D</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>D</mi></mrow></msub><mo></mo><mrow><mo>+</mo><mfrac><mrow><mrow><mi>L</mi><mo>·</mo><mi>SZ</mi></mrow><mo></mo><msub><mo>-</mo><mi>S</mi></msub><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow><mrow><mi>LS</mi><mo>+</mo><mi>Z</mi><mo></mo><msub><mo>-</mo><mi>S</mi></msub><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow></mfrac></mrow></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>39</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0005.tif" /><ul id="ul0021" list-style="none"><li id="ul0021-0001" num="0000"><ul id="ul0022" list-style="none"><li id="ul0022-0001" num="0486">V_C(s)<u style="single">Δ</u> Complex Clock Signal driving the UFD module</li><li id="ul0022-0002" num="0487">V_OCI<u style="single">Δ</u> The Complex Output Signal arising from clock activity at UFD module <b>7502</b>. This component is considered as a voltage resulting from charge injection due to the parasitic C_OLeff<br /> There are some high level considerations which reveal important aspects of the phenomena. The equation shows the following; </li><li id="ul0022-0003" num="0488">When V_C(s) is a pure DC waveform, V_OCIis zero. However, V_C(t) does possess both a transient and DC offset component. If the DC offset component is zero then V_C(t) would also be zero.</li><li id="ul0022-0004" num="0489">As the frequency content of the transients in V_C(s) are lower, then so too V_OCIwill typically become lower. However, this perceived monotonic correspondence of V_OCIto frequency components V_C(s) may not always hold because of resonances in the complex impedances surrounding UFD module <b>7502</b>. The DC offset performance of UFD module <b>7502</b> is a strong function of the Fourier signature for V_C(t), as is further described below.</li><li id="ul0022-0005" num="0490">When C_OLeff→zero, then V_OCI→zero.</li><li id="ul0022-0006" num="0491">The lower the source impedance and the lower the load impedance, the lower V_OCIbecomes.</li><li id="ul0022-0007" num="0492"><img file="US2013122846A1_D0006.tif" />_{UFD module}tends to provide some isolation from input impedances over the frequency ranges where the real [<img file="US2013122846A1_D0007.tif" />_{UFD module}] series component dominates. When real [<img file="US2013122846A1_D0008.tif" />_{UFD module}] is significant, <img file="US2013122846A1_D0009.tif" />_Lbecomes a consideration concerning V_OCI. <br /> C_OLeffis a parasitic which is well known and understood in conventional receiver systems. There are processes available which can reduce this parameter by a factor approaching 100. A value in one embodiment of UFD module <b>7502</b> would be on the order of: </li></ul></li></ul>

0000<br /><i>C</i>_OLeff{tilde over (−)}120 pf  Eq. 40

0000Hence, this could be reduced to 1-2 pf.

0493The amount of charge injected DC voltage variation at the output of UFD module <b>7502</b> is related to one or more of at least the following factors: <ul id="ul0023" list-style="none"><li id="ul0023-0001" num="0494"><img file="US2013122846A1_D0010.tif" />_S(s): The Input Source Impedance, which is typically complex.</li><li id="ul0023-0002" num="0495">L: This is a typically used bias inductor. Other arrangements are possible. This one is selected simply for illustration purposes.</li><li id="ul0023-0003" num="0496"><img file="US2013122846A1_D0011.tif" />_C(s): The Output Impedance of the Clock Source (C(t)).</li><li id="ul0023-0004" num="0497">C,R_L: Components utilized to load UFD module <b>7502</b>.</li><li id="ul0023-0005" num="0498">C_OLeff: This capacitance is a process parasitic and is shown as an effective capacitor formed from several physical capacitors, which usually dominates in terms of charge injection path. Although shown on the output node it may be actually split between output and input of UFD module <b>7502</b>. In fact, the input typically provides a significant LO re-radiation path.</li><li id="ul0023-0006" num="0499"><img file="US2013122846A1_D0012.tif" />_{UFD module}: Internal Impedance of UFD module <b>7502</b>.</li></ul>

0500Because <img file="US2013122846A1_D0013.tif" />′_S, <img file="US2013122846A1_D0014.tif" />_L, and <img file="US2013122846A1_D0015.tif" />_Care all complex impedances, there is always the chance that resonance's may occur for certain C_OLeff, such that V_OCIcould possess local maxima even as C_OLeffdecreases. In the case where <img file="US2013122846A1_D0016.tif" />_{UFD module}, <img file="US2013122846A1_D0017.tif" />_L, <img file="US2013122846A1_D0018.tif" />_S, and <img file="US2013122846A1_D0019.tif" />_Care dominated by real parts, the injection attenuation gains in dropping C_OLefffrom 120 pf to 2 pf are enormous. These attenuation gains may be roughly 35 dB in power, and half that in voltage. Hence, DC offset due to charge injection may be significantly attenuated by process control. An example of process control may be related to moving from CMOS (Complementary Metal Oxide Semiconductor) to DMOS (Double Diffused Metal Oxide Semiconductor). There are processes available which may include both CMOS and DMOS on the same substrate, possibly providing important performance options, particularly in the domain of gate overlap capacitance control. The effective gate overlap capacitance C_OLeffis a chief offender, which results from process oxide capacitance in conjunction with overlap parasitics related to transistor geometries.

0501Another method of artificially decreasing C_OLeffis by changing <img file="US2013122846A1_D0020.tif" />_C, to incorporate a series capacitor, which is much lower than C_OLeff. However, this must be done carefully to avoid negative substrate transients. A further useful circuit model allows

0000<maths id="MATH-US-00004" num="00004"><math overflow="scroll"><mrow><mrow><mrow><msubsup><mi>Z</mi><mi>s</mi><mi>′</mi></msubsup><mo>-</mo></mrow><mo>→</mo><mn>0</mn></mrow><mo>,</mo><mrow><mrow><msub><mi>Z</mi><mi>C</mi></msub><mo>-</mo></mrow><mo>→</mo><mn>0</mn></mrow><mo>,</mo><mrow><mrow><msub><mi>Z</mi><mrow><mi>D</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>D</mi></mrow></msub><mo>-</mo></mrow><mo>→</mo><mn>0</mn></mrow><mo>,</mo><mrow><msub><mi>Z</mi><mi>L</mi></msub><mo>→</mo><mrow><mfrac><mn>1</mn><mi>sC</mi></mfrac><mo>.</mo></mrow></mrow></mrow></math></maths><img file="US2013122846A1_D0021.tif" />

0000An embodiment of this circuit is shown in <figref idref="DRAWINGS">FIG. 76</figref>, as down-conversion circuit <b>7600</b>. Down-conversion circuit <b>7600</b> comprises a UFD module <b>7602</b>. UFD module <b>7602</b> comprises a UFT module (not shown). Under these conditions:

0000<maths id="MATH-US-00005" num="00005"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>V</mi><mi>OCI</mi></msub><mo>≈</mo><mrow><mrow><mo>-</mo><mrow><mo>(</mo><mfrac><msub><mi>C</mi><mi>OX</mi></msub><mrow><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>C</mi></mrow></mfrac><mo>)</mo></mrow></mrow><mo></mo><mrow><mo>(</mo><mrow><mi>W</mi><mo>·</mo><mi>L</mi></mrow><mo>)</mo></mrow><mo></mo><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>cp</mi></msub><mo>-</mo><msub><mi>V</mi><mi>T</mi></msub><mo>-</mo><msub><mi>V</mi><mi>in</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>41</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0022.tif" />

0502where: <ul id="ul0024" list-style="none"><li id="ul0024-0001" num="0000"><ul id="ul0025" list-style="none"><li id="ul0025-0001" num="0503">C_OX<u style="single">Δ</u> Oxide Capacitance, Function of Process.</li><li id="ul0025-0002" num="0504">W, L<u style="single">Δ</u> Fundamental Geometries related to the UFD module, which affect parasitic overlap capacitances.</li><li id="ul0025-0003" num="0505">V_cp<u style="single">Δ</u> Conditioned Clock Peak Excursion (unfiltered).</li><li id="ul0025-0004" num="0506">V_T<u style="single">Δ</u> Threshold Voltage related to the Process. <br /> Eq. 41 relates directly to the device physics of the UFD module. C_OLeffrelates to C_OXand the parasitics formed due to W and L. </li></ul></li></ul>

0507This model has some practical application because it can be used to predict compromises in the charge injection DC offset due to UFD module <b>7602</b> process parameters and the output capacitor C. For example, the model can predict, to a reasonable approximation, the results of a corresponding simulation. In the situations where <img file="US2013122846A1_D0023.tif" />′_S, <img file="US2013122846A1_D0024.tif" />_C, and <img file="US2013122846A1_D0025.tif" />_{UFD module}may not be precisely known, a circuit designer may at least select approximate specifications for UFD module <b>7602</b> designs using the simple model, and add more accurate impedances as they become known. Furthermore, to the degree C_OX, W, L, V_T, and V_cpcan be manipulated, the more V_OCIcan be reduced.

05087.1.3.3 Clock Waveform Impact on CI Induced Offsets

0509The previous section illustrated that the clock waveform can impact the efficiency of CI DC offset build up. This is an important concept because clock design is integral to the UFD module theory. The following formulation provides a Fourier series representation for a general clock pulse, and provides some insight into the frequency content of the excitation clock. The DC introduced by charge injection is a strong function of complex impedances around the UFD module. Signals which stimulate the UFD module may also play a role in the DC offset, depending on the clock signal's Fourier signature.

0510Clock pulse train V_C(t) may be represented by a Fourier series as follows:

0000<maths id="MATH-US-00006" num="00006"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><msub><mi>V</mi><mi>C</mi></msub><mo></mo><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mfrac><mrow><msub><mi>V</mi><mi>cp</mi></msub><mo></mo><msub><mi>T</mi><mi>A</mi></msub></mrow><mn>4</mn></mfrac><mo>+</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>1</mn></mrow><mi>∞</mi></munderover><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mrow><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mrow><msub><mi>V</mi><mi>cp</mi></msub><mo></mo><mrow><mo>(</mo><mfrac><mrow><mi>sin</mi><mo></mo><mrow><mo>(</mo><mrow><mi>n</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>π</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mrow><msub><mi>T</mi><mi>A</mi></msub><mo>/</mo><mn>2</mn></mrow></mrow><mo>)</mo></mrow></mrow><mrow><mi>n</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>π</mi></mrow></mfrac><mo>)</mo></mrow></mrow><mo></mo><mrow><mo>(</mo><mrow><mi>cos</mi><mo></mo><mrow><mo>(</mo><mfrac><mrow><mn>2</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>π</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow><msub><mi>T</mi><mi>S</mi></msub></mfrac><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>42</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0026.tif" />

0000An ideal rectangular clock pulse is illustrated in <figref idref="DRAWINGS">FIG. 77A</figref>, with zero rise and fall time. This may be considered to be a worst case scenario. In reality the clock waveform will consist of a repeating pulse train with a basic pulse shape possessing finite, non-zero, rise, and fall times.

0511The calculated Fourier series for V_C(t) is a well known result for sampling devices. As T_Adecreases, the Fourier spectrum extends ever greater in the frequency domain with significant harmonics.

0512<figref idref="DRAWINGS">FIG. 77B</figref> illustrates that the spectrum is a “picket fence” with harmonics separated by f_S=T_S⁻¹, and nulls at N·f_a, where f_a=T_A⁻¹. Hence, the greater the value of ratio T_S/T_A, the greater the number of harmonics out to the first null, and the greater number of components, spectrally, which can excite the process parasitic at higher and higher frequencies.

0513A sequence of plots in <figref idref="DRAWINGS">FIGS. 79-83</figref> and <b>86</b>A illustrate this concept of clock waveform attributes and relationship to the DC offset.

0514<figref idref="DRAWINGS">FIG. 78</figref> illustrates a down-conversion circuit <b>7800</b> used to determine DC offset due to charge injection, and possibly LO feed through, according to an embodiment of the present invention. Down-conversion circuit <b>7800</b> comprises a UFD module <b>7802</b>. UFD module <b>7802</b> comprises a UFT module (not shown).

0515<figref idref="DRAWINGS">FIG. 79</figref> shows the offset obtained with 3 different clock pulse widths (T_A) for the circuit of <figref idref="DRAWINGS">FIG. 78</figref>. The clock is configured to operate on a 2.4-2.5 GHz band signal using a 5th harmonic technique. The clock for the offset plots of <figref idref="DRAWINGS">FIG. 79</figref> was selected to down-convert 2.45 GHz.

0516<figref idref="DRAWINGS">FIG. 79</figref> shows that longer pulse widths may produce lower CI related offsets. <figref idref="DRAWINGS">FIG. 80</figref> illustrates a situation similar to that of <figref idref="DRAWINGS">FIG. 79</figref> utilizing a 3rd harmonic clock approach. As shown in <figref idref="DRAWINGS">FIG. 80</figref>, reducing the clock frequency components did not continue to reduce V_OCI. This may be due in part to the surrounding complex impedances which will possess local resonances or favor certain Fourier spectrums.

0517The circuitry surrounding UFD module <b>7802</b> may affect overall circuit performance. For example, <figref idref="DRAWINGS">FIG. 81</figref> shows offsets obtained using slightly lower bond wire inductance. <figref idref="DRAWINGS">FIG. 81</figref> illustrates how the results of <figref idref="DRAWINGS">FIG. 79</figref> may be affected by these changes.

0518<figref idref="DRAWINGS">FIG. 82</figref> illustrates the case of a fixed 204 ps T_Awith 10 ps rise and fall times, while permitting a variation in bond wire inductance. <figref idref="DRAWINGS">FIG. 82</figref> indicates that lower inductance may be better in some situations.

0519The previous plots related to cases with clock waveforms V_C(t) possessing 10 ps rise and fall times. <figref idref="DRAWINGS">FIG. 83</figref> illustrates the V_OCIresponse for a variety of rise and fall times, 204 ps T_A, and 5th harmonic operation.

0520It is interesting to note that there are two local minima for the DC offset performance with fast rise times representing one of those cases. This implies resonance in the complex impedances surrounding (and including) UFD module <b>7802</b>. Different circuit topologies will behave differently and different component types would operate differently due to their own parasitic elements. In addition, stretching to a <b>3</b>× or 5× aperture would produce different results.

05217.1.3.4 Bench Example

0522Experiments were conducted with hardware designed to operate in the 2.4 GHz ISM (Industry, Scientific, and Medical) band. 5th harmonic mode was utilized for the clock, with the clock rate being varied between 482.4 MHZ and 492.4 MHZ. The UFD module configuration was an I/Q receiver with matching networks and DC coupling. The input to the I/Q assembly was terminated with 50Ω.

0523The charts shown in <figref idref="DRAWINGS">FIGS. 84A</figref>, <b>84</b>B, <b>85</b>A, and <b>85</b>B record the results on the I port for a variety of LO drive levels and 3 operating channels, for two different assemblies: one with a clock port match and one without.

05247.1.3.5 Complementary Architecture

0525Up to this point the UFD module cores analyzed have been based on a non-complimentary structure. Complementary structures can be used with the important advantage of lower UFD module losses and greater IP2, IP3 performance. In addition, some charge injection cancellation should be possible. The results in <figref idref="DRAWINGS">FIG. 86A</figref> correspond to results recorded in <figref idref="DRAWINGS">FIG. 79</figref>. Careful examination shows that there may be a 4.25 dB reduction in CI induced DC offset possibly attributed either to the complementary UFD module architecture or the resulting modification to <img file="US2013122846A1_D0027.tif" />_{UFD module}.

05267.1.3.6 Spreading Code Results

0527Sections 7.1.3 and 7.1.3.1 outline the concept of using a local PN code to reduce the DC offset generated at a UFD module, or created due to LO re-radiation recapture. Maximal length codes, balanced codes, and other related code types may be used. Furthermore, the statistical properties of a code may be tailored in the time domain or frequency domain to accomplish desired DC reduction while minimizing the impact to the desired signal.

0528Experiments have been accomplished with UFD module circuit embodiments to illustrate the potential of these techniques. <figref idref="DRAWINGS">FIG. 86B</figref> shows an example spectral plot of a carrier tone at RF, corresponding to LO re-radiation at a UFD module.

0529<figref idref="DRAWINGS">FIG. 86C</figref> illustrates the LO re-radiation spectrum shown in <figref idref="DRAWINGS">FIG. 86B</figref> after modulation by an example modified maximal length linear PN sequence. In this example, the power spectral density is substantially modified by the code. On average, the power spectral density has been lowered by approximately 32 dB. This benefit may not be completely obtained unless the specification desired for re-radiation is referenced to the resolution bandwidth of the analyzer sweep. This is adjusted for wider bandwidth (faster) PN sequences with long repetition intervals. That is, the processing gain of interest here is the bandwidth expansion factor:

0000<maths id="MATH-US-00007" num="00007"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>BW</mi><mi>E</mi></msub><mo>=</mo><mfrac><msub><mi>BW</mi><mi>pn</mi></msub><msub><mi>resBW</mi><mi>spec</mi></msub></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>43</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0028.tif" />

Where:

0000<ul id="ul0026" list-style="none"><li id="ul0026-0001" num="0000"><ul id="ul0027" list-style="none"><li id="ul0027-0001" num="0530">BW_E<u style="double">Δ</u> Bandwidth expansion factor (unitless)</li><li id="ul0027-0002" num="0531">BW_pn<u style="single">Δ</u> Double Sided Bandwidth of PN Sequence</li><li id="ul0027-0003" num="0532">resBW_spec<u style="double">Δ</u> Resolution bandwidth for a particular re-radiation specification that is dictated by standards or regulatory agency.</li></ul></li></ul>

Then:

0533<br /><i>P</i>_BW=10 log₁₀(BW_E) dB  Eq. 44

0000P_BWis the effective processing gain due to LO bandwidth expansion factor alone, that is attained by using a special sequence at a UFD module clock port superposed on the clock. To some extent, BW_pncan be adjusted for a desired effect, although there may be other practical system constraints.

0534As predicted by equations in section 7.1.3, the DC offset at a UFD module output may be canceled using a special sequence, its correlation properties, and its effective system processing gain.

0535<figref idref="DRAWINGS">FIG. 86D</figref> shows an example PN modulated output of a UFD module configured to receive a 870 MHZ RF signal with a slight carrier frequency offset. A beat note represents the slight carrier offset (envelope of the baseband). In addition, the PN code impressed on the received signal by the special UFD module clock signal is visible.

0536The signal illustrated in <figref idref="DRAWINGS">FIG. 86D</figref> possesses substantial DC offset. <figref idref="DRAWINGS">FIG. 86E</figref> illustrates the result after PN rectification or correlation. The DC offset produces a PN code summed to the desired signal while the balanced PN modulation envelope is removed by correlation. The power in the remaining summed PN signal is directly proportional to the original UFD module DC offset plus all system offsets thereafter up to the post-correlator. The bandwidth of this ancillary PN code power is substantially wider than the bandwidth of the baseband signal by design. Hence, the post filter (sometimes a baseband matched filter) can remove much of the variance of the PN sequence. <figref idref="DRAWINGS">FIG. 86F</figref> illustrates the low pass output to recover the baseband beat note.

0537A goal is to choose an effective system processing gain PG_sys, which is high enough to drive significant variance from the low pass result. PG_sysis defined as follows:

0000<maths id="MATH-US-00008" num="00008"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>PG</mi><mi>sys</mi></msub><mo></mo><munder><mi>Δ</mi><mi>_</mi></munder><mo></mo><mn>10</mn><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><msub><mi>log</mi><mn>10</mn></msub><mo></mo><mfrac><mrow><mo>(</mo><mrow><msub><mi>BW</mi><mi>pn</mi></msub><mo>/</mo><mn>2</mn></mrow><mo>)</mo></mrow><msub><mi>BW</mi><mi>MF</mi></msub></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mn>45</mn></mrow></mtd></mtr></mtable></math></maths><img file="US2013122846A1_D0029.tif" />

0538BW_pn<u style="single">Δ</u> Double Sided PN Code Bandwidth

0539BW_MF<u style="single">Δ</u> Filter Bandwidth

0540The example run in the lab utilized a 10 kHz baseband signal bandwidth and a spreading rate of 5 MHz. In addition, the code was modified as an R<img file="US2013122846A1_D0030.tif" /> type. This technique may not provide all of the DC cancellation required but can be a powerful tool for many applications.

05417.1.4 UFD Module DC Offsets from Non-Linearities

0542Because the UFD module is at least a conversion device, an intercept point will determine output waveform integrity to a large extent. Two tone 2^ndorder intercept and two tone 3^rdorder intercept points are important. In particular, the two tone second order intercept point, IP2_1N, relates to DC offset. As the input begins to approach the UFD module rails, harmonic spectrums are generated in the signal path. Because the UFD module clock may excite harmonics, each harmonic spectrum may down-convert to DC, adding some DC offset. Because the phases of the down-conversion harmonics generally are complicated, the resulting DC offset may be non-systematic, even though the process is predictable by using complex math.

0543<figref idref="DRAWINGS">FIG. 86G</figref> illustrates an exemplary signal input harmonic spectrum and conversion clock harmonic spectrum. The harmonic spectrums for the input signal at f₂and f₃become more significant as the UFD module is pushed harder on its input.

0544Another concept useful in considering the IP2_INmechanism comes from a different view on the frequency doubling phenomena. Frequency doubling occurs in a square law device. Hence, for the 2^ndorder term, the non-linearity from the UFD module output may be approximated by;

0000<br />(<i>Ã</i>(<i>t</i>)cos(ω₀<i>t</i>+φ(<i>t</i>)))²=½<i>Ã</i>(<i>t</i>)₂(1+cos(2ω₀<i>t+</i>2φ(<i>t</i>)))  Eq. 46

0545Ã(t)<u style="single">Δ</u> Amplitude Domain Modulation

0546φ(t)<u style="single">Δ</u> Phase Domain Modulation

0547Ã(t) could represent the complex envelope of modulation from information impressed on the carrier (as well as noise). Likewise, φ(t) could contain information modulated onto the carrier as well as phase noise. The above equation illustrates that the 2× frequency component can be formed from the non-linearity but that Ã(t)²is also formed. The equation indicates that a DC component results from the squared envelope. This DC component is not desirable. Likewise, higher order inter-modulation can contribute to the problem, particularly even order terms.

0548In general, the output voltage of a non-linear system can be expanded in terms of its input voltage by a power series of the form shown in <figref idref="DRAWINGS">FIG. 86H</figref>. Usually it is difficult to predict k₁, k₂. . . precisely. Extending properties of linear systems to non-linear system descriptions permits another useful and more general equation:

0000<br /><i>y</i>_n(<i>t</i>)∫_−∞^∞<i> . . . ∫k</i>_n(<i>u</i>₁<i>, u</i>₂<i>, . . . u</i>_n)<i>X</i>(<i>t−u</i>₁)<i>X</i>(<i>t−u</i>₂) . . . <i>X</i>(<i>t−u</i>_n<i>du</i>₁<i>, du</i>₂<i>. . . du</i>_n)  Eq. 47

0000where y_n(t) is the system output and X(t) is the system input. This is the so called nth order impulse response for the system, found by an n-fold convolution kernel. <figref idref="DRAWINGS">FIG. 86I</figref> shows a block diagram representation of this system.

0549y₁(t) is the desired linear impulse response of the system. y₂(t) is the two-dimensional system convolution involving X(t). y₃(t) is the three-dimensional convolution of X(t) and the impulse response h₃(u₁,u₂,u₃), etc. This is known as the Volterra functional series representation of a system. For weak non-linearities, the first 3 terms of the series may provide enough information to characterize a system. This is the case for many communications systems.

0550Such nth order analysis in practice is often complex and tedious, yielding only a general feel for the expected result, unless circuit and network models are extraordinarily accurate. Nevertheless, in the approximation, the 2^ndorder term relating to the two tone 2^ndorder input intercept (IP2_IN) is one useful metric for measuring down-conversion linearity. Essentially, the DC offset from IP2_INis bounded at the upper end by the power of the 2^ndorder harmonic.

0551For instance, suppose that it is desired to suppress the power of the 2^ndorder term by 20 dB in a direct down-conversion device (no interference present). If the highest expected input RF signal of interest is −25 dBm, the system will require an input intercept (IP2_IN) of −5 dBm. This establishes a signal-to-DC offset ratio of at least 20 dB due to the 2^ndorder non linearity.

0552Now consider the case where other unwanted signals are present at the input to the non-linearity along with the signal of interest. Suppose the RF signal is at a level of −101 dBm, while the interference tone is a level of −30 dBm. Furthermore, assume that the system noise floor is near enough to −101 under linear conditions such that we desire an additional 10 dB margin on any 2^ndorder non-linearity folded back in band, so that our benchmark at 101 dBm is not affected.

0000<br />IP2_IN=(−30+111)−30=51 dBm  Eq. 48

0000Therefore, IP2_INcan become a significant specification when an interference or blocking tone is considered, and unfiltered due to a zero IF architecture.

0553This type of non-linear effect is dependent on input signal power to a great extent. Because the phenomenon is based on even-order intermods, differential design can cancel a significant portion of the difficulty, but imbalance may not remove it all. For instance, suppose that the input to the UFD module is at −15 dBm due to an LNA in front of the down-conversion. Suppose this is an interfering tone. Also, assume a 1KΩ baseband operating impedance and a 12 dB UFD module conversion loss. The suppression of the IP2_INat the UFD module output is then:

0000<br /><i>DC</i>(IP2)≦−15−12−81  Eq. 49

0000If the desired suppression is 81 dB, the output offset into 1KΩ is less than 0.126 mV due to 2^ndorder non linearities. This may be accommodated with an op amp circuit, for example. If a differential architecture is assumed, then arguably this signal can be processed in terms of common mode range.

0554In fact, in embodiments a UFD module with IP2_INof +40 dBm could be tolerated if 10 dB of cancellation is available from a differential architecture. Differential architectures may extend as great as a 30 dB benefit, for example, without special trimming.

05557.2 Example Embodiments to Address DC Offset and Re-Radiation Problems

0556Section 7.1 above discussed problems related to DC offset and re-radiation that occur during and after the down-conversion process, and were provided for illustrative purposes, and are not limiting. Embodiments were also provided for reducing or eliminating unwanted DC offset and re-radiation using techniques of spectral spreading followed by de-spreading, according to the present invention. Various embodiments related to the problems, method(s), and structure(s) described above are presented in this section (and its subsections). In particular, further applications of the UFT module are provided below in circuit configurations that reduce or eliminate problems of DC offset and re-radiation.

0557These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

05587.2.1 DC Offset

0559Exemplary embodiments are provided below for reducing or eliminating unwanted DC offset voltages. These unwanted DC offset voltages include unwanted DC offset voltages created by any source, including non-ideal circuit component operation, re-radiation recapture, local circuit signals traveling or radiating to other circuit sections, etc. The embodiments provided below are not limited to this use, but may have additional applications. For example, these embodiments may be applicable to reducing or eliminating unwanted circuit re-radiation.

05607.2.1.1 Reducing DC Offset by Spectral Spreading and De-Spreading

0561Embodiments for reducing DC offset by spectral spreading and de-spreading, as described above, are further described in the following sub-sections, and additional related embodiments are presented.

05627.2.1.1.1 Conventional Wireless Communications Receiver

0563<figref idref="DRAWINGS">FIG. 87</figref> shows an example conventional wireless communications down-conversion system <b>8700</b>. Down-conversion system <b>8700</b> comprises a down-conversion module <b>8702</b> and an amplifier <b>8704</b>. Down-conversion module <b>8702</b> typically comprises a super-heterodyne receiver. Down-conversion module <b>8702</b> may comprise multiple down-conversion stages. Amplifier <b>8704</b> may comprise an amplifier, a filter, other signal processing component(s), or any combination thereof.

0564Down-conversion module <b>8702</b> down-converts a modulated carrier signal <b>8706</b>, according to at least one local oscillator signal <b>8708</b>, to a down-converted baseband signal <b>8710</b>.

0565Down-converted baseband signal <b>8710</b> is input to amplifier <b>8704</b>. Amplifier <b>8704</b> amplifies, filters, and/or otherwise processes down-converted signal <b>8710</b>, and outputs baseband signal <b>8712</b>.

0566As described above, and shown in <figref idref="DRAWINGS">FIG. 87</figref>, DC offsets due to local oscillator signal <b>8708</b> may be input to the signal path at several points, with some possible points indicated by charge leakage and charge injection paths <b>8714</b>, <b>8716</b>, and <b>8718</b>. As described above, charge leakage and charge injection are well known effects. These DC offsets disadvantageously affect at least the dynamic range and accuracy of baseband signal <b>8712</b>. For instance, adding a significant DC offset to baseband signal <b>8712</b> may cause the output of subsequent amplifiers in the baseband signal path to approach the level of their power supplies, potentially causing the amplifiers to rail or become non-linear.

05677.2.1.1.2 Spread/De-Spread Receiver Embodiments of the Present Invention

0568An embodiment of the present invention addresses undesired DC offsets described above by modifying the local oscillator in such a manner that offsets are randomized and spectrally spread. This pseudo-random local oscillator signal is used to down-convert an input signal, such as a modulated carrier signal, and spread the spectrum of the down-converted signal. After some amount of amplification, filtering, and/or other optional processing, the randomized down-converted signal may be spectrally de-spread to a baseband signal. Because the down-converted signal is spectrally de-spread, offsets are spectrally spread. At least some of the offset, particularly the offset due to local oscillator re-radiation, is reduced or removed from the resulting baseband signal. The offset is spread over a frequency range.

0569<figref idref="DRAWINGS">FIG. 88A</figref> shows an exemplary spreader/de-spreader down-conversion system <b>8800</b>, according to an embodiment of the present invention. Spreader/de-spreader down-converter system <b>8800</b> comprises a UFD module <b>8802</b>, an amplifier <b>8804</b>, a first multiplier <b>8806</b>, a second multiplier <b>8808</b>, an oscillator <b>8826</b>, a pulse shaping circuit <b>8828</b>, and a code generator <b>8832</b>. UFD module <b>8802</b> comprises at least one UFT module. Amplifier <b>8804</b> may introduce an unwanted DC offset voltage onto a signal being down-converted by system <b>8800</b>. Spreader/de-spreader down-conversion system <b>8800</b> operates to reduce or eliminate this unwanted DC offset voltage.

0570Oscillator <b>8826</b> outputs oscillating signal <b>8830</b>. <figref idref="DRAWINGS">FIG. 88C</figref> shows an example waveform for oscillating signal <b>8830</b>. Oscillating signal <b>8830</b> is preferably a periodic sine wave, but may be other periodic signal waveforms such as square wave, triangle wave, ramp wave, and other waveforms.

0571Code generator <b>8832</b> outputs coded sequence signal <b>8816</b>. Coded sequence signal <b>8816</b> is preferably a signal coded according to a pseudo-random code sequence. For example, acceptable pseudo-random coding includes PN coding. Other applicable code schemes such as are also within the scope of the present invention, such as square waves and Manchester encoding. <figref idref="DRAWINGS">FIG. 88D</figref> shows at least a portion of an example coded sequence signal <b>8816</b>.

0572First multiplier <b>8806</b> receives oscillating signal <b>8830</b> and coded sequence signal <b>8816</b>. First multiplier <b>8806</b> multiplies oscillating signal <b>8830</b> and coded sequence signal <b>8816</b>, and outputs a coded oscillating signal <b>8814</b>. Coded oscillating signal <b>8814</b> comprises at least some cycles of oscillating signal <b>8830</b> modified (or spread or coded) according to coded sequence signal <b>8816</b>. <figref idref="DRAWINGS">FIG. 88E</figref> shows an example waveform for coded oscillating signal <b>8814</b>.

0573In a preferred embodiment, when coded sequence signal <b>8816</b> is a “high” signal and/or represents a “1”, the phase of corresponding cycle(s) of oscillating signal <b>8830</b> are not modified, and when coded sequence signal <b>8816</b> is a “low” signal and/or represents a “0” or a “−1”, the phase of corresponding cycle(s) of coded oscillating signal <b>8814</b> are shifted 180 degrees. For example, as shown in <figref idref="DRAWINGS">FIG. 88H</figref>, in the time that occurs prior to time line <b>8834</b>, coded sequence signal <b>8816</b> is high, and hence coded oscillating signal <b>8814</b> is essentially equal to oscillating signal <b>8830</b>. In the time occurring between time lines <b>8834</b> and <b>8836</b>, coded sequence signal <b>8816</b> is low, and hence coded oscillating signal <b>8814</b> is essentially equal to oscillating signal <b>8830</b> with its phase shifted by 180 degrees.

0574Pulse-shaping circuit <b>8828</b> inputs coded oscillating signal <b>8814</b>. The output of pulse-shaping circuit <b>8828</b> is a coded control signal <b>8818</b>, which preferably comprises a string of pulses. Coded control signal <b>8818</b> comprises at least some pulses that are modified (or spread or coded) according to coded sequence signal <b>8816</b>. <figref idref="DRAWINGS">FIG. 88F</figref> shows an example waveform for coded control signal <b>8818</b>. Pulse-shaping circuit <b>8828</b> controls the pulse width of pulses of coded control signal <b>8818</b>.

0575UFD module <b>8802</b> receives an input RF signal <b>8812</b> (although it could be an unmodulated signal) and coded control signal <b>8818</b>. <figref idref="DRAWINGS">FIG. 88B</figref> shows an example waveform for input RF signal <b>8812</b>. UFD module <b>8802</b> frequency down-converts and spectrally spreads input RF signal <b>8812</b> to down-converted spread spectrum signal <b>8820</b>, according to coded control signal <b>8818</b>. <figref idref="DRAWINGS">FIG. 88G</figref> shows an example waveform for down-converted spread spectrum signal <b>8820</b>.

0576For example, <figref idref="DRAWINGS">FIG. 88F</figref> shows an embodiment where coded control signal <b>8818</b> is PN coded. For a positive PN code chip (for example, prior to time line <b>8834</b>), the input RF signal <b>8812</b> is effectively down-converted to down-converted spread spectrums signal <b>8820</b> in a normal, non-inverted fashion. For a negative PN code chip (for example, between time lines <b>8834</b> and <b>8836</b>), the phase of one or more cycles of coded control signal <b>8818</b> are shifted by 180 degrees, and therefore the opposite phase of input RF signal <b>8812</b> is sampled. Hence, for a negative PN code chip, a segment of input RF signal <b>8812</b> is effectively inverted and down-converted to down-converted spread spectrum signal <b>8820</b>.

0577Down-converted spread spectrum signal <b>8820</b> is optionally amplified and/or otherwise processed by amplifier <b>8804</b> (or other circuitry or processing modules), and a processed down-converted spread spectrum signal <b>8822</b> results.

0578Unwanted DC offset may be summed into down-converted spread spectrum signal <b>8820</b> during and after down-conversion and spectral spreading, and during and after processing by amplifier <b>8804</b>.

0579Second multiplier <b>8808</b> receives coded sequence signal <b>8816</b> and processed down-converted spread spectrum signal <b>8822</b>. Second multiplier <b>8808</b> multiplies coded sequence signal <b>8816</b> and amplified down-converted spread spectrum signal <b>8822</b>. Down-converted spread spectrum signal <b>8822</b> is spectrally de-spread in second multiplier <b>8808</b>, and baseband signal <b>8824</b> is output. <figref idref="DRAWINGS">FIG. 88H</figref> shows an example waveform for baseband signal <b>8824</b>. The unwanted DC offset is spectrally spread in second multiplier <b>8808</b>, reducing or removing the offset from baseband signal <b>8822</b>. Baseband signal <b>8822</b> may be a baseband information signal, or may be an intermediate frequency (IF) signal.

0580For example, in an embodiment using PN coding, for a positive PN code chip, amplified down-converted spread spectrum signal <b>8822</b> is multiplied by 1 (not inverted) in second multiplier <b>8808</b>. For a negative PN code chip, the amplified down-converted spread spectrum signal <b>8822</b> is multiplied by −1 (inverted). In this manner down-converted spread spectrum signal <b>8822</b> is spectrally de-spread.

0581<figref idref="DRAWINGS">FIG. 88H</figref> shows a pulse <b>8838</b> in the example waveform of baseband signal <b>8824</b>. Pulse <b>8838</b> may result from the phase shift of coded oscillating signal <b>8814</b> in multiplier <b>8806</b> causing a delay between edges of coded sequence signal <b>8816</b> and down-converted spread spectrum signal <b>8820</b>. In preferred embodiments, each chip or pulse of control signal <b>8816</b> may be equal in length to a substantial number of cycles of oscillating signal <b>8830</b>, potentially in the hundreds or greater (the example of <figref idref="DRAWINGS">FIG. 88H</figref> does not show this). Because of this, pulse <b>8838</b> will occur relatively infrequently on baseband signal <b>8824</b>, is of high frequency relative to baseband signal <b>8824</b>, and hence may be filtered out of baseband signal <b>8824</b> by a conventional filter.

0582Although only a single down-conversion channel is illustrated in the example embodiment of <figref idref="DRAWINGS">FIG. 88A</figref>, the present invention may be extended to two or more channel embodiments, including I/Q modulation system embodiments. The spreading sequence, spreading rate, and sequence length may be selected according to the signaling scheme, data rate, and other factors, as would be apparent to persons skilled in the relevant art(s) from the teachings contained herein. Furthermore, the present invention is applicable to conventional down-converter embodiments, such as shown in <figref idref="DRAWINGS">FIG. 89</figref>.

0583<figref idref="DRAWINGS">FIG. 108</figref> depicts a flowchart <b>10800</b> that illustrates operational steps corresponding to the structures of <figref idref="DRAWINGS">FIGS. 88A and 89</figref>, for down-converting and spectrally spreading an input signal, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 108</figref> will be described.

0584In step <b>10802</b>, an input signal is down-converted. In embodiments, the input signal is down-converted with a universal frequency down-conversion module according to a coded control signal.

0585In step <b>10804</b>, the down-converted input signal is spectrally spread to a down-converted spread spectrum signal. In embodiments, step <b>10804</b> may be at least partially integral with step <b>10802</b>.

0586In step <b>10806</b>, the down-converted spread spectrum signal is processed. For instance, the down-converted spread spectrum signal may be amplified, filtered, or otherwise processed, as further described above. Furthermore, a DC offset voltage may be summed with the down-converted spread spectrum signal, as described further above.

0587In step <b>10808</b>, the down-converted spread spectrum signal is spectrally de-spread to a baseband signal. The down-converted spread spectrum signal is multiplied with a code used to code the control signal. Furthermore, during this step, the DC offset voltage is spectrally spread, as further described above.

0588For illustrative purposes, the operation of the invention is often represented by flowcharts, such as flowchart <b>10800</b> in <figref idref="DRAWINGS">FIG. 108</figref>. It should be understood, however, that the use of flowcharts is for illustrative purposes only, and is not limiting. For example, the invention is not limited to the operational embodiment(s) represented by the flowcharts. Instead, alternative operational embodiments will be apparent to persons skilled in the relevant art(s) based on the discussion contained herein. Also, the use of flowcharts should not be interpreted as limiting the invention to discrete or digital operation. In practice, as will be appreciated by persons skilled in the relevant art(s) based on the herein discussion, the invention can be achieved via discrete or continuous operation, or a combination thereof. Further, the flow of control represented by the flowcharts is provided for illustrative purposes only. Steps may occur in a different order than shown. Furthermore, as will be appreciated by persons skilled in the relevant art(s), other operational control flows are within the scope and spirit of the present invention.

05897.2.1.3 Charge Injection Reduction Embodiment

0590The spectral spreading/de-spreading embodiments described above reduce or eliminate DC offset from a variety of sources. In this section, an alternative embodiment, according to the present invention, is provided for reducing or eliminating DC offset due at least to charge injection. <figref idref="DRAWINGS">FIG. 90</figref> illustrates some aspects of charge injection related to the present invention. <figref idref="DRAWINGS">FIG. 90</figref> shows a UFD module <b>9000</b> comprising a UFT module <b>9002</b>, a storage device <b>9004</b>, and a reference potential <b>9006</b>. In an embodiment, UFT module <b>9002</b> comprises a MOSFET <b>9008</b>, and storage device <b>9004</b> comprises a capacitor <b>9010</b>, although the invention is not limited to this example.

0591An input RF signal <b>9014</b> is received by a first terminal <b>9028</b> of MOSFET <b>9008</b>. A control signal <b>9018</b> is received by a second terminal <b>9030</b> of MOSFET <b>9008</b>. A third terminal <b>9032</b> of MOSFET <b>9008</b> is coupled to a first terminal <b>9034</b> of storage device <b>9004</b>. A second terminal <b>9036</b> of storage device <b>9004</b> is coupled to reference potential <b>9006</b> such as a ground <b>9012</b>, or some other potential. In an embodiment, MOSFET <b>9008</b> contained within UFT module <b>9002</b> opens and closes as a function of control signal <b>9018</b>. As a result of the opening and closing of this switch, a down-converted signal, referred to as output signal <b>9016</b>, results.

0592A well known phenomenon called charge injection may occur in such a switching environment. As control signal <b>9018</b> applies a pulse waveform to the gate of MOSFET <b>9008</b>, MOSFET <b>9008</b> is caused to open and close. During this operation, charge allowed to flow along a DC path <b>9024</b> may build on the gate-to-drain and/or gate-to-source junctions of MOSFET <b>9008</b>, as indicated on <figref idref="DRAWINGS">FIG. 90</figref> as charge buildup <b>9020</b> (note that the source and drain terminals of MOSFET <b>9008</b> are essentially interchangeable). Charge buildup <b>9020</b> may leak from MOSFET <b>9020</b> through leakage path <b>9022</b>, and become stored on capacitor <b>9010</b>. This charge that becomes stored on capacitor <b>9010</b> may cause a change in the voltage across capacitor <b>9010</b>. This voltage change may accordingly appear on output signal <b>9016</b> as a potentially non-negligible DC offset voltage. This non-negligible DC offset voltage on output signal <b>9016</b> may lead to difficulties in recovering the baseband information content of output signal <b>9016</b>. Hence, it would be advantageous to reduce or prevent this potential generation of DC offset voltage caused by this interaction of control signal <b>9018</b> with UFD module <b>9000</b>.

0593<figref idref="DRAWINGS">FIG. 91</figref> illustrates an exemplary circuit configuration for reducing unwanted DC offset voltage caused by charge injection, according to an embodiment of the present invention.

0594<figref idref="DRAWINGS">FIG. 91</figref> shows UFD module <b>9000</b> of <figref idref="DRAWINGS">FIG. 90</figref>, with a capacitor <b>9126</b> coupled between input RF signal <b>9014</b> and UFD module <b>9000</b>. Capacitor <b>9126</b> is preferably a small valued capacitor, such as, but not limited to, 10 pF. The value for capacitor <b>9126</b> will vary depending upon the application, and accordingly its characteristics are implementation and application specific. Capacitor <b>9126</b> prevents DC current from flowing along the path shown as DC path <b>9024</b> in <figref idref="DRAWINGS">FIG. 90</figref>, and thus reduces or prevents the flow of charge to, and build up of charge on capacitor <b>9010</b>. This in turn reduces or prevents a DC offset voltage resulting from the above described charge injection from appearing on output signal <b>9016</b>. Hence, the baseband information content of output signal <b>9016</b> may be more accurately ascertained.

0595<figref idref="DRAWINGS">FIG. 109</figref> depicts a flowchart <b>10900</b> that illustrates operational steps corresponding to <figref idref="DRAWINGS">FIG. 91</figref>, for down-converting an input signal and reducing a DC offset voltage, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 109</figref> will be described.

0596In step <b>10902</b>, an input signal is coupled by a series capacitor to an input of a universal frequency down-conversion module.

0597In step <b>10904</b>, the input signal is frequency down-converted with the universal frequency down-conversion module to a down-converted signal. The input signal is down-converted according to a control signal. The control signal under-samples the input signal.

0598In step <b>10906</b>, a DC offset voltage in the down-converted signal generated during step <b>10904</b> is reduced. In an embodiment, the DC offset voltage is generated at least by charge injection effects due to interaction of the control signal with the universal frequency down-conversion module, as further described above.

0599It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

06007.2.1.4 Auto-Zero Compensation

0601Unwanted DC offset may be injected by circuit components in the intermediate frequency (IF) processing path or baseband processing path following a UFD module. In some cases, this DC offset voltage must be reduced or eliminated. In some situations, the output signal down-converted by the UFD module may be a low level signal, where even small DC offsets inserted by components following the UFD module may undesirably affect its value.

0602The previous section described inserting a series capacitor prior to the UFD module to reduce DC offset voltages due to charge injection. In embodiments, a capacitor may be added in series in the baseband processing path after a UFD module to reduce or eliminate DC offset voltages. In some situations, however, adding a capacitor in series in the baseband processing path after the UFD module is not desirable. For instance, in some situations, it may be difficult to charge such a series capacitor reliably.

0603<figref idref="DRAWINGS">FIG. 92A</figref> illustrates an exemplary down-conversion system <b>9252</b>, according to an embodiment of the present invention, that may be used to indicate potential points in a signal path where DC offset voltages may be injected. Down-conversion system <b>9252</b> comprises a UFD module <b>9246</b>, a filter <b>9248</b>, an amplifier <b>9202</b>, and an optional IF down-converter <b>9250</b>. UFD module <b>9246</b> comprises a UFT module <b>9254</b>. UFD module <b>9246</b> down-converts an input RF signal <b>9256</b>, as described elsewhere herein, and outputs a down-converted signal <b>9258</b>. Down-converted signal <b>9258</b> may be a baseband signal, in which case IF down-converter <b>9250</b> is not required, or may be an intermediate frequency signal. Filter <b>9248</b> receives and filters down-converted signal <b>9258</b>, and outputs a filtered signal <b>9260</b>. Amplifier <b>9202</b> receives and amplifies filtered signal <b>9260</b>, and outputs an amplified signal <b>9262</b>. Optional IF down-converter <b>9250</b>, when present, receives and further down-converts amplified signal <b>9262</b>, and outputs an output signal <b>9264</b>. Additional IF down-converter modules may be included as needed.

0604UFD module <b>9246</b>, filter <b>9248</b>, amplifier <b>9202</b>, and optional IF down-converter <b>9250</b> may each add a DC offset voltage to their respective outputs signals. As described above, the DC offset voltage may undesirably affect the value of the down-converted signal. It would be desirable to provide a circuit that may be inserted for any of the components shown in <figref idref="DRAWINGS">FIG. 92A</figref> (such as following such components), and any other applicable circuit components, to eliminate DC offset voltages at that point.

0605<figref idref="DRAWINGS">FIG. 92B</figref> illustrates an exemplary auto-zero compensation circuit <b>9200</b> for reducing or eliminating DC offset inserted by any of the above described circuit components, with amplifier <b>9202</b> of <figref idref="DRAWINGS">FIG. 92A</figref> shown as an example, according to an embodiment of the present invention. The present invention is also applicable to reducing or eliminating DC offsets inserted by other types of circuit components.

0606In the example circuit shown, auto-zero compensation circuit <b>9200</b> is located following amplifier <b>9202</b> (see also <figref idref="DRAWINGS">FIG. 92A</figref>). In other implementations, auto-zero compensation circuit <b>9200</b> may follow any applicable circuit component in the down-converted signal path, including a UFD module. While amplifier <b>9202</b> is located in the down-converted signal path, components of auto-zero compensation circuit <b>9200</b> are located largely outside of the down-converted signal path. Auto-zero compensation circuit <b>9200</b> provides many of the same advantages as having a capacitor located in series in the down-converted signal path. Auto-zero compensation circuit <b>9200</b> comprises a resistor <b>9204</b>, a switch <b>9206</b>, a capacitor <b>9208</b>, a first summer <b>9210</b>, a second summer <b>9212</b>, a first voltage reference <b>9214</b>, and a second voltage reference <b>9216</b>.

0607Amplifier <b>9202</b> receives an input signal <b>9260</b>, and outputs an amplified input signal <b>9262</b>. Amplified input signal <b>9262</b> may comprise an unwanted DC offset voltage due to amplifier <b>9202</b>. While an ideal amplifier has zero input offset voltage (i.e., DC offset voltage referred to the input) and no offset voltage drift, most actual amplifiers have offset voltages due to a mismatch of input transistors and resistors on the monolithic circuit. This input offset voltage may drift across temperature, and hence most amplifiers are specified with an input offset voltage temperature coefficient. An amplifier may suffer from further offset voltage from input bias currents. While an ideal amplifier has zero current flowing into and out of its inputs, most actual amplifiers have non-zero input bias currents flowing into and out of their inputs. These currents can create an input voltage that resembles a DC offset voltage when they flow through resistors coupled to the amplifier inputs. Auto-zero compensation circuit <b>9200</b> removes DC offset voltages and voltage drift created by these mechanisms.

0608A first terminal <b>9226</b> of resistor <b>9204</b> and a first terminal <b>9228</b> of switch <b>9206</b> are coupled to amplified input signal <b>9262</b>. A second terminal <b>9230</b> of resistor <b>9204</b> and a second terminal <b>9232</b> of switch <b>9206</b> are coupled to a first terminal <b>9234</b> of capacitor <b>9208</b> and a first input terminal <b>9236</b> of second summer <b>9212</b>. A third terminal <b>9244</b> of switch <b>9206</b> is coupled to a receive mode signal <b>9242</b>. A second terminal <b>9238</b> of capacitor <b>9208</b> is coupled to first voltage reference <b>9214</b>. A second input terminal <b>9240</b> of second summer <b>9212</b> is coupled to second voltage reference <b>9216</b>. First and second voltage references <b>9214</b> and <b>9216</b> may or may not be equal to the same voltage value.

0609A receiver system may incorporate one or more auto-zero compensation circuits <b>9200</b> in its down-converted signal path. When such a receiver system enters a receive mode, i.e., it has entered a mode where it is ready to down-convert received signals, a receive mode signal <b>9242</b> is activated. Receive mode signal <b>9242</b> causes switch <b>9206</b> to close, and capacitor <b>9208</b> charges to the output voltage of amplifier <b>9202</b>. Hence, capacitor <b>9208</b> attains, or is charged with the value of the output of amplifier <b>9202</b>, which comprises any DC offset voltage due to amplifier <b>9202</b>. Capacitor <b>9208</b> may be a relatively large value capacitor, such as 1.0-0.1 μF, but the invention is not limited to this range.

0610After switch <b>9206</b> is closed for a length of time sufficient to charge capacitor <b>9208</b> to the value of amplified output signal <b>9262</b>, (the output of amplifier <b>9202</b>), receive mode signal <b>9242</b> causes switch <b>9206</b> to open. When switch <b>9206</b> is open, the path from amplifier <b>9202</b> to the first terminal <b>9234</b> of capacitor <b>9208</b> is through resistor <b>9204</b>. Resistor <b>9204</b> may be a relatively large value resistor, but the invention is not limited to this example. In this configuration, capacitor <b>9208</b> relatively slowly follows the voltage of the output of amplifier <b>9202</b>. In this way, capacitor <b>9208</b> maintains the DC offset voltage value of amplifier <b>9202</b>, following any DC offset voltage drift due to changes in environmental temperature and the like.

0611Second summer <b>9212</b> adds the voltage stored in capacitor <b>9208</b> with the value of second voltage reference <b>9216</b>, and outputs adjusted DC offset voltage <b>9224</b>. Second voltage reference <b>9216</b> may be used to adjust or center the circuit output voltage, as described below. In alternate embodiments, second voltage reference <b>9216</b> and second summer <b>9212</b> are not present, and the first terminal <b>9234</b> of capacitor <b>9208</b> is coupled to first summer <b>9210</b>.

0612First summer <b>9210</b> subtracts the adjusted DC offset voltage <b>9224</b> from amplified input signal <b>9262</b>, and outputs DC offset adjusted output signal <b>9220</b> (which is received by the IF down-converter <b>9250</b> in the example of <figref idref="DRAWINGS">FIG. 92A</figref>). DC Offset adjusted output signal <b>9220</b> is substantially equal to input signal <b>9260</b> amplified by amplifier <b>9202</b>, centered according to second voltage reference <b>9216</b> (if present), with the DC offset due to amplifier <b>9202</b> substantially reduced or eliminated.

0613<figref idref="DRAWINGS">FIG. 110</figref> depicts a flowchart <b>11000</b> that illustrates operational steps corresponding to <figref idref="DRAWINGS">FIG. 92B</figref>, for reducing DC offset in a signal path, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 110</figref> will be described.

0614In step <b>11002</b>, a DC offset voltage in an input signal is stored while in a signal non-receive mode.

0615In step <b>11004</b>, the mode is changed to a signal receive mode.

0616In step <b>11006</b>, the input signal is followed relatively slowly to maintain the DC offset voltage and any DC offset voltage drift.

0617In step <b>11008</b>, the maintained DC offset voltage is summed with a centering voltage to form an adjusted DC offset voltage signal. A centering voltage such as second voltage reference <b>9216</b> may be used.

0618In step <b>11010</b>, the adjusted DC offset voltage signal is subtracted from the input signal to form a DC offset adjusted output signal.

0619It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

06207.2.1.5 Reducing DC Offset with Differential Configurations

0621DC offset voltages due to charge injection may also be reduced or eliminated through the use of differential UFD module configurations. Furthermore, circuit re-radiation may be reduced or eliminated through the use of differential UFD module configurations. Exemplary differential UFD module circuit embodiments are described below. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

0622In an embodiment, two UFD modules are arranged in a differential configuration, where a first UFD module receives an actual RF signal as an input, and a second UFD module receives circuit ground, or some other circuit voltage, as an input. Furthermore, both UFD modules receive the same control signal. As a result, the two UFD modules produce substantially similar DC offset voltages due to charge injection. The UFD module output signals may be subtracted from each other, and as a result the DC offset voltage due to charge injection in the output of the first UFD module will be subtracted out.

0623<figref idref="DRAWINGS">FIG. 93</figref> illustrates an exemplary differential DC offset voltage cancellation circuit <b>9300</b>, according to an embodiment of the present invention. Differential DC offset voltage cancellation circuit <b>9300</b> includes an optional LNA <b>9302</b>, a first UFD module <b>9358</b>, a second UFD module <b>9360</b>, a control signal generator <b>9310</b>, a dummy impedance <b>9312</b>, a second voltage reference <b>9314</b>, and a summer <b>9322</b>. In an embodiment, first UFD module <b>9358</b> comprises a first UFT module <b>9304</b>, a first voltage reference <b>9306</b>, and a first capacitor <b>9308</b>, and second UFD module <b>9360</b> comprises a second UFT module <b>9316</b>, a second capacitor <b>9318</b>, and a third voltage reference <b>9320</b>.

0624Optional LNA <b>9302</b> receives an input RF signal <b>9324</b> and outputs an amplified input RF signal <b>9326</b>.

0625Amplified input RF signal <b>9326</b> is received by a first terminal <b>9356</b> of first UFT module <b>9304</b>. A second terminal <b>9338</b> of first UFT module <b>9304</b> is coupled to a first terminal <b>9340</b> of first capacitor <b>9308</b>. First capacitor <b>9308</b> may be any type of applicable storage device. A third terminal <b>9342</b> of first UFT module <b>9304</b> receives a control signal <b>9328</b>. Control signal <b>9328</b> is generated by control signal generator <b>9310</b>. First UFT module <b>9304</b> down-converts amplified input RF signal <b>9326</b> according to control signal <b>9328</b> in a manner as described elsewhere herein. First UFT module <b>9304</b> outputs actual output signal <b>9330</b> (it is called the “actual” output signal <b>9330</b> because it is derived from input RF signal <b>9324</b>), which is stored on first capacitor <b>9308</b>. As described above, first UFT module <b>9304</b> may add unwanted DC offset voltage to actual output signal <b>9330</b>, due to charge injection effects.

0626A first terminal <b>9344</b> of second UFT module <b>9316</b> receives dummy input signal <b>9332</b> (it is called a “dummy” input signal <b>9332</b> because it is not a received signal, but is instead generated to address offset issues) from a first terminal <b>9346</b> of dummy impedance <b>9312</b>. A second terminal <b>9348</b> of dummy impedance <b>9312</b> is coupled to second voltage reference <b>9314</b>. Second voltage reference <b>9314</b> is a circuit voltage, preferably ground. Impedance <b>9312</b> approximates for second UFT module <b>9316</b> the input impedance presented to the input of first UFT module <b>9304</b> (that is, impedance <b>9312</b> is substantially equal to the input impedance of first UFT module <b>9304</b>). Impedance <b>9312</b> is implemented using any well known combination of circuit elements. A second terminal <b>9350</b> of second UFT module <b>9316</b> is coupled to a first terminal <b>9352</b> of second capacitor <b>9318</b>. A third terminal <b>9354</b> of second UFT module <b>9316</b> receives control signal <b>9328</b>. Second UFT module <b>9316</b> down-converts dummy input signal <b>9332</b> according to control signal <b>9328</b> in a similar fashion as described above. Second UFT module <b>9316</b> outputs dummy output signal <b>9334</b>, which is stored on second capacitor <b>9318</b>. Dummy output signal <b>9334</b> comprises unwanted DC offset voltage due to charge injection effects in second UFT module <b>9316</b>, similar to that generated by first UFT module <b>9304</b>. The DC offset voltages due to charge injection on actual output signal <b>9330</b> and dummy output signal <b>9334</b> are substantially similar due to the similar UFT module configurations.

0627Summer <b>9322</b> subtracts dummy output signal <b>9334</b> from actual output signal <b>9330</b>, and outputs output signal <b>9336</b>. Output signal <b>9336</b> is a down-converted version of input RF signal <b>9324</b>, with DC offset due to charge injection in UFT module <b>9304</b> substantially reduced or eliminated by subtracting out the DC offset similarly created in UFT module <b>9316</b>.

0628Preferably, the noise entering on first terminals <b>9356</b> and <b>9344</b> of UFT modules <b>9304</b> and <b>9316</b> is matched. If the frequency spectrum of the noise entering first UFT module <b>9304</b> on input RF signal <b>9324</b> is different than the noise entering second UFT module <b>9316</b> from second voltage reference <b>9314</b>, the difference may show up on output signal <b>9336</b>. One example of where the noise spectrums may be different is when there is a filter on input RF signal <b>9324</b> prior to first UFT module <b>9304</b>, which filters out some noise frequencies. This difference may be solved, for example, by placing a similar filter at the input of second UFT module <b>9316</b>.

0629<figref idref="DRAWINGS">FIG. 111</figref> depicts a flowchart <b>11100</b> that illustrates operational steps, corresponding to the structure of <figref idref="DRAWINGS">FIG. 93</figref>, for down-converting an input signal and canceling DC offset voltages, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 111</figref> will be described.

0630In step <b>11102</b>, an input signal is received.

0631In step <b>11104</b>, the input signal is frequency down-converted with a first universal frequency down-conversion module to an actual down-converted signal.

0632In step <b>11106</b>, a dummy input signal is received. In an embodiment, a dummy impedance is matched with the input impedance of an input of the first universal frequency down-conversion module. The matched dummy impedance is coupled to an input of the second universal frequency down-conversion module to form the dummy input signal.

0633In step <b>11108</b>, the dummy signal is frequency down-converted with a second universal frequency down-conversion module to a dummy down-converted signal.

0634In step <b>11110</b>, the dummy down-converted signal is subtracted from the actual down-converted signal to form an output signal. DC offset voltages due to said first and said second universal frequency down-conversion modules are canceled by the subtraction of step <b>11110</b>, as further described above.

0635<figref idref="DRAWINGS">FIG. 94A</figref> illustrates a second exemplary differential DC offset voltage cancellation circuit <b>9400</b>, according to an embodiment of the present invention. Differential DC offset voltage cancellation circuit <b>9400</b> is effective at reducing or eliminating DC offset voltages due to charge injection and at reducing or eliminating circuit re-radiation. Differential DC offset voltage cancellation circuit <b>9400</b> comprises a buffer/inverter <b>9402</b>, a first UFD module <b>9434</b>, a second UFD module <b>9436</b>, a control signal generator <b>9410</b>, and a summer <b>9422</b>. In an embodiment, first UFD module <b>9434</b> comprises a first UFT module <b>9404</b>, a first voltage reference <b>9406</b>, and a first capacitor <b>9408</b>, and second UFD module <b>9436</b> comprises a second UFT module <b>9416</b>, a second capacitor <b>9418</b>, and a second voltage reference <b>9420</b>.

0636<figref idref="DRAWINGS">FIG. 94B</figref> illustrates example waveforms related to differential DC offset voltage cancellation circuit <b>9400</b> of <figref idref="DRAWINGS">FIG. 94A</figref>, according to an embodiment of the present invention.

0637Buffer/inverter <b>9402</b> receives an input RF signal <b>9424</b>. <figref idref="DRAWINGS">FIG. 94B</figref> shows an example waveform for input RF signal <b>9424</b>. Buffer/inverter <b>9402</b> outputs a non-inverted amplified input RF signal <b>9412</b> and an inverted amplified input RF signal <b>9414</b>. Buffer/inverter <b>9402</b> may comprise any circuit component or equivalent that receives a single-ended signal and outputs a differential signal, such as a differential driver. Non-inverted amplified input RF signal <b>9412</b> and inverted amplified input RF signal <b>9414</b> are substantially similar signals, but inverted images of each other. <figref idref="DRAWINGS">FIGS. 94C and 94</figref> D show example waveforms for non-inverted amplified input RF signal <b>9412</b> and inverted amplified input RF signal <b>9414</b>, respectively. In the example of <figref idref="DRAWINGS">FIGS. 94C and 94D</figref>, buffer/inverter <b>9402</b> has a gain of 2, and therefore the amplitudes of non-inverted amplified input RF signal <b>9412</b> (<figref idref="DRAWINGS">FIG. 94C</figref>) and inverted amplified input RF signal <b>9414</b> (<figref idref="DRAWINGS">FIG. 94D</figref>) are two times greater than that of input RF signal <b>9424</b> (<figref idref="DRAWINGS">FIG. 94B</figref>).

0638First and second UFT modules <b>9404</b> and <b>9416</b> operate similarly to first and second UFT modules <b>9304</b> and <b>9316</b> of <figref idref="DRAWINGS">FIG. 93</figref>. First UFT module <b>9404</b> receives non-inverted amplified input RF signal <b>9412</b>. First UFT module <b>9404</b> operates to down-convert non-inverted amplified input RF signal <b>9412</b> according to a control signal <b>9428</b>, which is output by control signal generator <b>9410</b>. <figref idref="DRAWINGS">FIG. 94E</figref> shows an example waveform for control signal <b>9428</b>. First UFT module <b>9404</b> outputs a non-inverted output signal <b>9430</b>. Non-inverted output signal <b>9430</b> comprises DC offset voltage due to charge injection effects in first UFT module <b>9404</b>, as described above.

0639<figref idref="DRAWINGS">FIG. 94F</figref> shows an example waveform for non-inverted output signal <b>9430</b>. In this example, amplified input RF signal <b>9412</b> is down-converted to non-inverted output signal <b>9430</b> at a value of 0.4 Volts, with a DC offset voltage of 0.1 Volts added, resulting in a total of 0.5 Volts.

0640Second UFT module <b>9416</b> receives inverted amplified input RF signal <b>9414</b>. Second UFT module <b>9416</b> down-converts inverted amplified input RF signal <b>9414</b> according to control signal <b>9428</b>, and outputs inverted output signal <b>9432</b>. Inverted output signal <b>9432</b> comprises DC offset voltage due to charge injection in second UFT module <b>9416</b>. <figref idref="DRAWINGS">FIG. 94G</figref> shows an example waveform for inverted output signal <b>9432</b>. Due at least in part to the similarity in the layouts and circuit configurations of first and second UFT modules <b>9404</b> and <b>9416</b>, their resulting DC offset voltages due to charge injection will be substantially similar, and of the same polarity. In the example of <figref idref="DRAWINGS">FIG. 94G</figref>, inverted amplified input RF signal <b>9414</b> is down-converted to inverted output signal <b>9432</b> at a value of −0.4 Volts, with a DC offset voltage of 0.1 Volts added, resulting in a total of −0.3 Volts. As shown in <figref idref="DRAWINGS">FIGS. 94F and 94G</figref>, the polarities of non-inverted output signal <b>9430</b> and inverted output signal <b>9432</b> are opposite. The DC offset voltages added respectively to these signals by first UFT module <b>9404</b> and second UFT module <b>9416</b> are equal at 0.1 Volts.

0641Summer <b>9422</b> subtracts inverted output signal <b>9432</b> from non-inverted output signal <b>9430</b>, and outputs an output signal <b>9426</b>. <figref idref="DRAWINGS">FIG. 94H</figref> shows an example waveform for output signal <b>9426</b>. Because non-inverted output signal <b>9430</b> and inverted output signal <b>9432</b> comprise the same down-converted signal, but of opposite polarities, when subtracted by summer <b>9422</b>, the respective down-converted signals will add. Because the DC offset voltages in non-inverted output signal <b>9430</b> and inverted output signal <b>9432</b> are of the same polarity and of substantially the same amplitude, when they are subtracted by summer <b>9422</b> the DC offset voltages will substantially cancel. As a result, any DC offset voltage in output signal <b>9426</b> will be substantially reduced or eliminated. As shown in the example of <figref idref="DRAWINGS">FIGS. 94F-94H</figref>, the amplitudes of non-inverted output signal <b>9430</b> and inverted output signal <b>9432</b> combine in summer <b>9422</b> to equal 0.8 Volts, while the DC offset voltages of 0.1 Volts cancel each other. Thus, the embodiment of <figref idref="DRAWINGS">FIG. 94A</figref> both enhances signal amplitude and addresses DC offset issues.

0642Additionally, re-radiation may be substantially reduced or eliminated due to this configuration. Control signal noise produced in first and second UFT modules <b>9404</b> and <b>9416</b> due to pulses on control signal <b>9428</b> may travel back through buffer/inverter <b>9402</b>. If first and second UFT modules <b>9404</b> and <b>9416</b> are configured in a substantially similar fashion and receive the same control signal, they will produce substantially equivalent control signal noise. Because the control signal noise from second UFT module <b>9416</b> will be inverted by buffer/inverter <b>9402</b> when passing back through buffer/inverter <b>9402</b>, it will cancel when combined with the non-inverted control signal noise from first UFT module <b>9404</b> passing back through buffer/inverter <b>9402</b>. Furthermore, the noise matching concerns of the prior differential circuit embodiment of <figref idref="DRAWINGS">FIG. 93</figref> are not present in this embodiment.

0643<figref idref="DRAWINGS">FIG. 112</figref> depicts a flowchart <b>11200</b> that illustrates operational steps, corresponding to the structure of <figref idref="DRAWINGS">FIG. 94A</figref>, for down-converting an input signal and canceling DC offset voltages, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 112</figref> will be described.

0644In step <b>11202</b>, an input signal is received.

0645In step <b>11204</b>, the received input signal is amplified to a non-inverted output signal and an inverted output signal.

0646In step <b>11206</b>, the non-inverted output signal is down-converted with a first universal frequency down-conversion module to a non-inverted down-converted signal.

0647In step <b>11208</b>, the inverted output signal is down-converted with a second universal frequency down-conversion module to an inverted down-converted signal.

0648In step <b>11210</b>, the inverted down-converted signal is subtracted from the non-inverted down-converted signal to form an output signal. DC offset voltages in the non-inverted down-converted signal and the inverted down-converted signal produced by the first and second universal frequency down-conversion modules, respectively, are canceled.

0649In step <b>11212</b>, the first universal frequency down-conversion module and the second universal frequency down-conversion module are configured to generate substantially equal DC offset voltages given the same input signal.

0650It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

06517.2.1.6 Reducing DC Offset with Differential Outputs

0652Unwanted DC offset voltages may be reduced or canceled through the use of differential receiver circuit outputs. <figref idref="DRAWINGS">FIG. 95</figref> illustrates an exemplary differential receiver circuit <b>9500</b>, according to an embodiment of the present invention. Differential receiver circuit <b>9500</b> comprises a first impedance match <b>9502</b>, a second impedance match <b>9504</b>, a tank circuit <b>9506</b>, a differential UFD module <b>9508</b>, a control signal generator <b>9510</b>, and a resistor <b>9512</b>.

0653First and second impedance match <b>9502</b> and <b>9504</b> are optional, the necessity of which being determined on an application-by-application basis. In a preferred embodiment, first impedance match <b>9502</b> is a first inductor <b>9514</b>. In a preferred embodiment, second impedance match <b>9504</b> is a second inductor <b>9516</b>. However, other impedance match circuits may be used.

0654Tank circuit <b>9506</b> is optional, the necessity of which being determined on an application-by-application basis. In a preferred embodiment, tank circuit <b>9506</b> comprises a first capacitor <b>9518</b> and a third inductor <b>9520</b>, although other circuits may be used.

0655In a preferred embodiment, differential UFD module <b>9508</b> comprises a first UFT module <b>9522</b>, a second UFT module <b>9524</b>, and a storage module <b>9534</b>. In a preferred embodiment, storage module <b>9534</b> comprises a second capacitor <b>9526</b>.

0656A positive or “plus” signal input of a differential RF input signal <b>9528</b> is input through first impedance match <b>9502</b> to a first terminal <b>9536</b> of tank circuit <b>9506</b>. A negative or “minus” signal input of differential RF input signal <b>9528</b> is input through second impedance match <b>9504</b> to a second terminal <b>9538</b> of tank circuit <b>9506</b>.

0657First UFT module <b>9522</b> is coupled to first terminal <b>9536</b> of tank circuit <b>9506</b>, and receives the “plus” signal input of differential RF input signal <b>9528</b>. Second UFT module <b>9524</b> is coupled to second terminal <b>9538</b> of tank circuit <b>9506</b>, and receives the “minus” signal input of differential RF input signal <b>9528</b>.

0658First and second UFT modules <b>9522</b> and <b>9524</b> down-convert differential RF input signal <b>9528</b> according to a control signal <b>9532</b>, which is output by control signal generator <b>9510</b>, in a manner as described elsewhere herein. The outputs of first and second UFT modules <b>9522</b> and <b>9524</b> are stored in storage module <b>9534</b>, and output as differential output signal <b>9530</b>.

0659First UFT module <b>9522</b> outputs a “plus” output of differential output signal <b>9530</b>. Second UFT module <b>9524</b> outputs a “minus” output of differential output signal <b>9530</b>. Differential output signal <b>9530</b> is equal to the difference voltage between these “plus” and “minus” outputs.

0660A first terminal <b>9540</b> of storage module <b>9534</b> is coupled to the “plus” output of differential output signal <b>9530</b>. A second terminal <b>9542</b> of storage module <b>9534</b> is coupled to the “minus” output of differential output signal <b>9530</b>.

0661Resistor <b>9512</b> is optional, the necessity of which being determined on an application-by-application basis. Resistor <b>9512</b>, when present, operates as a load resistance, the value of which may be determined on an application-by-application basis. A first terminal <b>9544</b> of resistor <b>9512</b> is coupled to the “plus” output of differential output signal <b>9530</b>. A second terminal <b>9546</b> of resistor <b>9512</b> is coupled to the “minus” output of differential output signal <b>9530</b>.

0662Due to their similar layout and circuit configuration, and due to control signal <b>9532</b>, first UFT module <b>9522</b> and second UFT module <b>9524</b> each generate substantially equal DC offset voltages due to charge injection effects. The DC offset voltage generated by first UFT module <b>9522</b> is applied to first terminal <b>9540</b> of storage module <b>9534</b>. The DC offset voltage generated by second UFT module <b>9524</b> is applied to second terminal <b>9542</b> of storage module <b>9534</b>. Because differential output signal <b>9532</b> is measured across storage module <b>9534</b>, the DC offset voltages due to first and second UFT module <b>9522</b> and <b>9524</b> substantially cancel each other out.

0663<figref idref="DRAWINGS">FIG. 113</figref> depicts a flowchart <b>11300</b> that illustrates operational steps, corresponding to the structure of <figref idref="DRAWINGS">FIG. 95</figref>, for differentially down-converting an input signal, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 113</figref> will be described.

0664In step <b>11302</b>, an input signal is differentially received. For example, a positive node input signal and a negative node input signal are received.

0665In step <b>11304</b>, the differentially received input signal is down-converted with a differential universal frequency down-conversion module to a differential down-converted signal. The differential down-converted signal comprises a positive node down-converted signal and a negative node down-converted signal. In an embodiment, the differential universal frequency down-conversion module comprises a positive node switch (UFT) module and a negative node switch (UFT) module. The positive node switch module and the negative node switch module are configured to generate substantially equal DC offset voltages in the positive node down-converted signal and the negative node down-converted signal, respectively, as described above.

0666In step <b>11306</b>, the differential down-converted signal is measured between the positive node down-converted signal and the negative node down-converted signal. The DC offset voltages in the positive node down-converted signal and the negative node down-converted signal substantially cancel, as described above.

0667Further differential circuit configurations for canceling DC offset voltages will be apparent to persons skilled in the relevant art(s) from the teaching herein. Exemplary differential receiver circuit output embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

06687.2.2 Re-Radiation

0669Re-radiation, as described above, is an undesirable phenomenon where a signal comprising one or more frequency components generated by receiving circuitry is transmitted by an antenna. <figref idref="DRAWINGS">FIG. 44A</figref> illustrates an antenna <b>4406</b> that transmits circuit re-radiation signals <b>4414</b> and <b>4420</b>. Receiving circuitry, for example shown as a receiver <b>4402</b> and a local oscillator <b>4404</b>, related to antenna <b>4406</b> may produce the transmitted frequency components. For example, the frequency components may be generated in part by local oscillator <b>4404</b>. These generated frequency components may travel along re-radiation path <b>4418</b>, where they are transmitted by antenna <b>4406</b> as re-radiation signals <b>4414</b> and <b>4420</b>. When transmitted, these frequency components may undesirably interfere with one or more nearby receivers, such as nearby receiver <b>4408</b>. An antenna <b>4420</b> may receive re-radiation signal <b>4420</b>, which is down-converted by nearby receiver <b>4408</b>. One or more of the frequency components of received re-radiation signal <b>4420</b> may fall within a frequency range of interest of nearby receiver <b>4408</b>, interfering with the quality of the signals intended to be down-converted by nearby receiver <b>4408</b>.

0670As described above, re-radiation may be undesirably received back by the same antenna that transmitted the re-radiation. As shown in <figref idref="DRAWINGS">FIG. 44A</figref>, receiver <b>4402</b> may transmit re-radiation signal <b>4414</b>, which is subsequently reflected by an object <b>4412</b> as reflected re-radiation <b>4416</b>, which is then received by antenna <b>4406</b>. This is referred to as re-radiation recapture. If frequency components are received back by the same antenna that transmitted them, they may be down-converted, may further impair signals that are down-converted, and/or may cause undesirable DC offset voltages that may impair the down-converted signals. <figref idref="DRAWINGS">FIG. 44B</figref> shows an example local oscillator signal <b>4422</b>, of a frequency of f. If a signal such as local oscillator signal <b>4422</b> is re-radiated, and subsequently received by the circuit that transmitted it, it may combine with itself to create an undesired DC offset voltage. <figref idref="DRAWINGS">FIG. 44C</figref> shows the Fourier transform of local oscillator signal <b>4422</b>, with spectral components <b>4424</b> and <b>4426</b> at frequencies +f and −f. <figref idref="DRAWINGS">FIG. 44D</figref> shows a result of the convolution of local oscillator signal <b>4422</b> with itself, producing a DC spectral component <b>4432</b> representing an undesired DC offset voltage. <figref idref="DRAWINGS">FIG. 44D</figref> shows resulting spectral components <b>4428</b> and <b>4430</b> at frequencies +2f and −2f, and DC spectral component <b>4432</b> at a frequency of zero. DC spectral component <b>4432</b> may cause the same problems as DC offset voltages created by other mechanisms, such as those described elsewhere herein.

0671For at least these reasons, it is desirable to reduce or eliminate circuit re-radiation. Exemplary embodiments are provided below for reducing or eliminating circuit re-radiation. The embodiments provided below are not limited to this use, but may have additional applications. For example, these embodiments may be applicable to reducing or eliminating unwanted DC offset voltages.

06727.2.2.1 Reducing Re-Radiation by Adjusting Control Signal Attributes

0673In the present invention, a local oscillator may be used to generate a control signal used to down-convert received RF signals. The control signal may comprise frequency components related to the local oscillator frequency and its harmonics. As described above, one or more frequency components of the local oscillator signal may leak from a nearby antenna as circuit re-radiation. As a result, attributes of circuit re-radiation are directly related to attributes of control signal frequency components. Hence, re-radiation potentially may be reduced or eliminated by adjusting one or more attributes of the control signal frequency components. Control signal attributes that may be adjusted at least include control pulses width, control pulse amplitude, and/or control pulse phase.

0674<figref idref="DRAWINGS">FIG. 96</figref> shows an exemplary input RF signal <b>9602</b>. A π-pulse length control signal <b>9604</b> is also shown that may be applied to a UFD module to down-convert input RF signal <b>9602</b>. As shown, π-pulse length control signal <b>9604</b> comprises pulses that are of a length of π radians. In a receiver embodiment implementing a UFD module, a control signal such as π-pulse length control signal <b>9604</b> may be re-radiated from the receiver. In the time domain, the re-radiation may appear as noise pulses that are shaped similarly to pulses of the control signal. In certain situations, one or more of the frequencies of the re-radiated signal may undesirably fall within the output frequency bands of interest of the system implementing the receiver circuit. For instance, when down-converting a signal directly to baseband, a control signal frequency may be substantially equal to the frequency of the received RF carrier signal. If this control signal frequency is re-radiated, and then subsequently received and down-converted, it may result in one or more down-converted signal frequencies near or equal to DC, or at baseband, in a similar fashion to that described in <figref idref="DRAWINGS">FIGS. 44B-D</figref> above. It would be beneficial if the re-radiated signal components within the frequency bands of interest could be eliminated or moved.

0675In an exemplary embodiment for changing the frequency content of the re-radiated signal, the pulse width of the control pulses of the control signal may be lengthened. As shown in <figref idref="DRAWINGS">FIG. 96</figref>, a 3π-pulse length control signal <b>9606</b> has control pulses of a length of 3π. Because the control pulse width of 3π-pulse length control signal <b>9606</b> is wider than that of n-pulse length control signal <b>9604</b>, 3π-pulse length control signal <b>9606</b> is made up of lower frequency components. It is well known that signals comprising substantially square or rectangular pulses include a plurality of signals of various frequencies that add together to form the pulse shapes. As pulses become wider, the frequencies of the signals required to form them tend to become lower. Because 3π-pulse length control signal <b>9606</b> has wider pulses, and therefore contains lower frequency components, a re-radiated signal due to 3π-pulse length control signal <b>9606</b> will have lower frequency components. Even if the lower frequency components are re-radiated, and then received and down-converted, the down-converted components should be out-of-band. In an embodiment, a 3π-pulse length control signal <b>9606</b> configuration re-radiated at a 19 dB lower level than that of a π-pulse length control signal <b>9604</b>.

0676Frequency components of potential re-radiation can be lowered more by further widening the control pulses. For example, <figref idref="DRAWINGS">FIG. 96</figref> shows a 5π-pulse length control signal <b>9608</b> with control signal pulses of a width of 5π. 5π-pulse length control signal <b>9608</b> includes pulses wider than those of 3π-pulse length control signal <b>9606</b>. Because of this, as described above, 5π-pulse length control signal <b>9608</b> is made up of lower frequency signal components relative to 3π-pulse length control signal <b>9606</b>. Hence, relative to 3π-pulse length control signal <b>9606</b>, circuit re-radiation related to 5π-pulse length control signal <b>9608</b> is of lower frequency.

0677A pulse width can be widened even more as would be understood by persons skilled in the relevant arts from the teachings herein. To what degree the pulse width may be widened will be determined on an application by application basis. The pulse width may be varied by whole increments of π, or any fraction thereof. It should be understood that the above pulse width examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

0678<figref idref="DRAWINGS">FIG. 114</figref> depicts a flowchart <b>11400</b> that illustrates operational steps for down-converting an input signal with a variety of control signal pulse widths, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 114</figref> will be described.

0679In step <b>11402</b>, an input signal is frequency down-converted with a universal frequency down-conversion module to a down-converted signal. The input signal is down-converted according to a control signal comprising a train of pulses having pulse widths.

0680In step <b>11404</b>, a signal related to the control signal is re-radiated.

0681In step <b>11406</b>, the pulse widths are increased to decrease a frequency of the re-radiated signal. In an embodiment, the pulse widths may be selected according to the equation: pulse width=180+360·n degrees of a frequency of said input signal, wherein n is any integer ≧zero. As n is increased, a frequency of the re-radiated signal is decreased.

06827.2.2.1.1 I/Q Modulation Receiver Control Signal Considerations and Embodiments

0683Design considerations exist for I/Q modulation receiver circuits in regard to control signals. The embodiments provided above for changing control signal pulse widths are applicable to I/Q modulation receiver circuits. However, when modifying control signal pulse widths in regards to I/Q modulation receiver circuits to overcome problems with re-radiation as described above, or other problems, certain design constraints may need to be considered. For instance, in some embodiments, such as described below, pulses of the I-phase control signal and pulses of the Q-phase control signal may not overlap, and must be configured such that they do not overlap to fulfill this requirement. In alternate embodiments, such as described below, an I/Q modulation receiver circuit may be configured such that I-phase and Q-phase control signals may overlap. Exemplary embodiments are provided below for overcoming at least some design constraints related to control signal pulses for I/Q modulation receiver circuits, according to the present invention.

0684It should be understood that the following I/Q modulation receiver examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

06857.2.2.1.1.1 Non-Overlapping I/Q Control Signal Pulses Embodiments

0686<figref idref="DRAWINGS">FIG. 97</figref> illustrates an exemplary I/Q modulation receiver circuit <b>9700</b>, according to an embodiment of the present invention. I/Q modulation receiver circuit <b>9700</b> comprises a first UFD module <b>9702</b>, a second UFD module <b>9704</b>, a control signal generator <b>9706</b>, and a phase shifter <b>9708</b>. I/Q modulation circuit <b>9700</b> may use a variety of control signal configurations to down-convert I/Q modulated signals.

0687An input RF I/Q signal <b>9722</b> is received by first UFD module <b>9702</b>. First UFD module <b>9702</b> down-converts the I-phase signal portion of input RF I/Q signal <b>9722</b> according to a control signal <b>9728</b>, which is output by control signal generator <b>9706</b>. First UFD module <b>9702</b> outputs an I output signal <b>9724</b>.

0688In an embodiment, first UFD module <b>9702</b> comprises a first UFT module <b>9710</b>, a first storage module <b>9712</b>, and a first voltage reference <b>9714</b>.

0689Control signal <b>9728</b> is received by phase shifter <b>9708</b>. In an I/Q modulation embodiment, phase shifter <b>9708</b> preferably shifts the phase of control signal <b>9728</b> by 90 degrees, although other phase shifts are possible. Phase shifter <b>9708</b> outputs phase-shifted control signal <b>9730</b>.

0690Input RF I/Q signal <b>9722</b> is received by second UFD module <b>9704</b>. Second UFD module <b>9704</b> down-converts the Q-phase signal portion of input RF I/Q signal <b>9722</b> according to phase-shifted control signal <b>9730</b>. Second UFD module <b>9704</b> outputs a Q output signal <b>9726</b>.

0691In an embodiment, second UFD module <b>9704</b> comprises a second UFT module <b>9716</b>, a second storage module <b>9718</b>, and a second voltage reference <b>9720</b>. First and second voltage references <b>9714</b> and <b>9720</b> may or may not be equal to the same voltage value.

0692<figref idref="DRAWINGS">FIGS. 98A-98I</figref> shows an exemplary input RF I/Q signal <b>9722</b>, and several exemplary control signal waveforms, which may be used to down-convert input RF I/Q signal <b>9722</b>.

0693For example, an I-control signal <b>9802</b> is shown in <figref idref="DRAWINGS">FIG. 98B</figref>. I-control signal <b>9802</b> may be used to down-convert an I-phase signal portion of input RF I/Q signal <b>9722</b>. A corresponding Q-control signal <b>9804</b> is shown in <figref idref="DRAWINGS">FIG. 98C</figref>. Q-control signal <b>9804</b> is output by phase shifter <b>9708</b>. Q-control signal <b>9804</b> is shifted by 90 degrees from I-control signal <b>9802</b>. Q-control signal <b>9804</b> may be used to down-convert a Q-phase signal portion of input RF I/Q signal <b>9722</b>.

0694As illustrated in <figref idref="DRAWINGS">FIGS. 98B and 98C</figref>, pulses of I-control signal <b>9802</b> overlap the corresponding phase-shifted pulses of Q-control signal <b>9804</b>. In some embodiments where first and second UFT modules <b>9710</b> and <b>9716</b> comprises switches, overlapping pulses of I-control signal <b>9802</b> and Q-control signal <b>9804</b> will cause the switches in first and second UFT modules <b>9710</b> and <b>9716</b> to be simultaneously closed during a period pulse of overlap. Due to the overlap, first and second UFD modules <b>9702</b> and <b>9704</b> may not be able to properly down-convert the I- and Q-phase components of input RF I/Q signal <b>9722</b>. This is because during the period that switches inside the first and second UFD modules <b>9702</b> and <b>9704</b> are both closed, the switches will be attempting to transfer energy from input RF I/Q signal <b>9722</b> simultaneously. This may lead to non-negligible distortion of input RF I/Q signal <b>9722</b> in some embodiments. Hence, less than desirable input signal down-conversion accuracy may result.

0695In an another example, <figref idref="DRAWINGS">FIGS. 98D and 98E</figref> show a 3π I-control signal <b>9806</b> and a 3π Q-control signal <b>9808</b>. Pulses of 3π I-control signal <b>9806</b> and 3π Q-control signal <b>9808</b> overlap. Using these control signals, in some embodiments first and second UFD modules <b>9702</b> and <b>9704</b> may not be able to properly down-convert the I- and Q-phase components of input RF I/Q signal <b>9722</b>.

0696The overlap problem may be overcome by creating control signals with non-overlapping pulses. For example, <figref idref="DRAWINGS">FIGS. 98F and 98G</figref> show a non-overlapping I-control signal <b>9810</b> and a non-overlapping Q-control signal <b>9812</b>. Pulses on non-overlapping I-control signal <b>9810</b> are separated by 720 degrees, and may be used to down-convert the I-phase signal component of input RF I/Q signal <b>9722</b>. Pulses on non-overlapping Q-control signal <b>9812</b> are phased-shifted from pulses on non-overlapping I-control signal <b>9810</b> by 270 degrees, are separated from each other by 720 degrees, and may be used to down-convert the Q-phase signal component of input RF I/Q signal <b>9722</b>.

0697In a further example, <figref idref="DRAWINGS">FIGS. 98H and 98I</figref> show a non-overlapping I-control signal <b>9814</b> and a non-overlapping Q-control signal <b>9816</b>. Pulses on non-overlapping I-control signal <b>9814</b> are separated by 540 degrees, and may be used to down-convert the I-phase signal component of input RF I/Q signal <b>9722</b>. (Note that when pulses on non-overlapping I-control signal <b>9814</b> are separated by 180 degrees, 540 degrees, 900 degrees, etc., the information down-converted on consecutive pulses may be inverted relative to one another, and hence an inverter may be required to correct for this.) Pulses on non-overlapping Q-control signal <b>9816</b> are phased-shifted from pulses on non-overlapping I-control signal <b>9814</b> by 270 degrees, are separated from each other by 540 degrees, and may be used to down-convert the Q-phase signal component of input RF I/Q signal <b>9722</b>. (Note that when pulses on non-overlapping Q-control signal <b>9816</b> are separated by 180 degrees, 540 degrees, 900 degrees, etc., the information down-converted on consecutive pulses may be inverted relative to one another, and hence an inverter may be required to correct for this.)

0698Further control signal waveform configurations exist for implementing non-overlapping pulses, according to embodiments of the present invention, as would be recognized by persons skilled in the relevant art(s) from the teachings herein. I- and Q-control signal pulses may be widened, or made more narrow. I- and Q-control signal pulses may be made to occur further apart or closer together. A Q-control signal may be phase-shifted from a corresponding I-control signal by 90 degrees, 270 degrees, 450 degrees, 630 degrees, and so on, such that the I-control signal is matched with the I-phase input RF signal component, and the Q-control signal is matched with the Q-phase input RF signal component. Pulses on an I-phase control signal may be shifted from each other by any multiple of 180 (with one or more inverters possibly required, as described above) or 360 degrees. I- and Q-control signals may be formed to these requirements for use in I/Q modulation receiver circuit <b>9700</b> of <figref idref="DRAWINGS">FIG. 97</figref>, as long as their pulses do not overlap.

0699<figref idref="DRAWINGS">FIG. 115</figref> depicts a flowchart <b>11500</b> that illustrates operational steps corresponding to the structure of <figref idref="DRAWINGS">FIG. 97</figref>, for down-converting an RF I/Q modulated input signal, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 115</figref> will be described.

0700In step <b>11502</b>, an input RF I/Q modulated signal is frequency down-converted with a first universal frequency down-conversion module according to a control signal. The input signal is down-converted to an in-phase information signal. The control signal comprises a train of pulses. In an embodiment, the train of pulses are generated to have apertures approximately equal to 180+360·n degrees of a frequency of said input RF I/Q modulated signal, wherein n is any integer greater than or equal to 0.

0701In step <b>11504</b>, the control signal is phase-shifted. In embodiments, the control signal is phase-shifted by 90 degrees of a frequency of said input RF I/Q modulated signal. In alternative embodiments, the control signal may be shifted by 90+m·180 degrees, wherein m is any integer greater than or equal to 1. In embodiments, the control signal may be phase shifted such that pulses on the control signal do not overlap pulses on the phase-shifted control signal.

0702In step <b>11506</b>, the input RF I/Q modulated signal is frequency down-converted with a second universal frequency down-conversion module according to the phase-shifted control signal. The input signal is down-converted to a quadrature-phase information signal.

07037.2.2.1.1.2 Buffered I/Q Modulation Receiver Embodiment

0704Exemplary embodiments are provide below for I/Q modulation receiver circuits where control signal pulses may overlap. Such embodiments may provide advantages where it is desirable to modify control signal pulse attributes as described above to solve problems with circuit re-radiation, and other problems. Additional and alternate embodiments will be recognized by persons skilled in the relevant art(s) from the teachings herein, and are within the scope of the present invention.

0705<figref idref="DRAWINGS">FIG. 99</figref> illustrates an exemplary buffered I/Q modulation receiver circuit <b>9900</b>, according to an embodiment of the present invention. Buffered I/Q modulation receiver circuit <b>9900</b> allows for overlapping I- and Q-control signal pulses such as I-control signal <b>9802</b> and Q-control signal <b>9804</b> of <figref idref="DRAWINGS">FIG. 98</figref>.

0706Buffered I/Q modulation receiver circuit <b>9900</b> comprises an optional splitter <b>9902</b>, a first low noise amplifier (LNA) <b>9904</b>, a second LNA <b>9908</b>, a control signal generator <b>9910</b>, a first UFD module <b>9912</b>, a second UFD module <b>9914</b>, and a phase shifter <b>9916</b>. Buffered I/Q modulation receiver circuit <b>9900</b> is configured substantially similar to, and operates in a similar fashion to I/Q modulation receiver circuit <b>9700</b> of <figref idref="DRAWINGS">FIG. 97</figref>, with the addition of optional splitter <b>9902</b>, first LNA <b>9904</b>, and second LNA <b>9908</b>.

0707Optional splitter <b>9902</b> optionally splits an input RF I/Q signal <b>9930</b>, and outputs a first split input RF I/Q signal <b>9944</b> to first LNA <b>9904</b>, and a second split input RF I/Q signal <b>9946</b> to second LNA <b>9908</b>.

0708First LNA <b>9904</b> buffers and optionally amplifies first split input RF I/Q signal <b>9944</b>, and outputs a first buffered input RF I/Q signal <b>9936</b>.

0709Second LNA <b>9908</b> buffers and optionally amplifies second split input RF I/Q signal <b>9946</b>, and outputs a second buffered input RF I/Q signal <b>9938</b>.

0710First UFD module <b>9912</b> receives first buffered input RF I/Q signal <b>9936</b>. First UFD module <b>9912</b> down-converts first buffered input RF I/Q signal <b>9936</b> according to a control signal <b>9940</b>, which is output by control signal generator <b>9910</b>. First UFD module <b>9912</b> outputs I output signal <b>9932</b>. In an embodiment, first UFD module <b>9912</b> comprises a first UFT module <b>9918</b>, a first storage module <b>9920</b>, and a first voltage reference <b>9922</b>.

0711Phase shifter <b>9916</b> receives control signal <b>9940</b>, and outputs a phase-shifted control signal <b>9942</b>. Phase-shifted control signal <b>9942</b> is preferably shifted by 90 degrees from control signal <b>9940</b>, but may also be shifted by 270 degrees, 450 degrees, 630 degrees, and so on.

0712Second UFD module <b>9914</b> receives second buffered input RF I/Q signal <b>9938</b>. Second UFD module <b>9914</b> down-converts second buffered input RF I/Q signal <b>9938</b> according to phase-shifted control signal <b>9942</b>. Second UFD module <b>9914</b> outputs Q output signal <b>9934</b>. In an embodiment, second UFD module <b>9914</b> comprises a second UFT module <b>9924</b>, a second storage module <b>9926</b>, and a second voltage reference <b>9928</b>.

0713As described elsewhere herein, when first UFT module <b>9918</b> transfers energy from first buffered input RF I/Q signal <b>9936</b>, first buffered input RF I/Q signal <b>9936</b> will be distorted to some degree. Likewise, when second UFT module <b>9924</b> transfers energy from second buffered input RF I/Q signal <b>9938</b>, second buffered input RF I/Q signal <b>9938</b> will be distorted to some degree. First and second LNA <b>9904</b> and <b>9908</b> buffer the input RF I/Q signals entering first and second UFD modules <b>9912</b> and <b>9914</b> from input RF I/Q signal <b>9930</b>. Hence, input RF I/Q signal <b>9930</b> will not be substantially distorted by energy transfer occurring in either of first and second UFD module <b>9912</b> and <b>9914</b>. Because of this, the I- and Q-control signals used to cause first and second UFD modules <b>9912</b> and <b>9914</b> to down-convert their respective input RF I/Q signals may have overlapping I- and Q-pulses. Hence, for example, control signal <b>9940</b> may appear as I-control signal <b>9802</b> of <figref idref="DRAWINGS">FIG. 98</figref>, and phase-shifted control signal <b>9942</b> may appear as Q-control signal <b>9804</b>, phase-shifted by 90 degrees from, and having pulses overlapping with, control signal <b>9940</b>. It is noted that the invention is not limited to the example of <figref idref="DRAWINGS">FIG. 99</figref>. Other components to buffer or isolate first and second UFT modules <b>9918</b>, <b>9924</b> from each other could alternatively be used.

0714<figref idref="DRAWINGS">FIG. 116</figref> depicts a flowchart <b>11600</b> that illustrates operational steps corresponding to the structure of <figref idref="DRAWINGS">FIG. 99</figref>, for down-converting an RF I/Q modulated input signal, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 116</figref> will be described.

0715In step <b>11602</b>, an input RF I/Q modulated signal is buffered with a first low noise amplifier and a second low noise amplifier. In an alternative embodiment, instead of or in addition to buffering the input RF I/Q modulated signal as just described, the input RF I/Q modulated signal may be split into a first split RF I/Q modulated signal and a second split RF I/Q modulated signal.

0716In step <b>11604</b>, the first buffered (and/or first split) RF I/Q modulated signal is frequency down-converted with a first universal frequency down-conversion module according to a control signal. The input signal is down-converted to an in-phase information signal. The control signal comprises a train of pulses. In an embodiment, the train of pulses are generated to have apertures approximately equal to 180+360·n degrees of a frequency of said input RF I/Q modulated signal, wherein n is any integer greater than or equal to 0.

0717In step <b>11606</b>, the control signal is phase-shifted. In embodiments, the control signal is phase-shifted by 90+m·180 degrees of a frequency of said input RF I/Q modulated signal, wherein m is any integer greater than or equal to 0. In embodiments, the control signal may be phase shifted such that pulses on the control signal overlap pulses on the phase-shifted control signal.

0718In step <b>11608</b>, the second buffered (and/or second split) RF I/Q modulated signal is frequency down-converted with a second universal frequency down-conversion module according to the phase-shifted control signal. The input signal is down-converted to a quadrature-phase information signal.

07197.2.2.2 Reducing Re-Radiation with Placebo Down-Conversion Modules

0720<figref idref="DRAWINGS">FIG. 100</figref> illustrates an exemplary receiver <b>10000</b> with placebo circuit <b>10004</b>, according to an embodiment of the present invention. Receiver <b>10000</b> with placebo circuit <b>10004</b> reduces or frequency shifts potentially re-radiated control signal components such that their potentially adverse impact on a down-converted signal is reduced. The potentially re-radiated control signal components may be shifted out of the frequency bands of interest, such that they will have a reduced adverse impact on the down-converted signal.

0721Control signal frequency components may be adjusted or shifted through the use of one or more UFT modules, called “placebo” UFT modules, and one or more corresponding “placebo” control signals. In a placebo embodiment, an “actual” UFT module receives and down-converts a received RF input signal with an “actual” control signal as described elsewhere herein. Furthermore, a placebo UFT module receives a placebo control signal, and may also down-convert the received RF input signal, to output a down-converted signal. The actual control signal and one or more placebo control signals may cause circuit re-radiation. This resulting circuit re-radiation will be related to a combination of the actual control signal waveform and the one or more placebo control signal waveforms. Hence, attributes of the resulting circuit re-radiation may be manipulated by using various placebo control signal waveforms, to cause overall circuit re-radiation to be less harmful to circuit performance. Characteristics of a particular placebo control signal waveform may be determined on an application-by-application basis. The term “placebo” is used because the signal down-converted by the placebo circuitry is not necessarily used by subsequent signal processing hardware and software, but may actually remain unutilized. The signal down-converted by the “actual” circuitry is used by subsequent signal processing.

0722Receiver <b>10000</b> with placebo circuit <b>10004</b> comprises an actual UFD module <b>10002</b>, a placebo UFD module <b>10004</b>, a control signal generator <b>10006</b>, and a phase shifter <b>10008</b>.

0723Actual UFD module <b>10002</b> receives an input RF signal <b>10022</b>. Actual UFD module <b>10002</b> down-converts actual input RF signal <b>10022</b> according to a control signal <b>10028</b>, which is output by control signal generator <b>10006</b>, in a manner as described elsewhere herein. Actual UFD module <b>10002</b> outputs an actual output signal <b>10024</b>. In an embodiment, actual UFD module <b>10002</b> comprises an actual UFT module <b>10010</b>, an actual storage module <b>10012</b>, and an actual voltage reference <b>10014</b>.

0724Phase shifter <b>10008</b> receives control signal <b>10028</b>, and outputs a phase-shifted placebo control signal <b>10030</b>. Phase-shifted placebo control signal <b>10030</b> is preferably shifted such that pulses on phase-shifted placebo control signal <b>10030</b> do not overlap with pulses on control signal <b>10028</b>. In other embodiments, pulses on phase-shifted placebo control signal <b>10030</b> may overlap pulses on control signal <b>10028</b>, as would be understood by persons skilled in the relevant art(s) from the teachings herein.

0725Placebo UFD module <b>10004</b> receives input RF signal <b>10022</b>. Placebo UFD module <b>10004</b> down-converts input RF signal <b>10022</b> according to phase-shifted placebo control signal <b>10030</b>. Placebo UFD module <b>10004</b> outputs placebo output signal <b>10026</b>. In an embodiment, placebo UFD module <b>10004</b> comprises a placebo UFT module <b>10016</b>, a placebo storage module <b>10018</b>, and a placebo voltage reference <b>10020</b>.

0726<figref idref="DRAWINGS">FIG. 101</figref> shows an exemplary control signal waveform <b>10102</b>, and a corresponding exemplary placebo control signal waveform <b>10104</b> that is a delayed (or phase-shifted) version of control signal waveform <b>10102</b>. Control signal <b>10028</b> may comprise a control signal waveform such as control signal waveform <b>10102</b>. Phase-shifted placebo control signal <b>10030</b> may comprise a corresponding control signal waveform such as placebo control signal waveform <b>10104</b>.

0727In a receiver circuit embodiment that does not include a placebo UFD module <b>10004</b>, potential circuit re-radiation (and the frequency spectrum of such re-radiation) will be related to the control signal waveform being used, such as control signal waveform <b>10102</b>. In a receiver circuit embodiment that includes a placebo UFD module <b>10004</b>, the potential circuit re-radiation (and the frequency spectrum of such re-radiation) will be related to the control signal being used, such as control signal waveform <b>10102</b>, and the placebo control signal waveform being used, such as placebo control signal waveform <b>10104</b>.

0728<figref idref="DRAWINGS">FIG. 101</figref> shows a combined signal waveform <b>10106</b> that represents a combination of control signal waveform <b>10102</b> and placebo control signal waveform <b>10104</b>. The potential circuit re-radiation (and the frequency spectrum thereof) due to control signal waveform <b>10102</b> and placebo control signal waveform <b>10104</b> will be related to combined signal waveform <b>10106</b> (and the frequency spectrum thereof). As would be apparent to persons skilled in the relevant art(s), combined signal waveform <b>10106</b> has a different frequency spectrum than control signal waveform <b>10102</b>. By utilizing at least one placebo control signal in addition to an actual control signal, a potentially re-radiated frequency spectrum can be adjusted to move potentially harmful circuit noise and potentially resulting DC offset and/or re-radiated components to a non-critical frequency band in output signal <b>10024</b>.

0729Furthermore, as shown in <figref idref="DRAWINGS">FIG. 101</figref>, placebo control signal waveform <b>10104</b> may be phase-shifted by lesser or greater amounts from control signal waveform <b>10102</b>. Arrows <b>10108</b>, <b>10110</b>, <b>10112</b>, and <b>10114</b> indicate possible variations in the phase of placebo control signal waveform <b>10104</b>, with the corresponding variations in combined signal waveform <b>10106</b> indicated by arrows <b>10116</b>, <b>10118</b>, <b>10120</b>, and <b>10122</b>. By changing the phase of placebo control signal waveform <b>10104</b> in relation to control signal waveform <b>10102</b>, the frequency spectrum of potential re-radiation may be adjusted. Furthermore, changes in the amplitude and/or width of pulses on placebo control signal waveform <b>10104</b> may also be used to adjust the frequency spectrum and amplitude of potential re-radiation.

0730In embodiments, placebo output signal <b>10026</b> is not used in down-stream information signal processing. In alternative embodiments, placebo output signal <b>10026</b> may be used in down-stream information signal processing.

0731<figref idref="DRAWINGS">FIG. 117</figref> depicts a flowchart <b>11700</b> that illustrates operational steps corresponding to the structure of <figref idref="DRAWINGS">FIG. 100</figref> and waveforms of <figref idref="DRAWINGS">FIG. 101</figref>, for down-converting an input signal and altering circuit re-radiation, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 117</figref> will be described.

0732In step <b>11702</b>, an input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, wherein the input signal is down-converted according to a control signal, wherein the control signal comprises a train of pulses, wherein pulses of the control signal occur every 360+360·n degrees of a frequency of the input signal, wherein n is equal to any integer greater or equal 0.

0733In step <b>11704</b>, the control signal is phase-shifted, wherein the control signal is phase shifted in a range between 0 degrees and 360+360·n degrees of a frequency of the input signal (pulses of control signal and phase-shifted control signal may overlap). In alternative embodiments, the pulses are of width m degrees, and the control signal is phase-shifted in a range between m degrees and 360−m+360·n degrees of a frequency of the input signal (no overlap of pulses between control signal and phase-shifted control signal). In embodiments, the control signal is phase shifted to a phase-shifted control signal in order to adjust at least one frequency of the re-radiated signal. In further embodiments, the control signal is phase shifted to a phase-shifted control signal in order to adjust at least one frequency of the re-radiated signal to be above a frequency range of interest of the input signal.

0734In step <b>11706</b>, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, wherein the input signal is down-converted according to the phase-shifted control signal. The second universal frequency down-conversion module is used as a placebo universal frequency down-conversion module.

0735In step <b>11708</b>, a signal is re-radiated that is at least a function of the control signal and the phase-shifted control signal.

0736Exemplary receiver with placebo circuit embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, further placebo UFD modules with additional placebo control signals may be added. The invention is intended and adapted to include such alternate embodiments.

07377.2.2.3 Reducing Re-Radiation with Adjacent Apertures

0738Potential control signal circuit re-radiation may be reduced or eliminated by the use of adjacent control signal pulses or apertures. By creating control signal pulses that are adjacent, the rising and falling edges of adjacent pulses may partially or entirely cancel out any re-radiation due to the individual pulses.

0739<figref idref="DRAWINGS">FIG. 102</figref> illustrates an adjacent apertures receiver circuit <b>10200</b>, according to an embodiment of the present invention. Adjacent apertures receiver circuit <b>10200</b> comprises a first UFD module <b>10202</b>, a second UFD module <b>10204</b>, a control signal generator <b>10206</b>, and a phase shifter <b>10208</b>.

0740An input RF signal <b>10214</b> is received by first UFD module <b>10202</b>. First UFD module <b>10202</b> down-converts input RF signal <b>10214</b> according to a control signal <b>10220</b>, which is output by control signal generator <b>10206</b>, in a manner as described elsewhere herein. First UFD module <b>10202</b> outputs first output signal <b>10216</b>. First UFD module <b>10202</b> comprises a first UFT module <b>10210</b>.

0741Phase shifter <b>10208</b> receives control signal <b>10220</b>, and outputs a phase-shifted control signal <b>10222</b>. In an embodiment, the width of pulses on control signal <b>10220</b> and on phase-shifted control signal <b>10222</b> approach π radians, although other values could be used. Phase-shifted control signal <b>10222</b> is preferably shifted by π radians from control signal <b>10220</b>, although other values could be used.

0742Input RF signal <b>10214</b> is received by second UFD module <b>10204</b>. Second UFD module <b>10204</b> down-converts input RF signal <b>10214</b> according to phase-shifted control signal <b>10222</b>, in a manner as described elsewhere herein. Second UFD module <b>10204</b> outputs second output signal <b>10218</b>. Second UFD module <b>10204</b> comprises a second UFT module <b>10212</b>.

0743<figref idref="DRAWINGS">FIG. 103</figref> shows an exemplary control signal waveform <b>10302</b>, and a corresponding π-shifted control signal waveform <b>10304</b>. The potentially re-radiated signals (and their associated frequency spectrums) due to control signal <b>10220</b> and phase-shifted control signal <b>10222</b> will be related to their waveforms and frequency spectrums, which may be represented by control signal waveform <b>10302</b> and π-shifted control signal waveform <b>10304</b>, respectively, for example.

0744Because the width of pulses on control signal waveform <b>10302</b> and π-shifted control signal waveform <b>10304</b> are equal to or less than π radians, their combined potentially re-radiated signal will be related to combined signal waveform <b>10306</b>. As control signal waveform <b>10302</b> and π-shifted control signal waveform <b>10306</b> approach having pulse widths equal to π radians, combined signal waveform <b>10306</b> will approach the equivalent of a DC level, with a voltage level substantially equivalent to the pulse amplitudes. In other words, combined signal waveform <b>10306</b> will approach a DC level because as pulses of waveforms <b>10302</b> and <b>10304</b> approach a width of π, the rising and falling edges of the waveforms <b>10302</b> and <b>10304</b> will increasingly cancel each other.

0745The use of adjacent apertures may lead to reduced levels of circuit re-radiation, and improved circuit performance. Re-radiated signal components will be due to combined signal waveform <b>10306</b>. Specifically, re-radiated signal components will be due to transitions from low to high and high to low in waveform <b>10306</b>, shown as spikes <b>10308</b>, but the frequency content of such re-radiated signal components due to spikes <b>10308</b> will primarily be above the frequency bands of interest.

0746<figref idref="DRAWINGS">FIG. 118A</figref> depicts a flowchart <b>11800</b> that illustrates operational steps corresponding to the structure of <figref idref="DRAWINGS">FIG. 102</figref> and waveforms of <figref idref="DRAWINGS">FIG. 103</figref>, for down-converting an input signal and altering circuit re-radiation, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 118A</figref> will be described.

0747In step <b>11802</b>, an input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, wherein the input signal is down-converted according to a control signal, wherein the control signal comprises a train of pulses, wherein the pulses have widths less than or equal to 180+360·n degrees of a frequency of the input signal, wherein n is any integer greater than or equal to 0.

0748In step <b>11804</b>, the control signal is phase shifted, wherein the control signal is phase-shifted by 180+360·n degrees of a frequency of the input signal. In an embodiment, the pulses of the control signal are substantially adjacent to pulses of the phase-shifted control signal.

0749In step <b>11806</b>, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, wherein the input signal is down-converted according to the phase-shifted control signal.

0750In step <b>11808</b>, a signal is re-radiated that is at least a function of the control signal and the phase-shifted control signal. In an embodiment, a spike is formed in the re-radiated signal at a transition of the adjacent pulses of the control signal and the phase-shifted control signal. In an embodiment, a voltage amplitude of the spike approaches zero as the pulses of the control signal and the pulses of the phase-shifted control signal approach 180+360·n degrees in width (i.e., the pulses become more adjacent). In an embodiment, at least one frequency of the spike is above a frequency range of interest of the input signal. In embodiments, as the pulse widths approach 180+360·n degrees of a frequency of the input signal, the re-radiated signal approaches a DC level.

0751In alternate embodiments, other adjacent control signal pulse configurations may be used. <figref idref="DRAWINGS">FIG. 104</figref> illustrates an exemplary adjacent apertures receiver circuit <b>10400</b>, according to an embodiment of the present invention. Circuit <b>10400</b> operates substantially similarly to circuit <b>10200</b>, but produces four control signals instead of two. Control signal generator <b>10410</b> outputs control signal <b>10432</b>, with pulse widths of π, which occur once every 4π radians. Circuit <b>10400</b> comprises a first phase shifter <b>10412</b>, a second phase shifter <b>10440</b>, and a third phase shifter <b>10442</b>, each of which further shifts the phase of control signal <b>10432</b> by π radians. In this manner, four adjacent control signal generator pulses, each of pulse width π radians, are generated that approach the equivalent of a DC level. Other control signal aperture durations and/or sequences will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

0752Additional control signals may be used to produce even longer strings of adjacent pulses.

0753Furthermore, the use of adjacent apertures may reduce the need for input impedance matching and tank circuitry. This is because with adjacent apertures, the UFT modules in combination are closed for longer fractions of a control signal cycle and hence, the input signal is being stored more continuously (by a storage module, for example). Because the input signal is being stored more continuously, there is less opportunity or need to store the input signal in one or more input tank circuits during the periods when the UFT modules are open. In other words, more of the energy of the input waveform is being stored and used with adjacent apertures. Furthermore, having the UFT module(s) closed for longer periods of time affects the circuit input impedance, and may alter or decrease the need for input impedance matching.

0754<figref idref="DRAWINGS">FIG. 118B</figref> depicts a continuation of flowchart <b>11800</b> that illustrates additional operational steps to those shown in <figref idref="DRAWINGS">FIG. 118A</figref> corresponding to further adjacent aperture generators, such as shown in <figref idref="DRAWINGS">FIG. 104</figref>, for down-converting an input signal and altering circuit re-radiation, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 118B</figref> will be described.

0755In step <b>11810</b>, a phase-shifted control signal is phase shifted to a further phase-shifted control signal. The phase-control signal is phase shifted by the same amount as the prior phase shifter. This causes the current aperture or pulse to be the same width as, and adjacent to, the prior aperture.

0756In step <b>11812</b>, the input signal is frequency down-converted with a further universal frequency down-conversion module to a corresponding down-converted signal, wherein the input signal is down-converted according to the further phase-shifted control signal.

0757In step <b>11814</b>, a signal is re-radiated that is a function of at least the control signal and the phase-shifted control signals.

0758In step <b>11816</b>, operation proceeds to step <b>11810</b> if the number of universal frequency down-conversion modules (adjacent apertures) is less than some desired number x. This process forms a chain of adjacent apertures, of a number of pulses x.

0759Exemplary receivers using adjacent apertures embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, control signals with pulses of widths other than π radians where the control signals have different pulse widths, may be used. The invention is intended and adapted to include such alternate embodiments.

07607.2.3 Additional DC Offset and Re-Radiation Reduction Embodiments

0761Exemplary embodiments for DC Offset and/or re-radiation reduction or cancellation are described above. Such embodiments may be used alone or in combination, based on the application and on implementation issues. It should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, many of the components described herein are optional, whether or not explicitly indicated as such. The invention is intended and adapted to include such alternate embodiments.

07627.3 Example Embodiments to Improve Dynamic Range

0763Receivers, amplifiers, and other electronic circuits, may suffer from problems related to dynamic range. Generally, “dynamic range” refers to the ratio of the maximum to minimum signal input capability over which an amplifier or other component can operate within some specified range of performance. For instance, if an input signal to an amplifier causes the amplifier to exceed its dynamic range, i.e., the input signal amplitude is too large, the amplifier may no longer amplify properly, the amplifier may rail, and/or may operate in a non-linear region. In a receiver, the signal being amplified may be a down-converted signal. If the dynamic range of the amplifier, or other component, is exceeded, the value of the down-converted signal may be adversely affected.

0764The concept of dynamic range is further described in the following sub-sections. Furthermore, example methods and systems are provided in subsequent sections below for improving dynamic range.

07657.3.1 Adjusting Universal Frequency Down-Conversion Module Dynamic Range

0766Some circuit implementations may suffer from a lack of dynamic range. For instance, when input RF signals become too high or too low, they may cause a switch in a UFT module to remain continuously open or closed, regardless of the level of the control signal. This may result in problems with output signal linearity and output signal clipping, which may lead to errors in decoding the baseband output signal.

0767<figref idref="DRAWINGS">FIG. 105</figref> illustrates an exemplary circuit for improving dynamic range, according to an embodiment of the present invention. Improved dynamic range circuit <b>10500</b> of <figref idref="DRAWINGS">FIG. 105</figref> comprises a impedance match <b>10502</b>, a tank circuit <b>10504</b>, a UFD module <b>10506</b>, and a bias circuit <b>10508</b>. Bias circuit <b>10508</b> is used to adjust the center point of the input voltage range for UFD module <b>10506</b>, providing for greater input signal range.

0768In an embodiment, impedance match <b>10502</b> comprises an inductor <b>10510</b>. The operation of the present and of additional embodiments for impedance match <b>10502</b> are further described elsewhere herein.

0769In an embodiment, tank circuit <b>10504</b> comprises a capacitor <b>10512</b> and an inductor <b>10514</b>. The operation of the present and of additional embodiments for tank circuit <b>10504</b> are further described elsewhere herein.

0770UFD module <b>10506</b> comprises a UFT module <b>10516</b>, a storage module <b>10520</b>, and a first voltage reference <b>10524</b>. The operation of the present and of additional embodiments for UFD module <b>10506</b> are further described elsewhere herein. UFT module <b>10516</b> comprises a MOSFET switch <b>10518</b> in the example embodiment of <figref idref="DRAWINGS">FIG. 105</figref>. Storage module <b>10520</b> comprises a capacitor <b>10522</b> in the example embodiment of <figref idref="DRAWINGS">FIG. 105</figref>. The structure and operation of the present and of additional embodiments for UFT module <b>10516</b> and storage module <b>10520</b> are further described elsewhere herein.

0771An input RF signal <b>10540</b> is input through impedance match <b>10502</b> to be received by a first terminal <b>10550</b> of UFD module <b>10506</b>. First terminal <b>10550</b> of UFD module <b>10506</b> is coupled to a first terminal <b>10552</b> of tank circuit <b>10504</b>. MOSFET switch <b>10518</b> in UFD module <b>10506</b> down-converts input RF signal <b>10540</b> according to a control signal <b>10548</b>, which is output by control signal generator <b>10526</b>. The output of MOSFET switch <b>10518</b> is stored in storage module <b>10520</b>. MOSFET switch <b>10518</b> outputs an output signal <b>10542</b>. In the example embodiment of <figref idref="DRAWINGS">FIG. 105</figref>, MOSFET switch <b>10518</b> comprises a first terminal <b>10564</b> coupled to first terminal <b>10552</b> of tank circuit <b>10504</b>, a second terminal <b>10566</b> coupled to output signal <b>10542</b>, and a third terminal <b>10568</b> (gate) coupled to control signal <b>10548</b>.

0772Control signal generator <b>10526</b> generates control signal <b>10548</b>, as described elsewhere herein. Control signal <b>10548</b> preferably comprises a periodic signal, which preferably comprises a string of pulses. These pulses vary between a minimum and maximum voltage. For example, control signal <b>10548</b> may output pulses that vary between 0 volts and 2 volts, as shown in <figref idref="DRAWINGS">FIG. 106A</figref>.

0773Input RF signal <b>10540</b> also comprises a range of signal values. For instance, input RF signal <b>10540</b> may vary between +0.75 volts and −0.75 volts, as shown in FIG. <b>106</b>B. In the current example, when the value of input RF signal <b>10540</b> is equal to −0.75 volts, this value is less than the minimum voltage of control signal <b>10548</b> (0 volts) applied to MOSFET switch <b>10518</b>, and hence MOSFET switch <b>10518</b> will be in the closed state for all values of control signal <b>10548</b> because the voltage from terminal <b>10568</b> (gate) to terminal <b>10564</b> of MOSFET switch <b>10518</b> is always positive, causing MOSFET switch <b>10518</b> to always conduct.

0774Likewise, it will be recognized by persons skilled in the relevant art(s) that input RF signal <b>10540</b> may comprise signal amplitudes greater than the maximum voltage of control signal <b>10548</b> (not illustrated in <figref idref="DRAWINGS">FIGS. 106A and 106B</figref>) applied to MOSFET switch <b>10518</b>. When input RF signal <b>10540</b> is equal to such a value, MOSFET switch <b>10518</b> will remain in the open state, for all values of control signal <b>10548</b>, because the voltage from terminal <b>10568</b> (gate) to terminal <b>10564</b> of MOSFET switch <b>10518</b> would always be negative, preventing MOSFET switch <b>10518</b> from ever conducting. Both conditions where control signal <b>10548</b> cannot effect switching of MOSFET switch <b>10518</b> are undesirable.

0775One solution is to modify the voltage swing of control signal <b>10548</b> such that it varies from +0.75 to −0.75 volts or greater, as does input RF signal <b>10540</b>. This solution may not be possible in all situations, however. For instance, this solution may not be possible when only a single voltage supply is available.

0776A further solution for this problem is to bias input RF signal <b>10540</b> such that it varies within the maximum and minimum voltage range of pulses of control signal <b>10548</b>. Thus, as long as input RF signal <b>10540</b> varies within the voltage range of control signal <b>10548</b>, control signal <b>10548</b> will control the turning on and turning off of MOSFET switch <b>10518</b>. <figref idref="DRAWINGS">FIG. 106C</figref> shows an example biased input RF signal <b>10544</b>, that is biased to vary between +1.75 and +0.25 volts, within the range of control signal <b>10548</b>.

0777Bias circuit <b>10508</b> is used to adjust the bias applied to input RF signal <b>10540</b>. (It is noted that other bias configurations could alternatively be used.) Bias circuit <b>10508</b> comprises a second voltage reference <b>10528</b>, a first resistor <b>10530</b>, an optional capacitor <b>10532</b>, a third voltage reference <b>10534</b>, a second resistor <b>10536</b>, and a fourth voltage reference <b>10538</b>.

0778A first terminal <b>10554</b> of first resistor <b>10530</b> is coupled to a first voltage reference <b>10528</b>. A second terminal <b>10556</b> of first resistor <b>10530</b> is coupled to a first terminal <b>10558</b> of second resistor <b>10536</b> to create a bias point <b>10546</b>. Bias point <b>10546</b> is coupled to a second terminal <b>10560</b> of tank circuit <b>10504</b>. A second terminal <b>10562</b> of second resistor <b>10536</b> is coupled to fourth voltage reference <b>10538</b>.

0779First resistor <b>10530</b> and second resistor <b>10536</b> form a voltage divider circuit, to create bias point <b>10546</b>, as would be understood by persons skilled in the relevant art(s) from the teachings herein. Bias point <b>10546</b> provides a biasing voltage for input RF signal <b>10540</b>. A biased input RF signal <b>10544</b> is equal to input RF signal <b>10540</b> adjusted (e.g., added or subtracted) by the amount of voltage at bias point <b>10546</b>. In a preferred embodiment, biased input RF signal <b>10544</b> may be biased at the midpoint of the voltage swing of control signal <b>10548</b>. For example, biased input RF signal <b>10544</b> may be biased by bias point <b>10546</b> with a level of one volt, for a 0 volt to 2 volt varying control signal <b>10548</b>.

0780Optional capacitor <b>10532</b> coupled between bias point <b>10546</b> and third voltage reference <b>10534</b> may be optionally inserted to aid in stabilizing bias point <b>10546</b>.

0781Other embodiments for bias circuit <b>10508</b> will be apparent to persons skilled in the relevant art(s) from the teachings herein. For instance, <figref idref="DRAWINGS">FIG. 107</figref> illustrates an exemplary bias circuit <b>10708</b> according to an embodiment of the present invention, wherein a tank circuit <b>10504</b> and/or an impedance match circuit <b>10502</b> as shown in <figref idref="DRAWINGS">FIG. 105</figref> are not present. Bias circuit <b>10708</b> in <figref idref="DRAWINGS">FIG. 107</figref> adjusts a bias point for an input to UFD module <b>10506</b>. Bias circuit <b>10708</b> of <figref idref="DRAWINGS">FIG. 107</figref> places a bias directly on input RF signal <b>10540</b>, as opposed to bias circuit <b>10508</b> of <figref idref="DRAWINGS">FIG. 105</figref> which applies a bias voltage through tank circuit <b>10504</b>.

0782<figref idref="DRAWINGS">FIG. 119</figref> depicts a flowchart <b>11900</b> that illustrates operational steps corresponding to <figref idref="DRAWINGS">FIGS. 105-107</figref>, for improving dynamic range, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 119</figref> will be described.

0783In step <b>11902</b>, a bias voltage is applied to an input signal. In embodiments, the center voltage of the input signal is adjusted by application of the bias voltage. In embodiments, the input signal is coupled to a center terminal of a resistor divider circuit, which supplies the bias voltage. In an embodiment, a tank circuit is used to couple the input signal to the center terminal of the resistor divider circuit.

0784In step <b>11904</b>, the biased input signal is frequency down-converted with a first universal frequency down-conversion module to a down-converted signal.

0785Other embodiments for improving dynamic range include the use of complementary FETs. Complementary FET embodiments are further described in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals Having Optimized Switch Structures,” Ser. No. 09/293,095. Complementary FETs also have the advantage of using control signals of opposite polarity, which tends to reduce or cancel re-radiation due to a control signal.

0786Other circuit embodiments for improving dynamic range include modifying control signal pulse amplitude, and/or modifying the switch, or FET, size, as would be understood by persons skilled in the relevant art(s) from the teachings herein. It should be understood that the above bias circuit examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

07877.4 Example Receiver and Transmitter Embodiments for Addressing DC Offset and Re-Radiation

0788In this section, embodiments, according to the present invention, are provided for reducing or eliminating DC offset and/or reducing or eliminating circuit re-radiation in receivers, including I/Q modulation receivers and other modulation scheme receivers. These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

07897.4.1 Example I/Q Modulation Receiver Embodiments

0790<figref idref="DRAWINGS">FIG. 25</figref> illustrates an exemplary I/Q modulation receiver <b>2500</b>, according to an embodiment of the present invention. I/Q modulation receiver <b>2500</b> has additional advantages of reducing or eliminating unwanted DC offsets and circuit re-radiation.

0791I/Q modulation receiver <b>2500</b> comprises a first UFD module <b>2502</b>, a first optional filter <b>2504</b>, a second UFD module <b>2506</b>, a second optional filter <b>2508</b>, a third UFD module <b>2510</b>, a third optional filter <b>2512</b>, a fourth UFD module <b>2514</b>, a fourth filter <b>2516</b>, an optional LNA <b>2518</b>, a first differential amplifier <b>2520</b>, a second differential amplifier <b>2522</b>, and an antenna <b>2572</b>.

0792I/Q modulation receiver <b>2500</b> receives, down-converts, and demodulates a I/Q modulated RF input signal <b>2582</b> to an I baseband output signal <b>2584</b>, and a I/Q baseband output signal <b>2586</b>. I/Q modulated RF input signal comprises a first information signal and a second information signal that are I/Q modulated onto an RF carrier signal. I baseband output signal <b>2584</b> comprises the first baseband information signal. Q baseband output signal <b>2586</b> comprises the second baseband information signal.

0793Antenna <b>2572</b> receives I/Q modulated RF input signal <b>2582</b>. I/Q modulated RF input signal <b>2582</b> is output by antenna <b>2572</b> and received by optional LNA <b>2518</b>. When present, LNA <b>2518</b> amplifies I/Q modulated RF input signal <b>2582</b>, and outputs amplified IQ signal <b>2588</b>.

0794First UFD module <b>2502</b> receives amplified I/Q signal <b>2588</b>. First UFD module <b>2502</b> down-converts the I-phase signal portion of amplified input I/Q signal <b>2588</b> according to an I control signal <b>2590</b>. First UFD module <b>2502</b> outputs an I output signal <b>2598</b>.

0795In an embodiment, first UFD module <b>2502</b> comprises a first storage module <b>2524</b>, a first UFT module <b>2526</b>, and a first voltage reference <b>2528</b>. In an embodiment, a switch contained within first UFT module <b>2526</b> opens and closes as a function of I control signal <b>2590</b>. As a result of the opening and closing of this switch, which respectively couples and de-couples first storage module <b>2524</b> to and from first voltage reference <b>2528</b>, a down-converted signal, referred to as I output signal <b>2598</b>, results. First voltage reference <b>2528</b> may be any reference voltage, and is preferably ground. I output signal <b>2598</b> is stored by first storage module <b>2524</b>.

0796In a preferred embodiment, first storage module <b>2524</b> comprises a first capacitor <b>2574</b>. In addition to storing I output signal <b>2598</b>, first capacitor <b>2574</b> reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on I output signal <b>2598</b>, in a similar fashion to that of capacitor <b>9126</b> shown in <figref idref="DRAWINGS">FIG. 91</figref>. Refer to section 7.2.1.3 above for further discussion on reducing or eliminating charge injection with a series capacitor such as capacitor <b>9126</b>.

0797I output signal <b>2598</b> is received by optional first filter <b>2504</b>. When present, first filter <b>2504</b> is a high pass filter to at least filter I output signal <b>2598</b> to remove any carrier signal “bleed through”. In a preferred embodiment, when present, first filter <b>2504</b> comprises a first resistor <b>2530</b>, a first filter capacitor <b>2532</b>, and a first filter voltage reference <b>2534</b>. Preferably, first resistor <b>2530</b> is coupled between I output signal <b>2598</b> and a filtered I output signal <b>2507</b>, and first filter capacitor <b>2532</b> is coupled between filtered I output signal <b>2507</b> and first filter voltage reference <b>2534</b>. Alternately, first filter <b>2504</b> may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). First filter <b>2504</b> outputs filtered I output signal <b>2507</b>.

0798Second UFD module <b>2506</b> receives amplified I/Q signal <b>2588</b>. Second UFD module <b>2506</b> down-converts the inverted I-phase signal portion of amplified input I/Q signal <b>2588</b> according to an inverted I control signal <b>2592</b>. Second UFD module <b>2506</b> outputs an inverted I output signal <b>2501</b>.

0799In an embodiment, second UFD module <b>2506</b> comprises a second storage module <b>2536</b>, a second UFT module <b>2538</b>, and a second voltage reference <b>2540</b>. In an embodiment, a switch contained within second UFT module <b>2538</b> opens and closes as a function of inverted I control signal <b>2592</b>. As a result of the opening and closing of this switch, which respectively couples and de-couples second storage module <b>2536</b> to and from second voltage reference <b>2540</b>, a down-converted signal, referred to as inverted I output signal <b>2501</b>, results. Second voltage reference <b>2540</b> may be any reference voltage, and is preferably ground. Inverted I output signal <b>2501</b> is stored by second storage module <b>2536</b>.

0800In a preferred embodiment, second storage module <b>2536</b> comprises a second capacitor <b>2576</b>. In addition to storing inverted I output signal <b>2501</b>, second capacitor <b>2576</b> reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on inverted I output signal <b>2501</b>, in a similar fashion to that of capacitor <b>9126</b> shown in <figref idref="DRAWINGS">FIG. 91</figref>. Refer to section 7.2.1.3 above for further discussion on reducing or eliminating charge injection with a series capacitor such as capacitor <b>9126</b>.

0801Inverted I output signal <b>2501</b> is received by optional second filter <b>2508</b>. When present, second filter <b>2508</b> is a high pass filter to at least filter inverted I output signal <b>2501</b> to remove any carrier signal “bleed through”. In a preferred embodiment, when present, second filter <b>2508</b> comprises a second resistor <b>2542</b>, a second filter capacitor <b>2544</b>, and a second filter voltage reference <b>2546</b>. Preferably, second resistor <b>2542</b> is coupled between inverted I output signal <b>2501</b> and a filtered inverted I output signal <b>2509</b>, and second filter capacitor <b>2544</b> is coupled between filtered inverted I output signal <b>2509</b> and second filter voltage reference <b>2546</b>. Alternately, second filter <b>2508</b> may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Second filter <b>2508</b> outputs filtered inverted I output signal <b>2509</b>.

0802First differential amplifier <b>2520</b> receives filtered I output signal <b>2507</b> at its non-inverting input and receives filtered inverted I output signal <b>2509</b> at its inverting input. First differential amplifier <b>2520</b> subtracts filtered inverted I output signal <b>2509</b> from filtered I output signal <b>2507</b>, amplifies the result, and outputs I baseband output signal <b>2584</b>. Other suitable subtractor and/or amplification modules may be substituted for first differential amplifier <b>2520</b>, and second differential amplifier <b>2522</b>, as would be understood by persons skilled in the relevant art(s) from the teachings herein. Because filtered inverted I output signal <b>2509</b> is substantially equal to an inverted version of filtered I output signal <b>2507</b>, I baseband output signal <b>2584</b> is substantially equal to filtered I output signal <b>2509</b>, with its amplitude doubled. Furthermore, filtered I output signal <b>2507</b> and filtered inverted I output signal <b>2509</b> may comprise substantially equal noise and DC offset contributions of the same polarity from prior down-conversion circuitry, including first UFD module <b>2502</b> and second UFD module <b>2506</b>, respectively. When first differential amplifier <b>2520</b> subtracts filtered inverted I output signal <b>2509</b> from filtered I output signal <b>2507</b>, these noise and DC offset contributions substantially cancel each other.

0803Third UFD module <b>2510</b> receives amplified I/Q signal <b>2588</b>. Third UFD module <b>2510</b> down-converts the Q-phase signal portion of amplified input I/Q signal <b>2588</b> according to an Q control signal <b>2594</b>. Third UFD module <b>2510</b> outputs an Q output signal <b>2503</b>.

0804In an embodiment, third UFD module <b>2510</b> comprises a third storage module <b>2548</b>, a third UFT module <b>2550</b>, and a third voltage reference <b>2552</b>. In an embodiment, a switch contained within third UFT module <b>2550</b> opens and closes as a function of Q control signal <b>2594</b>. As a result of the opening and closing of this switch, which respectively couples and de-couples third storage module <b>2548</b> to and from third voltage reference <b>2552</b>, a down-converted signal, referred to as Q output signal <b>2503</b>, results. Third voltage reference <b>2552</b> may be any reference voltage, and is preferably ground. Q output signal <b>2503</b> is stored by third storage module <b>2548</b>.

0805In a preferred embodiment, third storage module <b>2548</b> comprises a third capacitor <b>2578</b>. In addition to storing Q output signal <b>2503</b>, third capacitor <b>2578</b> reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on Q output signal <b>2503</b>, in a similar fashion to that of capacitor <b>9126</b> shown in <figref idref="DRAWINGS">FIG. 91</figref>. Refer to section 7.2.1.3 above for further discussion on reducing or eliminating charge injection with a series capacitor such as capacitor <b>9126</b>.

0806Q output signal <b>2503</b> is received by optional third filter <b>2512</b>. When present, third filter <b>2512</b> is a high pass filter to at least filter Q output signal <b>2503</b> to remove any carrier signal “bleed through”. In a preferred embodiment, when present, third filter <b>2512</b> comprises a third resistor <b>2554</b>, a third filter capacitor <b>2558</b>, and a third filter voltage reference <b>2558</b>. Preferably, third resistor <b>2554</b> is coupled between Q output signal <b>2503</b> and a filtered Q output signal <b>2511</b>, and third filter capacitor <b>2556</b> is coupled between filtered Q output signal <b>2511</b> and third filter voltage reference <b>2558</b>. Alternately, third filter <b>2512</b> may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Third filter <b>2512</b> outputs filtered Q output signal <b>2511</b>.

0807Fourth UFD module <b>2514</b> receives amplified I/Q signal <b>2588</b>. Fourth UFD module <b>2514</b> down-converts the inverted Q-phase signal portion of amplified input I/Q signal <b>2588</b> according to an inverted Q control signal <b>2596</b>. Fourth UFD module <b>2514</b> outputs an inverted Q output signal <b>2505</b>.

0808In an embodiment, fourth UFD module <b>2514</b> comprises a fourth storage module <b>2560</b>, a fourth UFT module <b>2562</b>, and a fourth voltage reference <b>2564</b>. In an embodiment, a switch contained within fourth UFT module <b>2562</b> opens and closes as a function of inverted Q control signal <b>2596</b>. As a result of the opening and closing of this switch, which respectively couples and de-couples fourth storage module <b>2560</b> to and from fourth voltage reference <b>2564</b>, a down-converted signal, referred to as inverted Q output signal <b>2505</b>, results. Fourth voltage reference <b>2564</b> may be any reference voltage, and is preferably ground. Inverted Q output signal <b>2505</b> is stored by fourth storage module <b>2560</b>.

0809In a preferred embodiment, fourth storage module <b>2560</b> comprises a fourth capacitor <b>2580</b>. In addition to storing inverted Q output signal <b>2505</b>, fourth capacitor <b>2580</b> reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on inverted Q output signal <b>2505</b>, in a similar fashion to that of capacitor <b>9126</b> shown in <figref idref="DRAWINGS">FIG. 91</figref>. Refer to section 7.2.1.3 above for further discussion on reducing or eliminating charge injection with a series capacitor such as capacitor <b>9126</b>.

0810Inverted Q output signal <b>2505</b> is received by optional fourth filter <b>2516</b>. When present, fourth filter <b>2516</b> is a high pass filter to at least filter inverted Q output signal <b>2505</b> to remove any carrier signal “bleed through”. In a preferred embodiment, when present, fourth filter <b>2516</b> comprises a fourth resistor <b>2566</b>, a fourth filter capacitor <b>2568</b>, and a fourth filter voltage reference <b>2570</b>. Preferably, fourth resistor <b>2566</b> is coupled between inverted Q output signal <b>2505</b> and a filtered inverted Q output signal <b>2513</b>, and fourth filter capacitor <b>2568</b> is coupled between filtered inverted Q output signal <b>2513</b> and fourth filter voltage reference <b>2570</b>. Alternately, fourth filter <b>2516</b> may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Fourth filter <b>2516</b> outputs filtered inverted Q output signal <b>2513</b>.

0811Second differential amplifier <b>2522</b> receives filtered Q output signal <b>2511</b> at its non-inverting input and receives filtered inverted Q output signal <b>2513</b> at its inverting input. Second differential amplifier <b>2522</b> subtracts filtered inverted Q output signal <b>2513</b> from filtered Q output signal <b>2511</b>, amplifies the result, and outputs Q baseband output signal <b>2586</b>. Because filtered inverted Q output signal <b>2513</b> is substantially equal to an inverted version of filtered Q output signal <b>2511</b>, Q baseband output signal <b>2586</b> is substantially equal to filtered Q output signal <b>2513</b>, with its amplitude doubled. Furthermore, filtered Q output signal <b>2511</b> and filtered inverted Q output signal <b>2513</b> may comprise substantially equal noise and DC offset contributions of the same polarity from prior down-conversion circuitry, including third UFD module <b>2510</b> and fourth UFD module <b>2514</b>, respectively. When second differential amplifier <b>2522</b> subtracts filtered inverted Q output signal <b>2513</b> from filtered Q output signal <b>2511</b>, these noise and DC offset contributions substantially cancel each other.

0812<figref idref="DRAWINGS">FIG. 120</figref> depicts a flowchart <b>12000</b> that illustrates operational steps corresponding to <figref idref="DRAWINGS">FIG. 25</figref>, for down-converting a RF I/Q modulated signal and reducing DC offset voltages, according to an embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. In the following discussion, the steps in <figref idref="DRAWINGS">FIG. 120</figref> will be described.

0813In step <b>12002</b>, an input signal is received, wherein the input signal comprises an RF I/Q modulated signal.

0814In step <b>12004</b>, the input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, according to a first control signal. In an embodiment, the input signal is frequency down-converted to a non-inverted I-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a first phase of the in-phase signal portion of the RF I/Q modulated signal is under-sampled. In an embodiment, the RF I/Q modulated signal may be under-sampled every 3.0 cycles of a frequency of the RF I/Q modulated signal by the first control signal. Furthermore, in embodiments, a first DC offset voltage in the first down-converted signal is reduced by a capacitor of the first universal frequency down-conversion module.

0815In step <b>12006</b>, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, according to a second control signal. In an embodiment, the input signal is frequency down-converted to an inverted I-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a second phase of the in-phase signal portion of the RF I/Q modulated signal is under-sampled, wherein the second phase of the in-phase signal portion is of an opposite phase to the first phase under-sampled of the in-phase signal portion. The RF I/Q modulated signal may be sampled 1.5 cycles of a frequency of the RF I/Q modulated signal after under-sampling the RF I/Q modulated signal in step <b>12004</b>, for example. Furthermore, in embodiments, a second DC offset voltage in the second down-converted signal is reduced by a capacitor of the second universal frequency down-conversion module.

0816In step <b>12008</b>, the second down-converted signal is subtracted from the first down-converted signal to form a first output signal. In embodiments, a first DC offset voltage in the first down-converted signal and a second DC offset voltage in the second down-converted signal cancel one another.

0817In step <b>12010</b>, the input signal is frequency down-converted with a third universal frequency down-conversion module to a third down-converted signal, according to a third control signal. In an embodiment, the input signal is frequency down-converted to a non-inverted Q-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a third phase of the quadrature-phase signal portion of the RF I/Q modulated signal is under-sampled. The RF I/Q modulated signal may be under-sampled 0.75 cycles of the frequency of the RF I/Q modulated signal after under-sampling of the RF I/Q modulated signal occurs in step <b>12004</b>, for example. Furthermore, in embodiments, a third DC offset voltage in the third down-converted signal is reduced by a capacitor of the third universal frequency down-conversion module.

0818In step <b>12012</b>, the input signal is frequency down-converted with a fourth universal frequency down-conversion module to a fourth down-converted signal, according to a fourth control signal. In an embodiment, the input signal is frequency down-converted to an inverted Q-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a fourth phase of the quadrature-phase signal portion of the RF I/Q modulated signal is under-sampled, wherein the fourth phase of the quadrature-phase signal portion is of an opposite phase to the third phase under-sampled of the quadrature-phase signal portion. In an embodiment, the RF I/Q modulated signal may be sampled 1.5 cycles of the frequency of the RF I/Q modulated signal after under-sampling of the RF I/Q modulated signal occurs in step <b>12010</b>, for example. Furthermore, in embodiments, a fourth DC offset voltage in the fourth down-converted signal is reduced by a capacitor of fourth universal frequency down-conversion module.

0819In step <b>12014</b>, the fourth down-converted signal is subtracted from the third down-converted signal to form a second output signal. In embodiments, a third DC offset voltage in the third down-converted signal and a fourth DC offset voltage in the fourth down-converted signal cancel one another.

0820In step <b>12016</b>, a signal is re-radiated that comprises attenuated components of first, second, third, and fourth control signal pulses, wherein the attenuated components of the first, second, third, and fourth control signal pulses form a cumulative frequency, as discussed above.

0821In step <b>12018</b>, the first, second, third, and fourth control signal pulses are configured such that the cumulative frequency is greater than a frequency of the input signal, as discussed above.

08227.4.1.1 Example I/Q Modulation Control Signal Generator Embodiments

0823<figref idref="DRAWINGS">FIG. 26</figref> illustrates an exemplary block diagram for I/Q modulation control signal generator <b>2600</b>, according to an embodiment of the present invention. I/Q modulation control signal generator <b>2600</b> generates I control signal <b>2590</b>, inverted I control signal <b>2592</b>, Q control signal <b>2594</b>, and inverted Q control signal <b>2596</b> used by I/Q modulation receiver <b>2500</b> of <figref idref="DRAWINGS">FIG. 25</figref>. I control signal <b>2590</b> and inverted I control signal <b>2592</b> operate to down-convert the I-phase portion of an input I/Q modulated RF signal. Q control signal <b>2594</b> and inverted Q control signal <b>2596</b> act to down-convert the Q-phase portion of the input I/Q modulated RF signal. Furthermore, I/Q modulation control signal generator <b>2600</b> has the advantage of generating control signals in a manner such that resulting collective circuit re-radiation is radiated at one or more frequencies outside of the frequency range of interest. For instance, potential circuit re-radiation is radiated at a frequency substantially greater than that of the input RF carrier signal frequency.

0824I/Q modulation control signal generator <b>2600</b> comprises a local oscillator <b>2602</b>, a first divide-by-two module <b>2604</b>, a 180 degree phase shifter <b>2606</b>, a second divide-by-two module <b>2608</b>, a first pulse generator <b>2610</b>, a second pulse generator <b>2612</b>, a third pulse generator <b>2614</b>, and a fourth pulse generator <b>2616</b>.

0825Local oscillator <b>2602</b> outputs an oscillating signal <b>2618</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary oscillating signal <b>2618</b>.

0826First divide-by-two module <b>2604</b> receives oscillating signal <b>2618</b>, divides oscillating signal <b>2618</b> by two, and outputs a half frequency LO signal <b>2620</b> and a half frequency inverted LO signal <b>2626</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary half frequency LO signal <b>2620</b>. Half frequency inverted LO signal <b>2626</b> is an inverted version of half frequency LO signal <b>2620</b>. First divide-by-two module <b>2604</b> may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s).

0827180 degree phase shifter <b>2606</b> receives oscillating signal <b>2618</b>, shifts the phase of oscillating signal <b>2618</b> by 180 degrees, and outputs phase-shifted LO signal <b>2622</b>. 180 degree phase shifter <b>2606</b> may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s). In alternative embodiments, other amounts of phase shift may be used.

0828Second divide-by two module <b>2608</b> receives phase-shifted LO signal <b>2622</b>, divides phase-shifted LO signal <b>2622</b> by two, and outputs a half frequency phase-shifted LO signal <b>2624</b> and a half frequency inverted phase-shifted LO signal <b>2628</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary half frequency phase-shifted LO signal <b>2624</b>. Half frequency inverted phase-shifted LO signal <b>2628</b> is an inverted version of half frequency phase-shifted LO signal <b>2624</b>. Second divide-by-two module <b>2608</b> may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s).

0829First pulse generator <b>2610</b> receives half frequency LO signal <b>2620</b>, generates an output pulse whenever a rising edge is received on half frequency LO signal <b>2620</b>, and outputs I control signal <b>2590</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary I control signal <b>2590</b>.

0830Second pulse generator <b>2612</b> receives half frequency inverted LO signal <b>2626</b>, generates an output pulse whenever a rising edge is received on half frequency inverted LO signal <b>2626</b>, and outputs inverted I control signal <b>2592</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary inverted I control signal <b>2592</b>.

0831Third pulse generator <b>2614</b> receives half frequency phase-shifted LO signal <b>2624</b>, generates an output pulse whenever a rising edge is received on half frequency phase-shifted LO signal <b>2624</b>, and outputs Q control signal <b>2594</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary Q control signal <b>2594</b>.

0832Fourth pulse generator <b>2616</b> receives half frequency inverted phase-shifted LO signal <b>2628</b>, generates an output pulse whenever a rising edge is received on half frequency inverted phase-shifted LO signal <b>2628</b>, and outputs inverted Q control signal <b>2596</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an exemplary inverted Q control signal <b>2596</b>.

0833In a preferred embodiment, control signals <b>2590</b>, <b>2592</b>, <b>2594</b> and <b>2596</b> output pulses having a width equal to one-half of a period of I/Q modulated RF input signal <b>2582</b>. The invention, however, is not limited to these pulse widths, and control signals <b>2590</b>, <b>2592</b>, <b>2594</b>, and <b>2596</b> may comprise pulse widths of any fraction of, or multiple and fraction of, a period of I/Q modulated RF input signal <b>2582</b>.

0834First, second, third, and fourth pulse generators <b>2610</b>, <b>2612</b>, <b>2614</b>, and <b>2616</b> may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s).

0835As shown in <figref idref="DRAWINGS">FIG. 27</figref>, control signals <b>2590</b>, <b>2592</b>, <b>2594</b>, and <b>2596</b> comprise pulses that are non-overlapping. Furthermore, in this example, pulses appear on these signals in the following order: I control signal <b>2590</b>, Q control signal <b>2594</b>, inverted I control signal <b>2592</b>, and inverted Q control signal <b>2596</b>. Potential circuit re-radiation from I/Q modulation receiver <b>2500</b> may comprise frequency components from a combination of these control signals.

0836For example, <figref idref="DRAWINGS">FIG. 28</figref> shows an overlay of pulses from I control signal <b>2590</b>, Q control signal <b>2594</b>, inverted I control signal <b>2592</b>, and inverted Q control signal <b>2596</b>. When pulses from these control signals leak to through first, second, third, and fourth UFD modules <b>2502</b>, <b>2506</b>, <b>2510</b>, and <b>2514</b> of to antenna <b>2582</b> (shown in FIG. <b>25</b>), they may be radiated from I/Q modulation receiver <b>2500</b>, with a combined waveform that appears to have a primary frequency equal to four times the frequency of any single one of control signals <b>2590</b>, <b>2592</b>, <b>2594</b>, and <b>2596</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an example combined control signal <b>2702</b>.

0837<figref idref="DRAWINGS">FIG. 28</figref> also shows an example I/Q modulation RF input signal <b>2582</b> overlaid upon control signals <b>2590</b>, <b>2592</b>, <b>2594</b>, and <b>2596</b>. As shown in <figref idref="DRAWINGS">FIG. 28</figref>, pulses on I control signal <b>2590</b> overlay and act to down-convert a positive I-phase portion of I/Q modulation RF input signal <b>2582</b>. Pulses on inverted I control signal <b>2592</b> overlay and act to down-convert a negative I-phase portion of I/Q modulation RF input signal <b>2582</b>. Pulses on Q control signal <b>2594</b> overlay and act to down-convert a rising Q-phase portion of I/Q modulation RF input signal <b>2582</b>. Pulses on inverted Q control signal <b>2596</b> overlay and act to down-convert a falling Q-phase portion of I/Q modulation RF input signal <b>2582</b>.

0838As <figref idref="DRAWINGS">FIG. 28</figref> further shows in this example, the frequency ratio between the combination of control signals <b>2590</b>, <b>2592</b>, <b>2594</b>, and <b>2596</b> and I/Q modulation RF input signal <b>2582</b> is 4:3. Because the frequency of the potentially re-radiated signal, combined control signal <b>2702</b>, is substantially different from that of the signal being down-converted, I/Q modulation RF input signal <b>2582</b>, it does not interfere with signal down-conversion as it is out of the frequency band of interest, and hence may be filtered out. In this manner, I/Q modulation receiver <b>2500</b> reduces problems due to circuit re-radiation. As will be understood by persons skilled in the relevant art(s) from the teachings herein, frequency ratios other than 4:3 may be implemented to achieve similar reduction of problems of circuit re-radiation.

0839It should be understood that the above control signal generator circuit example is provided for illustrative purposes only. The invention is not limited to these embodiments. Alternative embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) for I/Q modulation control signal generator <b>2600</b> will be apparent to persons skilled in the relevant art(s) from the teachings herein, and are within the scope of the present invention.

08407.4.1.2 Detailed Example I/Q Modulation Receiver Embodiment with Exemplary Waveforms

0841<figref idref="DRAWINGS">FIG. 29</figref> illustrates a more detailed example circuit implementation of I/Q modulation receiver <b>2500</b>, according to an embodiment of the present invention.

0842<figref idref="DRAWINGS">FIGS. 30-40</figref> show waveforms related to an example implementation of I/Q modulation receiver <b>2500</b> of <figref idref="DRAWINGS">FIG. 29</figref>.

0843<figref idref="DRAWINGS">FIGS. 30 and 31</figref> show first and second input data signals <b>2902</b> and <b>2904</b> to be I/Q modulated with a RF carrier signal frequency as the I-phase and Q-phase information signals, respectively.

0844<figref idref="DRAWINGS">FIGS. 33 and 34</figref> show the signals of <figref idref="DRAWINGS">FIGS. 30 and 31</figref> after modulation with a RF carrier signal frequency, respectively, as I-modulated signal <b>2906</b> and Q-modulated signal <b>2908</b>.

0845<figref idref="DRAWINGS">FIG. 32</figref> shows an I/Q modulation RF input signal <b>2582</b> formed from I-modulated signal <b>2906</b> and Q-modulated signal <b>2908</b> of <figref idref="DRAWINGS">FIGS. 33 and 34</figref>, respectively.

0846<figref idref="DRAWINGS">FIG. 39</figref> shows an overlaid view of filtered I output signal <b>3902</b> and filtered inverted I output signal <b>3904</b>.

0847<figref idref="DRAWINGS">FIG. 40</figref> shows an overlaid view of filtered Q output signal <b>4002</b> and filtered inverted Q output signal <b>4004</b>.

0848<figref idref="DRAWINGS">FIGS. 35 and 36</figref> show I baseband output signal <b>2584</b> and Q baseband output signal <b>2586</b>, respectfully. A data transition <b>3202</b> is indicated in both I baseband output signal <b>2584</b> and Q baseband output signal <b>2586</b>. The corresponding data transition <b>3202</b> is indicated in I-modulated signal <b>2906</b> of <figref idref="DRAWINGS">FIG. 33</figref>, Q-modulated signal <b>2908</b> of <figref idref="DRAWINGS">FIG. 34</figref>, and I/Q modulation RF input signal <b>2582</b> of <figref idref="DRAWINGS">FIG. 32</figref>.

0849<figref idref="DRAWINGS">FIGS. 37 and 38</figref> show I baseband output signal <b>2584</b> and Q baseband output signal <b>2586</b> over a wider time interval.

08507.4.1.3 Example Single Channel Receiver Embodiment

0851<figref idref="DRAWINGS">FIG. 41</figref> illustrates an exemplary single channel receiver <b>4100</b>, corresponding to either the I or Q channel of I/Q modulation receiver <b>2500</b>, according to an embodiment of the present invention. Single channel receiver <b>4100</b> can down-convert an input RF signal <b>4106</b> modulated according to AM, PM, FM, and other modulation schemes. Refer to section 7.4.1 above for further description on the operation of single channel receiver <b>4100</b>.

08527.4.1.4 Alternative Example I/Q Modulation Receiver Embodiment

0853<figref idref="DRAWINGS">FIG. 42</figref> illustrates an exemplary I/Q modulation receiver <b>4200</b>, according to an embodiment of the present invention. I/Q modulation receiver <b>4200</b> receives, down-converts, and demodulates an I/Q modulated RF input signal <b>2582</b> to an I baseband output signal <b>2584</b>, and a Q baseband output signal <b>2586</b>. I/Q modulation receiver <b>4200</b> has additional advantages of reducing or eliminating unwanted DC offsets and circuit re-radiation, in a similar fashion to that of I/Q modulation receiver <b>2500</b> described above.

08547.4.1.5 Example Transmitter Embodiment

0855<figref idref="DRAWINGS">FIG. 43</figref> illustrates an exemplary I/Q modulation transmitter <b>4300</b> (only I channel is shown), according to an embodiment of the present invention. I/Q modulation transmitter has a configuration substantially similar to I/Q modulation receiver <b>2500</b>. Hence, an I/Q modulation transmitter <b>4300</b> and an I/Q modulation receiver <b>2500</b> may be implemented with at least some common circuit components.

0856I/Q modulation transmitter <b>4300</b> comprises an optional first filter <b>4302</b>, a second optional filter <b>4306</b>, and a third optional filter <b>4310</b>. When present, second and third optional filters <b>4306</b> and <b>4310</b> may comprise first and second resistors <b>4334</b> and <b>4336</b>, respectively. In alternative embodiments, second and third optional filters <b>4306</b> and <b>4310</b> may comprise inductors, capacitors, and/or other filtering elements, alone or in combination.

8. CONCLUSION

0857While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.