Integrated frequency translation and selectivity with a variety of filter embodiments

Integrated frequency conversion, frequency selection, and device with filter

Field of invention

The invention relates to a method and device for frequency conversion and frequency selection.

Known technology description

FIG. 1 is a block diagram of a conventional receiver 112. FIG. 2 shows a flowchart of the operation of the receiver 112. In step 206, the band selection filter 102 and the RF (radio frequency) spectrum 114 are displayed. An example of the RF spectrum 114 is shown in Figure 4A. The RF spectrum 114 includes frequency f₁, F₂, F₃, F₄Signal components. To illustrate, suppose that the receiver 112 is planned to receive frequency f₃Signal.

Basically, the band selection filter 102 is a broadband filter. Generally speaking, the characteristics of the band selection filter 102 are as shown in FIG. 4B. The band selection filter 102 has a center frequency fc and a band selection bandwidth 402. In the example of FIG. 1, the receiver 112 is receiving the RF spectrum 114, and the center frequency fc of the band selection filter 102 falls within the RF range. For example, the center frequency fc may be 90 MHz. Depending on the application, the band selection bandwidth 402 can be 50 MHz or greater. In the example, the center frequency fc is 900MHz and the band selection bandwidth 402 is 50MHz, and the passband of the band selection filter 102 (that is, the frequency band that is only slightly lost after passing through the filter with respect to frequencies outside the band) is 875MHz To 925MHz. According to this specification, the quality factor of the band selection filter 102, or Q, is equal to 18 (further note, Q is equal to the center frequency divided by the bandwidth, or in this case, 900MHz÷50MHz). The Q factor is basically provided to the bandpass filter to operate at RF. In fact, with the conventional filter technology, it is usually impossible to achieve a high Q factor at high frequencies, and it must be obtained under the best limit adjustment capability.

In step 206, the band selection filter 102 filters out signals outside the passband. To illustrate, suppose f₁And f₄Located outside the passband of the band selection filter 102, and f₂And f₃It is located inside the passband of the band selection filter 102 (this is the case of the example of FIGS. 4A and 4B). Therefore, in the example, the band selection filter 102 filters out₁And f₄Signal components. The band selection filter 102 is allowed to be located at the frequency f₂And f₃The signal component of the pass. The operation result of the band selection filter 102 is shown in FIG. 4C.

In steps 208 and 210, the signal output by the band selection filter 102 (referred to herein as the band selection filter spectrum 408) is processed by the low noise amplifier (LAN) 104 and the mixer 106. The LAN 104 is used to amplify the frequency band selection filtering spectrum 408, and the mixer 106 down-converts the frequency band selection filtering spectrum 408 using well-known techniques.

The LAN 104 and the mixer 106 operate linearly within a limited dynamic range. Outside of these ranges, the LAN 104 and the mixer 106 exhibit non-linear operation. The wider the band selection filter 102 (that is, the wider the passband), the more energy reaches the LAN 104 and the mixer 106. Therefore, the wider the band selection filter 102, the more likely it is to exceed the dynamic range of the LAN 104 and the mixer 106. To illustrate, assume that it is at frequency f₃The signal component 420 combines the frequency f₂The unwanted signal component 421 exceeds the linear range of the LAN 104 and the mixer 106 (this is a general practical example).

When operating a signal outside the linear range (that is, when operating in a non-linear behavior), the LAN 104 and/or the mixer 106 generate parasitic signal components. In the given example, when the signal components 420 and 421 are operated, the LAN 104 and the mixer 106 generate the parasitic signal component 404. See Figure 4D. Some spurious signal components 404 may overlap or interfere with the signal at the desired frequency. For example, as noted above, adjust the receiver 112 to receive at frequency f₃Signal (in the example of Fig. 4A-4G, after down-conversion, the frequency f₇Corresponds to f₃; Similarly, after down-conversion, the frequency f₆Corresponds to f₂)。

When processing the operating signal components 420 and 421, the LAN 104 and/or the mixer 106 operate at the frequency f₇There is a parasitic signal component 404C. The spurious signal component 404C and the frequency f₇The required signal components 420 overlap. This spurious signal component 404C interferes with the required signal component 420.

In step 212, the channel selection filter 108 filters the signal generated by the LAN 104 and 106 (for reference, the signal is referred to herein as the processed spectrum 410). The approximate characteristics of the channel selection filter 108 are shown in FIG. 4E. The channel selection filter 108 has f₇The center frequency and channel selection bandwidth 406. Center frequency f of channel selection filter 108₇It is lower than the center frequency of the band selection filter 102. For example, the center frequency f of the channel selection filter 108₇Can be 10MHz. Depending on the application, the quality factor of the channel selection filter 108, or Q, is 200 (as pointed out and further described above, Q is equal to the center frequency divided by the bandwidth, or 10MHz÷50MHz in this example). This Q factor is basically used for a narrow band pass filter (intermediate frequency) operating at IF. This example illustrates that the conventional filtering technique can be used to achieve a higher Q factor at a lower frequency.

As shown in FIG. 4F, in step 212, the effect of the channel selection filter 108 is to filter out the signal component at the frequency f6 and the parasitic components 404A, 404B, and 404D, and let any signal at the frequency f7 pass. The required signal component 420 and the spurious signal component 404C exist at the frequency f7 at the same time, and fall within the passband of the channel selection filter 108. Therefore, the required signal component 420 and the spurious signal component 404C pass through the channel selection filter 108 at the same time.

In step 214, the amplifier 110 amplifies the output signal of the channel selection filter 108 (for reference, this signal is referred to as the channel selection filter signal 412). The channel selection filter signal 412 includes both the required signal component 420 and the spurious signal component 404C. Therefore, the amplifier 110 simultaneously amplifies the required signal component 420 and the parasitic signal component 404C.

As noted above, if there is a chance to receive the required signal component 420, the parasitic signal component 404C will cause trouble. Therefore, since the receiver 112 uses a broadband, the band selection filter 102 preferentially uses non-linear elements for amplification and frequency conversion (that is, the LAN 104 and the mixer 106 are used respectively), and the receiver 112 suffers from potentially poor performance. As mentioned above, potential signal interference limits the applicability of the receiver 112.

Summary of the invention

The present invention refers to a method and device for frequency selection and frequency conversion. The present invention is applied to such a hair method and device at the same time.

In short, the present invention filters the input signal and down-converts the filtered input signal. According to the embodiment of the present invention, the filtering operation and the down-conversion operation are integrated and performed in a single manner.

According to the embodiment of the present invention, the filtering operation can effectively be performed prior to the down-conversion operation. In this way, the input filter proposed in the present invention, similar to but not limited to the front-end filter, can be used to perform frequency-selective operations.

In the preferred embodiment of the present invention, a relatively high Q factor can be achieved regardless of the center frequency.

In the preferred embodiment of the present invention, the input signal is an RF signal. Therefore, the frequency-selective operation can be performed by the Q RF filtering which is quite high in the present invention.

Therefore, the embodiment of the present invention is preferably used to perform front-end, narrow-band RF filtering, and then perform frequency down conversion.

In other words, the embodiments of the present invention provide precise frequency selectivity at high frequencies. In addition, the present invention provides frequency down conversion.

It is worth reminding that the present invention is not limited to the embodiments outlined here. The embodiments outlined in the text are described as follows with the other embodiments.

With reference to the accompanying drawings, the following describes further features and advantages of the present invention with respect to the structure and operation of different embodiments of the present invention. The element that appears for the first time in the figure will be indicated by the number at the left end as the corresponding reference label.

Detailed description of the preferred example

content

1 Technology

1.1 Filter

1.2 Other technical terms

2 Summary of the invention

3 Integrated down conversion and filtering

3.1 Concept description

3.2 High-level description

3.2.1 Operation instructions

3.2.2 Structure description

3.3 Example

3.3.1 The first embodiment: band-pass filtering and frequency conversion

3.3.1.1 Operation description

3.3.1.2 Structure description

3.3.2 The second embodiment: low-pass filtering and frequency description

3.3.2.1 Operation description

3.3.2.2 Structure description

3.3.3 The third embodiment: low-pass filtering and frequency description

3.3.3.1 Operation description

3.3.3.2 Structure description

3.3.4 Fourth embodiment: finite impulse response (FIR) filtering

3.3.5 Fifth embodiment: continuous average converter

3.3.6 The sixth embodiment: N-path filter

3.3.7 The seventh embodiment: passive filter

3.3.8 Other embodiments

3.4 Implementation example

3.4.1 Implementation example of integrated down conversion and filtering (UDF) module

3.4.2 UDF module component execution example

3.4.2.1.1 Down conversion and delay module

3.4.2.1.1.1 AC/DC Universal Frequency Down Conversion (UDF) Module

3.4.2.1.1.1 Additional energy conversion signal module

3.4.2.1.1.2 Smooth down conversion signal

3.4.2.1.1.3 Impedance matching

3.4.2.1.1.4 Storage and resonance structure

3.4.2.1.1.5 Charging and energy conversion concepts

3.4.2.1.1.6 Optimization and adjustment of gap width/duration cannot be ignored

3.4.2.1.1.6.1 Change input and output impedance

3.4.2.1.1.6.2 Instant gap control

3.4.2.1.1.7 Add bypass network

3.4.2.1.1.8 Using feedback to correct the energy conversion signal

3.4.2.1.1.9 Other impedance

3.4.2.1.1.10 Energy Conversion Down Conversion Example

3.4.2.2 Delay module

3.4.2.3 Zoom module

3.4.2.4 Adder

3.4.2.5 Control signal generator

3.4.2.6 Output sample and hold module

3.4.2.7 Output smoothing module

3.4.2.8 Intermediate point introduction example: high-frequency delay module

3.4.2.9 Intermediate point introduction example: additional filter

3.4.2.10 Intermediate point introduction example: down conversion module

3.4.2.11 Intermediate point introduction example: Up-conversion module

3.4.3 Implement UDF module with integrated circuit (IC)

3.4.4 Other execution

4 Design of integrated down-conversion and filtering UDF module

5 Adjustable UDF module

6 Amplifier

7 Application example

7.1 Receiver

7.2 Other application examples

8 in conclusion

1 Technology

This section roughly describes the various terms and concepts used in this application. The description in this section is for illustration and convenience, without limitation. Based on the thorough teaching provided here, those who are familiar with this technology can fully understand the meaning of these terms and concepts.

1.1 Filter

A filter is a device that allows electromagnetic signals of a specific frequency to pass through with only a slight attenuation. In detail, the filter allows signals in the frequency range (passband) to pass with only a slight attenuation. The filter does not allow signals outside the passband to pass (that is, the filter attenuates signals outside the passband).

There are many types of filters. Contains, for example, low-pass filters, high-pass filters, band-pass filters, concave filters, etc. The characteristics of these filters are roughly shown in Figures 6A-6D.

There are many conversion equations that describe the operation of the filter. For example and without limitation, the following quadratic equation represents the conversion equation of the second-order filter.

<img file="TW441164B_D0001.tif" />

Usually β₂Factorization of the coefficients to solve for z². It can be understood that doing this action will cause other coefficients to change accordingly. Will β₂The coefficients are not factorized, and Equation 1 is rewritten as follows (for the convenience of explanation, β is not clearly indicated here.₂The effect of unfactoring on other coefficients):

<img file="TW441164B_D0002.tif" />

It is worth mentioning that, in addition to the second-order filter of Equation 1, the present invention is not limited to the second-order filter (the present invention can be applied to filters of other orders).

A block diagram of a well-known concept for implementing this quadratic equation is shown in Figure 21. Z in Figure 21^-1Represents the unit delay operation (that is, z^-1The module uses the time unit to delay the input signal).

Binomial Equation 1 is applied to the second-order filtering form. By appropriately setting the coefficients of Equation 1, the conversion formulas for different second-order filters (low-pass, high-pass, concave, etc.) can be obtained. For example, the α in Equation 1₂And α₀Set to 0 to get the conversion equation of the band-pass filter. The obtained conversion equation expresses the operation of the band-pass wave device, as follows:

<img file="TW441164B_D0003.tif" />

Solve for VO to get the following formula:

<img file="TW441164B_D0004.tif" />

In the above formula, z is equal to:

<img file="TW441164B_D0005.tif" />

In Equation 4, f is the frequency and Fs is the sampling frequency of the system.

Put α in the second-order equation 1₂And α₁Set to 0 to get the conversion formula of the bottom pass filter. The resulting conversion formula corresponds to the low-pass filter, as follows:

<img file="TW441164B_D0006.tif" />

Solve for VO to get the following formula:

<img file="TW441164B_D0007.tif" />

The conversion formulas for other types of filters, such as high-pass filters and concave filters (without limitation), can be obtained in a similar way through the second-order equation 1.

It is worth mentioning that the conversion formula provided above is not only for band-pass filters and low-pass filters. A variety of filter conversion formulas can be obtained through different coefficient combinations in Equation 1 or other formulas that are different from Quadratic Equation 1.

There are many criteria for judging filter performance. For example, but not limiting, the performance of the second-order band-pass filter is usually determined by the quality factor, or Q. Figure 5 shows how to calculate the Q value of a second-order filter. Q is equal to the filter center frequency fc divided by the filter bandwidth BW. The bandwidth BW is measured at point 3DB below the maximum intensity of the filter. Therefore, if the center frequency fc of the filter is 1MHz and has a bandwidth of BW 50KHz, the Q value of the filter is

<img file="TW441164B_D0008.tif" />

1.2 Other technical terms

This saving briefly describes the various terms used in this application. The description in this section is for illustration and convenience, without limitation. Based on the thorough teaching provided here, those who are familiar with this technology can fully understand the meaning of these terms. The terminology throughout the specification will be described in detail here.

Amplification Module (AM): A module technology in which the intensity displacement (ie, change) of the transport signal can be regarded as a function of the information signal.

Analog signal: The change between the signal and the discrete state is compared, showing a fixed and continuous change.

Baseband: The frequency band occupied by any information signal generally for transmission and/or reception.

Baseband signal: Any information signal generally used for transmission and/or reception.

Transport frequency: The frequency of the transport signal. It is basically the center frequency of the transmitted signal after being modulated.

Transport signal: An EM wave that has at least adjustable characteristics and can be adjusted to carry information.

Control switch: switch on and off. Without limitation, the switch can be mechanical, electronic, optical, etc., or any combination thereof.

Demodulation: The process of removing or taking out from the transport signal.

Digital signal: A signal in which information is stored in a discrete manner compared to a continuous method.

Direct down conversion: A down conversion technique in which the transmitted signal is directly converted from the transmitted frequency (that is, the transport frequency) down to the basic band signal without passing through an intermediate frequency.

Down conversion: A program that performs frequency conversion where the final frequency is lower than the starting frequency.

Electromagnetic spectrum: A type of spectrum that contains waves with varying characteristics of electric and magnetic fields. This wave can be transmitted through general communication media, including air, space, cables, liquids, waveguides, micro-antennas, ribbon wires, optical fibers, etc., and it is not limited to this. The EM spectrum contains all frequencies greater than 0 Hz.

EM signal: EM spectrum signal. It is also commonly referred to as EM wave. Needless to say, even if it is not clearly pointed out, all the signals discussed in this article are EM signals.

Frequency Modulation (FM): A modulation technique in which the frequency of the transport signal is shifted (that is, changed) according to the function of the information signal.

One type of FM, called "frequency shift adjustment", is mainly used in digital communications, in which the frequency of the transport signal moves between discrete states, rather than continuously changing like analog information.

Harmonics: Harmonics are the sinusoidal elements of periodic waves. Its frequency is equal to an integer multiplied by the fundamental frequency of the periodic wave. In other words, if the periodic waveform has a fundamental frequency of "f" (also called the first harmonic), the frequency of the harmonic is "n.f", where "n" is 2, 3, 4, etc. The harmonic corresponds to n=2, which means the second harmonic, the harmonic corresponds to n=3, which means the third harmonic, and so on.

Information signal: a sending signal containing information. As used in the text, it refers to the original baseband signal at the source. When trying to modulate the information signal into a transport signal, it means "modulated baseband signal". The signal can be sound or data, analog or digital, or any other signal and a combination of these signals.

Intermediate frequency (IF): A signal whose frequency falls between the frequency of the baseband signal and the frequency of the transmitted signal. Modulation: The process of changing the physical characteristics of one or more signals so that information can be transmitted. Three commonly used modulation techniques are frequency modulation, phase modulation, and intensity modulation. Can make full use of these three technologies to change or use in combination.

Phase Modulation (PM): A modulation technique in which the phase of the transport signal is moved (that is, changed) according to the function of the information signal. A type of PM called "phase shift adjustment" is mainly used in digital communications, where the phase of the transport signal moves between discrete states, rather than continuously changing like an analog signal.

Sub-harmonic: The sub-harmonic of a periodic waveform is a sine wave whose frequency is an integer factor of the fundamental frequency of the periodic waveform. That is, the sub-harmonic frequency is the quotient obtained by dividing the fundamental frequency by an integer. For example, if the frequency of the periodic waveform is "f" (also called fundamental), the frequency of the sub-harmonics is "f/n", where n is 2, 3, 4, etc. The sub-harmonic corresponding to n=2 refers to the second sub-harmonic, the sub-harmonic corresponding to n=3 refers to the third sub-harmonic, and so on. The sub-harmonic wood body has harmonics, and i^thSub-harmonic i^thThe harmonic is the fundamental frequency of the original periodic waveform. For example, the third sub-harmonic (frequency "f/3") has a harmonic multiplied by an integer multiple of itself (that is, the second harmonic is "2. f/3", and the third harmonic is "3". .F/3 ", and so on). The third harmonic of the third sub-harmonic of the original signal (ie, "3. f/3") has the frequency of the original signal.

Up-conversion: The process of performing frequency conversion in which the final frequency is higher than the initial frequency.

2 Summary of the invention

The invention is a method and device for frequency selection and frequency conversion. The present invention is also an application of the method and device.

According to the present invention, frequency selection and frequency conversion are performed in a single (ie, integrated) operation. Frequency selection and frequency conversion are operated in a single integrated manner. The present invention can achieve high frequency selection before frequency conversion (input frequency refers to the frequency of the transmitted input spectrum after filtering), including RF (radio frequency) and other more Great frequency. It should be noted that the present invention is not limited to RF or higher frequencies. The invention can also operate at frequencies lower than radio frequencies.

The operation of the transceiver can facilitate the understanding of the present invention. Generally speaking, the transceiver 802 performs three main functions: frequency conversion 808, frequency selection 810, and amplification 812, as shown in FIG. 8. As shown in FIG. 1, in the conventional receiver 112, the mixer 106 performs the frequency transmission operation; the band selection filter 102 and the channel selection filter 108 jointly perform the frequency selection operation; the LAN 104 and the amplifier 110 jointly perform the amplification operation.

In the conventional receiver 112, the band selection filter 102 is located before the mixer 106. Therefore, in the conventional receiver 112, only a part of the frequency selection 810 is performed before the frequency conversion 808. Specifically, only band selection filtering (ie, broadband or image rejection filtering) is performed before the frequency selection operation 810; channel selection filtering (ie, narrowband filtering) is performed after the frequency conversion operation 808. The operation diagram of the conventional receiver 112 is shown in FIG. 3.

As described above, in the conventional receiver 112, signal elements near the required frequency cannot be filtered out by the band selection filter 102. This phenomenon is due to the wide bandwidth of the band selection filter 102 (to be precise, the bandwidth of the band selection filter 102 is greater than the bandwidth of the channel selection filter 108). These signal elements may exceed the dynamic range of the system and cause the LAN 104 and/or the mixer 106 to generate parasitic signal elements, which may interfere with other signals in the desired frequency (see Fig. 4A-4G). Therefore, since only band selection or broadband filtering is performed before the frequency transfer operation 808 or other operations related to the limited linear range elements (such as the mixer 106 and the LAN 104) (such as the amplification operation 812), it is known that the receiver 112 suffers from potentially poor performance. performance.

What we expect is to have the receiver 902 with the operation map shown in FIG. 9. In the receiver 902 of FIG. 9, before the frequency conversion operation 908 and the amplification operation 910, a relatively narrow bandwidth (for example, channel selection filtering) is used for filtering. The advantages of the functional arrangement of the receiver 902 can be found with reference to FIGS. 10A-10E.

Figure 10A shows that the frequency is f₁, F₂, F₃And f₄An example of the input spectrum 904 of a signal element. For example, the input spectrum 904 is an RF spectrum. To illustrate, suppose that the receiver 902 is tuned to receive a signal of frequency f3. In the receiver 902, the input spectrum 904 is first subjected to a frequency selection operation 906. In the example receiver 902, this frequency selection operation 906 includes channel selection filtering. The characteristics of this filtering are generally as shown in FIG. 10B, where the center frequency of the filter (the frequency selection operation 906 is performed) is f3 and the channel selection bandwidth is 1002.

In the example where the input spectrum 904 is an RF spectrum, the center frequency f3 is also an RF frequency. To illustrate, suppose that the center frequency f3 is 900 MHz. Preferably, the channel selection bandwidth 1002 includes a narrowband filter. For illustration and without limitation, the channel selection bandwidth 1002 may be 50 KHz, so that the passband related to the frequency selection operation 906 is 899.95 MHz to 900.05 MHz. Therefore, the frequency selection operation 906 of the receiver 902 represents the front end, the narrowband filtering operation at RF. The Q value of this filter is 900MHz divided by 50KHz, or 18,000. In this way, through the present invention, a filter with a high Q factor at high frequencies can be realized.

The frequency selection operation 906 filters out signal elements that do not fall within the passband associated with the frequency selection operation 906. For illustration purposes, assume that the signal elements at frequency f3 fall within the passband, and the signal elements at frequencies f1, f2, and f4 fall outside the passband (this example is shown in FIGS. 10A and 10B). Therefore, only the signal element located at f3 can pass the frequency selection operation 906. For reference, the signal element at frequency f3 refers to the filtered spectrum 914.

In the receiver 902 of FIG. 9, the frequency conversion operation 908 and the amplification operation 910 follow the frequency selection operation 906. Due to the operation of the frequency selection operation 906, these operations 908, 910 only process signal elements at frequency f3. Other signal elements (that is, the signal elements at frequencies f1, f2, and f4) are filtered out by the frequency selection operation 906. Therefore, these signal elements are not processed by the frequency conversion operation 908 and the amplification operation 910.

When the frequency conversion operation 908 and the amplification operation 910 process the filtered signal 914, no parasitic elements other than the filtered signal 914 will be generated. The result of the frequency conversion operation 908 operation is described in FIG. 10D, and the result of the amplification operation 910 operation is described in FIG. 10E. It is worth reminding that the ideal output signal 912 shown in FIG. 10E does not contain parasitic signal elements.

The present invention is a method and device for integrating down conversion and filtering (UDF). The present invention preferably performs at least the frequency selection operation 906 and the frequency conversion operation 908. According to an embodiment of the present invention, the frequency selection operation 906 performed by the present invention includes filtering at any frequency, such as RF or greater. Such filtering effect can be achieved by preferentially performing the frequency conversion operation 908, as shown in FIG. 9. Therefore, the advantages exhibited by the present invention are described above with reference to FIGS. 10A-10E.

In some embodiments, the filter bandwidth of the present invention conforms to narrowband filtering. Therefore, the present invention can accurately perform the narrowband filtering operation. In other embodiments, the bandwidth of the filter of the present invention is consistent with the broadband filter according to the application. Therefore, the present invention can accurately perform broadband filtering. However, these features of the present invention are presented herein for descriptive purposes only. The filtering capability of the present invention is not limited to the typical filter bandwidths of "narrowband filtering" and "wideband filtering". Instead, the integrated down-conversion and filtering (UDF) functions of the present invention can be designed in any filter bandwidth. The present invention is applicable to and capable of using any filter bandwidth for filtering.

As described above, the present invention can be operated by inputting electromagnetic signals with the same frequency or greater than RF. In these embodiments, the present invention performs filtering and down conversion at RF or greater frequencies. However, it should be understood that the present invention can not only operate at RF or higher frequencies. Instead, the present invention is basically applicable and capable of working at any frequency.

The present invention can be operated with any communication media, including radio, optical, etc., as well as various other types and combinations of these media.

The signal referred to herein can be modulated or unmodulated. The modulated signal can be generated using any modulation scheme, such as AM, FM, PM, etc., or a combination of these amplitude modulations. For example, a variety of different kinds of potpourri are shown in Figures 7A-7C.

The present invention will be described in detail below.

3 Integrated down conversion and filtering

The following sections describe the operation method of integrated down conversion and filtering (UDF) according to embodiments of the present invention. An exemplary embodiment of the structure to achieve this method is also described. It can be understood that the present invention is not limited to the following specific embodiments. Such as equivalents, extensions, changes, corrections, etc., all fall within the scope and spirit of the present invention.

3.1 Concept description

This section describes the concept of the invention.

FIG. 11 shows a conceptual block diagram of a UDF module 1102 according to an embodiment of the present invention. The UDF module 1102 performs at least a frequency conversion operation 908 and a frequency selection operation 906 (FIG. 9).

The effect achieved by the UDF module 1102 is to preferentially perform the frequency selection operation 906 before the frequency conversion operation 908 is performed. Therefore, the UDF module 1102 can effectively perform input filtering.

According to an embodiment of the present invention, this input filtering involves a relatively narrow bandwidth. For example, this input filtering may represent channel selection filtering, where the filter bandwidth may be 50KHz to 150KHz. However, it can be understood that the present invention is not only limited to this frequency range. The present invention is basically applicable to and capable of achieving filter bandwidth at frequencies greater than or less than these frequency values.

In the embodiment of the present invention, the input signal 1104 received by the UDF module 1102 is a radio frequency. The UDF module 1102 effectively inputs the RF input signal 1104 into the filter. In detail, in this embodiment, the UDF module 1102 can effectively perform the input of the RF input signal 1104 and channel selection filtering. Therefore, the present invention can achieve high selectivity at high frequencies.

The UDF module 1102 can effectively perform various types of filtering, including band-pass filtering, low-pass filtering, high-pass filtering, concave filtering, all-pass filtering, band-stop filtering, etc., and combinations of these filters.

Conceptually, the UDF module 1102 includes a frequency converter 1108. The frequency converter 1108 represents a part of the frequency conversion performed by the UDF module 1102 (down conversion).

Conceptually, the UDF module 1102 also includes a simulated input filter 1106 (sometimes referred to as an input filter simulator). Conceptually, the simulated input filter 1106 represents a part of the input filtering performed by the UDF module 1102.

In fact, the input filtering performed by the UDF module 1102 is integrated with the frequency conversion operation. The input filtering operation can be regarded as synchronized with the frequency conversion operation. This is why the input filter 1106 referred to in this article is the "simulation" input filter 1106.

The UDF module of the present invention has many advantages. For example, using the UDF module 1102 can achieve high frequency and high selectivity. This feature of the present invention can be confirmed by the high Q factor obtained. For example, the UDF module 1102 can be designed to have a filter center frequency fc at a level of 900 MHz, and a filter bandwidth at a level of 50 KHz. The Q value at this time is 18,000, which is expressed as follows.

<img file="TW441164B_D0009.tif" />

It can be understood that the present invention is not limited to high Q factors. Depending on the application, design, and/or implementation occasions, the filter considered in the present invention can be less than or greater than Qs. At the same time, the scope of the present invention includes filters whose Q factor cannot be used.

The invention exhibits additional advantages. For example, the filtering center frequency fc of the UDF module 1102 can be electrically adjusted statically or dynamically.

At the same time, the UDF module 1102 can be implemented without a large resistance, capacitor, or inductance. At the same time, the UDF module 1102 does not require high margins to maintain individual components, that is, its resistance, capacitance, inductance, etc. Therefore, the structure of the UDF module 1102 can integrate circuit design techniques and procedures in a friendly manner.

Based on the discussion herein, those familiar with this technology can fully understand these and other advantages of the UDF module 1102 of the present invention.

The advantages of the UDF module 1102 can be better understood by comparing the conventional receiver 112 (FIGS. 1 and 3). The frequency selection operations 302, 308 (that is, the band selection filter 102 and the channel selection filter 108) are different from the elements that perform 0306 (that is, the mixer 106).

At least part of the features and advantages exhibited by the UDF module 1102 are achieved by using new technology examples of frequency selection and conversion. Specifically, according to the present invention, the band selection filter 102 performs a frequency selection operation and a frequency conversion operation in a single, integrated operation. Conceptually as shown in FIG. 12, the display selection operation 1202 combines or integrates the frequency conversion operation 1204. At the same time, in FIG. 11, the simulated input filter 1106 and the frequency converter 1108 are indicated by dotted lines.

Referring to FIG. 13, as described above, the UDF module 1102 preferably performs frequency conversion 1204 prior to frequency selection 1202 (in another embodiment, the reverse is also possible). The overlap area 1302 described in FIG. 13 indicates that operations related to frequency conversion 1204 are provided at the same time to perform frequency selection 1202, and vice versa.

3.2 High-level description

This section provides a high-level description of integrating down conversion and filtering (UDF) according to the present invention. In fact, the operating procedures that integrate down-conversion and filtering are described at a high level. At the same time, the implementation of the structure to achieve this procedure is also described at a high level. The execution of the structure described here is for illustration only and will not be restricted. In particular, the procedures described in this section can be implemented using any number of structures, some of which are described in this section. According to the guidance in the text, people who are familiar with this technology can better understand the details of structure implementation.

3.2.1 Operation instructions

According to an embodiment of the present invention, the UDF module uses input signal sampling/request and output signal sampling/request to generate an output signal from the input signal. This operation is represented by step 1406 of flowchart 1402 (Figure 14). With this method of operation, the UDF module preferably performs input filtering and frequency down conversion in an integrated manner.

For illustration, the operation of the present invention is usually represented by a flowchart, such as the flowchart 1402 in FIG. 14. However, it can be understood that the flowchart is for illustrative purposes only and will not be restricted. For example, the present invention is not limited to the operation embodiment shown in the flowchart. On the contrary, according to the content discussed in the text, a person familiar with the technology can understand different embodiments. At the same time, the use of flowcharts should not be interpreted as meaning that the present invention is only limited to discrete or digital operations. In fact, based on the content discussed in the article, those skilled in the art can understand that the present invention can be achieved through discrete or continuous operations, or a combination of both. However, the control flow shown in the flowchart is for illustration only. As those skilled in the art can understand, other operation control procedures are included in the scope and spirit of the present invention. In addition, the commands of each step are different in different embodiments.

Referring to the flowchart 1602 of FIG. 16, the operation according to the embodiment of the present invention can be described in more detail.

In step 1606, the input signal is sampled. This input sample contains the information (such as amplitude, phase, etc.) contained in the input signal that appears during the sampling time.

As further described as follows, the result of repeating step 1606 converts the frequency of the input signal into a required lower frequency, such as an intermediate frequency (IF) or a fundamental frequency.

In step 1608, the input samples are kept (i.e., delayed).

In step 1610, one or more delayed input samples (some of which have been scaled), such as the delayed input samples of step 1608, are combined with one or more output signal (some of which have been scaled) delayed requests to generate The current request for the output signal.

Thus, according to the embodiment of the present invention, the output signal is generated before the input signal and/or the output signal is sampled/requested. (It is worth noting that in some embodiments according to the present invention, the current sampling/request of the input signal and/or output signal can be used to generate the current request of the output signal.)

As noted above, the operation of the present invention supports a variety of filter types, including band pass, low pass, high pass, concave, all pass, etc., and combinations of these types.

3.2.2 Structure description

FIG. 17 shows a UDF module 1702 according to an embodiment of the invention. The UDF module 1702 includes a part widely corresponding to the frequency converter 1108 (FIG. 11). The UDF module 1702 includes other parts, which widely correspond to the simulation input filter 1106. It should be noted that a part of the UDF module 1702 corresponding to the frequency converter 1108 also forms a part of the simulation input filter 1106. Regarding the present invention, it is further emphasized here that the frequency selection operation 1202 and the frequency conversion operation 1204 are performed in an integrated and single operation.

Note that the UDF module 1702 includes a zoom element 1790. These components are not necessary and are used to amplify the signal. The zoom element 1709 will be described in the next section. The elements discussed in the present invention do not consider the zoom element 1709.

The operation procedure of the UDF module 1702 will be described below with reference to the flowchart 1602 of FIG. 16.

In step 1606, the down conversion and delay module 1708 samples the input signal 1704. The execution of this sampling operation is consistent with the control signal 1734A. When step 1606 is repeatedly executed, the down conversion and delay module 1708 converts the input signal 1704 into a required low frequency signal, such as IF or baseband.

Therefore, the down-conversion and delay module 1708 down-converts the input signal 1704 to the required lower frequency.

In step 1608, the down conversion and delay module 1708 maintains (delays) the input samples. The delay operation of the down conversion and delay module 1708 provides the efficiency of the frequency selection operation 1202.

In step 1610, the down conversion and delay module 1708 is operated to combine one or more delayed input samples (some of which have been scaled) to generate the current request of the output signal 1706. In detail, the delay modules 1710A and 1710B delay the input signal 1704 sampled by the down-conversion and delay module 1708 (although, the two delay modules 1710A and 1710B are shown in the example of FIG. 17, the present invention is not affected by this embodiment. limit). The scaling modules 1716A, 1716B, 1716C, etc., from the down-conversion and delay module 1708 and the delay modules 1710A, 1710B, etc., scale the delayed input samples.

Delay modules 1722A, 1722B, 1722C, etc., delay the event of the input signal 1706 (note that the output signal 1706 appears at the nodes 1712 and 1718 at the same time). (Although the example in FIG. 17 shows three delay modules 1722A-1722C, the present invention is not limited by this embodiment) The zoom modules 1724A, 1724B, 1724C, etc. scale the output signal 1706 from the delay modules 1722A, 1722B, 1722C, etc. event.

The adder 1720 combines the delay of the output signal 1706 with the scaled input samples and the delay and scaled events to generate the event of the output signal 1706.

As noted above, different UDF module embodiments use different numbers and/or planned delay modules 1710 and 1722, and different numbers and/or planned delay modules 1716 and 1724. At the same time, the operations of the delay modules 1710 and 1722 and the zoom modules 1716 and 1724 will vary with different embodiments of the UDF module. For example, the delay introduction amount of each delay module 1710, 1722 will vary with different embodiments of the UDF module. At the same time, the scaling factors of the scaling modules 1716 and 1724 will vary with different embodiments of the UDF module. (Usually, the scaling factor of each scaling module 1716, 1724 can be any real number). For example, without limitation, in some embodiments, the zoom factor of one or more zoom modules may be zero. Therefore, it can be understood that the UDF module embodiments shown and discussed here are for illustrative purposes only. Based on the content discussed in this article, those familiar with the technology can fully understand the UDF module embodiments that are slightly or quite different from those discussed in this article.

3.3 Example

This section (and this subsection) describes the methods and structures related to the various embodiments described above. The embodiments described here are for illustrative purposes only and will not be limited. The present invention is not limited by these examples. According to the guidance in the text, those who are familiar with the technology can understand other various embodiments (including equivalents, extensions, changes, differences, etc.) of the embodiments described here. The present invention intends and appropriately includes these alternative implementations. example.

3.3.1 The first embodiment: band-pass filtering and frequency conversion

In the next section, the case where the embodiment of the present invention performs band-pass filtering and frequency conversion is described.

3.3.1.1 Operation description

The conversion equation of the band-pass filter is shown in Equation 3, which has been discussed above and is listed below again for convenience. As pointed out above, Equation 3 described here is for illustrative purposes only and does not limit the scope of the present invention.

Equation 3

As shown in Equation 3, the output signal VO is formed by adding the scaling delay value of the input signal VI and the scaling delay value of the output signal VO. In detail, at any given time t, the value of the output signal VO is equal to the scaled value of the input signal VI at time t-1, minus the scaled value of the output signal VO at time t-1, minus time t-2 The zoom value of the output signal VO at the time.

It is worth noting that Equation 3 provides the conversion equation for the band-pass filtered input signal VI. Equation 3 has nothing to do with the frequency of the Convert Input Signal VI. That is, Equation 3 has nothing to do with the down-conversion input signal VI. However, according to Equation 3, the present invention allows frequency conversion to be performed approximately simultaneously with band-pass filtering. This operation of the present invention is described with reference to the flowchart 1802 in FIG. 18.

In step 1806, at time t-1, the input signal VI is sampled. According to the present invention and the further description below, the input signal during the sampling period causes the input signal VI to be converted to a desired lower frequency (such as IF or baseband), so that the input sample becomes an event in which the input signal VI down-converts the image. As described below, this input sample is used for frequency selection operations. This further points out the integrated operation of the present invention.

In step 1808, at time t, the input samples held in step 1806 are released and scaled. The scaling value can be any real number, including 0.

In steps 1810 and 1812, at time t, the output signal VO event previously captured at time t-1 and held until this time is released and zoomed. The scaling value can be any real number, including 0.

In steps 1814 and 1816, at time t, the output signal event previously captured at time t-2 and held until this time is released and zoomed. The scaling value can be any real number, including 0.

In step 1818, at time t, combine the input signal VI_t-1Zoom and delay samples and output signal VO_t-1And VO_t-2Zoom and delay events to generate the current output signal event VO_t。

3.3.1.2 Structure description

FIG. 19 is a block diagram of a UDF module 1950 according to an embodiment of the present invention. A part of the UDF module 1950 corresponds to the frequency converter 1108 (FIG. 11), and a part corresponds to the input filter 1106. It is worth noting that the part corresponding to the frequency converter 1108, that is, the down conversion and delay module 1908, also forms a part of the input filter 1106. This points out the preferred part of the present invention, in which the frequency selection operation 1202 and the frequency conversion operation 1208 are performed in an integrated single operation.

Fig. 19 UDF module 1950 executes the operation steps of flowchart 1802 (Fig. 18). However, it can be understood that the scope and spirit of the present invention includes other structural embodiments that perform the steps of the flowchart 1802. For those who are familiar with this technology, according to the content discussed in this article, the characteristics of other structural embodiments will be more clear.

Please refer to the flowchart 1802 of FIG. 18 to describe the operation of the UDF module 1950 in detail. Referring to FIG. 20 at the same time, the table 2002 indicates example values of nodes in the UDF module 1950 under continuous time increments.

In step 1806, at time t-1, the down-conversion and delay module 1908 down-samples the input signal VI. Input sample to VI_t-1Express. As noted above, when step 1806 is performed, the down conversion and delay module 1908 converts the frequency of the input signal VI into the required low frequency, such as IF or baseband. Therefore, the input sampling VI_t-1Indicates the down conversion event of the Input Signal VI. Hereinafter, the down conversion and delay module 1908 is further described.

At the same time, in step 1806, the down conversion and delay module 1908 preferably keep the input sampling VI within 1 time unit_t-1. See unit 2004 of table 2002. As seen in Equation 3, the above-mentioned band-pass filter conversion equation requires an input sample and hold 1 time unit. Therefore, when performing this part of step 1806, the down conversion and delay module 1908 is performing a part of the frequency selection operation. Therefore, it should be clearly understood from the above description that the down conversion and delay mode resistance 1908 contribute to the frequency conversion operation 1204 and the frequency selection operation 1202 at the same time.

In step 1808, at time t, the down conversion and delay module 1908 releases the input samples held in a single time unit (that is, VI_t-1), and scaled by the input scaling module 1909. Therefore, the signal represented at node 1902 (see unit 2006 in table 2002): α₁. VI_t-1。

Previously, at time t-1, the first delay module 1912 captured the event of the output signal VO. The event of this output signal VO is VO_t-1Express. In step 1810, at time t, the first delay module 1912 releases the output signal VO_t-1event. In step 1812, the output signal VO_t-1The event is scaled by the first scaling module 1916. After operating the first zoom module 1916, the value appearing at node 1904 (see cell 2012 in table 2002): -β₁. VO_t-1。

Previously, at time t-1, the second delay module 1914 captured the event of the output signal VO stored in the first delay module 1912 (it is worth noting that the first delay module 1912 samples the output signal VO in order to This event is obtained at t-2). The event of this output signal VO is VO_t-2Express. At time t, the second delay module 1914 releases the output signal VO_t-2event.

In step 1816, the second scaling module scales the output signal VO_t-2event. After operating the second zoom module 1918, the value generated at node 1906 is as follows (see unit 2016 in table 2002): -β₀. VO_t-2。

In step 1816, the totalizer 1910 adds the values of nodes 1902, 1904, and 1906. The sum indicates the current event of the output signal VO. This output signal event is VO_tRepresents and is equal to the following value (see area 2008 in table 2002): α₁. VI_t-1-β₁. VO_t-1-β₀. VO_t-2。

3.3.2 The second embodiment: low-pass filtering and frequency description

In the example of the present invention, the execution of low-pass filtering and frequency conversion will be described in the next section.

3.3.2.1 Operation description

Equation 6 represents the conversion equation of the low-pass filter. Equation 6 introduced earlier is reproduced as follows for convenience. As mentioned above, Equation 6 provided in this article is for reference only, and is not limited.

<img file="TW441164B_D0010.tif" />

As shown in Equation 6, the input signal VI scaling event delayed by 2 time units is added to the output signal VI scaling event delayed by 1 and 2 time units respectively to achieve a low-pass filtering operation.

It is worth noting that the low-pass conversion equation of Equation 6 has nothing to do with the frequency conversion operation 1204. However, the present invention allows frequency conversion to be performed approximately simultaneously with low-pass filtering according to Equation 6. This operation of the present invention will be described with reference to the flowchart 2202 of FIG. 22.

In step 2206, at time t-2, the input signal VI is sampled. Enter samples to VI_t-2Express. According to the present invention and the following further description, the sampling value of the input signal converts the frequency of the input signal VI into an ideal lower frequency (such as IF or baseband), so that the input sample becomes an event of the image down conversion of the input signal VI. It is better to keep the input sample for 2 time periods.

At the same time in step 2206, enter the sample VI_t-2Keep for 2 time units. It can be proved from Equation 6 that in order to achieve the low-pass filtering operation, the input signal VI event must be maintained for 2 time units. Therefore, step 2206 forms part of the frequency selection operation 1202. Therefore, when step 2206 is performed, one aspect of the present invention performs a frequency selection operation 1202. Therefore, the down conversion and delay module 2308 contributes to the frequency conversion operation and the frequency selection operation at the same time.

In step 2208, at time t, release the input signal VI that has been maintained for 2 time units_t-2. In step 2210, scale the input signal VI_t-2。

In steps 2212 and 2214, at time t, release and zoom the output signal VO that has been maintained for 1 time unit_t-1。

In steps 2216 and 2218, at time t, release and zoom the output signal VO that has been maintained for 2 time units_t-2。

In step 2220, at time t, combine the scaled input sample VI_t-2And the scaled output signal VO_t-1And VO_t-2Event to generate the current output signal VO_t-2event.

3.3.2.2 Structure description

FIG. 23 is a block diagram of a UDF module 2302 according to an embodiment of the present invention. The UDF module 2302 includes a part corresponding to the frequency converter 1108 and a part corresponding to the input filter 1106. It is worth noting that the part of the UDF module corresponding to the frequency converter 1108 also forms the part of the simulated input filter 1106.

The UDF module 2302 is a structural embodiment for executing the operation steps of the flowchart 2202. However, it should be understood that the scope and spirit of the present invention include other structural embodiments for executing the steps of the flowchart 2202. According to the discussion here, people familiar with related technologies should be able to clearly understand the characteristics of other structural embodiments.

Now, the operation of the UDF module 2302 will be described with reference to the flowchart 2202 of FIG. 22.

At time t-2, the down conversion and delay module 2308 samples the input signal VI. This input sample is based on VI_t-2Express. According to the control signal 2324A, the down conversion and delay module 2308 samples the input signal VI and obtains the input sample VI_t-2. As described further below, the down-conversion and delay module 2308 performs sampling by converting the input signal VI frequency into an ideal lower frequency such as IF or baseband.

Therefore, enter the sample VI_t-2Indicates the event that the Input Signal VI down-converts the image.

At the same time in step 2206, the down conversion and delay module 2308 will input the sample VI_t-2Keep for 1 time unit. At time t-1, enter the sample VI_t-1It is captured by the delay module 2310 and kept for an extra time unit. It can be proved by the low-pass filter conversion equation of Equation 6, that in order to perform the low-pass filter operation, the input signal VI must be maintained or delayed by 2 time units. As just mentioned, the delay operation is performed by the down conversion and delay module 2308 and the delay module 2310 together. Therefore, when step 2206 is performed, the down-conversion and delay module 2308 provides the frequency selection operation 1202 and the frequency conversion operation 1204 to perform actions.

In step 2208, at time t, use the delay module 2310 to release the input sample VI that has been held/delayed for 2 time units_t-2。

In step 2210, at time t, enter the sample VI_t-2The zoom module 2312 is used for zooming.

Previously at time t-1, the delay module 2316 captured the event of the output signal VO. The event of this output signal VO is VO_t-1Express. In step 2212, at time t, the delay module 2316 is used to release the output signal VO_t-1event.

In step 2214, at time t, output signal VO_t-1The event is scaled by the scaling module 2320.

Previously at time t-1, the delay module 2318 captured the output signal VO event stored in the delay module 2316. The event of this output signal VO is VO_t-2Express. In step 2212, at time t, the delay module 2318 is used to release the output signal VO_t-2event.

In step 2218, at time t, output signal VO_t-2The event is scaled by the scaling module 2322.

In step 2220, at time t, combine the scaled input sample VI_t-2And the scaled output signal VO_t-1And VO_t-2Event to generate the current output signal VO event.

3.3.3 The third embodiment: low-pass filtering and frequency description

The embodiments of the UDF module described above are for illustrative purposes only. The present invention is not limited by this embodiment.

For example, a person familiar with related technologies should be able to use a variety of different conversion equations to obtain a given set of filter characteristics. The elements of this conversion equation can be arranged and planned to meet specific goals and/or needs.

In a similar way, there can be many different UDF modules. In these embodiments, the contained elements are appropriately selected and arranged to meet specific purposes and/or requirements.

For example, and not limited to this, a UDF module 4402 containing the operation map described in FIG. 44 can be constructed. This operating characteristic is like introducing filtering in combination with the midpoint of frequency conversion. This embodiment will be described in subsequent sections.

It is worth noting that the midpoint insertion embodiment shows that the present invention has great flexibility. In particular, the UDF module embodiment according to the present invention can be constructed using a variety of components and component plans. According to the guidance in this article, people familiar with related technologies should be able to understand other UDF module embodiments.

3.3.3.1 Operation description

Equation 3 discussed earlier represents the conversion equation of the band-pass filter. For convenience, Equation 3 is restated as follows. As pointed out earlier, Equation 3 described in this article is for illustrative purposes only and is not limited by this.

<img file="TW441164B_D0011.tif" />

Therefore, in step 2406, the frequency conversion operation 4410 and the frequency selection operation 4408 are performed in a single and integrated manner.

In steps 2408 and 2410, at time t, the input signal VI that has been maintained for 1 time unit_HFt-1High-frequency events are released and selectively filtered and zoomed. Preferably, the filtering done at this point is related to the wide filter bandwidth (for example, wideband filtering as opposed to narrowband filtering).

In steps 2416 and 2414, at time t, release and zoom the output sample VO from step 2406 that has been maintained for 1 time unit_t-1。

In steps 2416 and 2418, at time t, the output signal VO event that has been maintained for 2 time units is released and scaled. Output signal VO event to VO_t-2Express.

In step 2420, at time t, the scaled VO_t-1And zoomed VO_t-2Add up. It is worth noting that VO_t-1And VO_t-2The frequency of is lower than the frequency of the input signal 2504. This is due to VO_t-1Obtained from the sampling operation related to frequency down conversion (described in step 2406), and VO_t-2From VO_t-1Obtained.

At the same time, in step 2420, the zoomed VO_t-1With zoomed VO_t-2The sum is up-converted to approximately the same frequency as the input signal VI.

In step 2422, at time t, the high-frequency output signal VO_HFtThe current event is down-converted to the required low frequency, such as IF or baseband. This result is the low frequency output signal VO_LFtEvent, where LF means "low frequency".

3.3.3.2 Structure description

FIG. 25 is a block diagram of a UDF module 2502 according to an embodiment of the present invention. The UDF module 2502 includes a part corresponding to the frequency converter 1108 and a part corresponding to the input filter 1106. It is worth noting that the part of the UDF module 2502 corresponding to the frequency converter 1108 is also a part of the part of the UDF module corresponding to the input filter 1106.

The UDF module 2502 is a structural embodiment for executing the operation steps of the flowchart 2402. However, it should be understood that the scope and spirit of the present invention include other structural embodiments for executing the steps of the flowchart 2402. According to the discussion in the text, those who are familiar with related technologies will be able to fully understand the characteristics of other embodiments.

The operation of the UDF module 2502 will be described in detail with reference to the flowchart 2402 of FIG. 24.

In step 2405, the high-frequency delay module 2506 captures the event of the input signal VI before time t-1. For example, at time t-1, the high-frequency delay module 2506 captures the event of the input signal VI. This input signal VI event is based on the VI_HFt-1Express.

In step 2406, at time t-1, the down-conversion delay module 2514 samples the input signal VO_HFRepresents the high frequency. High frequency output signal VO_HFThe frequency of is roughly equal to the frequency of the input signal VI. As described further below, the down-conversion and delay module 2514 passes the high-frequency output signal VO_HFThe method of frequency conversion to the required low frequency sample the high frequency output signal VO_HF。

At the same time in step 2406, the down-conversion and delay module 2514 keeps output sampling VO_t-1。

In step 2408, at time t, release the input signal VI captured by the high-frequency delay module 2506 at time t-1_HFt-1event.

In step 2410, at time t, input signal VI_HFt-1The event is selectively filtered by the filter 2508 and scaled by the scaling module 2510.

In step 2412, at time t, the down conversion and delay module 2514 releases the output sample VO from step 2406_t-1。

In step 2414, at time t, the scaling module 2518 scales the output sample VO_t-1。

Previously at time t-1, the low-frequency delay module 2516 captured the output samples VO stored in the down-conversion and delay module 2514_t-2event. In step 2416, at time t, output signal VO_t-2The event is released by the low-frequency delay module 2516.

In step 2418, at time t, output signal VO_t-2The event is scaled by the scaling module 2520.

In step 2420, at time t, the adder 2522 converts the scaled output signal VO_t-1Sample and scaled output signal VO_t-2The total of events. Recalling the foregoing, VO_t-1And VO_t-2The frequency of is lower than the frequency of the input signal 2504. This is due to VO_t-1Obtained from the sampling operation related to frequency down conversion (as described in step 2406), and VO_t-2From VO_t-1Obtain (as described in step 2416).

At the same time, in step 2420, use the up-conversion module 2524 to convert the scaled VO_t-1And VO after zooming_t-2The sum of is converted up to make the frequency roughly equal to the frequency of the input signal VI.

In step 2422, at time t, the input signal VI_HFt-1Zoom event and output signal VO_t-1Zoom sample and output signal VO_t-2Combined with zoom events. The result is a high-frequency output signal VO_HFtOf current events. Its worth noting that the high-frequency output signal VO_HFtThe frequency of the event is usually equal to the frequency of the input signal VI.

In step 2424, at time t, the down-conversion module 2526 outputs the high-frequency output signal VO_HFtThe current event is down-converted to the required low frequency, such as IF or baseband. This result produces a low-frequency output signal VO_LFtevent.

3.3.4 Fourth embodiment: finite impulse response (FIR) filtering

The above-mentioned filtering embodiment is characterized by a wireless impulse response (IIR) filter. Generally speaking, in an IIR filter, the output is a function of input and output.

There is also a finite impulse response (FIR) filter. Generally speaking, in FIR filters, the output is only a function of the input.

As described above, according to the embodiment of the present invention, the output signal is generated from the current and/or previous samples/events of the input signal and/or the output signal. Therefore, the present invention refers to IIR and FIR filters.

According to an embodiment of the present invention, this section discusses FIR filters in detail.

First, consider Equation 11 of Figure 54A. Equation 11 is a general filter transfer function. Contains a variety of filters, including linear phase filters, which can be represented by the example of Equation 11 and/or changes.

For example, the band-pass filter transfer function of the example of Equation 3 can be derived from Equation 11. This equation is shown in Equation 12-14 in FIG. 54A, where Equation 14 is equivalent to Equation 3.

The IIR filter conversion equation can be derived from Equation 11. In this display, equations 15 and 16 of Fig. 54B represent example IIR filter conversion equations.

Figure 55 illustrates an integrated down conversion and filtering (UDF) module 5502. The UDF module 5502 is an example FIR filter and corresponds to the example IIR filter conversion equation 16.

The UDF module 5502 includes a frequency converter 5508, of which the down conversion and delay module 5506 is preferred. The down conversion and delay module 5506 samples the input signal 5504. As discussed further below, the down conversion and delay module 5506 performs sampling operations by converting the input signal 5504 to a lower frequency such as IF or baseband (this sampling operation is performed according to the control signal 5522). Therefore, the down-conversion and delay module 5506 down-converts the input signal 5504 to the desired lower frequency. In some embodiments, the operation of the down conversion and delay module 5506 is sometimes referred to as "integration and conversion" because the present invention provides multiple advantages, such as enhancing energy conversion during frequency conversion operations. The following provides a more detailed description of the method for performing frequency down conversion of the present invention, and is further provided in U.S. U.S.A. S. Patent "Method and System for Down-Converting Electromagnetic Signals".

As the proof of the FIR filter conversion equation in Equation 17, in order to perform filtering, the input signal must be maintained or delayed in different time units. As just mentioned, the down conversion and delay module 5506 participates in this delay operation. Therefore, the down conversion and delay module 5506 is provided for the frequency selection operation 1202 and the frequency conversion operation 1204 at the same time. It is further demonstrated in FIG. 55 that the frequency converter 5508 (including the down conversion and delay module 5506) is part of the filter 5510.

The example UDF module 5502 also includes a delay module 5512, a zoom module 5514, 5516, and a totalizer 5518. According to the teaching provided in this article, people familiar with this technology can understand the operation of these elements.

The example UDF module 5502 includes two taps at the same time (the tap is used to branch between two points, in this example, it is used between the input signal and the totalizer 5518). Other FIR embodiments include more than two taps. For example, many FIR embodiments include at least 16 taps. Some FIR embodiments include more than 16 taps, such as 50 or 256 taps, etc., or more. Those who are familiar with this technology should understand according to the teaching provided in this article that the number of taps is determined by the conversion formula used, and the method is to execute the conversion formula.

FIR embodiments according to the present invention can be implemented using linear phase.

An example FIR conversion formula is shown in Equation 19 in Figure 54C. This conversion formula is for illustrative purposes only, not as a limitation. Also see Equation 18 in Figure 54C. The conversion equation represents a low-pass filter with the following characteristics: 3db 0.17 clock (control signal), at least 9db is rejected at 0.5 clock. Other characteristics are shown in Figure 62.

An example UDF module 6102 corresponding to the FIR conversion formula is shown in FIG. 61. UDF module 6102 is mapped to EQS. The FIR conversion formula of 18 and 19. Those familiar with this technology should understand the structure and operation of this UDF module according to the teaching provided in this article. It should be noted that the present invention is not limited by this implementation. Those skilled in the art should understand other conversion formulas based on the principles of the present invention based on the teaching provided herein, and the UDF module embodiments and execution examples are included in the scope and spirit of the present invention.

It is worth noting that EQ. The FIR conversion equation represented by 19 is provided for illustrative purposes only, and is not limited. Those familiar with this technology should be able to understand the design and structure of different conversion formulas to achieve other filtering functions and characteristics, and these different conversion formulas are included in the scope and spirit of the present invention. Those familiar with the technology should understand the conversion formula as a UDF module based on the teaching provided herein, and these UDF module embodiments and execution methods fall within the scope and spirit of the present invention.

3.3.5 Fifth embodiment: continuous average converter

In the embodiments discussed above, although the phases of these control signals are sometimes different, they still have the same frequency. In this embodiment, according to the circuit design and implementation requirements, all control signals must be at the same frequency position (although similar requirements can sometimes be met).

5618 is charged as a function of input signal 5612. In other words, during the CS1 pulse, the capacitor 5618 accumulates charge. The capacitor 5618 has enough capacity to hold the charge. With reference to the above, an example size of a capacitor that achieves this functionality is provided.

When the switch 5620 turns off the output module 5610 according to the pulse in CS2, the capacitor 5618 starts to discharge. Therefore, in the example of FIG. 57A, there are 4 CS1 pulses in each CS2 pulse. Before the output module 5610 switch 5620 starts to discharge, the charge is within 4 CS1 pulses (or equivalent to four samples of the switch 5616 The time it takes) to charge the capacitor 5618. Thus, since f1&gt;f2, the capacitor 5618 accumulates charge from several samples before discharging.

The accumulation of these charges averages the samples taken by the input signal 5612. This average job has many advantages. For example, without restrictions, the averaging operation can evenly amortize the noise to increase the signal-to-noise ratio. This advantage can optimize the CS1 pulse gap.

The averaging operation provided by the present invention also provides filtering effects. In other words, the UDF module 5602 filters the input signal 5612. Therefore, this embodiment of the present invention (shown as an example in FIG. 56) is sometimes referred to as "timely average filtering".

The output module 5614 establishes the filter cutoff frequency 5704 (for example, see FIG. 57B).

In an embodiment, the ratio of f1 to f2 is sufficient to allow the capacitor 5618 to be fully charged before the capacitor 5618 is discharged when the output module 5610 is switched off. When choosing the frequency of CS1 and CS2, as with other characteristics of CS1 and CS2 (such as pulse width or gap), and other components such as capacitor 5618 and resistor 5622, what is considered is the ideal charging capacity of capacitor 5618, and when switch 5620 is closed When the capacitor 5618 discharges ideally, and the time is the same.

3.3.6 The sixth embodiment: N-path filter

Another type of filter is called "n-path filter". The n-path filter includes n taps.

The present invention is described with respect to the n-path filter. Figure 58A illustrates an n-path filter (UDF module 5802) according to an embodiment of the invention.

According to the embodiment of the present invention, each tap preferably includes a frequency converter 5804, which includes a down conversion and delay module (DDM) 5806.

The down conversion and delay module 5806 samples the input signal 5814. In the following further description, the down-conversion and delay module 5806 performs sampling by converting the frequency of the input signal 5814 into a low frequency such as IF or baseband. The input sample represents the event that the input signal 5814 down-converts the image. Therefore, the down-conversion and delay module 5806 down-converts the input signal 5814 to the required low frequency. Since the present invention provides multiple advantages, such as enhanced energy conversion during frequency conversion operations, in some embodiments, the operation of the down conversion and delay module 5806 is sometimes referred to as "integration and conversion." The down-conversion method of the present invention is described in detail as follows, and is further provided in the US pending patent "Method and System for Down-Conversion Electromagnetic Signal", please refer to the above.

The down conversion and delay module 5806 also keeps (delays) the input samples for a period of time.

From the filter conversion formula discussed here, it can be proved that in order to perform filtering, the input signal 5814 must be maintained or delayed in different time units. As mentioned earlier, the down conversion and delay module 5608 participates in this delay operation. Therefore, the down conversion and delay module 5608 is provided to perform the frequency selection operation 1202 and the frequency conversion operation 1204. In fact, according to the teachings herein, when the frequency conversion operation 1204 is performed, the down conversion and delay module 5608 also performs at least a part of the frequency selection operation 1202, and vice versa. Therefore, according to the present invention, the frequency selection operation 1202 and the frequency conversion operation 1204 are performed in an integrated manner. It is further demonstrated in FIG. 58A that the frequency converter 5604 (including the down conversion and delay module 5608) is part of the filter 5812.

In the example of FIG. 58A, the down conversion and delay module 5608 is implemented using switches and capacitors. The present invention provides descriptions for other down-conversion and delay module 5608 embodiments. These other embodiments are described here, and are further provided in the US pending patent "Method and System for Down-Converting Electromagnetic Signals".

In the embodiment of FIG. 58A, the control signal has the same frequency and different non-overlapping phases (alternatively, the control signal can be regarded as a single control signal with multiple non-overlapping phases). In Fig. 58A, the control signals are represented by ψ1, ψ2,..., ψn. Examples of control signals (where n is equal to 3) are shown in Figures 59A-59C.

Since the control signal has non-overlapping phases, the switches in the down conversion and delay module 5806 are closed at different times. In other words, the down conversion and delay module 5806 samples the input signal 5814 at different times. In this way, the sampling of the input signal 5814 can be regarded as a rotary tap through the down conversion and delay module 5806.

When the corresponding control signal is pulsed, the down-conversion and delay module 5806 samples and maintains the sampled value (that is, the delayed sampled value). Therefore, the down conversion and delay module 5806 delays the respective samples. Since the control signal has a non-overlapping delay, the delay introduced by the down-conversion and delay module 5806A at any time is different from the delay introduced by the other down-conversion and delay modules 5806B and 5806C. In addition, for the same reason, the delay introduced by the directional down conversion and delay module 5806 is different at different times.

Therefore, the taps corresponding to the filter conversion formula factors change over time. For example, suppose that the filter conversion formula performed by UDF 5802 in Figure 58A includes a z-2 factor. At time tn, this factor can be provided by down-conversion and delay module 5806A; at time tn+1, this factor can be provided by down-conversion and delay module 5806B; at time tn+2, this factor can be provided by down The conversion and delay module 5806C is provided; at time tn+3, this factor can be provided by the down conversion and delay module 5806A; and so on. Therefore, we can say that the delay factor is determined by the rotary tap.

The UDF module 5802 of FIG. 58A includes an additional switch 5801. In some embodiments, these switches can be regarded as part of DDMs 5806 or external to DDMs 5806. These switches 5801 prevent signal leakage. These switches are activated by non-overlapping phase clock signals. Generally, although other phase relationships are possible in the present invention, the clock of a given switch 5801 is delayed by 1 phase relative to the switches in the DDM 5806. At any time, the output signal 5816 is only combined with one DDM 5806 through the operation of the switch 5801.

According to the present invention, the n-path filter can be an IIR filter or an FIR filter. An example of an FIR filter according to the present invention is shown in Fig. 58A. The IIR filter according to the present invention is shown in Fig. 58B.

3.3.7 Seventh Embodiment: Passive Filter

The present invention is described with respect to passive filters. Generally speaking, passive filters do not include any amplifiers such as buffer amplifiers.

FIG. 60 shows an example of a passive filter (UDF module 6002) according to an embodiment of the present invention. However, the present invention is not limited by this example. The example in FIG. 60 shows an IIR filter. The UDF module 6002 includes a frequency converter 6008, which preferably includes a down conversion and delay module (DDM) 6010.

The down conversion and delay module 6010 samples the input signal 6006. As further described below, the down conversion and delay module 6010 performs sampling by converting the frequency of the input signal 6006 into a low frequency such as IF or baseband. The input sample represents the event that the input signal 6006 down-converts the image. Therefore, the down-conversion and delay module 6010 down-converts the input signal 6006 into the required low frequency. Since the present invention provides multiple advantages, such as enhanced energy conversion during frequency conversion operations, in some embodiments, the operation of the down conversion and delay module 6010 is sometimes referred to as "integration and conversion." The method of performing frequency down conversion of the present invention is described in detail as follows, and is further provided in the US pending patent "Method and System for Down Conversion of Electromagnetic Signals", please refer to the above.

The down conversion and delay module 6010 also keeps (delays) the input samples for a period of time.

From the filter conversion formula discussed here, it can be proved that in order to perform filtering, the input signal 6006 must be maintained or delayed in different time units. As just mentioned, the down conversion and delay module 6010 participates in this delay operation. Therefore, the down conversion and delay module 6010 is provided to perform the frequency selection operation 1202 and the frequency conversion operation 1204. In fact, it can be clearly understood from the teachings herein that when the frequency conversion operation 1204 is performed, the down conversion and delay module 6010 also performs at least a part of the frequency selection operation 1202, and vice versa. Therefore, according to the present invention, the frequency selection operation 1202 and the frequency conversion operation 1204 are performed in an integrated manner. It is further demonstrated in FIG. 60 that the frequency converter 6008 (including the down-conversion and delay module 6010) is shown as part of the filter 6004.

In the example of FIG. 60, the down conversion and delay module 6010 is implemented using switches and capacitors. The present invention provides descriptions for other down-conversion and delay module 6010 embodiments. These other embodiments are described here, and are further provided in the US pending patent "Method and System for Down-Converting Electromagnetic Signals", as other applications are referred to above.

Although the present invention is not limited by this embodiment, the example of FIG. 60 includes three additional delay modules 6012, 6014, and 6016. Different embodiments may include more or less than three additional delay modules. We should be able to understand that the number of delay modules is determined according to the desired filter characteristics, the conversion formula used, and its implementation method.

It is worth noting that the control signals used by the UDF module 6002 preferably have the same frequency and non-overlapping phases. Non-overlapping pulses can prevent signal leakage.

Although not shown in FIG. 60, the sampled value and the delayed sampled value can be weighted (in the embodiment, the weight can be changed statically or dynamically), thus allowing different types of filters and filtering characteristics to be achieved, and the effect of amplification can be achieved.

3.3.8 Other embodiments

The embodiments described above are for illustrative purposes only. These examples do not limit the invention. Based on the teachings herein, those familiar with the technology should be able to understand alternative embodiments that are slightly or fundamentally different from those described herein. For example, a similar embodiment is shown in Figure 63. This alternative embodiment also includes the UDF module embodiment. The UDF module embodiments proposed here include the above-mentioned undiscussed filtering types, such as high-pass filtering, concave filtering, and so on. These alternative embodiments are included in the scope and spirit of the present invention.

3.4 Execution example

This section presents example operations and/or structural implementations of the above-mentioned methods, structures, and/or embodiments. The implementation presented here is for illustration only and is not limited to this. The invention is not limited to the specific embodiments described herein. According to the teaching in this article, those familiar with the technology should be able to understand the alternative implementation methods (including equivalents, extensions, changes, etc.). These alternative implementation methods all fall within the scope and spirit of the present invention.

3.4.1 Implementation example of integrated down conversion and filtering (UDF) module

Figure 26 shows the integrated down conversion and filtering (UDF) module 2622. The UDF module 2622 performs the frequency conversion operation 1204 and the frequency selection operation 1202 in an integrated manner. The integration method is as described above, and is further described as follows.

In the example of FIG. 26, the frequency selection operation 1202 performed by the UDF module 2622 includes a band-pass filter conversion operation. As noted above, EQ.3 is an example of a band-pass filter conversion formula. For convenience, EQ.3 is listed below. As mentioned above, the EQ.3 described here is for illustrative purposes only and does not set limits.

<img file="TW441164B_D0012.tif" />

In the example of FIG. 26, the UDF module 2622 performs band-pass filtering according to the band-pass filter conversion formula example EQ.3.

UDF module 2622 includes down conversion and delay module 2624, first and second delay modules 2628 and 2630, first and second zoom modules 2632 and 2634, and output sample and hold module 2636, and (can be Additional) Output smoothing module 2638. Other UDF module embodiments are composed of different plans for these components, and/or a subset of these components, and/or the addition of other components. For example, without limitation, in the plan shown in FIG. 26, the output smoothing module 2638 is determined as needed (not necessary). Those who are familiar with the techniques discussed in this article should be able to understand alternative embodiments of the UDF module.

In the embodiment of FIG. 26, as described below, the down-conversion and delay module 2624 and the first and second delay modules 2628 and 2630 include switches, which are composed of two phases ψ₁And ψ₂The clock is controlled. ψ₁And ψ₂It is best to have the same frequency and non-overlapping (in other words, several similar two-clock signals with these characteristics can be used). As used here, the term "non-overlapping" is defined as two or more signals, and only one signal is activated at any time. In some embodiments, the signal is activated at a high level. In other embodiments, the signal is activated in the low position. For example, see Figures 33A and 33B.

Usually, each switch is in ψ₁Or ψ₂Close at the rising edge, and at the next corresponding ψ₁Or ψ₂Open at the falling edge. However, the present invention is not limited to this example. As far as those familiar with related technologies can understand, other clock routines can be used to control the switch.

In the example of Figure 26, suppose that α₁Equal to 1. In this way, the output of the down conversion and delay module 2624 will not be scaled. However, it can be confirmed from the above embodiment that the present invention is not limited by this example.

Figure 27A shows the filtering characteristics of an example UDF module 2622. The example UDF module 2622 has a filter center frequency of 900.2MHz and a filter bandwidth of 570KHz. The passband of the UDF module 2622 is between 899.915MHz and 900.485MHz. The Q factor of the UDF module 2622 is approximately 1579 (that is, 900.2 MHz divided by 570 KHz).

In the example where the input signal VI frequency is 900.2MHz and the control or sampling signal is 16MHz, sample waveforms appearing at nodes in UDF module 2622 are shown in Figure 28A-28E. Figure 28F shows the VI corresponding to the example of Figure 28A-28E . Figures 28A-28F show an in-band example, because the frequency of the input signal VI falls within the passband range of the UDF module 2622. In this way, as predicted by the frequency response of FIG. 27B, the UDF module 2622 amplifies the input signal by a factor close to 5.

In the example where the input signal VI frequency is 897MHz and the control or sampling signal is 16MHz, other series of sample waveforms appearing in UDF module 2622 are shown in Figure 29A-29E. Figure 29F shows the VI corresponding to the example in Figures 29A-29E. Figures 29A-29F show out-of-band examples because the frequency of the input signal VI (ie, 897MHz) does not fall within the passband range of the example UDF module 2622. Thus, as predicted by the frequency response of FIG. 27B, the UDF module 2622 attenuates the input signal by a factor of approximately 0.57.

Referring now to table 1502 (FIG. 15), it shows example values at nodes in UDF module 2622 under several consecutive time increments to describe the operation of UDF module 2622. Assume that in table 1502, UDF module 2622 starts operating at time t-1. As pointed out below, the UDF module 2622 reaches a stable state several time units after the start of the operation. Those familiar with related technologies should understand that for a given UDF module, the number of time units required to reach a stable state depends on the UDF module's planning.

At time t-1, at ψ₁On the rising edge, the switch 2650 in the down conversion and delay module 2624 is closed. This allows the capacitor 2652 to be charged to the input signal VI_t-1The current value of so that node 2602 is located in VI_t-1. This is shown in unit 1504 in FIG. 15. In fact, in combination with the down conversion and delay module 2624, the switch 2650 and the capacitor 2652, the frequency of the input signal VI can be converted into a lower frequency required such as IF or baseband. In this way, the value stored in the capacitor 2652 represents an event in which the input signal VI down-converts the image. The operation of the down conversion and delay module 2624 is further described below.

At the same time at time t-1, at ψ₁On the rising edge, turn off the switch 2658 in the first delay module 2628, so that the capacitor 2660 is charged to VO_t-1, So that node 2606 is located at VO_t-1. This is shown in unit 1506 of table 1502 (in practical terms, VO_t-1Unconfirmed at this point. However, for the sake of convenience, for the purpose of explanation, continue to use VO_t-1)。

At the same time at time t-1, at ψ₁At the rising edge, the switch 2666 in the second delay module 2630 is closed, and the capacitor 2668 is charged to the value stored in the capacitor 2664. However, at this time, the value of the capacitor 2664 is not defined, so the value of the capacitor 2668 is not defined. This is shown in cell 1510 of table 1502.

At time t-1, at ψ₂At the rising edge, the switch 2654 in the down conversion and delay module 2624 is closed, and the capacitor 2656 is charged to the level of the capacitor 2652. Therefore, the capacitor 2656 is charged to VI_t-1, So that node 2604 is located in VI_t-1. This is shown in cell 1510 of table 1502.

The UDF module 2622 can optionally include a capacitor 2652 and a 2656 joint gain module 2690A. The joint gain module 2690A operates with the current power supply to charge the capacitor 2656 from the capacitor 2652 without the charge flowing out. For the same reason, UDF module 2622 can include other joint gain modules 2690B-2690G. It should be understood that in many embodiments and applications of the present invention, these joint gain modules 2690B-2690G are only additional options. Those who are familiar with related technologies should be able to understand the structure and operation of the joint gain module 2690.

At time t-1, at ψ₂At the rising edge, the switch 2662 in the first delay module 2628 is closed, and the capacitor 2664 is charged to the level of the capacitor 2660. Therefore, the capacitor 2664 is charged to VO_t-1, So that node 2608 is located in VI_t-1. This is shown in cell 1514 of table 1502.

At time t-1, at ψ₂At the rising edge, the switch 2670 in the second delay module 2630 is closed, and the capacitor 2672 is charged to the value stored in the capacitor 2668. However, at this time, the value of the capacitor 2668 is undefined, so the value of the capacitor 2672 is undefined. This is shown in cell 1515 of table 1502.

At time t, at ψ₁On the rising edge, close the switch 2650 in the down conversion and delay module 2624, allowing the capacitor 2652 to charge to VI_t. Therefore, node 2602 is located in VI_t. This is shown in cell 1516 of table 1502.

At time t, at ψ₁On the rising edge, turn off the switch 2658 in the first delay module 2628, so that the capacitor 2660 is charged to VO_t. Therefore, node 2606 is located at VO_t. This is shown in cell 1520 of table 1502.

At time t, at ψ₁At the rising edge, the switch 2666 in the second delay module 2630 is closed, and the capacitor 2668 is charged to the level of the capacitor 2664. Therefore, the capacitor 2668 is charged to VO_t-1. Make node 2610 located in VO_t-1. This is shown in cell 1524 of table 1502.

At time t, at ψ₂At the rising edge, the switch 2654 in the down conversion and delay module 2624 is closed, and the capacitor 2656 is charged to the level of the capacitor 2652. Therefore, the capacitor 2656 is charged to VI_t, So that node 2604 is located in VI_t. This is shown in cell 1528 of table 1502.

At time t, at ψ₂At the rising edge, the switch 2662 in the first delay module 2628 is closed, and the capacitor 2664 is charged to the level of the capacitor 2660. Therefore, the capacitor 2664 is charged to VO_t, So that node 2608 is located at VO_t. This is shown in cell 1532 of table 1502.

At time t, at ψ₂At the rising edge, the switch 2670 in the second delay module 2630 is closed, so that the capacitor 2672 in the second delay module 2630 is charged to the level of the capacitor 2668 in the second delay module 2630. Therefore, the capacitor 2672 is charged to VO_t-1, So that node 2612 is located at VO_t-1. This is shown in unit 1536 in FIG. 15.

At time t+1, at ψ₁On the rising edge, close the switch 2650 in the down conversion and delay module 2624, allowing the capacitor 2652 to charge to VI_t+1. Therefore, node 2602 is located in VI_t+1. This is shown in cell 1538 of table 1502.

At time t+1, at ψ₁On the rising edge, turn off the switch 2658 in the first delay module 2628, so that the capacitor 2660 is charged to VO_t+1. Therefore, node 2606 is located at VO_t+1. This is shown in cell 1542 of table 1502.

At time t+1, at ψ₁At the rising edge, the switch 2666 in the second delay module 2630 is closed, and the capacitor 2668 is charged to the level of the capacitor 2664. Therefore, the capacitor 2668 is charged to VO_t-1. Make node 2610 located in VO_t. This is shown in cell 1546 of table 1502.

In the example of FIG. 26, the first scaling module 2632 uses a scaling factor of -0.1 to scale the value at the node 2608 (that is, the output of the first delay module 2628). Therefore, at time t+1, the value of node 2614 is -0.1*VO_t. Similarly, the second scaling module 2634 uses a scaling factor of -0.8 to scale the value at the node 2612 (that is, the output of the second delay module 2630). Therefore, at time t+1, the value of node 2616 is -0.8*VO_t-1。

At time t+1, the input value of the totalizer 2626 is: node 2604 is VI_t, Node 2614 is -0.1*VO_t, Node 2616 is -0.8*VO_t-1(In the example of FIG. 26, the values of the nodes 2614 and 2616 are added by the second totalizer 2625, and the total value is presented on the totalizer 2626). Therefore, at time t+1, the signal generated by the totalizer is equal to VI_t-0.1*VO_t-0.8*VO_t-1。

At time t+1, at ψ₁On the rising edge, the switch 2691 in the output sample and hold module 2636 is closed, thus allowing the capacitor 2692 to charge to VO_t-1. Therefore, the capacitor 2692 is charged to VO_t-1, Equal to the sum produced by the adder 2626. As noted earlier, this value is equal to VI_t-0.1*VO_t-0.8*vO_t-1. This is shown in cell 1550 of table 1502. This value is provided to the output smoothing module 2638 to smooth the signal to generate the output signal VO_t+1event. After inspection, it can be clearly found that this VO_t+1The value conforms to the EQ.3 band-pass filter conversion formula.

3.4.2 UDF module component execution example

The following sections describe implementation examples of UDF modules according to embodiments of the present invention. The execution of this example is for illustrative purposes only and is not limited.

3.4.2.1 Down conversion and delay module

Referring to FIG. 17 for illustration only, the down conversion and delay module 1708 performs the frequency conversion operation. In an embodiment, the down-conversion and delay module 1708 samples the input signal VI so that the input samples form a down-conversion signal. In the example execution, the down-conversion signal represents the intermediate frequency (IF) of the input signal VI. In other embodiments, the down-conversion signal is a demodulated baseband signal. The present invention is not limited to these embodiments.

In addition to performing frequency conversion operations, the down conversion and delay module 1708 also delays output samples for frequency selection (filtering) operations. Therefore, the down conversion and delay module 1708 contributes to the frequency conversion operation and the frequency selection operation at the same time.

The following further describes the down conversion and delay modules.

3.4.2.1.1 Universal Frequency Down Conversion (UDF) Module for AC Current

In Figure 26, the down conversion and delay module 2624 is used as a representative to describe the example implementation of the down conversion and delay module, such as 1708 in Figure 17, 1908 in Figure 19, 2308 in Figure 23, and 2514 in Figure 25 . The down conversion and delay module 2624 preferably includes a switch 2650 and a capacitor 2652. The switch 2650 and the capacitor 2652 are operated to down-convert the input signal VI. This aspect of the invention will be described in this section. In particular, the following discussion uses frequency conversion (UFT) modules to illustrate.

FIG. 53 shows that the alias module 5300 (also referred to herein as the AC universal frequency down conversion module) uses the AC universal frequency conversion (UFT) module 5302 to perform down conversion to convert the EM input signal 5304. In a specific embodiment, the alias module 5300 includes a switch 5308 and a capacitor 5310. The electronic alignment of electronic components is flexible. That is, during operation, the switch 5308 is connected in series with the input signal 5304, and the capacitor 5310 is closed to the ground (although it is possible to implement a plan different from the ground, such as a differential module, etc.). In the second embodiment (see FIG. 53A-1), the capacitor 5310 is connected in series with the input signal 5304 and the switch 5308 is closed to the ground (although a different scheme from the ground, such as a differential module, can be implemented). The alias module 5300 with UFT module can be adapted to the wide variation of the alias frequency electromagnetic signal which is lower than the frequency of the EM input signal 5304.

In one embodiment, the alias module 5300 down-converts the input signal 5304 into an intermediate frequency (IF) signal. In another embodiment, the alias module 5300 down-converts the input signal 5304 into a demodulated baseband signal. In another embodiment, the input signal 5304 is a frequency amplitude modulation (FM) signal, and the alias module 5300 down-converts the input signal into a non-FM signal such as a phase amplitude modulation (PM) signal or an amplitude modulation (AM) signal . The above embodiments are described as follows.

In one embodiment, the control signal 5306 (which is the control signal ψ₁In an example, controlling the switch 2650 in FIG. 26 includes a series of pulses that are repeatedly executed at an alias rate equal to or less than twice the frequency of the input signal 5304. In this embodiment, since the frequency of the input signal 5304 is lower than the Nyquist rate, the control signal 5306 is regarded as an alias signal. Preferably, the frequency of the control signal 5306 must be lower than the input signal 5304.

In FIG. 53D, the series of pulses 5318 controls the switch 5308 to generate the down-conversion output signal 5312 with the alias input signal 5304 and the control signal 5306. More specifically in the embodiment, the switch 5308 is closed at the first edge of each pulse 5320 in FIG. 53D and opened at the second edge of each pulse. When the switch 5308 is closed, the output signal 5304 is combined with the capacitor 5310, and the charge is transferred from the input signal to the capacitor 5310. The stored charge during the continuous pulse forms the down-conversion output signal 5312.

Sample waveforms are shown in Figure 53B-53F.

FIG. 53B shows the analog amplifier module (AM) carrying the signal 5314, which is an example of the input signal 5304. For the sake of illustration, in FIG. 53C, the analog AM bearer signal part 5316 illustrates the part of the analog AM bearer signal 5314 at an increased time scale. Analog AM bearer signal part 5316 illustrates that from time t₀To t₁The AM bearer signal 5314.

FIG. 53D illustrates an example alias signal 5318, which is an example of the control signal 5306. The alias signal 5318 and the analog AM bearer signal portion 5316 have approximately the same time scale. In the example shown in FIG. 53D, the alias signal 5318 includes a series of pulses 5320 with negligible gaps approaching 0 (the present invention is not limited by this embodiment). Those familiar with the technology should be able to understand that the so-called pulse gap refers to the pulse width. The pulse 5320 is repeatedly generated at the alias rate, or the repeated rate of the pulse alias signal 5318. The following describes how to determine the alias rate.

As noted above, the continuous pulse 5320 (ie, the control signal 5306) controls the switch 5308 to alias the analog AM bearer signal 5316 (ie, the input signal 5304) at the alias rate of the alias signal 5318. In this embodiment, in particular, the switch 5308 is closed at the first edge of each pulse and opened at the second edge of each pulse. When the switch 5308 is closed, the input signal 5304 is connected to the capacitor 5310, and the charge is transferred from the input signal 5304 to the capacitor 5310. In this article, transferring charge during the pulse is the so-called "sampling". The example sample 5322 forms the down-conversion signal portion 5324 (FIG. 53E), which corresponds to the analog AM bearer signal portion 5316 (FIG. 53C) and the continuous pulse 5320 (FIG. 53D). The charge stored during the continuous sampling of the AM carrying signal 5314 forms the down-conversion signal 5324 (FIG. 53E), which is an example of the down-conversion output signal 5312 (FIG. 53A). In FIG. 53F, the demodulated baseband signal 5326 represents the demodulated baseband signal 5324 after filtering on a compressed time scale. As shown in the figure, the down-conversion signal 5326 and the AM carrying signal 5314 have approximately the same "amplitude profile". Therefore, Figures 53B-53F illustrate the down conversion of the AM bearer signal 5314.

For illustrative purposes, but without limitation, the waveforms shown in Figures 53B-53F are discussed here.

As noted above, the alias rate of the control signal 5306 determines whether the input signal 5304 is down-converted to an IF signal, or down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or AM signal. Generally speaking, the relationship between the input signal 5304, the alias rate of the control signal 5306, and the down-conversion output signal 5312 is explained as follows:

(Frequency of input signal 5304)=n(Frequency of control signal 5306) ±(Frequency of output signal 5312 down-converted)

In this example, it refers to the situation where "+" is discussed. The value of n represents the harmonic or half-harmonic of the input signal 5304 (that is, n=0.5, 1, 2, 3,...).

When the alias rate of the control signal 5306 is shifted from the frequency of the input signal 5304, or its harmonic or half-harmonic shift, the input signal 5304 is down-converted to the IF signal. This is because the pulses in the sample occur at different phases in the subsequent cycle of the input signal 5304. Therefore, sampling forms a low-frequency oscillation sample. If the input signal 5304 contains low-frequency changes such as amplitude, frequency, phase, etc., or any combination of the above, the stored charge during the sampling period responds to the low-frequency change, resulting in a change similar to that when down-converting the IF signal. For example, to down-convert a 901MHz input signal to a 1MhzIF signal, the frequency of the control signal 5306 can be calculated as follows:

<img file="TW441164B_D0013.tif" />

Where n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 5306 is roughly equal to 1.8GHz, 900MHz, 450MHz, 300MHz, 225MHz, etc.

Alternatively, when the alias rate of the control signal 5306 is approximately equal to the frequency of the input signal 5304, or approximately equal to its harmonic or half-harmonic, the input signal 5304 is directly down-converted to the demodulated baseband signal. Because there is no need to modify the modulation, the sampling pulse and the input signal 5304 then cycle roughly at the same position. Therefore, sampling forms a fixed output baseband signal. If the input signal 5304 contains low-frequency changes such as amplitude, frequency, phase, etc., or any combination of the above, the stored charge during the sampling period reacts to the low-frequency change, resulting in a change similar to the demodulation of the baseband signal. For example, to directly down-convert a 900MHz input signal to a demodulated baseband signal, the frequency of the control signal 5306 can be calculated as follows:

<img file="TW441164B_D0014.tif" />

Where n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 5306 can be roughly equal to 1.8GHz, 900MHz, 450MHz, 300MHz, 225MHz, etc.

Alternatively, to down-convert the input FM signal to a non-FM signal, the frequency within the FM bandwidth must be down-converted to baseband (ie, 0IF). For example, the frequency offset keyed in (FSK) signal (a subset of FM) is down-converted into a phase offset keyed (PSK) signal (a subset of PM), and the FSK signal has a low frequency F₁And high frequency F₂(That is, [(F₁+F₂)÷2]) is converted down to 0 IF. For example, set F₁Equal to 899MHz and F₂The FSK signal equal to 901MHz is down-converted to the PSK signal, and the alias rate of the control signal 5306 can be calculated as follows:

<img file="TW441164B_D0015.tif" />

Down-conversion signal frequency=0 (that is, baseband)

<img file="TW441164B_D0016.tif" />

Where n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 5306 can be roughly equal to 1.8GHz, 900MHz, 450MHz, 300MHz, 225MHz, etc. The frequency of the down-converted PSK signal is roughly equal to the low frequency F₁And high frequency F₂Half of the difference between.

In another embodiment, the FSK signal is down-converted to an amplitude shift keyed (ASK) signal (a subset of AM), which is not the low frequency F of the FSK signal₁Is high frequency F₂Convert down to 0 IF. For example, set F₁Equal to 899MHz and F₂The FSK signal equal to 901MHz is down-converted to the ASK signal, and the control signal 5306

<img file="TW441164B_D0017.tif" />

For the first case, where n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 5306 can be roughly equal to 1.8GHz, 900MHz, 450MHz, 300MHz, 225MHz, etc. For the second case, where n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 5306 can be roughly equal to 1.802 GHz, 901 MHz, 450.5 MHz, 300.333 MHz, 225.25 MHz, etc. The frequency of the down-converted AM signal is roughly equal to the low frequency F₁And high frequency F₂Half of the difference between (that is, 1MHz).

In an embodiment, the pulse of the control signal 5306 has a gap that is close to zero and can be ignored. Make UFT module 5302 a high input impedance device. When the input signal is expected to have the least interference, it is very useful to use this kind of planning.

In an embodiment, the pulse of the control signal 5306 has a non-negligible gap that deviates from zero. Make UFT module 5302 a low input impedance device. This allows the lower input impedance of the UFT module 5302 to roughly match the source impedance of the input signal 5304. At the same time, it can improve the energy conversion from the input signal 5304 down-conversion to the output signal 5312, thereby increasing the efficiency of the UTF module 5302 and the signal-to-noise (s/n) ratio.

When the pulse of the control signal 5306 has a non-negligible gap, the alias module 5300 refers to the energy conversion module or the gate conversion module, and the control signal 5306 refers to the energy conversion signal. The following describes an example system and method for generating and optimizing the control signal 5306 in the energy conversion module and other ways to improve the energy conversion and/or signal-to-noise ratio.

3.4.2.1.1.1 Additional energy conversion signal module

FIG. 66 shows an energy conversion system 6601, which includes an optional energy conversion signal module 6602, which can perform any function change or combination, including generating an energy conversion signal 6406.

In an embodiment, the optional energy conversion signal module 6602 includes a gap generator. FIG. 65C shows the gap generator 6520 as an example. The slot generator 6520 generates a non-negligible slot pulse 6526 from the input signal 6524. The input signal 6524 can be any type of periodic signal, such as sine, square wave, sawtooth wave, etc. The system that generates the input signal 6524 is described below.

The width of the pulse 6526 slot is determined by the branch 6522 of the delay slot generator 6520. Generally, as the desired pulse width increases, the difficulty of meeting the requirements of the slit generator 6520 decreases. In other words, for a given EM input frequency to generate non-negligible slit pulses, the components used in the exemplary slit generator 6520 do not require the rapid response required to operate the sampling system at the same EM input frequency.

The example logic and execution flow shown by the gap generator 6520 are for illustrative purposes only. What kind of logic is actually used? The example gap generator 6520 includes an optional inverter 6528, which is completely opposite to the other examples provided herein. FIG. 65D shows an example implementation of the gap generator 6520. Additional examples of slot execution logic are provided in Figures 65A and 65B. FIG. 65A shows a rising edge pulse generator 6540, which generates a pulse 6526 on the rising edge of the input signal 6524. FIG. 65B shows the falling edge pulse generator 6550, which generates pulses 6526 on the falling edge of the input signal 6524.

In an embodiment, as shown in FIG. 66, the input signal 6524 is generated outside the energy conversion signal module 6602. Alternatively, the input signal 6624 can be generated internally by the energy conversion signal module 6602. The input signal 6524 can be generated by an oscillator, such as the oscillator 6530 shown in FIG. 65E. The oscillator 6530 can be installed inside or outside the energy conversion signal module 6602. The oscillator 6530 may be provided outside the energy conversion system 6601. The output of the oscillator 6530 can be any form of waveform.

The type of down conversion performed by the energy conversion system 6601 depends on the alias rate of the energy conversion signal 6406, which is determined by the frequency of the pulse 6526. The frequency of the pulse 6526 is determined by the frequency of the input signal 6524. For example, when the frequency of the input signal 6524 is approximately equal to the harmonic or sub-harmonic of the EM signal 6404, the EM signal 6404 is directly down-converted to baseband (that is, when the EM signal is an AM signal or PM signal), or converted from FM To non-FM signal. When the frequency of the input signal 6524 is approximately equal to the harmonics or sub-harmonics of different frequencies, the EM signal 6404 is down-converted to the intermediate signal.

The optional energy signal module 6602 can be executed on hardware, software, firmware or a combination of these.

3.4.2.1.1.2 Smooth down conversion signal

Referring back to FIG. 53A, the down-converted output signal 5321 can be smoothed by filtering as needed.

3.4.2.1.1.3 Impedance matching

At the frequencies of interest (ie, EM input, and intermediate/baseband frequencies), the energy conversion module 5300 has input and output impedances roughly defined in (1) the regular cycle of the switch module (ie, UFT5302), and (2) The impedance of the storage module (ie, the capacitor 5310).

First, a preferred embodiment is that the slit width is close to 1/2 of the cycle of the down-converted EM signal, and the slit width (ie, the "off time") can be reduced. Once the gap width is reduced, the input and output characteristic impedance of the energy conversion module increases. Alternatively, once the gap width is increased from 1/2 of the period of the down-converted EM signal, the impedance of the energy conversion module decreases.

One of the steps to determine the characteristic input impedance of the energy conversion module is to measure its value. In an embodiment, the characteristic input impedance of the energy conversion module is 300 ohms. An impedance matching circuit can be used to effectively combine the input EM signal with source impedance, such as 50 ohms, and the impedance of the energy conversion module, such as 300 ohms. The action of impedance matching can be achieved in many different ways, including directly providing the necessary impedance or using impedance matching circuits, as described below.

Referring to Figure 67, a special embodiment using RF as the input signal, assuming that the impedance 6712 is quite low, for example, about 50 ohms, and the input impedance 6716 is about 300 ohms, the initial planning of the input impedance matching module 6706 includes an inductor 6906 and a capacitor 6908 , As planned in Figure 69. When moving from low impedance to high impedance, inductor 6906 and capacitor 6908 are feasible plans. The inductance 6906 and the capacitor 6908 form an L matching, and those who are familiar with related technologies should be familiar with the calculation methods of these values.

The output characteristic impedance can be impedance matched to consider the expected output frequency. One of the steps to determine the characteristic output impedance of the energy conversion module is to measure its value. Balance the extremely low impedance stored in the input EM frequency. The storage module should have an impedance at the desired output frequency, preferably greater than or equal to the load being driven (for example, in the embodiment, the storage module at the desired output frequency of 1MHz The impedance is 2K ohm and the ideal drive load is 50 ohms). The additional advantage of impedance matching is that the same components can be used to filter out unwanted signals.

In the embodiment, the characteristic output impedance of the energy conversion module is 2Kohms. The impedance matching circuit can effectively combine the down-conversion signal with, for example, 2K onms output impedance to 50 ohms output impedance. Impedance matching can be accomplished through different methods, including directly providing the necessary load impedance or using a matching circuit as described below.

When matching from high impedance to low impedance, the capacitor 6914 and the inductor 6916 can be planned as shown in FIG. 69. The capacitor 6914 and the inductance 6916 form an L matching, and those familiar with the technology should understand how to calculate the value of the component.

According to the present invention, the planning of the input impedance matching module 6706 and the output impedance matching module 6708 is regarded as the initial point of impedance matching. In some cases, the initial design can be used without further optimization. In other cases, the initial design can be further optimized according to different design limits and considerations.

Like other optional optimized structures and/or components used, the influence of their original limits on the characteristic impedance of the energy conversion module should be considered.

3.4.2.1.1.4 Storage and resonance structure

Resonant storage devices and other resonant structures can be used to further optimize the energy conversion characteristics of the present invention. For example, when the switch is turned on, the resonant structure whose energy is related to the input frequency can be stored from the input signal, and it can be judged during the cycle whether the structure is otherwise limited by the maximum possible efficiency. Resonant storage devices and other resonant structures may include surface acoustic wave (SAW) filters, dielectric resonators, duplexers, capacitors, inductors, etc.

An example is shown in Figure 79A. Two additional examples are shown in Figure 74 and Figure 82. Those who are familiar with the technology can use the teachings in this article to understand other alternative implementation schemes. These implementation schemes can be achieved by using the characteristics of parallel and series (storage) resonance circuits.

Fig. 79A shows different implementation schemes of the series storage circuit. The first parallel resonance or storage circuit includes a capacitor 7938 and an inductor 7920 (reservoir 1). The second storage circuit includes a capacitor 7934 and an inductor 7936 (reservoir 2).

As those familiar with related technologies can understand, the parallel storage circuit provides:

Low impedance is lower than the resonance frequency and adopts low impedance;

The low impedance is higher than the resonance frequency and adopts low impedance;

The high impedance is close to the resonance frequency and the high impedance is adopted.

As shown in the example of FIG. 79A, the first and second storage circuits resonate at about 920 MHz. At resonance, the impedance of the circuit is quite high. Therefore, in the resonance structure shown in FIG. 79A, the two storage circuits exhibit a relatively high impedance for an input frequency of 950MHz, while at the same time, the output range is designed for a frequency of 50MHz, and exhibits a relatively low impedance.

The energy conversion signal 7942 controls the switch 7914. When the energy conversion signal 7942 is used to control the opening and closing of the switch 7914, high-frequency signal components are not allowed to pass through the storage device 1 and the storage device 2. However, with a slight attenuation, the lower signal component (50 MHz in this embodiment) generated by the system is allowed to pass through the storage 1 and the storage 2. The functions of the storage device 1 and the storage device 2 further separate the input and output signals from the same node, so that a more stable input and output impedance can be generated. Capacitors 7918 and 7940 are used to store the output signal energy at 50 MHz between energy conversion pulses.

The inductance 7910 can be connected in series with the storage capacitor 7912 to further optimize the energy conversion. In the example shown, the series resonance frequency of this circuit is about 1GHz. This circuit increases the energy conversion characteristics of the system. The ratio of the impedance of the inductor 7910 to the impedance of the storage capacitor 7912 is preferably kept relatively small so that the main available energy can be transferred to the storage capacitor 7912 during operation. Examples of output signals A and B are shown in Figures 79B and 79C, respectively.

In FIG. 79A, circuit elements 7904 and 7906 form input impedance matching. Circuit elements 7932 and 7930 form an output impedance matched to 50 ohm resistor 7928. Circuit elements 7922 and 7924 form a second output impedance matched to 50 ohm resistor 7926. Capacitors 7908 and 7912 are used as storage capacitors in the embodiment. The voltage source 7946 and the resistor 7902 generate a 950 MHz signal with a 50 ohm output impedance as the input of the circuit. The circuit element 7916 includes a 150 MHz oscillator and a pulse generator to generate an energy conversion signal 7942.

Figure 74 shows a shunt storage circuit 7410 in a single-ended-to-single-ended system 7412. Similarly, Figure 82 shows the shunt storage circuit 8210 in the system 8212. The storage circuits 7410 and 8210 reduce the driving source impedance and improve the transient response. The storage circuits 7410 and 8210 can store the energy from the input signal and provide a lower driving source impedance to transmit the energy throughout the closed switch gap. The instantaneous nature of the switching slot can be regarded as an additional input frequency that has a response of a large component frequency higher than the input frequency (that is, a frequency higher than the output frequency can also effectively pass through the slot). The resonant circuits or structures of the exemplary resonant storage devices 7410 and 8210 can transmit energy throughout the instantaneous frequency response of the switch (that is, the capacitor in the resonant storage device exhibits low driving source impedance during the instantaneous period of the slot).

The above example receptacles and resonance structures are for illustrative purposes only, but no restrictions are imposed. Alternative plans can also be used. The various resonant storage devices and structures discussed can be used in combination or alone, as described below.

3.4.2.1.1.5 Charging and energy conversion concepts

Now referring to Figures 90A-F, the concept of charge conversion is described. FIG. 90A shows a circuit 9002 including a switch S and a capacitor 9006 having a capacitance value C. The switch S is controlled by a control signal 9008, including a pulse 19010 with a gap.

In Fig. 90B, Equation 29 shows that, for a capacitor 9006, the charge q on a capacitor with a capacitance value C is proportional to the voltage V passing through the capacitor, where:

q = Coulomb charge

C=Faraday capacitance

V=Voltage

A=input signal amplitude

Wherein Equation 30, the voltage V in Equation 29 can be rewritten in Equation 31. In Equation 32, the charge change Δq after the time t is represented by Δq(t), and is rewritten in Equation 33. Using the characteristics of equation 34 plus multiplication trigonometry, equation 33 can be rewritten as equation 35 and rewritten as equation 36.

It is worth noting that the sin term of Equation 30 is only a function of the gap T. Therefore, when T is equal to an odd multiple of π (that is, π, 3π, 5π), Δq(t) has a maximum value. Therefore, when the value of the slot T is π or the input sinusoid has a time interval of 180 degrees, the capacitor 9006 experiences the greatest change. Conversely, when T is equal to 2π, 4π, 6π,..., it has the smallest change.

Equations 37, 38, and 20 integrate Equation 29 to solve for q(t), allowing the charge of capacitor 9006 to be plotted on the same coordinate axis with respect to time as the input sinusoid sin(t), as shown in Figure 90C. Once the value of the slot T drops or tends to pulse, the charge on the capacitor C or the phase between q(t) and sin(t) tends to zero. This is shown in Figure 90D, indicating that the largest pulse charge transition occurs at the maximum input voltage. As shown in the figure, when the value of T decreases, only a relatively small charge is converted.

The power/charge relationship is shown in Equations 21-26 in Figure 90E, showing that power is proportional to charge, and converted charge is inversely proportional to insertion loss.

The concept of insertion loss is shown in Figure 90F. Generally, the noise pattern of the loss passive device is numerically equal to the insertion loss of the device. Alternatively, the noise pattern of any device cannot be smaller than the insertion loss. The insertion loss can be explained by Equation 27 or 28. From the above discussion, it can be found that as T increases, more charge is converted from the input to the capacitor 9006, increasing the power conversion from input to output. It can be observed that since the relevant modulation amplitude and phase information maintain the converted power, there is no need to accurately regenerate the input voltage during output.

3.4.2.1.1.6 Optimization and adjustment of gap width/duration cannot be ignored

3.4.2.1.1.6.1 Change the input and output impedance

According to the embodiment of the present invention, the energy conversion signal (ie, the control signal 5306 in FIG. 53A) is used to change the input impedance, see EM signal 5304, and to change the output impedance of the driving load. Hereinafter, an example of this embodiment will be described using the gate switching module 7001 shown in FIG. 70A. The method described below is not limited to the gate switching module 7001.

In FIG. 70A, when the switch 7006 is turned off, the impedance in the circuit 7002 is roughly the impedance in the storage module. Here, the storage capacitor 7008 is illustrated as being formed in parallel with the load impedance 7012. When switch 7006 is turned on, the impedance at point 7014 approaches infinity. By the ratio of the time when the switch 7006 is turned on and the time when the switch 7006 is turned off, the average impedance at point 7014 can vary from the impedance of the storage module of the parallel load 7012 to the highest obtainable impedance when the switch 7006 is turned on. The switch 7006 is controlled by the energy conversion signal 7010. In this way, the impedance at the point 7014 can be changed by controlling the gap width of the energy conversion signal in combination with the alias rate.

Referring to FIG. 68A, the following describes an example of a method of changing the energy conversion signal 7006 of FIG. 70A, in which the circuit 6802 receives the input oscillating signal 6806 and outputs a pulse train such as the doubled output signal 6804. The circuit 6802 can be used to generate the energy conversion signal 7006. An example waveform of the 6804 is shown in Figure 68C.

By changing the delay of the transmission signal of the inverter 6808, it can be shown that the pulse width of the doubled output signal 6804 changes accordingly. Increasing the delay of the signal transmitted by the inverter 6808 can increase the pulse width. The signal transmitted by the inverter 6808 can be delayed by introducing an R/C low-pass network at the output of the inverter 6808. Those who are familiar with related technologies should be able to understand other ways to change the delay of the signal transmitted by the inverter 6808.

3.4.2.1.1.6, 2 Real-time gap control

In the embodiment, the slit width/duration is adjusted in real time. For example, referring to the timing diagrams of FIGS. 83B-F, the clock signal 8314 (FIG. 83B) is used to generate the energy conversion signal 8316 (FIG. 83F) including the energy conversion pulse 8318 and the variable slit 8320. In an embodiment, the clock signal 8314 is reversed by the reverse clock signal 8322 (FIG. 83D). As shown by the delayed clock signal 8324 (FIG. 83E), the clock signal 8314 is also delayed. Perform an AND operation on the reverse clock signal 8314 and the delayed clock signal 8324. When the delayed clock signal 8324 and the reverse clock signal 8322 are excited at the same time, an energy conversion signal 8316 is generated, which is an excited state-energy conversion pulse 8318 . The amount of delay assigned to the delayed clock signal 8324 roughly determines the width or duration of the slot 8320. Alternatively, the original clock signal 8314 is delayed first and then reversed, and the result of the AND operation of the original clock signal 8314 is generated.

Fig. 83A shows an example of the slot control system 8302, which can adjust the slot in real time. That is, the slot control system 8302 example includes an RC circuit 8304, including a variable voltage capacitor 8312 and a resistor 8326. That is, the slot control system 8302 includes an inverter 8306 and an AND gate 8308 at the same time. The AND gate 8308 optionally includes an actuation input 8310 to activate/close the AND gate 8308. The RC circuit 8304, that is, the slot control system 8302, optionally includes an amplifier 8328.

The operation of the slot control circuit will be described with reference to timing diagrams 83B-F. The real-time control system 8302 receives the input clock signal 8314 and provides it to the inverter 8306 and the RC circuit 8304 at the same time. The inverter 8306 outputs an inverted clock signal 8322 and provides it to the AND gate 8308. The RC circuit 8304 delays the clock signal 8314 and outputs the delayed clock signal 8324. The amount of delay is mainly determined by the capacitance of the variable voltage capacitor 8312. Generally, as the capacitance decreases, the delay decreases.

Before being provided to the AND gate 8308, the delayed clock signal 8324 can be selectively amplified by an additional (non-essential) amplifier 8328. Amplification is desirable. For example, the RC constant of the RC circuit 8304 attenuates the signal below the threshold of the AND gate 8308.

The AND gate 8308 performs an AND operation on the delayed clock signal 8324, the inverted clock signal 8322, and the selective actuation signal 8310 to generate an energy conversion signal 8316. The gap 8320 can be adjusted instantly by changing the voltage value of the variable voltage capacitor 8312.

In an embodiment, the slot 8320 is controlled to achieve the best power conversion. For example, in an embodiment, the slot 8320 is controlled to achieve maximum power conversion. Alternatively, the slot 8320 is controlled to perform variable gain control (for example, automatic gain control-AGC). In this embodiment, the power conversion is reduced by reducing the gap 8320.

It can be quickly seen from this article that many of the proposed slot circuits and other circuits can be modified as shown in Figure 66H-K. The correction or selection of the gap can be performed at the design level to maintain a fixed value in the circuit, or in an alternative embodiment, can be dynamically adjusted to compensate, or address different design purposes, such as in different operating frequency bands, such as RF signals located in 900MHz and 1.8GHz, with enhanced effect to receive RF signals, etc.

3.4.2.1.1.7 Add bypass network

According to the embodiment of the present invention, a bypass network is added to improve the efficiency of the energy conversion module. This kind of bypass network can be regarded as a device that expands the synthesis gap. The bypass network component is selected so that the bypass network provides a lower impedance to the switch module instantaneously (that is, greater than the frequency of the received EM signal) and provides a modulated high frequency to the input EM signal (that is, When the RF frequency is greater than 100 ohm).

Due to the shaping of the network, the time of the input signal connected to the opposite side of the switch module is longer, which can be realized by a capacitor or a series resonant inductor-capacitor. Typically, a network that resonates in series at the input frequency can be used. If it refers to considering the gap of the energy conversion signal, this shaping can improve the conversion efficiency of the input signal and achieve the best state at a very low frequency.

For example, referring to FIG. 80, a bypass switch module 8004 is shown by a bypass network 8002 (capacitor 8012 is shown in this example). In this embodiment, for example, for a given input frequency on the energy conversion signal 8006, the bypass network increases the efficiency of the energy conversion module when the gap width is less than the optimal slot width. The bypass network may have a different plan from that shown in Figure 80. An alternative example is shown in Figure 76. Similarly, FIG. 81 shows another example bypass network 8102 that includes a capacitor 8104.

The following discussion will demonstrate the effect of minimizing the gap and the benefits provided by the bypass network. In Fig. 84, the initial circuit has a 550ps gap at the beginning, and the output is 2.8m Vpp under a load of 50 ohm in Fig. 88A. Change the gap to 270ps as shown in Figure 85. The result is shown in Figure 88B. Under a load of 50 ohm, the output is reduced to 2.5m Vpp. In order to compensate for this loss, a bypass network can be added. The special implementation example is the same as that shown in 89A. In Figure 86, a circuit with a bandpass network has three values at the same time, and adjustments are made around the circuit to compensate for the impedance change caused by the bandpass network and the narrow gap. Fig. 87 proves that these changes added to the circuit, if there is no passband network, it cannot be adjusted by the embodiment with the passband network in Fig. 86 to increase the benefit. Figure 89B shows the result of using the circuit of Figure 87, where only 1.88Vpp can be implemented to a 50ohm load.

3.4.2.1.1.8 Using feedback to correct the energy conversion signal

FIG. 66 shows an embodiment of the system 6601, in which the down-conversion signal 6608B is used as the feedback 6606 to control different features of the energy conversion module 6604 to modify the down-conversion signal 6608B.

Generally, the down conversion signal 6608B varies with the frequency and the phase difference function between the EM signal 6404 and the energy conversion signal 6406. In the embodiment, the down conversion signal 6608B is used as the feedback 6606 to control the frequency and the phase relationship between the EM signal 6404 and the energy conversion signal 6406. This can be achieved using the example logic of Figure 71A. The example circuit in FIG. 71A can be included in the energy conversion signal module 6602. Based on the teachings herein, persons familiar with related technologies should be able to understand alternative embodiments. Alternative embodiments fall within the scope and spirit of the invention. In this embodiment, state-computer is used as an example.

In the example of FIG. 71A, the state computer 7104 reads the analog-to-digital converter, A/D7102, and controls the digital-to-analog converter, DAC 7106. In the embodiment, the state-computer includes the previous and current memory locations to store and read the results returned by the A/D 7102. In an embodiment, the state-computer 7104 uses at least 1 memory flag.

The DAC 7106 controls the input of the voltage controlled oscillator VCO 7108, and the VCO 7018 controls the frequency input of the pulse generator 7110. In the embodiment, a similar pulse generator is shown in FIG. 65C. The pulse generator generates an energy conversion signal 6406.

In an embodiment, the state-computer 7104 operates according to the state computer flowchart 7119 in FIG. 71B. The result of the operation is used to correct the frequency and phase relationship between the energy conversion signal 6406 and the EM signal 6404, so as to roughly maintain the amplitude of the down conversion signal 6608E at the optimal level.

The amplitude of the down conversion signal 6608B can vary with the amplitude of the energy conversion signal 6406. In an embodiment, as shown in FIG. 64A, the switch module 6502 is a FET, and the gate 6418 receives the energy conversion signal 6406. The amplitude of the energy conversion signal 6406 can determine the "on" impedance of the FET, which affects the down conversion signal 6608B The amplitude. The energy conversion signal module 6602 shown in FIG. 71C can be an analog circuit for activating the automatic gain control function. Based on the teachings herein, persons familiar with related technologies should be able to understand alternative embodiments. Alternative embodiments fall within the scope and spirit of the invention.

3.4.2.1.1.9 Other impedance

The embodiments described above are for illustrative purposes only. These implementations are not intended to limit the invention. Among the alternative embodiments, based on the teachings herein, persons familiar with the related art should be able to understand alternative embodiments slightly or specifically different from this text, and the alternative embodiments fall within the scope and spirit of the present invention.

3.4.2.1.1.10 Energy Conversion Down Conversion Example

The following example embodiments are for illustrative purposes only. The present invention is not limited by these examples.

Figure 72 is a diagram of an example circuit that uses a 101.1MHz clock to convert a 915MHz signal to a 5MHz signal.

Figure 73 shows an example analog waveform for the circuit of Figure 72. Waveform 7202 is the input to the circuit and shows the distortion caused by the switch being closed. Waveform 7204 is the unfiltered output of the storage unit. Waveform 7206 is the impedance matching the output of the down converter under different time scales.

Figure 74 is a diagram of an example circuit that uses a 101.1MHz clock to convert a 915MHz signal to a 5MHz signal. The circuit has an external storage circuit to improve the conversion efficiency.

Figure 75 shows an example analog waveform for the circuit of Figure 74. Waveform 7402 is the input to the circuit and shows the distortion caused by the switch being closed. Waveform 7404 is the unfiltered output of the storage unit. Waveform 7406 is the output of the down converter after the impedance matching circuit.

Figure 76 is a diagram of an example circuit that uses a 101.1MHz clock to convert a 915MHz signal to a 5MHz signal. This circuit has a switching bypass circuit to improve conversion efficiency.

Figure 77 shows an example analog waveform for the circuit of Figure 76. Waveform 7602 is the input to the circuit and shows the distortion caused by the switch being closed. Waveform 7604 is the unfiltered output of the storage unit. Waveform 7606 is the output of the down converter after the impedance matching circuit.

Figure 78 shows a diagram of the example circuit of Figure 72, connected to an FSK source that changes between 913 and 917 MHz at a baud rate of 500K baud (codes per second). Figure 91 shows the original FSK waveform 7802 and the down-conversion waveform 7804 at the output of the load impedance matching circuit.

3.4.2.2 Delay module

As mentioned above, the delay module delays the samples/events of the input signal by a specified amount. For example, in the embodiment of the UDF module 2622 shown in FIG. 26, the first and second delay modules 2628 and 2630 are operated to delay the event of the output signal VO. Specifically, the first delay module 2628 delays the event of the output signal VO by 1 time unit. The second delay module 2630 also delays the event of the output signal VO by 1 time unit. However, the second delay module 2630 receives input from the first delay module 2628. Therefore, the effect of the second delay module 2630 (combined with the first delay module) is to delay the event of the output signal VO by 2 time units. The second and third elements of the band-pass filter conversion formula using the EQ.3 example are necessary.

In the embodiment of the UDF module 2622 shown in FIG. 26, the first delay module 2628 and the second delay module 2630 are implemented separately using sample and hold circuits. For the convenience of description, the sample and hold circuit is described in Figure 45. (As mentioned in the article, other UDF module embodiments include a delay module, and this delay module is also implemented using a sample and hold circuit. Alternatively, those familiar with related technologies should understand that a generally well-known delay circuit can be used Or processor/software)

In detail, FIG. 45 shows two sample and hold circuits 4501 and 4503. Sampling and holding 4501, 4503 have the same structure and operating procedures. Generally, the first delay module 2628 and the second delay module 2630 can be executed using a sample and hold 4501 or a sample and hold 4503. Preferably, the first delay module 2628 and the second delay module 2630 are executed according to the example plan shown in FIG. 45.

The sample and hold 4501, 4503 respectively include a first switch 4508, 4524 and a second switch 4512, 4528. The first switches 4508 and 4524 and the second switches 4512 and 4528 are controlled by the clock signal 4550. Preferably, the clock signal 4550 has two phases ψ₁And ψ₂. Preferably, ψ₁And ψ₂Have the same frequency but do not overlap each other. The first switch 4508, 4524 by ψ₁control. Preferably, the first switch 4508 and 4524 are at ψ₁The rising edge closes, and at the subsequent ψ₁The falling edge opens. The second switch 4512, 4528 by ψ₂control. Preferably, the second switch 4512, 4528 is at ψ₂The rising edge closes, and at the subsequent ψ₂The falling edge opens. ψ₁And ψ₂An example of this is shown in Figure 48. It is worth noting that the present invention is not limited by these switch conversions. In other embodiments, other switch conversions can be used. Further, other circuit plans can be used.

The sample and hold 4501 and 4503 also include electric capacitors 4510 and 4526 and second capacitors 4514 and 4530, respectively. The sample and hold 4501, 4503 can optionally include integrated gain modules 4520, 4522, 4532, 4534, and the operation method is as described above.

Now, please refer to the flowchart 4602 of FIG. 46 to describe the operation of sampling and holding 4501, 4503. You can also refer to Table 4702 to point out that sample values of specific nodes in 4501 and 4503 are sampled and held in several consecutive time increments. In the example of table 4702, it is assumed that the sampling and holding 4501, 4503 starts operation at time t. Sampling and holding 4501, 4503 requires one or more cycles to reach a steady state. According to the teachings of this article, people familiar with the relevant technology should be able to know the number of cycles required to reach a steady state.

In step 4604, at time t, ψ₁At the rising edge, switch 4508 is closed. As the first switch 4508 is closed, the first capacitor 4510 is charged to VI_tMake node 4516 be in VI_t. This is shown in table 4702, cell 4704.

Note that the first switch 4524 of the sample and hold 4503 is also at time t, ψ₁Close at the rising edge. In this way, the capacitor 4526 in the sample and hold 4503 is charged to the same level as the capacitor 4514 stored in the sample and hold 4501. However, in the example circuit discussed, at time t, ψ₁The value of the second capacitor 4514 at the rising edge is not defined. Therefore, as indicated by unit 4705 of table 4702, the charge of the first capacitor 4526 at time t is undefined.

In step 4606, at time t, ψ₂At the rising edge, the second switch 4512 in the sample and hold 4501 is closed. This causes the second capacitor 4514 to be charged to the level of the first capacitor 4510. Therefore, the second capacitor 4514 is charged to VI_tMake the value of node 4518 become VI_t. This is shown in table 4702, cell 4708.

At the same time at time t, ψ₂At the rising edge, the second switch 4528 in the sample and hold 4503 is closed. This allows the second capacitor 4530 to be charged to the same level as the first capacitor 4526 in the sample and hold 4503. However, as described above, the charge of the first capacitor 4526 has not yet been defined at this time. Therefore, as indicated by unit 4709 of table 4702, the charge of the second capacitor 4530 is undefined at this time.

In step 4608, at time t+1, ψ₁At the rising edge, close the sample and hold switch 4508 of 4501. Charge the first capacitor 4510 to VI_t+1Make node 4516 be in VI_t+1. This is shown in table 4702, cell 4710.

The first switch 4524 that samples and holds 4503 at the same time is also at time t+1, ψ₁Close at the rising edge. In this way, the first capacitor 4526 in the sample and hold 4503 is charged to the same level as the capacitor 4514 in the sample and hold 4501. Therefore, the first capacitor 4526 is charged to VI_tSo that node 4536 is in the VI_t. This is shown in table 4702, cell 4714.

In step 4610, at time t+1, ψ₂At the rising edge, the second switch 4512 in the sample and hold 4501 is closed. In this way, the second capacitor 4514 in the sample and hold 4501 is charged to the level of the first capacitor 4510. In other words, the second capacitor 4514 is charged to VI_t+1Make node 4518 be in VI_t+1. This is shown in table 4702, cell 4718.

Similarly, at time t+1, ψ₂At the rising edge, the second switch 4528 in the sample and hold 4503 is closed. In this way, the second capacitor 4530 is charged to the level of the first capacitor 4526 in the sample and hold 4503. In other words, the second capacitor 4530 is charged to VI_tSo that node 4538 is located in the VI_t. This is shown in table 4702, cell 4722.

Figure 48 shows another sampling and holding 4501, 4503 operation. Figure 48 shows the ψ of the clock 4550₁And ψ₂. As mentioned above, the first switch 4508 and 4524 are at ψ₁The rising edge closes, and at ψ₁The falling edge opens. The second switch 4512, 4528 is in ψ₂The rising edge closes, and at ψ₂The falling edge opens.

Now consider sampling and holding 4501. When the first switch 4508 is turned off, the first capacitor 4510 starts to be charged to the input signal VI and continues to be charged until the first switch 4508 is turned on. When ψ₁When it is high, turn off the first switch 4508. Therefore, when ψ₁When it is high, sample and hold 4501 sampling input signal VI. This is represented by the sampling period 4802 of FIG. 48. Figure 48 also indicates the hold period 4804. In the hold period 4808, the input signal VI samples stored in the first capacitor 4510 are maintained in the sample and hold 4501. Specifically, keep this input sample in the first capacitor 4510 until the next ψ₁Rising edge (at time t+1). At the same time, at time t, at ψ₂At the rising edge, the second switch 4512 is turned off and the second capacitor 4514 is charged to this input sample. This value remains in the second capacitor 4514 until the next ψ at time t+1₂Rising edge.

Therefore, in the sample and hold 4501, VI is sampled at the beginning of time t, and remains in the sample and hold 4501 until the time period t expires. So, sample and hold 4501 to sample VI at time t; this sample VI_tWill not be passed to the next sample and hold 4503 until time t+1. Therefore, the sample and hold 4501 can effectively hold and delay the samples of the input signal VI within 1 time period. This delay period is represented by 4806 in Fig. 48.

In fact, when the first switch 4508 is turned off, the first capacitor 4510 changes along the input signal VI (that is, within the sampling period 4802 at time t). At time t, ψ₁The charge stored in the first capacitor 4510 at the falling edge forms the input sampling VI_t. In other words, enter the sample VI_tDefined as at time t, ψ₁Sampling and holding 4501 at the falling edge. The input sample VI defined in the input sample and hold 4501₁Until the next ψ₁It is not redefined before the falling edge (that is, the falling edge ψ at time t+1₁). Therefore, the delay of the sample and hold 4501 can be regarded as the delay 4807 shown in FIG. 48.

Therefore, this section will further focus the discussion on the delay modules 2628 and 2630 implemented using the sample and hold circuit, such as the example UDF module 2622 in FIG. 26. However, the present invention is not limited by this embodiment. On the contrary, the delay module in the UDF module can be implemented by any device or circuit that can predetermine the delay of the incoming signal.

For example, referring to the delay modules 1710 and 1722 of FIG. 17 for illustration only, they can be implemented separately using a switched capacitor topology 3204, as shown in FIG. 32. Switching capacitor topology 3204 contains two clock signals ψ₁And ψ₂Operate switches 3208 and 3206. ψ₁And ψ₂Examples of representation are shown in Figures 33A and 33B.

In addition to the delayed input signal VI, as shown in Figure 32, a special switched capacitor can also scale the input signal as shown in the following formula:

<img file="TW441164B_D0018.tif" />

Therefore, when using the switched capacitors as shown in FIG. 32, the switched capacitors execute the delay modules 1710, 1722 and the related zoom modules 1716, 1724 at the same time.

The delay modules 1710 and 1722 can also be executed separately using the analog delay row, for example, the analog delay row 3404 in FIG. 34. As those familiar with related technologies can understand, the analog delay column 3404 is composed of capacitors, inductors, and/or resistors. The analog delay column 3404 is used to delay a known amount of delay signal. In some embodiments, the analog delay column 3404 is composed of other elements that can achieve this function, such as a sampler.

The above implementation examples are for illustrative purposes only and are not limited. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.3 Zoom module

The scaling module in the UDF module is used to scale the individual input delivered. Such scaling provides UDF module filtering characteristics (such as filtering center frequency and bandwidth).

Referring to the UDF module 1702 of FIG. 17 for illustrative purposes only, the scaling modules 1716 and 1724 can be implemented by using any device and circuit capable of scaling the input signal according to a known amount. The zoom factor can be less than 1 (reduction in this example) or greater than 1 (enlargement in this example). In more detail, the scaling factor can be any real number, including zero.

For example, each zoom module 1716 and 1724 can use a resistance reducer 3504 as shown in FIG. 35. As those familiar with related technologies can understand, the resistance reducer can have many types and designs. FIG. 36 shows an example of the resistance reducer 3602. The example resistance reducer 3602 reduces the input V1 using the following formula:

<img file="TW441164B_D0019.tif" />

Those who are familiar with the related technology will be able to understand the circuit diagrams of other resistance reducers in the UDF module 1702 that the zoom modules 1716 and 1724 are suitable for.

The amplifier/reducer 3704 can also be implemented using zoom modules 1716 and 1724. Figure 37 shows an example amplifier 3704. Those familiar with the related technology will be able to understand that the amplifiers in the UDF module and the zoom modules 1716 and 1724 can be implemented using different circuit components, such as operational amplifiers (OP AMPS), transistors, and FETs.

The above execution example is for illustrative purposes only. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.4 Adder

With reference to FIG. 17, an adder 1720 (also referred to herein as an adder) for illustrative purposes adds up the inputs. The adder 1720 can use any device or circuit that can add a total of input signals.

For example, the adder 1720 may use the resistance adder 3804 (FIG. 38). As those familiar with related technologies can understand, there are many different planning methods for resistance totalizers. FIG. 39 shows an example resistance totalizer 3902, which can be used to perform the task of executing the adder 1720. However, the present invention is not limited by this example.

The adder 1720 can also be implemented using the OP AMP adder 4004 (Figure 40). As those who are familiar with related technologies can understand, OP AMP totalizer can have many different planning methods. For illustration, Figure 41 shows the OP AMP adder 4102. Those who are familiar with the relevant technology will be able to understand the structure and operation of the OP AMP adder 4102. It should be understood that the present invention is not limited to the example OP AMP adder 4102 provided in FIG. 41.

The adder 1720 can also be implemented in combination with an adder element, as shown in the embodiment of FIG. 26.

The above execution example is for illustrative purposes only. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.5 Control signal generator

Referring to FIG. 17 for illustrative purposes only, the UDF module 1702, the down conversion and delay module 1708, and the delay modules 1710, 1722 operate according to the control signals 1734A-1734F. Preferably, the control signals 1734A-1734F represent two-phase control signals, that is, have ψ₁And ψ₂Two-phase control signal. Preferably, ψ₁And ψ₂Have the same frequency and do not overlap each other.

Figures 43B and 43D show ψ₁And ψ₂Example. The present invention can use any device and circuit capable of generating the two-phase control signal. FIG. 42 shows an example implementation of the control signal generator 1790.

The control signal generator 1790 includes an oscillator 4204 and an optional signal shaper 4205, which can generate a series of pulses at the sampling frequency fs. Shown in Figure 43A. The signal separator 4206 separates the oscillating signal into two identical signals. Examples of these two signals are shown in Figures 43B and 43C. These two signals are located at nodes 4216 and 4214 in the control signal generator 4202, respectively.

The signal separator 4206 may cause signal attenuation. Therefore, some embodiments of the present invention also include an amplifier.

Delay module 4208 delays one of the signals to generate ψ at node 4218₂. Shown in Figure 43D.

As noted above, in some embodiments, one or more control signals ψ₁And/or ψ₂It is useful to adjust the gap (width) of the pulse internally. In some embodiments, the optional slot optimization module 4210 performs the adjustment control signal ψ₁And/or ψ₂The task of the inner pulse gap. The structure and operation of the embodiment of the slot optimization module 4210 are described in detail in the pending US patent entitled "Method and System for Down-Converting Electromagnetic Signals".

The above execution example is for illustrative purposes only. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.6 Output sample and hold module

Some embodiments of the UDF module may include an input sample and hold module. For example, the example UDF module 2622 shown in FIG. 26 includes an input sample and hold module 2636. Preferably, the input sampling and holding module 2636 is located at the input end of the adder 2626.

As the foregoing embodiment proves, the output signal VO generated by the UDF module basically represents the output of the adder (although some implementation power and applications are not in this example). For example, as shown in the UDF module in Figure 17. In some implementation situations of the UDF module, as shown in FIG. 26, the value presented at the output of the adder 2626 does not always represent a valid event of the output signal VO. This is due to the transmission of the signal through the UDF module. The output sample and hold module 2636 ensures that only the effective value output by the adder 2626 can be presented in downstream devices other than the UDF module.

In the example in Figure 26, the value at the output of the adder 2626 is only located at ψ₁Guaranteed to be effective at the rising edge. Therefore, the switch 2691 in the output sample and hold module 2636 is at ψ₁The rising edge is turned off, thus allowing the capacitor 2692 in the output sample and hold module 2636 to be charged to the value at the output of the adder 2626. The value in the capacitor 2692 is provided to the output smoothing module 2638. The signal generated by the output smoothing module 2638 represents the output signal VO. For example, following the above description, it is shown in unit 1550 of table 1502.

The above execution example is for illustrative purposes only. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.7 Output smoothing module

Some embodiments of the UDF module may include an output smoothing module. For example, the UDF module 2622 of FIG. 26 includes an output smoothing module 2636. The output smoothing module 2638 smoothes the signal generated by the output sample and hold module 2636. It should be noted that the output smoothing module is a non-essential component.

The above execution example is for illustrative purposes only. According to the teachings of this article, people familiar with related technologies will be able to understand other implementation examples.

3.4.2.8 Intermediate point introduction example: high-frequency delay module

Referring to FIG. 25, the high-frequency delay module 2506 used in the UDF module 2502 of the midpoint introduction embodiment of the present invention can be implemented by any device that can delay relatively high-frequency signals or signal events within a given time. For example, the signal frequency can be RF or higher (but the invention is not limited to these frequencies-the signal frequency can be less than RF).

Any and well-known delay line and/or outgoing structure can be used to implement the high frequency delay module 2506. For example, a transmission line with a known length can be used to implement the high-frequency delay module 2506. As those who are familiar with related technologies will know. A transmission line of known length can be used to obtain a specific amount of delay.

According to the teachings of this article, those familiar with related technologies will be able to understand other devices or structures for implementing the high-frequency delay module 2506.

3.4.2.9 Intermediate point introduction example: additional filter

Referring to FIG. 25, the filter 2508 selectively used in the UDF module 2502 of the embodiment introduced at the midpoint of the present invention can be implemented using any and appropriate filtering device. Preferably, the filter 2508 is a high frequency, broadband filter. Any and appropriate conventional filtering topologies can be used, such as LC structure, strip line, and/or sawtooth filters. According to the discussion in this article, those familiar with related technologies will be able to understand various devices or structures for implementing the filter 2508.

3.4.2.10 Intermediate point introduction example: down conversion module

Referring to FIG. 25, the down-conversion module 2526 used in the UDF module 2502 of the midpoint introduction embodiment of the present invention can be implemented by any device capable of performing frequency down-conversion. For example, any well-known frequency down conversion device using mixers and oscillators can be used. According to the discussion in this article, those familiar with related technologies will be able to understand other devices that can perform frequency down conversion.

According to an embodiment of the present invention, the down conversion module 2526 may be replaced by a universal frequency down conversion (UFD) module. The UDF module is described above.

3.4.2.11 Intermediate point introduction example: Up-conversion module

Referring to FIG. 25, the up-conversion module 2524 used in the UDF module 2502 of the midpoint introduction embodiment of the present invention can be implemented by any device capable of performing frequency up-conversion. For example, any well-known frequency up-conversion device using mixers and oscillators can be used. According to the discussion in this article, people familiar with related technologies will be able to understand other devices that can perform frequency up-conversion.

3.4.3 Implement UDF module with integrated circuit (IC)

The present invention focuses on UDF modules implemented on integrated circuits (ICs).

Considering IC manufacturing technology helps to understand the technology in this aspect of the invention.

When manufacturing filters, basically filter components, such as capacitors, inductors, resistors, etc., require very tight tolerances. On the contrary, the value of the components used in the UDF module of the present invention does not require high precision. In detail, for a given individual circuit element used in Renhe UDF module, high precision is not required.

In other words, according to the present invention, the filter parameters are determined according to the ratio of component values. For example, the switching capacitor shown in Figure 32 above, where the scaling factor is determined by the ratio of C1 and C2.

As those familiar with related technologies will understand, it is very difficult for today's manufacturing technology to achieve tight tolerances for the values of individual circuit components, especially when operating at high frequencies (such as RF or higher). However, current technology allows the ratio of circuit component values to have tight tolerances. And this is true for all operating frequencies. In this way, the present invention can provide benefits to the IC manufacturing process. An advantage provided by the present invention in this respect is that the UDF module can be implemented as an IC.

Other aspects of UDF module can be implemented by IC.

For example, a UDF module component suitable for performing frequency conversion operations, such as a universal frequency down conversion module, can be achieved with a limited number of components. As shown in the embodiment of FIG. 26, the frequency down conversion operation is mainly performed by the switch 2650 and the capacitor 2652.

At the same time, according to the present invention, input filtering can be achieved with a limited number of components. See the example UDF module 2622 in Figure 26 again.

Furthermore, the purpose of the invention can be achieved without using large capacitors, inductors, or resistors, as described below.

Therefore, the structure of the present invention is quite suitable for integrated circuit design and manufacturing. Therefore, according to the teachings of this article, those familiar with the related technology will be able to understand the implementation of the UDF module embodiment using the integrated circuit of the existing manufacturing technology.

3.4.4 Other execution

The above execution is for illustration only. This implementation is not intended to limit the invention. According to the teachings of this article, people familiar with related technologies will be able to understand other slightly or specifically different implementation examples. These alternative implementations all fall within the spirit and scope of the present invention.

4 Design of integrated down-conversion and filtering UDF module

The design method of the integrated down conversion and filtering (UDF) module according to an embodiment of the present invention will now be described. This method can be used in any and UDF module embodiments discussed or considered herein.

It should be noted that this method is for illustrative purposes only and is not intended to limit the scope of the present invention. According to the teachings of this article, those familiar with related technologies will be able to understand other slightly or specifically different alternative design methods.

Referring now to the flowchart 4902 in FIG. 49, in step 4904, the UDF module is designed to exhibit the desired frequency conversion characteristics. This feature can include the desired input signal and the desired output signal. This feature can also include down-conversion of the input signal to IF signal, down-conversion to demodulated baseband signal, down-conversion from FM signal to PM or AM signal, etc. This feature also includes that energy conversion should increase during the frequency conversion process.

In step 4906, the UDF module is designed to exhibit the desired frequency selection characteristics. This feature can include the filter type implemented by the UDF module (low pass, high pass, band pass, all pass, band cut, concave, etc.), filter center frequency, filter bandwidth, filter passband, etc.

Note that the execution priority of steps 4904 and 4906 can be determined by oneself.

In step 4908, the UDF module is constructed according to the design considerations of steps 4904 and 4906.

Now referring to the flowchart 5002 of FIG. 50, the operation procedure of the steps of the flowchart 4902 will be described in detail.

Step 4904 (design the UDF module to exhibit the desired frequency conversion characteristics) is represented by step 5004 in FIG. 50. Preferably, the desired frequency conversion characteristics of the UDF module can be established through the selection of the sampling rate. As mentioned above, other considerations are further described in the pending US patent, titled "Method and System for Down-Converting Electromagnetic Signals", please refer to the above.

Step 4906 (design the UDF module to show the desired frequency selection characteristics) is represented by steps 5006-5010 in FIG. 50, and is described as follows.

In step 5006, a low-pass conversion formula for the S-plane can be obtained/selected. As those familiar with the relevant technology will understand, the filter generally designed starts with a low-pass filter at the required cut-off frequency. As those familiar with related technologies will understand, there are many formulas and/or design tables for low-pass conversion formulas, including Butterworth, Chebyshev, elliptic filters, etc. Any one and one item can be obtained/selected using the S-plane low-pass conversion formula in step 5006.

In step 5008, the S-plane low-pass conversion formula obtained in step 5006 is converted into a Z-plane low-pass conversion formula. Step 5008 uses the mathematical formula in EQ.8 to replace the S variable in the S-plane low-pass conversion formula. As those familiar with related technologies will understand, there are other S-plane to Z-plane conversion formulas. The present invention can use any and available conversion formulas.

<img file="TW441164B_D0020.tif" />

In EQ.8, T represents the reciprocal of the sampling rate (determined by step 5004). In other words, T is equal to 1/(sampling rate).

In step 5010, if necessary, the Z-plane low-pass conversion formula can be modified to obtain the desired filtering characteristics. Preferably, the correcting action in step 5010 can use any and well-known conversion formulas. In FIG. 51, a well-known conversion formula is provided (the conversion formulas of FIG. 51 are independent of each other, in which the conversion from the S plane to the Z plane is performed in step 5008). In this mathematical formula, θ_pRepresents the cut-off frequency of the S low-pass conversion formula obtained in steps 5006 and 5008.

Table 5102 in Figure 51 is from Oppenheim and Schafer, Digital Signal Processing, Prentice-Ha11, New Jesey, 1975, page 230.

As those familiar with related technologies will understand, there are other conversion mathematics. Any and similar conversion formulas can be adopted by the present invention.

When using the example conversion of Table 5102, the transposition and formula of units 5106 and 5114 can be used to obtain the Z-plane high-pass conversion formula from the Z-plane low-pass conversion formula in step 5008. The transpose and formula of the units 5108 and 5116 can be used to obtain the Z-plane band-pass conversion formula from the Z-plane low-pass conversion formula in step 5008. The transpose and formulas of the units 5110 and 5118 can be used to obtain the Z-plane band-cut conversion formula from the Z-plane low-pass conversion formula in step 5008. The transpose and formula of the units 5104 and 5112 can be used to obtain the modified Z-plane low-pass conversion formula from the Z-plane low-pass conversion formula in step 5008.

The filter characteristics such as center frequency and passband are established from the equations and transformations of FIG. 51. For example, consider a band-pass filter, once the conversion of unit 5108 is applied to the Z-plane low-pass conversion formula generated in step 5008, the original low-pass cutoff frequency θ_pIndicates the center frequency of the band pass filter. The pass band of the band-pass filter is expressed as ω₁And ω₂definition.

It should be noted that the Z-plane conversion formula generated by referring to the above steps 5006 and 5008, and 5010 can have different types and/or come from the conversion formula EQS.1-6. In particular, according to the present invention, arbitrary or at least a large number of filter conversion formulas can be generated by any or at least a large number of programs. According to the teachings herein, those familiar with related technologies will be able to understand other implementation examples.

Also referring to FIG. 50, in step 4908, the UDF module is created according to the design considerations of steps 5004-5010. For example, consider the number and arrangement of delay elements in the UDF module 17020 UDF module 1702 (such as the down-conversion delay module 1708 and the delay modules 1710, 1722) in FIG. The delay factor in the formula is specified. This has been discussed in the previous chapter. The sampling rate selected in step 5004 corresponds to the control signal 1734. The constants in the filter conversion formula (after steps 5006, 5008, and 5010) are determined by the scaling modules 1716, 1724 (and optional 1790).

5 Adjustable UDF module

As noted above, referring to FIG. 17 for illustrative purposes only, the frequency conversion and selection characteristics of the UDF module 1702 are mostly established by the control signal 1734 (including the sampling clock) and the scaling modules 1716 and 1724. In the UDF module embodiment, each parameter is adjustable, including the control signal 1734 and the scaling modules 1716 and 1724. Therefore, the frequency conversion and selection characteristics of the UDF modules according to the control signal 1734 and the zoom modules 1716 and 1724 are adjustable. In some embodiments, these characteristics can be adjusted electrically.

Regardless of whether the input signal is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or AM signal, etc., or whether the energy conversion is increased during the frequency conversion process, including the desired output signal The frequency conversion characteristics of the frequency can be adjusted by the control signal 1734 (such as the rate and/or pulse of the slot).

Frequency selection characteristics including filter center frequency, filter bandwidth, filter passband, filter type, etc. can be obtained by adjusting the zoom module 1716 and/or the zoom factor of the control signal 1734 (such as the rate and/or pulse of the slot).

The scaling factor can use adjustable elements such as adjustable resistors, capacitors, and inductors, and execute the scaling modules 1716 and 1722 to adjust the scaling factor. These adjustable elements are electrically adjustable.

The adjustable device can be controlled manually. Instead, the UDF module embodiment includes a control module that can automatically control these adjustable devices (in some embodiments, the control module operates according to commands that are input and/or issued). The control module can be operated in real time, so that the UDF module can be dynamically adjusted. The control module can be executed by a software control processor, a state mechanism, etc., or a combination of these.

6 Amplifier

As mentioned above, the integrated down-conversion and filtering module according to the embodiment of the present invention involves frequency down-conversion and filtering at the same time. According to an embodiment of the present invention, the present invention integrates down conversion and filtering including signal amplification. The features of the present invention are discussed in this section.

Back to the conversion formula of the aforementioned EQ.2 band-pass filter example. (It should be noted that EQ.2 is for illustrative purposes only, and the present invention can be applied to other conversion formulas and other filtering types).

<img file="TW441164B_D0021.tif" />

Multiply the numerator by the coefficient K, and use the factor K to achieve the purpose of enlargement or reduction. K is a real number. Therefore EQ.2 can be rewritten as follows:

<img file="TW441164B_D0022.tif" />

Solving for VO can get:

<img file="TW441164B_D0023.tif" />

In the embodiment of the present invention, as defined in EQS.9 and 10, the effect of zooming can be realized by inserting a zoom module with a zoom factor K in the feedforward path of each UDF module. For example, consider the UDF module 1702 of FIG. 17. A zoom module 1790 with a zoom factor K is inserted into each feedforward path to achieve the purpose of zooming in or reducing K times. The zoom module 1790 is electrically adjustable.

Instead, the zoom factor of the zoom module 1716 is adjusted in conjunction with the zoom factor K for zooming in/out. In this embodiment, the scaling factor of the scaling module 1716 affects both the filtering operation and the enlargement/reduction operation.

It should be noted that this feature of the present invention is not essential. The amplifier is not necessarily required, and the zoom module 1790 can be omitted (or the zoom factor is set to 1).

The present invention provides amplitude adjustment. The amplitude obtained by the UDF module can be adjusted by the scaling factor of the scaling module 1716. This amplitude adjustment can be performed statically or dynamically, and is implemented electrically.

This adjustment can be controlled manually, or automatically controlled by a processor that includes software, hardware state equipment, or a combination of the two according to the control module. In some embodiments, the control module operates according to commands entered and/or issued by the user.

The amplitude characteristics of the present invention have been described in this text by using the exemplary UDF module 1702 of FIG. 17 for illustration only. The amplitude characteristics described here can be equivalently applied to other UDF modules.

7 Application example

The following sections describe applications related to the UDF module of the present invention. The present invention includes these application examples. It can be understood that the present invention is not limited to these application examples. According to the teachings of this article, people familiar with related technologies will be able to understand other equivalents, extensions, changes, deviations, etc. In particular, any application needs to use at least the frequency conversion operation and the frequency selection operation in the UDF module. These applications fall within the scope and spirit of the present invention.

7.1 Receiver

As mentioned above, referring to Figure 8, the receiver performs three main functions:

Frequency conversion 808, frequency selection 810, and amplification 812.

The embodiment of the integrated down conversion and filtering (UDF) module performs the frequency conversion operation 808 and the frequency selection module 810. In some embodiments, the frequency selection operation 810 performed by the UDF module represents input filtering at any frequency, including RF or greater frequencies. Therefore, this embodiment of the UDF module performs the main function of the receiver in addition to the amplification operation.

Therefore, the receiver of the present invention can be formed by combining the UDF module 1102 and the amplifier. As shown in Figure 30.

According to the receiver 3002, the UDF module 3006 uses the method described here to perform integrated frequency selection and conversion operations on the input signal 3004. The amplifier 3008 amplifies the output of the UDF module 1102 to generate an output signal 3010. The operation of the receiver 3002 is shown in the flowchart 3102 of FIG. 31.

In some applications, the output signal level generated by the UDF module 3006 is sufficient for the downstream programs. In this case, the amplifier is not necessary. In this example, the embodiment of the UDF module 3006 shown in FIG. 30 (which performs frequency selection and conversion, but does not perform the amplification operation) is sufficient to play the role of the receiver.

As noted above, some UDF module embodiments also perform zoom-in operations. In this embodiment, the UDF module performs the main functions of the receiver, that is, frequency conversion 808, frequency selection 810, and amplification 812. In this embodiment, a single UDF module can be used as a receiver.

As those familiar with related technologies can understand, the receiver 3002 can be implemented on an integrated circuit (IC). As discussed above, the UDF module can be executed on the IC. Depending on the application, the UDF module performs most of the functions required by the receiver. Therefore, any receiver implemented using the UDF module embodiment can be implemented on the IC. The embodiment of the present invention refers to a receiver implemented on an IC.

7.2 Other application examples

The application examples described above are for illustrative purposes only. These applications are not intended to limit the invention. According to the teachings of this article, those familiar with related technologies will be able to understand other alternative, slightly or different application examples. These alternative application examples fall within the spirit and scope of the present invention.

For example, as shown in FIGS. 52A-52C, the UDF embodiment can be used in applications related to filtering and frequency conversion (or any combination and sequence). At the same time, the UDF embodiment can be used in filtering situations with or without down conversion (in the later example, the UDF embodiment and the extension of the frequency down conversion are minimized), as shown in FIG. 52D. Furthermore, the UDF embodiment can be applied in down-conversion situations with or without filtering (in a later example, this UDF embodiment passes all frequencies), as shown in FIG. 52E.

In addition, the UDF embodiment can be applied to situations related to enlargement or reduction, as shown in FIG. 52F. It should be noted that these features of the present invention can be combined. In particular, according to the application, one or more filtering, frequency conversion, and amplification/reduction operations can be appropriately combined as needed.

8 in conclusion

Exemplary implementations of the systems and components of the present invention have been fully described herein. The execution of these examples is for illustrative purposes only and is not limited. Other implementation embodiments, such as the system and component software of the present invention and software/hardware implementation may be included in the present invention. According to the teachings herein, people familiar with related technologies will be able to understand this implementation embodiment.

Although a number of examples have been cited above for the application embodiments of the present invention, it should be noted that these examples are for illustrative purposes only and are not limited. As such, the breadth and scope of the present invention will not be limited by any of the foregoing and exemplary embodiments. It is defined by the following patent scope and equivalence.

<p>112 receiver</p><p>102 Band selection filter</p><p>114 RF spectrum</p><p>402 Band selection bandwidth</p><p>106 mixer</p><p>408 Band selection filter spectrum</p><p>420 Signal component</p><p>404 Spurious signal component</p><p>420 and 421 signal components</p><p>404A, 404B, and 404D parasitic components</p><p>404C signal component</p><p>412 Channel selection filter signal</p><p>110 Amplifier</p><p>802 transceiver</p><p>808 Frequency conversion</p><p>810 Frequency selection</p><p>812 enlarge</p><p>902 receiver</p><p>908 Frequency conversion operation</p><p>910 Zoom in</p><p>904 Input spectrum</p><p>902 receiver</p><p>906 Frequency selection operation</p><p>1002 The channel selection bandwidth is</p><p>914 Filtered signal</p><p>1102 UDF module</p><p>302, 308 Frequency selection operation</p><p>1202 Select action</p><p>1204 Frequency conversion operation</p><p>1106 Simulation input filter</p><p>1108 Frequency converter</p><p>1302 Overlapping area</p><p>1702 UDF module</p><p>1790 Zoom element</p><p>1708 Down conversion and delay module</p><p>1704 Input signal</p><p>1734A control signal</p><p>1706 Output signal</p><p>1710A, 1710B delay module</p><p>1716A, 1716B, 1716C zoom module</p><p>1722A, 1722B delay module</p><p>1950 UDF module</p><p>1908 Down conversion and delay module</p><p>1909 Zoom module</p><p>1902 node</p><p>1912 First delay module</p><p>1916 The first zoom module</p><p>1904 node</p><p>1914 Second delay module</p><p>1918 Second zoom module</p><p>1906 node</p><p>1910 Totalizer</p><p>2302 UDF module</p><p>2308 Down conversion and delay module</p><p>2324A control signal</p><p>2310 Delay module</p><p>2312 Zoom module</p><p>2316 Delay module</p><p>2502 UDF module</p><p>2506 High frequency delay module</p><p>2514 Down conversion and delay module</p><p>2518 Zoom module</p><p>2504 Input signal</p><p>2526 Down conversion module</p><p>5502 UDF module</p><p>5508 Frequency converter</p><p>5506 Down conversion and delay module</p><p>5504 Input signal</p><p>5522 Control signal</p><p>5512 Delay module</p><p>5514, 5516 zoom module</p><p>5518 Totalizer</p><p>6102 UDF module</p><p>5602 UDF module</p><p>5606 Frequency converter</p><p>5608 Down conversion and delay module</p><p>5612 Input signal</p><p>5616 switch</p><p>5618 Capacitor</p><p>5610 Output module</p><p>5612 Input signal</p><p>5804 Frequency converter</p><p>5806B, 5806C delay module</p><p>5806A down conversion and delay module</p><p>5801 switch</p><p>6002 UDF module</p><p>6008 Frequency converter</p><p>6010 Down conversion and delay module</p><p>6006 Input signal</p><p>6012, 6014, 6016 delay module</p><p>2622 UDF module</p><p>2624 Down conversion and delay module</p><p>2632 and 2634 first and second zoom modules</p><p>2636 Output sample and hold module</p><p>2652 Capacitor</p><p>2628 Charge the first delay module</p><p>2658 switch</p><p>2660 Capacitor</p><p>2606 node</p><p>2630 Second delay module</p><p>2666 switch</p><p>2668 Capacitor</p><p>2664 Capacitor</p><p>2656 Capacitor</p><p>2690A Joint Gain Module</p><p>2690B-2690G Joint Gain Module</p><p>2670 switch</p><p>2672 Capacitor</p><p>2602 node</p><p>2606 node</p><p>2614 node</p><p>2626 Totalizer</p><p>2691 switch</p><p>2692 Capacitor</p><p>5300 Alias module</p><p>5302 Universal Frequency Conversion (UFT) Module for Alternating Current</p><p>5304 Input signal</p><p>5308 switch</p><p>5310 Capacitor</p><p>5306 Control signal</p><p>5316 Analog AM bearer signal part</p><p>5320 pulse</p><p>5324 Down-conversion signal part</p><p>5326 Demodulate baseband signal</p><p>5312 Down-conversion output signal</p><p>6601 Energy conversion system</p><p>6602 Energy conversion signal module</p><p>6406 Energy conversion signal</p><p>6520 Gap generator</p><p>6524 Input signal</p><p>6526 Slit pulse</p><p>6522 Branch</p><p>6528 Inverter</p><p>6524 Input signal</p><p>6530 Oscillator</p><p>6404 EM signal</p><p>6321 Down-conversion output signal</p><p>6712 impedance</p><p>6716 input resistance</p><p>6706 Input impedance matching module</p><p>6906 inductance</p><p>6908 capacitance</p><p>6914 capacitance</p><p>6916 inductance</p><p>7938 capacitance</p><p>7920 inductance</p><p>7934 capacitance</p><p>7936 inductance</p><p>7942 Energy conversion signal</p><p>7914 switch</p><p>7918 and 7940 capacitors</p><p>7910 inductance</p><p>7912 capacitance</p><p>7904 and 7906 circuit components</p><p>7932 and 7930 circuit components</p><p>7928 resistance</p><p>7946 power source</p><p>7902 resistance</p><p>7916 Circuit element</p><p>7942 Energy conversion signal</p><p>7412 Single-ended to single-ended system</p><p>7410 Shunt storage circuit</p><p>8212 system</p><p>8210 Shunt storage circuit</p><p>9002 Circuit</p><p>9008 Control signal</p><p>19010 pulse</p><p>7001 Gate conversion module</p><p>7002 Circuit</p><p>7008 capacitance</p><p>7012 Load impedance</p><p>6802 Circuit</p><p>6806 Input oscillating signal</p><p>6808 Inverter</p><p>8314 Clock signal</p><p>8318 Energy conversion pulse</p><p>8320 aperture</p><p>8316 Energy conversion signal</p><p>8324 Clock signal</p><p>8304 RC circuit</p><p>8312 Variable voltage capacitor</p><p>8326 resistance</p><p>8302 Slot control system</p><p>8306 Inverter</p><p>8308 AND gate</p><p>8310 Actuation input</p><p>8328 Amplifier</p><p>8002 Bypass network</p><p>8004 Bypass switch module</p><p>8006 Energy conversion signal</p><p>8104 capacitance</p><p>8102 Bypass network</p><p>6608B Down-conversion signal</p><p>6404 EM signal</p><p>6406 Energy conversion signal</p><p>7104 State computer</p><p>7102 Analog-to-digital converter A/D</p><p>7106 Digital analog converter DAC</p><p>7108 Voltage controlled oscillator VCO</p><p>7110 Pulse generator</p><p>6502 Switch module</p><p>7202 Wave</p><p>7206 Wave</p><p>7802 FSK waveform</p><p>7804 Downconverting the waveform</p><p>4501 and 4503 sample and hold circuit</p><p>4508,4524 First switch</p><p>4512, 4528 second switch</p><p>4550 Clock signal</p><p>4510, 4526 capacitor</p><p>4514, 4530 capacitor</p><p>4520, 4522, 4532, 4534 integrated gain module</p><p>4516 node</p><p>1710, 1722 delay module</p><p>3204 Switched capacitor topology</p><p>1716, 1724 zoom module</p><p>1710, 1722 delay module</p><p>3404 Analog delay column</p><p>3504 Resistance reducer</p><p>3602 Resistance reducer</p><p>1720 Adder</p><p>3902 Resistance totalizer</p><p>4004 Totalizer</p><p>4102 Totalizer</p><p>1708 Down conversion and delay module</p><p>1710, 1722 delay module</p><p>1734A-1734F control signal</p><p>1790 Control signal generator</p><p>4204 Oscillator</p><p>4205 Signal shaper</p><p>4206 Signal separator</p><p>4202 Control signal generator</p><p>4208 Delay module</p><p>4210 Gap optimization module</p><p>2691 switch</p><p>2638 Output smoothing module</p><p>3002 receiver</p><p>3006 UDF module</p><p>3004 Input signal</p>

The present invention will be described with reference to the following drawings, in which:

figure 1. It is the block diagram of the conventional receiver;

figure 2. Shows a flowchart of the operation of the conventional receiver in FIG. 1;

image 3. Show the operation corresponding diagram of the conventional receiver in Fig. 1:

Figures 4A-4G show waveforms used to illustrate the operation of the conventional receiver of Figure 1;

Figure 5. Used to illustrate the method of calculating the filter quality factor;

Figure 6A-6D. Display the characteristics of different types of filters;

Figure 7A-7C. Display different types of adjustment diagrams;

Figure 8. The display is the block diagram of the receiver and the functions performed by the receiver;

Figure 9. Shows a corresponding diagram of the operation of the receiver according to the preferred embodiment of the present invention;

Figure 10A-10E. Display the waveform used to describe the operation map of Figure 9:

Figure 11. Shows a block diagram of an integrated down conversion and filtering (UDF) module according to an embodiment of the present invention;

Figure 12. Shows a block diagram of the UDF module in FIG. 11, which describes the integrated frequency selection operation and frequency conversion operation of the present invention;

Figure 13. Shows a block diagram of the UDF module in FIG. 11, which illustrates that according to an embodiment of the present invention, the frequency conversion operation is performed in priority over the frequency selection operation;

Figure 14. Describe the operation flow chart of the integrated down conversion and filtering (UDF) module according to the embodiment of the present invention;

Figure 15. Display a graph showing sample values at nodes in the sample UDF module (shown in Figure 26) under continuous time increments;

Figure 16. Show the detailed operation flow chart of implementing integrated down-conversion and filtering using the embodiment of the present invention;

Figure 17. Shows a detailed block diagram of a UDF example according to an embodiment of the present invention;

Figure 18. Shows a flow chart of the operation of performing integrated down conversion and filtering using an embodiment of the present invention, where the filtering operation includes a band-pass filtering operation;

Figure 19. Show the example execution of the operation steps in Figure 18;

Figure 20. Show a graph of sample values at the UDF module node in Figure 19 under continuous time increments;

Figure 21. Block diagram showing filter examples;

Figure 22. Shows a flow chart of the operation of performing integrated down conversion and filtering using an embodiment of the present invention, where the filtering operation includes a low-pass filtering operation;

Figure 23. Show an example of the UDF module used to execute the steps of the flowchart in Figure 22;

Figure 24. Show the operation flowchart of the midpoint introduction embodiment of the present invention;

Figure 25. Show an example of the UDF module used to perform the operation steps of the flowchart in Figure 24;

Figure 26. Show the execution example of the UDF module according to the embodiment of the present invention;

Figures 27A and 27B. Show the filter characteristics of the UDF module in Figure 26;

Figures 28A-28F and 29A-29F show the waveforms used to illustrate the UDF module in Figure 26;

Figure 30. Shows a block diagram of an example transceiver according to an embodiment of the present invention;

Figure 31. Shows a flowchart of the operation of the receiver in FIG. 30 according to an embodiment of the present invention;

Figure 32. Shows an example of a switched capacitor used to implement the delay module in the UDF module example according to the embodiment of the present invention;

Figures 33A and 33B. Display the pipe signal with two phases 1 and 2;

Figure 34. Shows an analog delay line example of a delay module used to execute the UDF module example according to an embodiment of the present invention;

Figure 35. Shows an example of a resistance attenuator used to implement a proportional module in the UDF module example according to the embodiment of the present invention;

Figure 36 shows an example of a resistive attenuator;

Figure 37. Shows an example of an amplifier capable of executing a proportional module in the UDF module example according to the embodiment of the present invention;

Figure 38. An example of an impedance totalizer capable of performing summation/addition in the UDF module example according to the embodiment of the present invention is shown;

Figure 39 shows an example of an impedance totalizer;

FIG. 40 shows an example of an OPAMP (operational amplifier) totalizer capable of performing summation/addition in the UDF module example according to an embodiment of the present invention;

Figure 41. Show the OPAMP adder example;

Figure 42. Shows an example of a control signal generator according to an embodiment of the present invention;

Figure 43A-43D. Show the signal appearing at the node in the control signal generator in Figure 42;

Figure 44. Shows an operation corresponding diagram of an example UDF module according to an alternative embodiment of the present invention;

Figure 45. Shows an example operation and hold circuit according to an embodiment of the present invention;

Figure 46. Show the flow chart of the example operation and holding circuit of Fig. 45;

Figure 47. Display the list of sampled values at the node in the sample and hold circuit in Figure 45;

Figure 48. Display the sampled two-phase clock signal used to control the switches in the sample and hold circuit of Figure 45;

Figure 49. Show the flow chart of the UDF module designed according to the embodiment of the present invention;

Figure 50. Show the detailed flow chart of the UDF module designed according to the embodiment of the present invention and its method;

Figure 51. It shows an example of the conversion formula table that can be used when the UDF module designed according to the embodiment of the present invention is used.

Figure 52A-52F. Shows an application example of the UDF module according to the embodiment of the present invention;

53A and 53A-1 show examples of alias modules according to an embodiment of the present invention;

Figures 53B-53F show examples of waveforms used to describe the operation of the alias modules in Figures 53A and 53A-1;

Figures 54A-54C show filtering-related equations related to an embodiment of the present invention;

Figure 55. Shows a block diagram of an integrated down conversion and filtering (UDF) module that implements finite impulse response (FIR) according to an embodiment of the present invention;

Figure 56. Shows a block diagram of an integrated down-conversion and filtering (UDF) module that performs real-time average filtering according to an embodiment of the present invention;

Fig. 57A shows an example of the control signal used to describe the operation of the UDF module in Fig. 56;

Fig. 57B shows an example of the filter passband used to describe the operation of the UDF module of Fig. 56;

58A and 58B show a block diagram of an integrated down conversion and filtering (UDF) module of an n-path filter according to an embodiment of the present invention;

Figure 59A-59C. Show an example of the control signal for operating the UDF module in Figure 58A;

Figure 60. Shows a block diagram of an integrated down-conversion and filtering (UDF) module for passive filtering according to an embodiment of the present invention;

Figure 61. Shows a block diagram of an example of an FIR filter according to an embodiment of the present invention;

Figure 62. Show the characteristics of the FIR filter example;

Figure 63. Shows a block diagram of a UDF module according to another embodiment of the present invention;

Figure 64A-D. Shows the execution example of the switching module according to the embodiment of the present invention;

Figure 65A-D. Show examples of gap generators;

Figure 65E. Show the oscillator according to the embodiment of the present invention:

Figure 66. Shows an energy conversion system with a selective energy conversion signal module according to an embodiment of the present invention;

Figure 67. Shows an alias module with input and output impedance matching according to an embodiment of the present invention;

Figure 68A. Show examples of pulse generators;

Figure 68B and C show waveforms related to the pulse generator of Figure 68A;

Figure 69. An example of an energy converter having a switching module and a reactive storage module according to an embodiment of the present invention is shown;

70A-B show an example of an energy conversion system according to an embodiment of the present invention;

FIG. 71A shows an example of an energy conversion signal module according to an embodiment of the present invention;

Figure 71B shows a flow chart of the operation of the statement machine according to an embodiment of the present invention;

Figure 71C shows an example of an energy conversion signal module;

Figure 72. Shows a circuit diagram of down-converting a 915MHz signal to a 5MHz signal using a 101.1MHz clock according to an embodiment of the present invention;

Figure 73. Shows the analog waveform of the circuit in FIG. 72 according to an embodiment of the present invention;

Figure 74. Shows a circuit diagram of down-converting a 915 MHz signal to a 5 MHz signal using a 101 MHz clock according to an embodiment of the present invention;

Figure 75. Shows the analog waveform of the circuit in FIG. 74 according to an embodiment of the present invention;

Figure 76. Shows a circuit diagram of down-converting a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock according to an embodiment of the present invention;

Figure 77. Shows the analog waveform of the circuit in Fig. 76 according to an embodiment of the present invention;

Figure 78. A diagram showing the circuit of Figure 72 connected to an FSK source varying between 913 and 917 MHz at a baud rate of 500 baud according to an embodiment of the present invention;

Figure 79A. An example of an energy conversion system according to an embodiment of the present invention is shown;

Figure 79B, 79C. Show the timing diagram example of the system example in Figure 79A.

Figure 80. Shows an example of a bypass network according to an embodiment of the present invention;

Figure 81. Shows an example of a bypass network according to an embodiment of the present invention;

Figure 82. Show examples of embodiments of the present invention;

Figure 83A. Shows an example of a time slot control circuit according to an embodiment of the present invention;

FIG. 83B shows a timing diagram of an example of a clock signal of a time slot control circuit according to an embodiment of the present invention;

Figure 83C. Shows a timing diagram of an example of selecting a valid signal by the slot control circuit in time according to an embodiment of the present invention;

Figure 83D. Shows a timing diagram of an example of a reverse clock signal of a time slot control circuit according to an embodiment of the present invention;

Figure 83E. Shows a timing diagram of an example of a delayed clock signal of a time slot control circuit according to an embodiment of the present invention;

Figure 83F. Shows a timing diagram of an example of energy conversion including timely control of slit pulses according to an embodiment of the present invention;

Figure 84. Show examples of embodiments of the present invention:

Figure 85. Show examples of embodiments of the present invention;

Figure 86. Show examples of embodiments of the present invention;

Figure 87. Show examples of embodiments of the present invention;

Figure 88A. Show the timing diagram of the embodiment in FIG. 84;

Figure 88B. Shows a timing diagram of the embodiment in FIG. 85;

Figure 89A. Shows a timing diagram of the embodiment in FIG. 86;

Figure 89B. Shows a timing diagram of the embodiment in FIG. 87;

Figure 90A. Show examples of embodiments of the present invention;

FIG. 90B shows an equation for determining charge conversion according to an embodiment of the present invention;

Figure 90C. Shows the relationship between the charging of the capacitor and the gap according to the embodiment of the present invention;

Figure 90D. Shows the relationship between the charging of the capacitor and the gap according to the embodiment of the present invention;

Figure 90E. Shows the relationship equation of power charging according to the embodiment of the present invention;

Figure 90F. Shows the insertion loss equation according to the embodiment of the present invention;

Figure 91. The original FSK waveform 7802 and the down-converted waveform 7804 are displayed.