Method and system for reduction of decoding complexity in a communication system
Abstract
Method and System for Utilization of an Outer Decoder in a Broadcast services Communication System is described. Information to be transmitted is provided to a systematic portion of a plurality of transmit buffers and encoded by an outer decoder communicatively coupled to the transmit buffer. The resulting redundant bits are provided to a parity portion of each transmit buffer. The content of the transmit buffers, is multiplexed and encoded by an inner decoder to improve protection by adding redundancy. The receiving station recovers the transmitted information by an inverse process. Because a decoding complexity depends on the size of a systematic portion of the transmit buffer, reasoned compromise between a systematic portion size and number of transmit buffers yields decreased decoding complexity.

Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
54 claims: 50 independent, 4 dependent
- 1一種甩於降低解碼複雜度之編碼方法,其包含:以一第一碼編碼複數個緩衝區中之每一個緩衝區內之系統性位元;多工處理該複數個緩衝區之內容;以及以一第二碼編碼該多工處理過之內容以提供一組訊框。
- 2如申請專利範圍第1項之方法,其中該等利用一第一碼編碼複數個緩衝區中之每一個緩衝區內之系統性位元包含:以一區塊碼編碼該複數個緩衝區中之每一個緩衝區內之系統性位元。
- 3如申請專利範圍第1項之方法,其中該等利用一區塊碼編碼複數個緩衝區中之每一個緩衝區內之系統性位元包含:以一里德所羅門碼編碼該複數個緩衝區中之每一個緩衝區內之系統性位元。
- 4如申請專利範圍第1項之方法,其中該以一區塊碼編碼複數個緩衝區中之每一個緩衝區內之系統性位元包含:自該等緩衝區中之每一個緩衝區接續地提供一位元區塊。
- 5如申請專利範圍第4項之方法,其中該自該等緩衝區中之每一個緩衝區接續地提供一位元區塊包含:提供一位元區塊,該位元區塊包含該複數個緩衝區中每一個緩衝區之其中一列。
- 6如申請專利範圍第1項之方法,其中該以一第二碼編碼該多工處理過之內容用以提供一組訊框包含:識別一所要予以編碼之位元區塊;以及 以一第二碼編碼該位元區塊。
- 7如申請專利範圍第6項之方法,其中該識別一所要予以編碼之位元區塊包含:識別一接收自一緩衝區之位元區塊。
- 8一種降低解碼複雜度之方法,其包含:藉由一第二解碼器解碼接收到的訊框;解多工處理正確解碼後之訊框予複數個緩衝區;以及處理該複數個緩衝區中之每一個緩衝區。
- 9如申請專利範圍第8項之方法,其中該解多工處理正確解碼後之訊框予複數個緩衝區包含:識別一屬於一緩衝區之位元區塊;以及提供該位元區塊予該緩衝區。
- 10如申請專利範圍第9項之方法,其中該識別一屬於一緩衝區之位元區塊包含:識別一位元區塊,該位元區塊包含一由第二解碼器予以解碼之訊框。
- 11如申請專利範圍第8項之方法,其中該處理複數個緩衝區中每一個緩衝區之內容包含:提供該複數個緩衝區中每一個緩衝區之系統性部分予更高層。
- 12如申請專利範圍第8項之方法,其進一步包含:若訊框未予正確解碼,則指示一清除予一電信耦接至緩衝區之解碼器,其中該緩衝區將接收正確解碼後之訊框。
- 13如申請專利範圍第12項之方法,其中該處理複數個緩衝區中每一個緩衝區之內容包含:若系統性部分可予以回復,則藉由一解碼器解碼該緩衝區之系統性部分;以及提供該複數個緩衝區中每一個緩衝區之系統性部分予更高層。
- 14一種用於降低解碼複雜度之方法,其包含:以一第一碼編碼複數個傳送緩衝區中每一個緩衝區之系統性位元;多工處理該複數個緩衝區之內容;以一第二碼編碼該多工處理過之內容以提供一組訊框;傳送該組訊框;以一第二解碼器解碼接收到之訊框;解多工處理正確解碼後之訊框予複數個接收緩衝區;以及處理每一個接收緩衝區之內容。
- 15如申請專利範圍第14項之方法,其中該以一第一碼編碼複數個傳送緩衝區中每一個緩衝區之系統性位元包含:以一區塊碼編碼複數個緩衝區中每一個緩衝區之系統性位元。
- 16如申請專利範圍第15項之方法,其中以一區塊碼編碼複數個緩衝區中每一個緩衝區之系統性位元包含:以一里德所羅門碼編碼複數個緩衝區中每一個緩衝區之系統性位元。
- 17如申請專利範圍第14項之方法,其中該多工處理複數個第一緩衝區之內容包含:自每一個緩衝區接續提供一位元區塊。
- 18如申請專利範圍第17項之方法,其中該自每一個緩衝區接續提供一位元區塊包含:提供一位元區塊,該位元區塊包含該傳送緩衝區中之一列。
- 19如申請專利範圍第14項之方法,其中該以一第二碼編碼該多工處理過之內容用以提供一組訊框包含:識別一所要予以編碼之位元區塊;以及以一第二碼編碼該位元區塊。
- 20如申請專利範圍第19項之方法,其中該識別一所要予以編碼之位元區塊包含:將該位元區塊識別成一接收自一緩衝區之位元區塊。
- 21如申請專利範圍第14項之方法,其中該解多工處理正確解碼後之訊框予複數個接收緩衝區包含:識別一屬於一緩衝區之位元區塊;以及提供該位元區塊予該緩衝區。
- 22如申請專利範圍第21項之方法,其中該識別一屬於一緩衝區之位元區塊包含:將一位元區塊識別成一包含一經由該第二解碼器予以解碼後之訊框之位元區塊。
- 23如申請專利範圍第14項之方法,其中該處理每一個接收緩衝區之內容包含: 將每一個緩衝區之系統性部分提供予更高層。
- 24如申請專利範圍第14項之方法,其進一步包含:若訊框未予正確解碼,則指示一清除予一電信耦接至接收緩衝區之第一解碼器,其中該接收緩衝區將接收正確解碼後之訊框。
- 25如申請專利範圍第24項之方法,其中該處理每一個緩衝區之內容包含:若系統性部分可予以回復,則以一第一解碼器解碼該緩衝區之系統性部分;以及提供每一個緩衝區之系統性部分予更高層。
- 26一種用於降低解碼複雜度之裝置,其包含:複數個緩衝區;複數個編碼器,該複數個編碼器中的每一個編碼器係電信耦接至該複數個緩衝區中的每一個緩衝區;一多工器,其被電信耦接至該複數個緩衝區;以及一內部編碼器,其被電信耦接至該多工器。
- 27如申請專利範圍第26項之裝置,其中該複數個緩衝區中的每一個緩衝區係經過建構以:儲存系統性位元及同位位元。
- 28如申請專利範圍第26項之裝置,其中該複數個編碼器中的每一個編碼器係經過建構以:編碼系統性位元用以提供同位位元。
- 29如申請專利範圍第28項之裝置,其中該複數個編碼器中的每一個編碼器係經過建構以: 用一區塊碼編碼該等系統性位元。
- 30如申請專利範圍第26項之裝置,其中該編碼器中的每一個編碼器係經過建構以:用一里德所羅門碼編碼該等系統性位元。
- 31如申請專利範圍第26項之裝置,其中該多工器係經過建構以:自該複數個緩衝區中的每一個緩衝區接續提供一位元區塊予該內部編碼器。
- 32如申請專利範圍第31項之裝置,其中該位元區塊包含該緩衝區中之一列。
- 33如申請專利範圍第26項之裝置,其中該內部編碼器係經過建構以:識別一所要予以編碼之位元區塊;以及用一內部碼編碼該位元區塊。
- 34如申請專利範圍第33項之裝置,其中該所要予以編碼之位元區塊包含:一位元區塊,其係接收自該多工器。
- 35一種用於降低解碼複雜度之裝置,其包含:一第一解碼器;一解多工器,其被電信耦接至該第一解碼器;複數個緩衝區,其被電信耦接至該解多工器;以及複數個解碼器,其中每一個解碼器皆電信耦接至該複數個緩衝區中之每一個緩衝區。
- 36如申請專利範圍第35項之裝置,其中該第一解碼器係經 過建構以:解碼一接收到的訊框;提供一正確解碼過之訊框;以及若接收到的訊框未予正確解碼,則指示一清除。
- 37如申請專利範圍第35項之裝置,其中該解多工器係經過建構以:識別一屬於一緩衝區之位元區塊;以及提供該位元區塊予該緩衝區。
- 38如申請專利範圍第37項之裝置,其中該屬於一緩衝區之位元區塊包含:一含有一由該第一解碼器予以解碼之訊框之位元區塊。
- 39如申請專利範圍第35項之裝置,其中該複數個解碼器中的每一個解碼器係經過建構以:在系統性部分可予以回復時,藉由一外部解碼器解碼該緩衝區之系統性部分。
- 40如申請專利範圍第35項之裝置,其中該複數個緩衝區中的每一個緩衝區係經過建構以:將系統性部分提供予更高層。
- 41一種用於降低解碼複雜度之裝置,其包含:複數個傳送緩衝區:複數個編碼器,其中每一個編碼器皆電信耦接至該複數個傳送緩衝區中的每一個緩衝區;一多工器,其被電信耦接至該複數個傳送緩衝區;一內部編碼器,其被電信耦接至該多工器; 一第一解碼器;一解多工器,其被電信耦接至該第一解碼器;複數個接收緩衝區,其被電信耦接至該解多工器;以及複數個解碼器,其中每一個解碼器皆電信耦接至該複數個接收緩衝區中的每一個緩衝區。
- 42如申請專利範圍第41項之裝置,其中該複數個傳送緩衝區係經過建構以:儲存系統性位元及同位位元。
- 43如申請專利範圍第41項之裝置,其中該複數個編碼器中的每一個編碼器皆經過建構以:編碼系統性位元用以提供同位位元。
- 44如申請專利範圍第43項之裝置,其中該複數個編碼器中的每一個編碼器皆經過建構以:用一區塊碼編碼該等系統性位元。
- 45如申請專利範圍第41項之裝置,其中該複數個編碼器中的每一個編碼器皆經過建構以:用一里德所羅門碼編碼該等系統性位元。
- 46如申請專利範圍第41項之裝置,其中該多工器係經過建構以:自該等傳送緩衝區中的每一個緩衝區接續提供一位元區塊予該內部編碼器。
- 47如申請專利範圍第46項之裝置,其中該位元區塊包含該緩衝區中之一列。
- 48如申請專利範圍第41項之裝置,其中該內部編碼器係經過建構以:識別一所要予以編碼之位元區塊;以及用一內部碼編碼該位元區塊。
- 49如申請專利範圍第48項之裝置,其中該所要予以編碼之位元區塊包含:一接收自該多工器之位元區塊。
- 50如申請專利範圍第41項之裝置,其中該第一解碼器係經過建構以:解碼一接收到的訊框;提供一正確解碼後之訊框;以及若接收到的訊框未予正確解碼,則指示一清除。
- 51如申請專利範圍第41項之裝置,其中該解多工器係經過建構以:識別一屬於一緩衝區之位元區塊;以及提供該位元區塊予該緩衝區。
- 52如申請專利範圍第51項之裝置,其中該屬於一緩衝區之位元區塊包含:一含有由該第一解碼器予以解碼之訊框之位元區塊。
- 53如申請專利範圍第41項之裝置,其中該複數個解碼器中的每一個解碼器皆經過建構以:若系統性部分可予以回復,則藉由一外部解碼器解碼該緩衝區之系統性部分。
- 54如申請專利範圍第41項之裝置,其中該複數個緩衝區中 之每一個緩衝區皆經過建構以:將該緩衝區之系統性部分提供至更高層。
Independent claims54
59 paragraphs, as filed
Method and system for reducing decoding complexity in communication system
Background of the invention
field
The present invention relates to a communication system. More particularly, the present invention relates to a system and method for reducing decoding complexity in a communication system.
background
Communication systems have been developed to enable information signals to be transmitted from a source station to a physically distinguished target station. When transmitting an information signal from a source station through a signal channel, the information signal is first converted into a format suitable for effective transmission through the communication channel. The conversion or modulation of the information signal includes changing the parameters of the carrier according to the information signal, and the conversion or modulation method makes the carrier generated by the modulation limited to the bandwidth of the communication channel. At the target station, the original information signal is copied from the modulated carrier received through the communication channel. This replication is generally achieved through the opposite modulation process used by the originating station.
Modulation also facilitates multi-directional proximity, that is, transmitting and/or receiving many signals simultaneously through a common communication channel. A multi-directional proximity communication system usually includes a plurality of subscriber units, which require intermittent services with a short duration rather than continuous access to the same communication channel. There are many multi-directional proximity techniques known in the art, such as time-sharing multi-directional proximity (TDMA), frequency division multi-directional proximity (FDMA), and amplitude modulation multi-directional proximity (AM). Another type of multi-directional proximity technology is the code division multi-directional proximity (CDMA) spread spectrum system, which complies with "TIA/EIA/IS-95 mobile station-base station compatibility for dual-mode broadband spread spectrum cellular systems Standard", later regarded as IS-95 standard. The use of CDMA technology in the multi-directional proximity communication system is disclosed in U.S. Patent No. 4,901,307 entitled "Use Spread-spectrum multi-directional proximity communication system using artificial satellites or terrestrial repeaters" and US Patent No. 5,103,459 titled "System and Method for Waveform Generation in CDMA Cellular Telephone System", both of which have been assigned To the assignee of the present invention.
A multi-directional proximity communication system can be wireless or wired and can carry voice and/or data. An embodiment of a communication system carrying voice and data at the same time is a system based on the IS-95 standard. The IS-95 standard details the transmission of voice and data through a communication channel. A method for transmitting data with a fixed size of the encoding channel frame is described in detail in U.S. Patent No. 5,504,773, entitled "Method and Apparatus for Transmitting Data Format", which is assigned to the recipient of the present invention. Let people. According to the IS-95 standard, the data or sound system is divided into 20 millisecond wide data rate as high as 14.4 Kbps encoding channel frame. Examples of additional communication systems that carry voice and data at the same time include the "3rd Generation Mobile Communication Partnership Project" (3GPP) included in a set of documents including document number 3G TS 25.211, 3G TS 25.212, 3G TS 25.213, and 3G TS 25.214 (W-CDMA standard), or "TR-45.5 physical layer standard for cdma2000 spread spectrum system" (IS-2000 standard).
The one-only data communication system embodiment is a high data rate (HDR) communication system that complies with the TIA/EIA/IS-856 industry standard, which is then regarded as the IS-856 standard. The HDR system is based on a communication system that was disclosed in the application titled "Method and Apparatus for High-speed Packet Data Transmission", which was included on November 3, 1997 and assigned to the assignee of the present invention ( co-pending) Patent Case Serial No. 08/963,386. The HDR communication system defines a set of data rates ranging from 38.4 kbps to 2.4 Mbps, and an access point (AP) can use this set of rates to send data to the user station (access point, AT). Since AP is similar to base station, it is similar to unit cell and sector. The related terminology is the same as the related terminology of sound system.
In a multi-directional proximity communication system, communication between users is conducted through one or more base stations. A first user at a user station connects to a second user at a second user station by transmitting data on a reverse link to the base station. The base station receives the data and can forward the data to another base station. The data is on the same base station, or other base stations, and is sent to the second user station on the previous link. Forward connection means transmission from a base station to a user station and anti-forward connection means transmission from a user station to a base station. Similarly, communication can be conducted between a first user at a user station and a second user at a landline station. A base station receives data from a user on a reverse link, and forwards the data to a second user via a public switched telecommunication network (PSTN). In many communication systems, such as IS-95, W-CDMA, IS-2000, the forward link and the reverse link are configured with different frequencies.
The above-mentioned wireless communication service is an embodiment of a point-to-point communication service. In contrast, broadcast services provide point-to-multipoint communication services. The basic mode of the broadcasting system consists of a user broadcasting network served by one or more central stations. The broadcasting network transmits information with specific content to users, such as news, movies, sports events, and vice versa. kind. The subscriber station of each broadcast network user monitors a common broadcast forward link signal. Since the central station determines the content fixedly, users usually cannot communicate back. Examples of common broadcast service communication systems include television broadcasting, radio broadcasting, and the like. These communication systems are generally highly specialized communication systems. Recently, advances in wireless cellular telephone systems have made use of the existing broadcast service infrastructure-mainly The trend of point-to-point cellular telephone systems. (As used herein, the term "cellular" system includes communication systems that utilize both mobile phones and PCS frequencies.) The information signals to be exchanged between endpoints in a communication system are usually organized into multiple packets. To illustrate, a packet is a group of bytes arranged in a specific format, which includes data (information column) and control elements. These control elements include, for example, cyclic redundancy check (CRC), parity bits, and other metric formats known to the bank. The packet is then formatted according to the communication channel architecture to fit the frame. The signal frame transmitted between the source and target after proper modulation is affected by the characteristics of the communication channel, such as signal-to-noise ratio, attenuation, time variation, and other similar characteristics. These characteristics respectively affect the modulated signal in different communication channels. Therefore, the consideration required for the transmission of the modulated signal through a wireless communication channel is different from the transmission of the modulated signal through a wired communication channel such as a coaxial cable or an optical cable. In addition to selecting a modulation suitable for a specific communication channel, other methods for protecting information have been devised. These methods include, for example, numbering, repetition of symbols, staggered arrangement, and other methods known to the people in the industry. However, these methods add additional information. Therefore, an engineering compromise must be made between the reliability of information signal transmission and the amount of additional information. Even with the above-mentioned protection of information signals, the status of the communication channel will still be attenuated to the point where the target station cannot decode (clear) some packets. In a data-only communication system that allows communication from the target end to the source end to give feedback, one solution is to use the automatic repeat request (ARQ) made by the target station to retransmit non-decoded packets. However, under certain conditions, ARQ can overload the communication system. In addition, as stated in the broadcast communication system, these users did not connect back to the base station. Therefore, other information protection methods are needed.
1. The application serial number No. 09/933,912 included in the application titled "Method and System for Utilizing External Decoder in Broadcasting Service Communication System" was transferred to the assignee of the present invention on August 20, 2001, as detailed in the broadcast The use of external decoders in the system. As stated in the application serial number 09/933,912, the information bit stream to be transmitted is first encoded by an external decoder and then encoded by an internal encoder. As shown in FIG. 1, from a higher layer, the information bit stream 102 to be transmitted is sent to a transmission buffer 104. The transmission buffer is depicted in more detail in FIG. 2. Referring to FIG. 2, the bits fill the systematic portion 204(1) of the transmit buffer 104 (of FIG. 1) from left to right, row by row. The systematic part 204(1) contains k columns 208 of length L. 1, once the systematic part 204(1) (of FIG. 2) is filled, the external block encoder 106 is activated to encode the bits in the systematic part 204(1) (of FIG. 2) in a straight line orientation to Generate (nk) (Figure 2) additional parity row 210. This straight-line orientation is executed line by line for the binary outer code, that is, m=1. For non-binary codes, that is, m>1, every m adjacent rows in the same column are regarded as an m-bit symbol. The m-bit symbols along the top k columns are read by an external encoder to generate nk m-bit symbols filling the corresponding lower nk columns in these rows.
The external encoder includes, for example, a systematic Reed-Solomon (RS) encoder. Referring back to FIG. 1, the content of the transmission buffer 104 is then sent to a physical layer 108. At the physical layer 108, the individual frames are encoded by an internal encoder (not shown), which generates the encoded frames. The architecture of the internal encoder can be a well-known architecture to those in the industry. The systematic rows and the same bit rows of the buffer can be interleaved during transmission to reduce a large number of systems The performance lists the chance of being cleared when the total number of internal codes cleared exceeds the external code correction performance. These frames are further processed according to the selected modulation architecture, such as cdma2000, WCDMA, UMTS, and other modulation architectures known to the industry. The processed frame is then transmitted through a communication channel 110.
The transmitted frame is received at the target station and sent to a physical layer 112. At the physical layer 112, the individual frames are demodulated and sent to an internal decoder (not shown). The internal decoder decodes each frame, and if the decoding is successful, it outputs a correctly decoded frame; or if the decoding is unsuccessful, it clears it. The success or failure of decoding must be judged with high accuracy. The high-accuracy decision is made by, for example, including a long (for example, 16-bit) cyclic redundancy check (CRC) in the frame after the external encoding and before the internal encoding. Be reached. The CRC contained in the decoded frame is compared with a CRC calculated from the bits of the decoded frame. If the two CRCs are exactly the same, the decoding is declared successful.
If the internal decoder is unable to decode the frame, the decoder declares clear and instructs the external block decoder 116 that the frame is disappearing. This process continues until the parity field is correctly received and transferred to the parity portion 114(2) of the receiving buffer 114 as many symbolic frames as cleared. The receiver stops receiving any remaining frames and an external decoder (not shown) is activated to restore the cleared systematic frames. The restored systematic frame is sent to a higher layer.
It is well known in the industry that the complexity of decoding/error correction calculation increases as the number of columns in the transmission buffer 104 increases. Since the computational complexity of decoding/error correction affects the hardware complexity and power consumption of the receiving end, there are The need for methods and systems.
Summary of the invention
The specific embodiment disclosed here meets the above requirements by providing a method of using an external code to encode systematic bits in each of a plurality of buffers and a system for executing the method; The content of the buffer; and the multiplexed content is encoded by an external code to provide a set of frames.
In another aspect of the present invention, the received frame set is decoded by an internal decoder; the correctly decoded frames are demultiplexed into a plurality of buffers; and each buffer is The content is processed further. If the systematic part of a buffer has been decoded correctly; then the process includes providing the content of the systematic part to a higher layer. Or, if it is determined that the external decoder decodes the systemic part of the buffer content, then the external decoder is activated and the returned content is sent to the higher layer along with the systemic part of the content correctly received.
Figure 1 depicts the prior art physical layer processing process;
Figure 2 depicts a transmission buffer;
Figure 3 depicts a physical layer processing process according to a specific embodiment of the present invention;
Detailed description of the invention
definition
The word "exemplary" is used herein to mean "acting as an embodiment, example, or description." Any specific embodiment described herein as "exemplary" is not necessarily inferred to be better or more advantageous than other specific embodiments.
The term point-to-point communication is used here to mean a kind of communication between two user stations through a dedicated communication channel.
The term broadcast communication or point-to-multipoint communication is used here to mean a type of communication in which a plurality of user stations simultaneously receive communication from a source.
The predicate packet is used here to mean a group of bits arranged in a specific format, including data (information column) and control elements. These control elements include, for example, a front column, a quality metric system, and other kinds of frames known to the people in the bank. The quality metric system includes, for example, a cyclic redundancy check (CRC), parity bits, and other frames known to the industry.
The term access network is used here to mean a collection of base stations (BS) and one or more base station controllers. Access the network to transmit data packets between multiple user stations. The access network can be further connected to additional networks outside the access network, such as the company's internal network or the Internet, and can transmit data packets between an access terminal and these external networks.
The predicate base station is used here to mean the hardware with which the user station communicates. Unit cell means hardware or geographic coverage area, depending on the context in which the term is useful. The segment is the division of the unit cell. Since the segment has the attribute of a unit cell, these unit cell technologies can be easily extended to the segment.
The predicate user station here is used to refer to the hardware that accesses the network and communicates with it. A user station can be mobile or localized. A user station can be any data device that communicates via a wireless channel or via a wired channel such as optical fiber cable or coaxial cable. A user station can further be any of many types of devices including but not limited to PC cards, compact flash memory, external or internal modems, or wired or wireless telephones. One is and one base station is established The subscriber station in the active telecommunication channel connection process is said to be in the connection establishment state. A user station that has established an active telecommunication channel connection with a base station is called an active user station, and is said to be in a transmission state.
The predicate physical channel is used here to mean a kind of communication wire, in which a signal is transmitted through the communication wire in terms of modulation characteristics and coding.
The predicate logic channel is used here to mean a communication wiring located in the communication protocol layer of the base station or user station.
The predicate communication channel/link is used here to mean a physical channel or a logical channel depending on the context.
The term reverse channel/connection is used here to mean a communication channel/connection through which the user station sends signals to the base station.
The forward channel/link is used here to mean a communication channel/link through which a base station sends a signal to a user station.
The term soft handover is used here to mean a communication between a user station and two or more sections, where each section belongs to a different unit cell. The anti-link communication is received by two sections, and the front link communication is carried on the forward link of two or more sections at the same time.
The term soft handover is used here to mean a communication between a user station and two or more sections, where each section belongs to the same unit cell. The reverse link is received by two sections, and the forward link communication is carried on one of the links of two or more sections at the same time.
The predicate removal is used here to mean that the message recognition has failed.
The predicate dedicated channel is used here to mean a channel modulated by information specific to individual user stations.
The predicate shared channel is used here to mean a channel modulated by information shared between all user stations.
The predicate entity layer is here specifically used to refer to the part of the communication protocol between a source and a target. The function of this part is to send and receive data. The physical layer corresponds to layer 1 of the Open System Interconnection in the International Standards Organization model.
The higher layer of the predicate is used here exclusively to mean the part of the communication protocol between an originating end and a target end on the physical layer. These higher layers correspond to layers 2 to 7 of the International Standards Organization model for open system interconnection.
illustrate
According to a specific embodiment of the present invention, as shown in FIG. 3, the information bit stream 302 to be transmitted from a higher layer is demultiplexed and sent to the transmission buffer 304(i). The bits fill the systematic portion 306(1) of the transmit buffer 304(1) row by row from left to right. The systematic part 306(1) contains k columns of length L. In a specific embodiment, the length L of the buffer corresponds to the length of the wireless field with additional information (such as the CRC that helps the internal decoder and the tail element for the internal encoder). Once the systematic portion 306(1) of the buffer 304(1) is full, the procedure is repeated for the remaining transmission buffers 304(2)-304(p). Once the systematic part 306(i) of the transmission buffer 304(i) is full, the external block encoder 310(i) is activated to encode the bits in the systematic part 306(i) in a straight-line orientation to generate (nk) The additional parity row 308(i). This straight-line orientation is executed line by line for the binary outer code system, that is, m=1. For non-binary codes, that is, m>1, every m adjacent rows in the same column are regarded as an m-bit symbol. The m-bit symbols along the top k columns are from the outside The encoder reads it to generate nk m-bit symbols that fill the corresponding lower nk columns in these rows.
In another embodiment, the length L of the buffer is equal to the number of wireless frame bits without additional information divided by the code size m of the external decoder. In this specific embodiment, the first group of m rows from the transmission buffer 304(i) are sent out in the first wireless frame, and the second group of m bit rows are sent out in the second wireless frame. Send out until the entire buffer transfer is complete. Once the systematic part 306(1) of the transmission buffer 304(1) is filled, the procedure is repeated for the remaining transmission buffers 304(2)-304(p). Once the systematic part 306(i) of the transmission buffer 304(i) is filled, the external block encoder 310(i) is activated to encode the bits in the systematic part 304(i) to generate m(nk) additional parity bit row 308(i). The straight-line orientation operation is performed line by line for the two-digit external code, that is, m=1. For non-binary codes, that is, m>1, one m-bit symbol is formed for every m columns in a row. The k symbols from the top km column in the row are read by an external encoder to generate (nk) filled m-bit symbols corresponding to the lowest m(nk) column in the row.
In a specific embodiment, the external encoder 310(i) includes a systematic Reed Solomon (RS) encoder. The contents of the transmission buffer 304(i) are then sent to a multiplexer 312. The multiplexer 312 loops through the transmission buffers 304(l)-304(p), and selects a subsequent transmission after a bit block containing a predetermined number of bits has been sent from a previous buffer 304(il) Buffer 304(i). In a specific embodiment, the predetermined number of bits in a block is equal to L. The countermeasures tend to evenly allocate data corruption caused by the interference of the physical channel 316 between the buffers 304(i). However, people in the bank understand that other multi-tasking countermeasures can be applied equally Application, and can be used without departing from the scope of the present invention. The multiplexed bit block is sent to the physical layer 314 of the originating end. At the physical layer 314, additional additional information bits (such as CRC check codes) are added to each bit block, and the resulting structure is encoded by an internal encoder (not shown), which generates Frame after encoding. The architecture and multiplexer of the external and internal encoders can be, for example, the architecture of FIG. 3. These frames are further processed according to the selected modulation architecture. In a specific embodiment, the processing is performed according to the IS-2000 standard. The processed frame is then transmitted through a communication channel 316.
The transmitted frame is received at the target station (not shown) and sent to the physical layer 318 at the target station. At the physical layer 318, individual frames are demodulated and sent to an internal decoder (not shown). In a specific embodiment, the internal decoder decodes each frame, and if the decoding is successful, it outputs a correctly decoded frame; or if the decoding is unsuccessful, it declares clear. The success or failure of decoding must be judged with high accuracy. In a specific embodiment, the accuracy is achieved by including a long (for example, 16 bits) cyclic redundancy check (CRC) in the frame after the outer encoding and before the inner encoding as described above. However, we recognize that other mechanisms for frame quality indication can be used. The CRC contained in the decoded frame is compared with the CRC calculated from the bits of the decoded frame, and if the two CRCs are exactly the same, the decoding is declared successful. Further processing at the physical layer continues according to the result determined by the internal decoder.
The correctly decoded frame is sent to a demultiplexer 320, and the demultiplexer 320 uses a method that is inverse to the method used in multiplexing to allocate the receiving delay. The frame after correct decoding in the flush area 322(i). If all systematic k frames are correctly decoded by the internal decoder for a specific receive buffer 322(i), then these systematic signals from the systematic part 324(i) of the receive buffer 322(i) The box is sent to a higher level.
If the internal decoder is unable to decode the frame, the decoder declares clear and instructs the demultiplexer 320 that the frame is disappearing. The demultiplexer 320 sends the information to the external block decoder 328(i) telecommunication coupled to the receiving buffer 322(i), where the frame belongs to the receiving buffer 322(i). The process continues until the systematic part 324(i) and parity part 326(i) of the receiving buffer 322(i) accumulate enough systematic frames and correctly received parity frames, or until the receiving buffer 322(i) ) Fill up. Then start an external decoder (not shown) to restore the cleared systemic frame. The systemic frames after these responses are sent to higher layers.
If the total number of correctly received frames in the receive buffer 322(i) is less than k, according to a specific embodiment, the external decoder is not activated because the decoding is not guaranteed to succeed. The systematically received frame and the identification of the missing bits are sent to the higher layer. In another embodiment, the receiver uses the decoded bits from the internal decoder (such as the decoded bits indicated by the failed CRC check to be unreliable) to recover the systematic bits. According to a specific embodiment, the receiver decodes the unreliable bits from the internal decoder and finds the most approximate character code. In another embodiment, the receiver uses the measurement of the signal quality of the frame cleared in the buffer to select the frame with the highest signal-to-noise ratio and sufficient error to form a sub-buffer with k rows . The receiver then performs bit inversion (at the same time in a row, the bit with a value of 0 is changed to a value of 1, and vice versa) and checks whether the bit inversion is within the word code. In a specific embodiment, the bit Meta-inversion is performed on the lowest reliability bit first and continues in the order of increasing reliability. The reliability of a bit can be judged based on the internal decoding metric system, for example, the signal-to-noise and interference ratio during frame transmission, such as Yamamoto metric, re-encoding symbol error rate, re-encoding energy metric, and others The metric system known to the bank, or a combination of these metric systems. If the word code is not found, continue bit inversion through all remaining rows for all unreliable columns. If the character code is not found, continue bit inversion with an increasing number of bit inversions (that is, change 2 bits at a time, then 3 bits, up to the maximum number of bits) until the character code is found or all combinations are completed. In another specific embodiment, the CRC from the unreliable list is used to verify the success of the entire decoding in this case. These frames are sent to the higher layer only when the CRC from all the rows match; otherwise, only the bits from the reliable row are sent to the higher layer.
In order to improve the reliability of decoding, in another specific embodiment, demodulation and internal decoding are performed on correctly received frames in more than k buffers. According to another specific embodiment, demodulation and internal decoding are performed on all frames in the buffer. In these two specific embodiments, the external decoding is performed on the k (or km) column with the highest quality. The quality can be determined based on the internal decoding metric system, such as the signal-to-noise and interference ratio during frame transmission, such as Yamamoto metric system, re-encoding symbol error rate, re-encoding energy metric system, and other metric systems known to the industry, or such A combination of the metric system. The use of the quality metric system for quality estimation is disclosed in detail in U.S. Patent No. 5,751,725 titled "Method and Apparatus for Determining Receiving Data Rate in Variable Rate Communication System" and U.S. Patent No. 5,774,496 titled "Communication Receiver" Method and device for determining the data rate for transmitting variable rate data", the above two The patent case is assigned to the assignee of the invention.
The person of the bank will recognize that the number of the sending buffer 304 is a trade-off between the additional information in processing and the potential data loss, and the receiving buffer 322 is also the same. The small k value that leads to more transmit/receive buffers increases the additional information in processing. On the other hand, the large value of k that results in fewer transmission/reception buffers increases the size of the transmission buffer, which removes large data blocks when the contents of the transmission buffer cannot be recovered because the cleared rows exceed (nk) rows. The large transmission buffer size also increases the memory requirements of the target.
We understand that information and signals can be represented by any of a variety of different technologies and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be used voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any of the above The group gives to show.
Those skilled in the art can further understand that the various descriptive logic blocks, modules, circuits, and algorithm steps connected to the specific embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly describe the interchangeability between hardware and software, various descriptive elements, blocks, modules, circuits, and steps have generally been described in terms of their functions as described above. The realization of the function as a hardware or a soft system depends on the specific application and design constraints required by the entire system. The professionals in the industry can implement the required functions in various ways for each specific application, but the judgment of the implementation should not be interpreted to depart from the scope of the present invention.
The various descriptive logic blocks, modules, and circuits described in the specific embodiments disclosed herein can be connected to general-purpose processors, digital signal processors (DSP), Application-specific integrated circuit (ASIC), programmable field gate array (FPGA) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any device designed to perform the functions described herein The combination is realized or executed. A general-purpose processor can be a microprocessor, but for other options, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a computing element, such as a combination of a DSP and a microcontroller, a plurality of microprocessors, one or more microprocessors connected to the DSP core, or any other combination of such structures.
The steps of the method or algorithm described in connection with the specific embodiments described herein can be directly embodied in hardware, a software module executed by a processor, or a combination of the two. The software module can be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, scratchpad, hard disk, removable disk, CD-ROM, or known in the art Any other form of storage media. An exemplary storage medium is coupled to the processor, and the processor can read information formats from the storage medium and write information into the storage medium. In another option, the storage medium can be integrated into the processor. The processor and storage medium can be placed in an ASIC. ASIC can be attributed to a user side. In another option, the processor and the storage medium may be discrete components in a user terminal.
The foregoing descriptions of the disclosed specific embodiments are used to enable those in the industry to make or use the present invention. Various modifications made to these specific embodiments will soon be apparent to those skilled in the art, and the derivative principles defined here can be applied to other specific embodiments without departing from the spirit or scope of the present invention. Therefore, it is not intended to limit the present invention to the specific embodiments shown here, but It is hoped that the broadest category is consistent with the principles and novel features disclosed here.
A part of the disclosure of this patent document contains subject matter subject to copyright protection. The copyright owner has no objection to this patent document or the copying made by anyone disclosed by the patent, because this patent case is displayed in the patent files or records of the Patent and Trademark Office. In addition, all matters related to copyright are reserved.
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33 members in 12 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 09976591 | United States of America | – | |
| 97659101 | United States of America | A | |
| 97659101 | United States of America | A | |
| 20010976591 | – | – | – |
| US20010976591 | – | – | – |
Members33
| Document | Office | Kind | |
|---|---|---|---|
| US2003072384A1 | United States of America | A1 | |
| WO03034598A2 | World Intellectual Property Organization (WIPO) | A2 | |
| AU2002342013A1 | Australia | A1 | |
| WO03034598A3 | World Intellectual Property Organization (WIPO) | A3 | |
| TW569544BThis record | Taiwan Province of China | B | |
| KR20040041687A | Republic of Korea | A | |
| EP1435134A2 | European Patent Office (EPO) | A2 | |
| CN1602588A | China | A | |
| JP2005532701A | Japan | A | |
| BR0213215A | Brazil | A | |
| KR100892891B1 | Republic of Korea | B1 | |
| JP4274942B2 | Japan | B2 | |
| US7649829B2 | United States of America | B2 | |
| US2010107041A1 | United States of America | A1 | |
| EP1435134B1 | European Patent Office (EPO) | B1 | |
| AT470994T | Austria | T | |
| ATE470994T1 | Austria | T1 | |
| DE60236677D1 | Germany | D1 | |
| CN101848064A | China | A | |
| EP2239856A2 | European Patent Office (EPO) | A2 | |
| CN101867448A | China | A | |
| EP2242181A2 | European Patent Office (EPO) | A2 | |
| US2010272124A1 | United States of America | A1 | |
| EP2242181A3 | European Patent Office (EPO) | A3 | |
| EP2239856A3 | European Patent Office (EPO) | A3 | |
| CN1602588B | China | B | |
| CN101867448B | China | B | |
| EP2242181B1 | European Patent Office (EPO) | B1 | |
| EP2239856B1 | European Patent Office (EPO) | B1 | |
| ES2402472T3 | Spain | T3 | |
| CN101848064B | China | B | |
| US8713400B2 | United States of America | B2 | |
| US8730999B2 | United States of America | B2 |
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| Annulment or lapse of patent due to non-payment of feesLapsedMM4A | MM4A | |
| Issue of patent certificate for granted invention patentGrantedGD4A | GD4A |
Numbers
- Publication
- 569544
- Publication, DOCDB
- 569544
- Publication, EPODOC
- TW569544B
- Application
- 91123466
- Application, DOCDB
- 91123466
- Application, EPODOC
- TW200291123466
Titles4
- Chinese
- 於通信系統中降低解碼複雜度之方法與系統
- English
- METHOD AND SYSTEM FOR REDUCTION OF DECODING COMPLEXITY IN A COMMUNICATION SYSTEM
- Unlabeled
- 於通信系統中降低解碼複雜度之方法與系統
- Unlabeled
- Method and system for reducing decoding complexity in communication system
Classification
- CPC, 8
- H04L1/0057
- H04L27/26
- H03M13/2909
- H03M13/293
- H03M13/2936
- H04L1/0041
- H04L1/0045
- H04L1/0066
- IPC, 4
- H03M13 29
- H03M13 15
- H04J3 00
- H04L1 00