EP2242181B1

Concatenated encoding and decoding for multilayer communication protocol

Abstract

This record has no abstract on file.

EP2242181B1, drawing sheet 1
Sheet 1 of 3

Term

Term ended

Expired 8 October 2022, 4 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

16 claims: 6 independent, 10 dependent

  1. 1
    An encoding method, the method comprising:encoding systematic bits stored in a systematic buffer portion (306) of each of a plurality of buffers (304) with a first code to generate parity bits;multiplexing content of the plurality of buffers (304) to provide multiplexed blocks of bits;adding respective error detection bits to each block of bits of multiplexed blocks of bits;encoding said multiplexed content and the error detection bits with a second code to provide a set of frames;wherein said content in each of the plurality of buffers comprises: said systematic bits stored, in said systematic buffer portion (306) of each of the plurality of buffers;and said parity bits stored in a parity buffer portion (308), said parity buffer portion distinct from said systematic buffer portion (306) of each of the plurality of buffers;and wherein said multiplexing is performed directly on the content in said plurality of buffers.
  2. 4
    The method claimed in claim 1 wherein said encoding said multiplexed content with said second code to provide a set of frames comprises:identifying a block of bits to be encoded;and encoding the block of bits with said second code, and wherein said identifying a block of bits to be encoded preferably comprises: identifying a block of bits received from a buffer.
  3. 5
    A method, comprising:encoding systematic bits stored in a systematic buffer portion (306) of each of a plurality of transmit buffers (304) with an first code to generate parity bits;multiplexing content of the plurality of transmit buffers (304) to provide multiplexed blocks of bits;adding respective error detection bits to each block of bits of multiplexed blocks of bits;encoding said multiplexed content and the error detection bits with a second code to provide a set of frames;transmitting the set of frames;decoding received frames by a second decoder;de-multiplexing correctly decoded frames to a plurality of receive buffers (322);and processing content of each of the plurality of receive buffer, said content of each receive buffer including systematic portion (324) and parity portion, wherein said content in each of the plurality of transmit buffers (304) comprises said systematic bits stored in said systematic buffer portion (306) of each of the plurality of buffers, and said parity bits stored in a parity buffer portion (308), said parity buffer portion distinct from said systematic buffer portion (306) wherein said multiplexing is performed directly on the content in said plurality of transmit buffers (304) of each of the plurality of buffers.
  4. 9
    An encoding apparatus, comprising:a plurality of buffers (304);a plurality of encoders (310), each of said plurality of encoders being communicatively coupled to one of said plurality of buffers for encoding systematic bits stored in a systematic buffer portion (306) of the respective buffer to generate parity bits;a multiplexer (312) communicatively coupled to said plurality of buffers for multiplexing content of the plurality of buffers to provide multiplexed blocks of bits;means (314) for adding respective error detection bits to each block of bits of multiplexed blocks of bits;and an inner encoder communicatively coupled to said multiplexer (312) for encoding said multiplexed content and the error detection bits, wherein said content in each of the plurality of buffers comprises: said systematic bits stored in said systematic buffer portion (306) of each of the plurality of buffers;and said parity bits stored in a parity buffer portion (308), said parity buffer portion distinct from said systematic buffer portion (306) of each of the plurality of buffers;and wherein said multiplexing is performed directly on the content in said plurality of buffers.
  5. 12
    An apparatus, comprising a plurality of transmit buffers (304);a plurality of encoders (310), each of said plurality of encoders being communicatively coupled to one of said plurality of transmit buffers for encoding systematic bits stored in a systematic buffer portion (306) of the respective transmit buffer to generate parity bits;a multiplexer (312) communicatively coupled to said plurality of transmit buffers for multiplexing content of the plurality of transmit buffers to provide multiplexed blocks of bits;means (314) for adding respective error detection bits to each block of bits of multiplexed blocks of bits;an inner encoder communicatively coupled to said multiplexer for encoding said multiplexed content and the error detection bits;a first decoder;a de-multiplexer (320) communicatively coupled to said first decoder;a plurality of receive buffers (322) communicatively coupled to said demultiplexer, wherein content of each receive buffer includes systematic portion and parity portion;and a plurality of decoders (328), each of said plurality of decoders being communicatively coupled to one of said plurality of receive buffers, wherein said content in each of the plurality of transmit buffers (304) comprises said systematic bits stored in said systematic buffer portion (306) of each of the plurality of buffers, and said parity bits stored in a parity buffer portion (308), said parity buffer portion distinct from said systematic buffer portion (306) of each of the plurality of buffers wherein said multiplexing is performed directly on the content in said plurality of transmit buffers (304).
  6. 16
    A memory encoded with codes for executing instruction to cause a processor to perform the steps of any of claims 1 to 8.