EP1435134A2

Method and system for reduction of decoding complexity in a communication system

Abstract

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Projected expiry passed 8 October 2022, 4 years ago.

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54 claims: 14 independent, 40 dependent

  1. 1
    Claims of equivalent WO 03034598 A2 CLAIMS 1. An encoding method for reducing decoding complexity, the method comprising:encoding systematic bits in each of a plurality of buffers with a first code;multiplexing content of the plurality of buffers;and encoding said multiplexed content with as second code to provide a set of frames.
  2. 5
    The method claimed in claim 4 wherein said providing a block of bits successively from each of the plurality of buffers comprises:providing a block of bits comprising a row of each of the plurality of buffers.
  3. 6
    The method claimed in claim 1 wherein said encoding said multiplexed content with an second code to provide a set of frames comprises:identifying a block of bits to be encoded;and encoding the block of bits with a second code.
  4. 7
    The method claimed in claim 6 wherein said identifying a block of bits to be encoded comprises:identifying a block of bits received from a buffer.
  5. 8
    A method reducing decoding complexity, comprising:decoding received frames by an second decoder;de-multiplexing correctly decoded frame to a plurality of buffers;and processing content of each of the plurality of buffers.
  6. 14
    A method for reducing decoding complexity, comprising:encoding systematic bits in each of a plurality of transmit buffers with an first code;multiplexing content of the plurality of buffers;encoding said multiplexed content with an second code to provide a set of frames;transmitting the set of frames;decoding received frames by an second decoder;de-multiplexing correctly decoded frame to a plurality of receive buffers;and processing content of each received buffer.
  7. 18
    The method claimed in claim 17 wherein said providing a block of bits successively from each buffer comprises:providing a block of bits comprising a row of the transmitting buffer.
  8. 19
    The method claimed in claim 14 wherein said encoding said multiplexed content with an second code to provide a set of frames comprises:identifying a block of bits to be encoded;and encoding the block of bits with an second code.
  9. 20
    The method claimed in claim 19 wherein said identifying a block of bits to be encoded comprises:identifying the block of bits as a block of bits received from a buffer.
  10. 26
    An apparatus for reducing decoding complexity, comprising:a plurality of buffers;a plurality of encoders, each of said plurality of encoders being communicatively coupled to one of said plurality of buffers;a multiplexer communicatively coupled to said plurality of buffers;and an inner encoder communicatively coupled to said multiplexer.
  11. 31
    The apparatus claimed in claim 26 wherein said multiplexer is configured to:provide a block of bits successively from each of said plurality of buffers to said inner encoder.
  12. 35
    An apparatus for reducing decoding complexity, comprising:an first decoder;a de-multiplexer communicatively coupled to said first decoder;a plurality of buffers communicatively coupled to said de-multiplexer;and a plurality of decoders, each of said plurality of decoders being communicatively coupled to one of said plurality of buffers.
  13. 41
    An apparatus for reducing decoding complexity, comprising:a plurality of transmit buffers;a plurality of encoders, each of said plurality of encoders being communicatively coupled to one of said plurality of transmit buffers;a multiplexer communicatively coupled to said plurality of transmit buffers;an inner encoder communicatively coupled to said multiplexer;a first decoder;a de-multiplexer communicatively coupled to said first decoder;a plurality of receive buffers communicatively coupled to said demultiplexer;and a plurality of decoders, each of said plurality of decoders being communicatively coupled to one of said plurality of receive buffers.
  14. 46
    The apparatus claimed in claim 41 wherein said multiplexer is configured to:provide a block of bits successively from each of said plurality of transmit buffers to said inner encoder.