Method and apparatus for the formatting of data for transmission

Method and device for formatting and transmitting data

Background of the invention

This patent application is a partial continuation of the co-pending U.S. Patent Application No. 08/171,146 and is therefore related to the organization of data for transmission. The U.S. Patent Application No. 08/171,146 was filed on December 21, 1993 and named It is "METHOD AND APPARATUS FOR FORMATTING DATA FOR TRANSMISSION" and it is a continuation of U.S. Patent Application No. 07/822,164, while U.S. Patent Application No. 07/822,164 was filed on January 16, 1992 and has now been abandoned. More specifically, the present invention relates to a novel and improved method and device for formatting vocoder data, non-vocoder data and signal data for transmission.

The field of digital communication uses various digital data configurations for transmission. Data bits are organized according to common formats for transmission via communication media.

Therefore, one object of the present invention is to provide a data format that facilitates transmission of various types of data and data of various transmission rates in a structured format.

The present invention is a novel and improved method and system for formatting digital data for transmission through a transmission medium.

It is very important to use data formats in communication systems that allow complete transmission of data between users. Communication systems that intend to transmit various types of data at various transmission rates, such as code division multiple access (CDMA) communication systems, must select a data format that can achieve maximum flexibility within a predetermined structure. In addition, if resources are to be maximized, the sharing of this format should be allowed to allow different types of data to be organized together. In this case, the data must be structured in an appropriate way so that the data can be directly retrieved according to the corresponding type and transmission rate.

According to the present invention, this project provides a method and device for configuring various types of data and using various transmission rates to become a unique structured format for transmission. The data to be transmitted can be vocoder data or different types of non-vocoder data. These data are organized into frames of predetermined duration for transmission. The data frame depends on the data, and the organization becomes one of many data transfer rates. Vocoder data is provided at one of many data transmission rates and organized in frames according to a predetermined format. The frame can be formatted to the highest frame data transfer rate by sharing the vocoder data and non-vocoder data. Non-vocoder data can also be organized into the highest frame data transmission rate. Additional control data can be provided in the data frame to support various aspects of transmission and received responses.

The characteristics, objectives, and advantages of the present invention should become more obvious when reading the detailed description set forth below together with the accompanying drawings. The same reference characters in all the drawings correspond to the same components and among them: 1 is a block diagram showing an exemplary example of the transmitter part of a transceiver; Figures 2a-2l are a series of diagrams showing various data transmission rates, types and modes of frame data formats for transmission rate group 1; 3 is a diagram showing the construction of a demonstration circuit of the Cyclic Redundancy Check (CRC) and Tail Bit Generator in Figure 1; Figures 4a-4c are the flowcharts of the formatting of the data frame; Figures 5a-5d use A series of graphics to show the sequence of code symbols in the interleaver array transmitted with data rates of 9.6, 4.8, 2.4, and 1.2 kilobits per second (kbps) respectively; Figures 6a-6c show the sequence of code symbols corresponding to each encoder Fig. 7 is a block diagram showing the long code generator of Fig. 1; Fig. 8a-8c is a series of pictures showing the long code mask of various channel types; and Fig. 9a-9y is for display A series of graphs in the frame data format of various data transmission rates, types and modes in the transmission rate group 2;

Now please refer to the accompanying drawings. FIG. 1 shows an exemplary example of the transmitter portion 10 of a CDMA mobile station transceiver or PCN mobile phone. The CDMA cellular communication system uses a forward CDMA channel to transmit information from the cellular base station to the mobile station. On the contrary, a reverse CDMA channel is used to transmit information from the mobile station to the cell base station. The characteristics of the transmission of the signal from the mobile station can be the type of access channel or traffic channel transmission. The incoming channel is used for short signal messages, such as call initiation, call response, and registration. The traffic channel is used to transmit (1) primary traffic, generally including user voice, or (2) secondary traffic, generally user data, or (3) signal traffic, such as command and control signals, or (4) ) A combination of primary and secondary communications or (5) a combination of primary communications and signal communications.

The transmitter part 10 enables data to be transmitted on the reverse CDMA channel with a data transmission rate of 9.6 kbps, 4.8 kbps, 2.4 kbps or 1.2 kbps. The data transmission rate of the reverse traffic channel can be any of these data transmission rates, and the data transmission rate of the incoming channel is 4.8 kbps. The transmission duty cycle of the reverse traffic channel will change as the data transmission rate changes. More specifically, the transmission duty cycle of each transmission is listed in Table 1. When the transmission duty cycle changes proportionally as the data transmission rate changes, the actual burst transmission rate is fixed at 28,800 code symbols per second. Because the 6-code symbol is modulated into one of 64 Walsh symbols for transmission, the Walsh symbol transmission rate will be fixed at 4800 Walsh symbols per second, resulting in a fixed Walsh chip transmission rate of 307.2 kilochips per second (kcps) .

All data transmitted on the reverse CDMA channel are subject to convolution coding, block interleaving, 64-element modulation, and direct sequence virtual noise (PN) spread before transmission. Table I further defines the relationship between the data and symbols of the various transmission rates of the reverse traffic channel and the transmission rate. The relevant numbers of incoming channels are exactly the same, except that the transmission rate is fixed at 4.8 kbps and the duty cycle is 100%. As described below, each bit transmitted on the reverse CDMA channel is convolution-encoded with a transmission rate of 1/3 code. Therefore, the code symbol transmission rate is always three times the data transmission rate. The transmission rate of the direct sequence spreading function is fixed at 1.2288 megahertz (MHz), so that each Walsh chip is spread by exactly four PN chips.

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The transmitter part 10, when operating in a mode where the main traffic exists, uses digital signals to transmit audio signals, such as voice and/or background noise, via the transmission medium. To facilitate the digital transmission of audio signals, well-known techniques are used to sample and digitize these signals. For example, in FIG. 1, the sound is converted into an analog signal by the microphone 12 and the analog signal is then converted into a digital signal by the codec 14. The codec 14 generally uses a standard 8-bit/μ-law format to perform the analog-to-digital conversion process. On the other hand, the analog signal can be directly converted into a digital format in a uniform pulse code modulation (PCM) format. In an exemplary embodiment, the codec 14 uses a sampling rate of 8 kHz and provides an output of 8 bits per sample at the sampling rate to achieve a data transmission rate of 64 kbps.

The 8-bit samples are output from the codec 14 to the vocoder 16, and the vocoder 16 performs the μ-law/uniform code conversion process. In the vocoder 16, the samples are organized into input data frames, where each frame contains a predetermined number of samples. In a preferred implementation of the vocoder 16, each frame contains 160 samples or, at a sampling rate of 8 kHz, 20 milliseconds of speech. It should be understood that other sampling rates and frame sizes can be used. The voice samples of each frame are subjected to variable transmission rate coding by the vocoder 16 and the synthesized parameter data is formatted into a corresponding data packet. The vocoder data packet is then output to the microprocessor 18 and related circuits for transmission and formatting. The microprocessor 18 generally includes program instructions stored in a program instruction memory, a data memory, and appropriate interfaces and related circuits known in the art.

One of the preferred implementations of the vocoder 16 uses a code-induced linear prediction (CELP) coding technique to provide a variable transmission rate of the coded speech data. Perform linear predictive coder (LPC) analysis on a constant number of samples, and perform pitch and codebook search on a variable number of samples depending on the transmission rate. Co-pending U.S. Patent Application No. 08/004,484 describes in more detail a variable transmission rate vocoder of this type. U.S. Patent Application No. 08/004,484 was filed on January 14, 1993 and is the No. As a continuation of No. 07/713,661, US Patent Application No. 07/713,661 was filed on June 11, 1991 and is now abandoned and assigned to the assignee of the present invention and is mentioned here as a reference. The vocoder 16 can be constructed in an application-specific integrated circuit (ASIC) or a digital signal processor.

In the variable transmission rate vocoder just mentioned, the length of the speech analysis frame is 20 milliseconds, and this means that the captured parameters are output to the microprocessor 18 with 50 bursts per second. In addition, the data output rate is from about 8 kbps to 4 kbps to 2 kbps, and to 1 kbps.

At full speed, also known as transfer rate 1, the data transfer rate between the vocoder and the microprocessor is 8.55 kbps. For full-speed data, the parameters of each frame are coded and represented by 160 bits. The full-speed data frame also contains 11-bit parity checking, which results in a full-speed frame containing a total of 171 bits. In the full-speed data frame, if the parity bit is not included, the transfer rate between the vocoder and the microprocessor will be 8 kbps.

At half speed, also known as transmission rate 1/2, the data transmission rate between the vocoder and the microprocessor is 4 kbps and 80 bits are used to encode the parameters of each frame. At 1/4 speed, also known as transmission rate 1/4, the data transmission rate between the vocoder and the microprocessor is 2 kbps and 40 bits are used to encode the parameters of each frame. At 1/8 speed, also known as transmission rate 1/8, the data transmission rate between the vocoder and the microprocessor is slightly less than 1 kbps and 16 bits are used to encode the parameters of each frame.

In addition, the frame transmitted between the vocoder and the microprocessor may not carry any information. This type of frame, called an empty frame, can be used for signals or other non-vocoder data.

Then the vocoder data packet is output to the microprocessor 18 and the CRC and tail bit generator 20 to complete the transmission format. The microprocessor 18 receives parameter data packets and a rate display every 20 milliseconds, and the rate display is used to encode the rate of the speech sample frame. The microprocessor 18 also receives secondary traffic data inputs to be output to the generator 20, if any. The microprocessor 18 also internally generates signal data to be output to the generator 20. Regardless of whether the nature of the data is primary traffic, secondary traffic or signal traffic, if it exists, it is output from the microprocessor 18 to the generator 20 in a frame of every 20 milliseconds.

The generator 20 generates and appends a set of parity check bits, frame quality display bits or cyclic redundancy check (CRC) bits to the end of all full-speed and half-speed frames, and the CRC is displayed as frame quality at the receiver. For the full-speed frame, whether the data is full-speed primary, secondary or signal traffic, or a combination of half-speed primary and secondary traffic, or a combination of half-speed primary and signal traffic, the generator 20 is best based on the first item Formula to generate a set of frame-quality display bits. For the half-speed data frame, the generator 20 also preferably generates a set of frame quality display bits according to the second polynomial. The generator 20 further generates a set of encoder tail bits at the end of the frame for all frame rates, and if the frame quality display bit exists, the set of encoder tail bits immediately follow the frame quality display bit, and If the frame quality display bit does not exist, it immediately follows the data. Hereinafter, further details of the operation of the microprocessor 18 and the generator 20 will be provided with reference to FIGS. 3 and 4.

The reverse traffic channel frame provided by the generator 20 at a transmission rate of 9.6 kbps is a frame that is 192 bits long and lasts 20 milliseconds. These boxes include single mixed mode bits, auxiliary format bits, if present, message bits, a 12-bit frame quality display, and 8 tail bits, as shown in Figures 2a-2e and 2i-2l. In any frame where the message bit is only the main traffic information, the mixed mode bit is set to '0'. When the mixed mode bit is '0', the box will contain mixed mode bits, 171 main traffic bits, 12-frame quality display bits and 8 tail bits.

The mixed mode bit of the frame containing the secondary or signal signal is set to '1'. If the blend mode bit is set to '1', the box is in'blank-and-burst' or'dim-and-burst' format. The "blank and glitch" operation is the operation where the entire frame acts as the main or signal signal, and the "blur and glitch" operation is the operation of the main and secondary or signal signals sharing the frame.

The first bit immediately after the mixed mode bit is the traffic type bit. The traffic type bit is used to specify whether the frame contains secondary or signal traffic. If the traffic type bit is '0', the box contains signal traffic, and if the traffic type bit is '1', the box contains secondary traffic. Figures 2b-2e and 2i-2l show the traffic type bits. The two bits immediately after the traffic type bit are the traffic mode bit. These two traffic mode bits specify the combination of the data in the frame.

In a better configuration, only the main traffic is to use the transmission rate of 4.8 kbps, 2.4 kbps, and 1.2 kbps to transmit in a frame. Generally, only the transmission rate of 9.6 kbps is used to support mixed mode operation, although other transmission rates can be easily configured. Support mixed mode operation. The frame formats of these specific transmission rates are shown in Figures 2f-2h. As far as the transmission rate of 4.8 kbps is concerned, the frame length is 96 bits and the bits are distributed in the 20 millisecond interval of the frame as described below. The 4.8 kbps transmission rate frame contains 80 main traffic bits and 8 frame quality display bits. With 8 tail bits. As far as the 2.4 kbps transmission rate is concerned, the frame length is 48 bits and the bits are also distributed in the 20 millisecond interval of the frame as described below. The 2.4 kbps transmission rate frame contains 40 main traffic bits and 8 tail bits. As far as the transmission rate of 1.2 kbps is concerned, the frame length is 24 bits and the bits are also distributed in the 20 millisecond interval of the frame as described below. The 1.2 kbps transmission rate frame contains 16 main traffic bits and 8 tail bits.

In a preferred embodiment, the incoming channel data is generated by the microprocessor 18 and transmitted at a transmission rate of 4.8 kbps. Therefore, the preparation method of the data is the same as that of 4.8 kbps frame format data, such as encoding, interleaving into Walsh encoding. In the coding method constructed for 4.8 kbps data, redundant data will be generated whether it is reverse traffic channel data or incoming channel data. Unlike the reverse traffic channel in which redundant data is removed during transmission, all data in the incoming channel, including redundant data, will be transmitted. The details of the transmission of the incoming channel data frame will be provided below.

Figures 2a-2l show the frame format of the frame output by the generator 20 with frame transmission rates of 9.6 kbps, 4.8 kbps, 2.4 kbps and 1.2 kbps. Figure 2a shows the 9.6 kpbs frame used only for transmitting the main traffic. This box contains 1 mixed mode bit. 171 main traffic data bits, 12 frame quality display bits and 8 tail bits, and the mixed mode bit is set to '0' to show that the frame only contains main traffic data.

Figure 2b shows the 9.6 kbps blur and glitch frame used for the transmission of the main traffic and signal traffic with a transmission rate of 1/2. This box contains 1 mixed mode bit. 1 traffic type bit, 2 traffic mode bit, 80 main traffic bit, 88 signal traffic bit, 12 frame quality display bit and 8 tail bit, and mixed mode bit is set to 1 for display The frame does not only contain the main traffic. The traffic type bit is set to 0 to show that the frame contains signal data, and the traffic mode bit is set to 00 to show that the frame contains the main traffic and signal with a transmission rate of 1/2. Communications.

Figure 2c shows the 9.6 kbps blur and glitch frame used for the transmission of the main traffic and signal traffic with a transmission rate of 1/4. This frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 40 main traffic bit, 128 signal traffic bit, 12 frame quality display bit and 8 tail bit. The mixed mode bit is set to 1 to show that the frame does not only contain the main traffic, the traffic type bit is set to 0 to show that the frame contains signal data, and the traffic mode bit is set to 01 to show that the frame contains the transmission rate. 1/4 of the main communications and signal communications.

Figure 2d shows the 9.6 kbps blur and glitch frame used for the transmission of main traffic and signal traffic with a transmission rate of 1/8. The frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 16 main traffic bit, 152 signal traffic bit, 12 frame quality display bit and 8 tail bit. The mixed mode bit is set to 1 to show that the frame does not only contain the main traffic, the traffic type bit is set to 0 to show that the frame contains signal data, and the traffic mode bit is set to 10 to show that the frame contains the transmission rate. 1/8 of the main communications and signal communications.

Figure 2e shows the 9.6 kbps blank and glitch boxes used for signal transmission. This box contains 1 mixed mode bit. 1 traffic type bit, 2 traffic mode bit, 168 signal traffic bit, 12 frame quality display bit and 8 tail bit, and the mixed mode bit is set to 1 to show that the frame does not only contain the main For traffic, the traffic type bit is set to 0 to show that the frame contains signal data, and the traffic mode bit is set to 11 to show that the frame only contains signal traffic.

Figure 2f shows the 4.8 kbps frame used only for the transmission of the main traffic with a transmission rate of 1/2. This frame contains 80 main traffic bits, 8 frame quality display bits and 8 tail bits. Figure 2g shows 2.4 kbps used only for the transmission of the main traffic with a transmission rate of 1/4. This frame contains 40 main traffic bits and 8 tail bits. Figure 2h shows the 1.2 kbps frame used only for the transmission of the main traffic with a transmission rate of 1/8. This frame contains 16 main traffic bits and 8 tail bits.

Figure 2i shows the 9.6 kbps ambiguity and glitch frames used for the transmission of primary and secondary traffic with a transmission rate of 1/2. This frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 80 main traffic bit, 88 secondary traffic bit, 12 frame quality display bit and 8 tail bit. The mixed mode bit is set to 1 to show that the frame does not only contain the main traffic, the traffic type bit is set to 1 to show that the frame contains secondary data, and the traffic mode bit is set to 00 to show that the frame contains Primary and secondary communications with a transmission rate of 1/2.

Figure 2j shows the 9.6 kbps blur and glitch frames used for the transmission of primary and secondary traffic at a rate of 1/4. This frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 40 main traffic bit, 128 secondary traffic bit, 12 frame quality display bit and 8 tail bit. The mixed mode bit is set to 1 to show that the frame does not only contain primary traffic, the traffic type bit is set to 1 to show that the frame contains secondary data, and the traffic mode bit is set to 1 to show that the frame contains Secondary data, the traffic mode bit is set to 01 to show that the frame contains the primary traffic and secondary traffic with a transmission rate of 1/4.

Figure 2k shows the 9.6 kbps ambiguity and glitch frames used for the transmission of primary and secondary traffic with a transmission rate of 1/8. This frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 16 main traffic bit, 152 secondary traffic bit, 12 frame quality display bit and 8 tail bit. The mixed mode bit is set to 1 to show that the frame does not only contain primary traffic, the traffic type bit is set to 1 to show that the frame contains secondary data, and the traffic mode bit is set to 10 to show that the frame contains Primary and secondary communications with a transmission rate of 1/8.

Figure 21 shows the 9.6 kbps blank and burst boxes used for the transmission of secondary traffic. The frame contains 1 mixed mode bit, 1 traffic type bit, 2 traffic mode bit, 168 secondary traffic bit, 12 frame quality display bit and 8 tail bit, and the mixed mode bit is set 1 to show that the box does not contain only primary traffic, the traffic type bit is set to 1 to show that the box contains secondary data, and the traffic mode bit is set to 11 to show that the box only contains secondary traffic.

Fig. 3 shows an exemplary construction of a component for formatting data according to Figs. 2a-21. In FIG. 3, data is sent from the microprocessor 18 (FIG. 1) to the generator 20. The generator 20 includes a data buffer and control logic 60, CRC circuits 62 and 64, and a tail bit circuit 66. Together with the data provided by the microprocessor, a transmission rate command can also be optionally provided. The data is transferred from the microprocessor to the logic 60 every 20 milliseconds frame, and the data is temporarily stored in the logic 60. For each frame, the logic 60 can count the number of bits transmitted by the microprocessor or alternatively can use the transfer rate command and clock cycle count to format the data frame.

Each frame of the communication channel includes a frame quality display. Considering the transmission rate of 9.6 kbps and 4.8 kbps, the frame quality display is CRC. Regarding the 2.4 kbps and 1.2 kbps transmission rates, the frame quality display is included because there is no need to transmit additional frame quality bits. The frame quality display supports the second function of the receiver. The first function is to determine the transmission rate of the frame, and the second function is to determine whether an error occurs in the frame. The receiver uses the combination of decoder information and CRC check to make these decisions.

Regarding the transmission rate of 9.6 kbps and 4.8 kbps, the frame quality display (CRC) is calculated by using all the bits of the frame, except for the frame quality display (CRC) itself and the tail bit. Logic 60 provides 9.6 kbps and 4.8 kbps transmission rate data to CRC circuits 62 and 64, respectively. The circuits 62 and 64 are generally constructed as a series of shift registers, modulo-2 adders (usually mutual exclusion or gates) and switches, as shown in the figure.

The 9.6 kbps transmission rate data uses a 12-bit frame quality display (CRC), and the frame quality display is transmitted using a 192-bit frame as discussed with reference to Figures 2a-2e and 2i-2l. As shown in the CRC circuit 62 in Figure 3, the generator polynomial for the 9.6 kbps transmission rate is as follows: g(x)=x¹²+x¹¹+x¹⁰+x⁹+x⁸+x⁴+x+1 (1)

Data with a transmission rate of 4.8 kbps uses an 8-bit CRC, and the CRC is transmitted using a 96-bit long frame. As shown in the CRC circuit 64 in Figure 3, the generator polynomial for the 4.8 kbps transmission rate is as follows: g(x)=x⁸+x⁷+x⁴+x³+x+1 (2)

Initially, all shift register components of circuits 62 and 64 are set to logic 1 ('1') by the enable signal from logic 60. In addition, the logic 60 sets the switches of the circuits 62 and 64 to the upper position.

Regarding the data of the 9.6 kbps transmission rate, the register of the circuit 62 then counts the sequence of the main traffic, the secondary traffic or the signal bit or the mixture of these bits and the corresponding mode/format display bit. 172 Input to the circuit 62 again. After the 172-bit clock passes through the circuit 62, the logic 60 then sets the switch of the circuit 62 to the down position and the register of the circuit 62 then clocks an additional 12 times. Because of the additional 12 timings of the circuit 62, 12 additional output bits are generated, and the 12 additional output bits are frame quality display bits (CRC bits). The frame quality display bits are added to the end of the 172 bits output by the circuit 62 according to the order of calculation. It should be noted that the 172 bits output from the logic 60 and passed through the circuit 62 are not disturbed by the calculation of the CRC bits and therefore the order and value of the bits output from the circuit 62 are the same as the order and value of their input.

Regarding the data of the 9.6 kpbs transmission rate, the bits are input from the logic 60 to the circuit 64 in the following order. As far as the main traffic is included, the bits are input from the logic 60 to the circuit 64 in the order of a single mixed mode (MM) bit followed by 171 main traffic bits. In terms of "blur and glitch" situations that include mainly signal and signal services. The bits are input from logic 60 in the order of a single MM bit, a traffic type (TT) bit, a pair of traffic type (TM) bits, 80 main traffic bits, and 86 signal traffic bits. To circuit 64. As far as the "fuzzy and glitch" situation including primary and secondary traffic is concerned, the bits are based on a single MM bit, TT bit, a pair of TM bits, 80 primary traffic bits, and 87 signal traffic. The order of the bits is input from the logic 60 to the circuit 64. As far as the "blank and glitch" data format only includes signal signals, the bits are input from logic 60 to circuit 64 in the order of a single MM bit, TT bit and 168 signal signal bit. As far as the "blank and glitch" data format includes only secondary traffic, the bits are input from the logic 60 to the circuit 64 in the order of a single MM bit, TT bit and 169 secondary traffic bits.

Similarly, in terms of data with a transmission rate of 4.8 kbps, the register of circuit 64 clocks 80 times to input 80-bit main traffic data or 80-bit incoming channel data from logic 60 to circuit 64. After the 80-bit timing passes through the circuit 64, the logic 60 then sets the switch of the circuit 64 to the down position and the register of the circuit 64 then counts an additional 8 times. Because of the additional 12 timings of the circuit 62, 12 additional output bits are generated, and the 12 additional output bits are CRC bits. The CRC bits are added to the end of the 80 bits output by the circuit 64 again according to the order of calculation. It should be noted that the 80 bits output from the logic 60 and passed through the circuit 64 are not disturbed by the calculation of the CRC bits and therefore the order and value of the bits output from the circuit 64 are the same as the order and value of their input.

The bit output from either of the circuits 62 and 64 is sent to the switch 66, and the switch 66 is controlled by the logic 60. The 40 and 16-bit main traffic data output from the logic 60 for the 2.4 kbps and 1.2 kbps data frames are also input to the switch 66. The switch 66 selects the output (up position) that provides the input data or the last bit (down position) at the logic zero ('0') value. The switch 66 is usually set to the upper position so that the data from the logic 60 and the data from the circuits 62 and 64, if present, can be output from the generator 20 to the encoder 22 (FIG. 1). Regarding the 9.6 kbps and 4.8 kbps frame data, after the CRC bit timing passes through the switch 66, the logic 60 sets the switch to maintain an 8 clock cycle in the lower position so as to generate 8 tail bits of all zeros. Therefore, in the case of 9.6 kbps and 4.8 kbps data frames, the data output to the encoder for this frame contains 8 tail bits appended to the CRC bits. Similarly for the 2.4 kbps and 1.2 kbps frame data, after the main traffic bit passes through the switch 66 from the logic 60, the logic 60 sets the switch to maintain the 8 clock cycle in the lower position so that the 8 tail bits of all zeros are generated again . Therefore, in the case of 2.4 kbps and 1.2 kbps data frames, the data output to the encoder for this frame includes 8 tail bits appended to the main traffic bit.

Figures 4a-4c show a series of flowcharts showing the operation of the microprocessor 18 and the generator 20 to combine data into the proposed frame format. It should be noted that various methods can be constructed to provide various traffic types and transmission rate priorities for transmission. In a demonstration construction, when a signal signal is to be transmitted, when the vocoder data exists, a "fuzzy and glitch" format can be selected. The microprocessor 18 can generate an instruction to the vocoder 18 to make the vocoder use half speed to encode the speech sample frame, no matter what rate the vocoder usually uses to encode the sample frame. Then the microprocessor 18 combines the half-speed vocoder data and the signal signal into a 9.6 kbps frame. In this case, the number of speech frames encoded by half-speed can be limited to avoid deterioration of speech quality. In addition, the microprocessor 18 can wait until the half-speed vocoder data frame is received before starting to combine the data into a "fuzzy and glitch" format. In this case, in order to ensure real-time transmission of signal data, the maximum number of consecutive frames other than half-speed can be limited before sending the command to the vocoder for half-speed encoding. Secondary traffic can be transferred in a similar way in the "fuzzy and burst" format (Figure 2b-2d and Figure 2i-2k).

The data format of "blank and burst" shown in Figures 2e and 21 is also the same. The vocoder can be instructed not to encode the frame of speech samples or the microprocessor ignores the vocoder data when constructing the data frame. For the priority of the frame format of the main traffic that generates various transmission rates, there are many possibilities for "fuzzy and burst" and "blank and burst" traffic.

Please refer to Figure 1 again, the 20 millisecond frame of 9.6 kbps, 4.8 kbps, 2.4 kbps and 1.2 kbps data is therefore output from the generator 20 to the encoder 22. In this exemplary embodiment, the encoder 22 is preferably a cyclotron encoder, and the cyclotron encoder is an encoder known in the art. The encoder 22 preferably uses a convolution code with a transmission rate of 1/3 and a restricted length of k=9 to encode data. For example, the encoder 22 uses g₀=557 (octal), g₁=663 (octal) and g₂=711 (octal) generator function to build. As is known in the art, convolutional coding involves modulo-2 addition of selected joints of a tandem time-shift delayed data sequence. The length of the data sequence delay is k-1, where k is the code limit length. Because this preferred example uses a code with a transmission rate of 1/3, the encoder generates a three-code symbol every time a data bit is input to the encoder, and the code symbol (c₀), (c₁) And (c₂). Code symbol (c₀), (c₁) And (c₂) Are respectively generated by the generator function g₀, G₁With g₂To produce. The code symbols are output from the encoder 22 to the block interleaver 24. The output code symbol is in accordance with the code symbol (c₀) First, the code symbol (c₁) The second AND symbol (c₂) The final sequence is sent to the interleaver 24. The state of the encoder 22 at startup is all zero. In addition, using tail bits at the end of each frame can reset the encoder 22 to a state of all zeros.

The symbols output from the encoder 22 are sent to the block interleaver 24, and the block interleaver 24 provides a code symbol repetition under the control of the microprocessor 18. By using traditional random access memory (RAM) and the symbols are stored in the RAM and can be addressed by the microprocessor 18, the code symbols can be stored in an appropriate way to achieve the code symbols that change with the data channel change Repeat rate.

For the data transmission rate of 9.6 kbps, the code symbol is not repeated. Under the data transmission rate of 4.8 kbps, each code symbol is repeated once, that is, each symbol appears twice. Under 2.4 kbps data transmission rate, each code symbol repeats 3 times, that is, each symbol appears 4 times. Under 1.2 kbps data transmission rate, each code symbol repeats 7 times, that is, each symbol appears 8 times. For all data transmission rates (9.6, 4.8, 2.4, and 1.2 kbps), code repetition causes data to be output from the interleaver 24 at a constant code symbol transmission rate of 28,800 code symbols per second. The code symbols that are repeated on the reverse traffic channel are not transmitted more than once. Instead, all code symbol repetitions are deleted before the actual transmission to only one code symbol repetition, due to the variable transmission discussed in more detail below Duty cycle. It should be understood that the use of code symbol repetition is a convenient way to illustrate the operation of the interleaver and the data burst randomizer, and this operation will be discussed in more detail below. It should be further understood that it is easy to design a construction that does not use code symbol repetition and achieves the same result and maintains the description of the present invention.

All code symbols to be transmitted on the reverse traffic channel and the incoming channel will be interleaved before modulation and transmission. The block interleaver 24 constructed in a manner known in the art provides output of code symbols within a time interval of 20 milliseconds. The interleaver structure is generally a rectangular array with 32 columns and 18 rows, that is, 576 cells. The code symbols are written into the interleaver according to rows, and the data repetition rate is 9.6, 4.8, 2.4 and 1.2 kbps, so that the 32 is completely filled.^＊18 matrix. Figures 5a-5d show the sequence of writing the repetitive code symbols into the interleaver array for data transmission rates of 9.6, 4.8, 2.4, and 1.2 kbps, respectively.

The reverse traffic channel code symbols are output from the interleaver according to the column. The microprocessor 18 also controls the addressing of the interleaver memory to output symbols in the proper order. The interleaver column should preferably be output in the following order: at 9.6 kbps: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 at 4.8 kpbs: 1 3 2 4 5 7 6 8 9 11 10 12 13 15 14 16 17 19 18 20 21 23 22 24 25 27 26 28 29 31 30 32 at 2.4 kbps: 1 5 2 6 3 7 4 8 9 13 10 14 11 15 12 16 17 21 18 22 19 23 20 24 25 29 26 30 27 31 28 32 at 1.2 kbps: 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 16 17 25 18 26 19 27 20 28 21 29 22 30 23 31 24 32.

The incoming channel code symbols are also output from the interleaver 24 according to the column. The microprocessor 18 again controls the addressing of the interleaver memory to output symbols in the proper order. The interleaver column outputs the incoming channel code symbols at a transmission rate of 4.8 kbps in the following order: 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 2 18 10 26 6 22 14 30 4 20 12 28 8 24 16 32.

It should be noted that other coding rates, such as the transmission rate 1/2 convolution code used for the forward transmission channel, and various other symbol interleaving formats, can be easily designed using the basic description of the present invention.

Please refer to FIG. 1 again. The interleaved code symbols are output from the interleaver 24 to the modulator 26. In this preferred embodiment, the modulation of the reverse CDMA channel uses a 64-element quadrature signal. In other words, one of 64 possible modulation symbols is transmitted every 6 code symbols. The 64-ary modulation symbol is one of the 64 quadrature waveforms that are best generated by the Walsh function. The modulation symbols are shown in Figures 6a-6c and numbered from 0 to 63. Modulation symbol is selected according to the following formula: Modulation symbol number = c₀+2c₁+4c₂+8c₃+16c₄+32c₅ (3) where c₅Represents the last or most recent binary value ('0' and '1') code symbol of each group of 6 code symbols constituting a modulation symbol and c₀Represents the first or oldest binary value code symbol. The time interval required to transmit a single modulation symbol is called the "Walsh symbol" interval and is approximately equal to 208.333 microseconds. The time interval related to 1/64 of the modulation symbol is called "Walsh chip" and is approximately equal to 3.2552083333... microseconds.

Each modulation or Walsh symbol is the input from the output of the self-modulator 26 to the modulo-2 adder, mutual exclusion or gate 28. The Walsh symbol is output from the modulator at a transmission rate of 4800 symbols per second (sps), and 4800 sps corresponds to a Walsh chip transmission rate of 307.2 kilochips per second (kcps). The other input of the gate 28 is provided by the long code generator 30. The long code generator 30 cooperates with the mask circuit 32 to generate a masked virtual noise (PN) code called a long code sequence. The chip transmission rate of the long code sequence provided by the generator 30 is 4 times the Walsh chip transmission rate of the modulator 26, that is, the PN chip transmission rate is 1.2288 million chips per second (Mcps). The gate 28 combines the two input signals to output data with a chip transmission rate of 1.2288 Mcps.

The long code sequence is a length of 2⁴²The time shift of the sequence of -1 chips is generated by a linear generator known in the art using the following polynomial: p(x)=x⁴²+x³⁵+x³³+x³¹+x²⁷+x²⁶+x²⁵+x²²+x²¹+x¹⁹+x¹⁸+x¹⁷+x¹⁶+x¹⁰+x⁷+x⁶+x⁵+x³+x²+x¹+1 (4)

Figure 7 shows the generator 30 in more detail. The generator 30 includes a sequence generator area 70 and a mask area 72. The area 70 includes a sequence of shift registers and modulo-2 adders (generally mutually exclusive or gates) coupled together to generate a 42-bit code according to Equation 4. Then, the 42-bit wide mask provided by the mask circuit 32 is used to mask the 42-bit state variable output from the area 70 to generate the long code.

Area 72 contains a series of inputs and gates 74₁-74₄₂, And the gates have an input for receiving a corresponding mask bit of the 42-bit wide mask. Each and gate 74₁-74₄₂The other input receives the output from one of the corresponding shift registers in the area 70. And gate 74₁-74₄₂The output of the adder 76 performs a modulo-2 addition to form a single bit output of each 1.2288 MHz clocked shift register of the area 70. The adder 76 is generally built in a serial configuration of mutual exclusion or gates known in the art. Therefore, the actual output PN sequence as shown in FIG. 7 is generated by the modulo-2 addition of all 42 mask output bits of the sequence generator 70.

The mask used for PN spreading depends on the type of channel the mobile station is using to transmit. Please refer to FIG. 1, the activation information is sent from the microprocessor 18 to the generator 30 and the circuit 32. The generator 30 activates the circuit in response to the activation information. The mask 32 also outputs a 42-bit mask in response to the activation information, and the activation information shows the type of the mask to be provided. Therefore, the mask circuit 32 can be configured as a memory including a mask for each transmission channel type. Figures 8a-8c provide exemplary definitions of mask bits for each channel type.

More specifically, when the incoming channel is used for transmission, the definition of the mask is shown in Figure 8a. In the incoming channel mask, the mask bit M₂₄To M₄₁Set to '1'; mask bit M₁₉To M₂₃Set as the selected incoming channel number; mask bit M₁₆To M₁₈Set the code channel of the related call channel, that is, the range is generally from 1 to 7; the mask bit is M₉To M₁₅Set as the registration area of the current base station; and mask bit M₀To M₈Set the pilot PN value of the current CDMA channel.

When the reverse traffic channel is used for transmission, the definition of the mask is shown in Figure 8b. The mobile station uses one of the two long codes that are unique to the mobile station, and the two long codes are the only common long code for the electronic serial number (ESN) of the mobile station and for each mobile identification number (MIN ) Is the only private long code, and MIN is generally the phone number of the mobile station. In the public long code, the mask bit M₃₂To M₄₁Set to '0' and mask bit M₀To M₃₁Set as the ESN value of the mobile station.

We further intend that the private long code can be constructed as shown in Figure 8c. The private long code can provide additional security because only the base station and mobile station know the private long code. The private long code will not be transmitted unencrypted on the transmission medium. In the private long code, the mask bit M₄₀To M₄₁Set to '0' and '1' respectively; and the mask bit M₀To M₃₉It can be set according to the pre-determined assignment method.

Please refer to Figure 1, the output of gate 28 serves as an input of a pair of modulo-2 adders, mutually exclusive or gates 34 and 36, respectively. The other inputs of the gates 34 and 36 are the second and third PN sequences, respectively, and the second and third sequences are the I and Q channel "short codes" generated by the I and Q channel PN generators 38 and 40, respectively. The reverse access channel and reverse traffic channel are therefore subject to OQPSK spread before actual transmission. The offset orthogonal spread spectrum of this reverse channel uses the same I and Q PN codes as the forward channel I and Q pilot PN codes. The length of the I and Q PN codes generated by generators 38 and 40 is 2¹⁵And it is best to have a zero time offset code relative to the forward channel. For further understanding, a pilot signal is generated for each base station on the forward channel. The pilot channel signal of each base station is spread by I and Q PN codes as just described. The I and Q PN codes of the base station are offset from each other, and the difference between the base station transmissions is provided by the shift of the code sequence. The generation function of I and Q short PN code should be as follows: P_I(x)=x¹⁵+x¹³+x⁹+x⁸+x⁷+x⁵+1 (5) and P_Q(x)=x¹⁵+x¹²+x¹¹+x¹⁰+x⁶+x⁵+x⁴+x³+1 (6) The generators 38 and 40 can be constructed as structures known in the technical field to provide an output sequence according to the methods (5) and (6).

The I and Q waveforms are output from gates 34 and 36, respectively, and these waveforms serve as inputs to finite impulse response (FIR) filters 42 and 44, respectively. The FIR filters 42 and 44 are digital filters that limit the bandwidth of the synthesized I and Q waveforms. The digital filters change the shape of the I and Q waveforms so that the synthesized spectrum lies within a given spectrum mask. The filters 42 and 44 can be constructed according to well-known digital filter technology and preferably provide the desired frequency response.

The binary inputs '0' and '1' leading to the digital filters 42 and 44 and generated by the PN spreading function are mapped to +1 and -1, respectively. The sampling frequency of the digital filter is 4.9152 megahertz (MHz) = 4^＊1.2288MHz. An additional binary '0' and '1' input sequence synchronized with the I and Q digital waveforms is sent to the digital filters 42 and 44. This special sequence, called the mask sequence, is the output produced by the data burst randomizer. The mask sequence is multiplied by the I and Q binary waveforms to generate ternary (-1, 0, and +1) inputs to digital filters 42 and 44.

As discussed earlier, the data transfer rate of the reverse traffic channel is equal to one of the transfer rates of 9.6, 4.8, 2.4, or 1.2 kbps and changes in units of frames. Because the frame length of the incoming channel and the reverse traffic channel is fixed at 20 milliseconds, the number of information bits in each frame is 192, 96, 48 or 24 to use 9.6, 4.8, 2.4 or 1.2 kbps data transmission respectively Rate to deliver. As mentioned earlier, the information is encoded using a convolutional encoder with a transmission rate of 1/3 and then the code symbol is repeated 1, 2, 4, or 8 times for data transmission rates of 9.6, 4.8, 2.4, or 1.2 kbps, respectively. The symbol transmission rate of the synthesized repetition code is therefore fixed at 28,800 symbols per second (sps). This 28,800 sps stream is subject to block interleaving as described earlier.

Before transmission, the reverse traffic channel interleaver output stream is gated using a time filter that allows the transmission of some interleaver output symbols and deletes other symbols. The duty cycle of the transmission gate therefore changes as the data transmission rate changes. When the data transmission rate is 9.6 kpbs, the transmission gate allows all interleaver output symbols to be transmitted. When the data transmission rate is 4.8 kbps, the transmission gate allows 1/2 of the output symbols of the interleaver to be transmitted, and so on. This selection process works by dividing the 20 millisecond frame into 16 equal length (ie 125 millisecond) intervals, called the power control group. Some power control groups are selected to be on (that is, transmit), while other groups are selected to be off (that is, not to transmit).

The assignment of the power control group selected as on and selected as off is called the data burst randomization function. The power control group selected to be turned on makes their positions virtually randomized within the frame so that the actual traffic load of the reverse CDMA channel is evenly distributed, assuming that the frames of each load cycle are randomly distributed. The power control group selected as on must be such that each code symbol input to the repetition process should be transmitted only once without repetition. In the interval selected as off, the mobile station will not transmit energy, thus reducing the interference to other mobile stations operating on the same reverse CDMA channel. This symbol strobe occurs before transmission filtering.

When the mobile station transmits on the incoming channel, the transmission selection process is not used. When transmitting on the incoming channel, the code symbols are repeated once before transmission (each symbol appears twice).

In the construction of the data burst randomization function, the data burst randomizer logic 46 generates a 0 and 1 mask stream, and the mask stream randomly masks the redundant data generated by the code repetition. The mask stream pattern is determined by the frame data transmission rate and the 14-bit block obtained from the long code sequence generated by the generator 30. The masking bits are synchronized with the data stream and the data is selectively masked by the operation of the digital filters 42 and 44 using these bits. The 1.2288 MHz long code sequence output from the generator 30 within the logic 46 is input to a 14-bit shift register, and the shift register is shifted at a rate of 1.2288 MHz. The contents of the shift register are loaded into the 14-bit latch exactly one power control group (1.25 milliseconds) before the boundary of each reverse traffic channel frame. The logic 46 uses this data and the rate input from the microprocessor 18 to determine the specific power control group to allow the data to pass through the filters 42 and 44 for transmission based on a predetermined algorithm. The logic 46 therefore outputs one ('0') or ('1') for the entire power control group for each power control group depending on whether the data is to be filtered out ('0') or passed ('1'). At the corresponding receiver side, determine the appropriate power control group where the data is located, and the receiver also uses the same long code sequence as the frame and the determined corresponding transmission rate.

The I channel data output from the filter 42 is directly sent to the digital-to-analog (D/A) converter and anti-aliasing filter circuit 50. However, the Q channel data is output from the filter 44 to the delay element 48, and the delay element 48 causes a 1/2 PN chip time delay (406.9 nanoseconds) of the Q channel data. The Q channel data is output from the delay component 48 to a digital-to-analog (D/A) converter and anti-aliasing filter circuit 52. The circuits 50 and 52 convert the digital data into an analog type and filter the analog signal. The signals output from the circuits 50 and 52 are sent to an offset quadrature phase keying (OQPSK) modulator 54, and the signals are modulated in the modulator 54 and output to the radio frequency transmitter circuit 56. The circuit 56 amplifies, filters and frequency up-converts the signal for transmission. The signal is output from the circuit 56 to the antenna 58 for transmission to the base station.

It should be understood that the exemplary embodiment of the present invention discusses the formatting of data for modulation and transmission for mobile stations. It should be understood that the data formatting is the same for a cell base station, but the modulation may be different.

In an improved embodiment, the present invention can be designed to operate at two different sets of data transfer rates. In the first demonstration example, the main traffic is transmitted in frames using transmission rates of 9.6 kbps, 4.8 kbps, 2.4 kbps and 1.2 kbps. These transmission rates include a group of data transmission rates referred to herein as transmission rate group 1. In an improved embodiment of the present invention, the main traffic can also be transmitted in frames with transmission rates of 14.4 kpbs, 7.2 kpbs, 3.6 kpbs, and 1.8 kpbs, thus allowing higher transmission rate vocoders and other data. These transmission rates include a group of data transmission rates referred to herein as transmission rate group 2. The data transmission using the transmission rate of the transmission rate group 1 is performed as described above. The transmission of the data frame of the transmission rate group 2 is performed in a similar manner, but the generation of the frame quality display (CRC) bit and the allocation of the frame bit are slightly different from the convolutional coding of the frames. These differences will be explained in detail below.

In the exemplary embodiment of the present invention, the frame of transmission rate group 1 uses a transmission rate that is different from the frame of transmission rate group 2 to be convolution-encoded. The transmission rate group 1 block uses the transmission rate 1/3 for convolution coding, and the transmission rate group 2 block uses the transmission rate 1/2 for convolution coding. This demonstration example is equipped with two separate rotary encoders. The convolutional encoder 22 is a convolutional encoder that encodes the transmission rate 1/3 of the transmission rate group 1 frame, and the convolutional encoder 23 is a convolutional encoder that encodes the transmission rate 1/2 of the transmission rate group 2 frame. The switch 21 receives the RATE SET signal from the microprocessor 18 and guides the frame to the correct rotary encoder accordingly.

It should be noted that the coded symbol transmission rate from the convolution encoder 23 is 28.8 ksps, 14.4 ksps, 7.2 ksps and 3.6 ksps, and is the same as the transmission rate provided by the convolution encoder 22. This allows the transmission of the transmission rate group 2 block immediately after the convolution coding of the block to be performed exactly as described for the transmission rate group 1 block.

In this exemplary example, the generator polynomial used for the frame quality display of the transmission rate group 2 of the generator 20 is as follows: for a 12-bit frame quality display g(x)=x¹²+x¹¹+x¹⁰+x⁹+x⁸+x⁴+x+1; (7)

For 10-bit frame quality display g(x)=x¹⁰+x⁹+x⁸+x⁷+x⁶+x⁴+x³+1； (8)

For 8-bit frame quality display g(x)=x⁸+x⁷+x⁴+x³+x+1; (9)

For 6-bit frame quality display g(x)=x⁶+x²+x+1. (10)

The design and construction of an encoder that uses these polynomials to generate frame-quality display bits are the same as those described for transmission rate group 1.

One of the final difference between the transmission rate group 2 box and the transmission rate group 1 box is that it contains a display bit. The removal of the display bit is to display a frame removal of the feedback signal that has occurred from the receiving system of the communication device to the remote transmission device. In this demonstration example. Set this bit when the personal station cannot determine the data transfer rate of the received frame or detects an error. This bit can be determined by other types of received signal quality measures, such as the received signal strength. In response, the remote transmission device can enhance its signal by increasing its transmission energy or by reducing its data transmission rate. The removal bit can be set by the microprocessor 18 or an additional component, removing the display component 19, and both the microprocessor 18 and the removing display component 19 can operate on the frame removal signal (FRAME ERASURE SIGNAL) from the receiving system of the communication device. ) (Not shown).

Table II shown below shows the contents of the demonstration frame of the two data transmission rate groups. As mentioned earlier, as far as the transmission rate group 1 frame is concerned, the 9600 bps frame contains 172 information bits. 12 frame quality display bits and 8 tail bits, 4800 bps frame contains 80 information bits, 8 frame quality display bits and 8 tail bits, 2400 bps frame contains 40 information bits and 8 tail bits, and 1200 bps The frame contains 16 information bits and 8 tail bits. Regarding the 2 frames of the transmission rate group, the 14,400 bps frame contains 267 information bits, 1 removes the display bit, 12 frames quality display bit and 8 tail bits, the 7200 bps frame contains 125 information bits, 1 removes the display bit , 10 frame quality display bits and 8 tail bits, 3600 bps frame contains 55 information bits, 1 removes display bits, 8 frame quality display bits and 8 tail bits, and 1800 bps frame contains 21 information bits, 1 Remove the display bits, 6-frame quality display bits and 8 tail bits.

<tables><img file="TW301827B_D0002.tif" /></tables>

Figures 9a-9y show the frame format of the frame generated by the transmission rate group 2. Figure 9a shows the 14.4 kpbs box used for the transmission of the main traffic at full speed. The frame provides one bit as the above-mentioned removal display bit and provides a reserved bit. A mixed mode bit is set to 0 to show that the frame only contains the main traffic data. Then the box provides 265 main traffic bits. Then there are 12 frames of quality display bits and 8 tail bits.

Figure 9b shows the 14.4 kbps blur and glitch frame used for half-speed transmission of main traffic and signal traffic. The frame provides a bit as the above-mentioned removal display bit and provides a reserved bit. The mixed mode bit is set to 1 to show that the packet contains data other than the main traffic. The frame provides 4 frame mode bits to display the data type of the packet. The frame mode bit is set to 0000 to show that the data in the packet is half-speed main traffic and signal traffic. This frame has 124 main traffic bits and 137 signal traffic bits. This frame is followed by 12 frame quality display bits and 8 tail bits.

Figure 9c shows the 14.4 kbps blur and glitch frame used for the transmission of 1/4-speed main traffic and signal traffic. The frame provides a bit to remove the display bit and provides a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 0001 to show that the data in the packet is 1/4-speed main traffic and signal traffic. The frame has 54 main traffic bits and 207 signal traffic bits. This frame is followed by 12 frame quality display bits and 8 tail bits.

Figure 9d shows the 14.4 kbps blur and glitch frame used for the transmission of 1/8-speed main traffic and signal traffic. The frame provides a bit to remove the display bit and provides a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 0010 to show that the data in the packet is 1/8-speed main traffic and signal traffic. The frame has 20 main traffic bits and 241 signal traffic bits and includes 12 frame quality display bits and 8 tail bits.

Figure 9e shows the 14.4 kbps blank and glitch boxes used for signal transmission. The frame provides a bit to remove the display bit and provides a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 0011 to show that the data in the packet is a signal service. This frame has 261 signal signal bits, 12 frame quality display bits and 8 tail bits.

Figure 9f shows the 7.2 kbps box used only for half-speed main traffic transmission. The frame provides a removal display bit. The mixed mode bit is set to 0. This frame provides 124 main traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9g shows the 7.2 kbps blur and glitch frame used for the transmission of 1/4-speed main traffic and signal traffic. The frame provides a removal display bit. The mixed mode bit is set to 1.3 and the frame mode bit is set to 000. The frame has 54 main traffic bits, 67 signal traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9h shows the 7.2 kbps blur and glitch frame used for the transmission of 1/8-speed main traffic and signal traffic. The frame provides a removal display bit. The mixed mode bit is set to 1.3 and the frame mode bit is set to 001. The frame has 20 main traffic bits, 101 signal traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9i shows the 7.2 kbps blank and glitch frames used for signal transmission. The frame provides a removal display bit. The mixed mode bit is set to 1.3 and the frame mode bit is set to 010. The frame has 121 signal service bits, 10 frame quality display bits and 8 tail bits.

Figure 9j shows the 3.6 kbps box used only for the transmission of 1/4-speed main traffic. The frame provides a removal display bit. The mixed mode bit is set to 0. The frame does not provide frame mode bits. This frame has 54 main traffic bits, 8 frame quality display bits and 8 tail bits.

Figure 9k shows the 3.6 kbps blur and glitch frame used for the transmission of 1/8-speed main traffic and signal traffic. The frame provides a removal display bit. The mixed mode bit is set to 1.2 and the frame mode bit is set to 00. The frame has 20 main traffic bits, 32 signal traffic bits, 8 frame quality display bits and 8 tail bits.

Figure 91 shows the 3.6 kbps blank and glitch boxes used for signal transmission. The frame provides a removal display bit. The mixed mode bit is set to 1.2 and the frame mode bit is set to 01. This frame has 52 signal service bits, 8 frame quality display bits and 8 tail bits.

Figure 9m shows the 1.8 kbps frame used only for the transmission of 1/8-speed main traffic. The frame provides a removal display bit. The mixed mode bit is set to 0. The frame does not provide frame mode bits. This frame has 20 main traffic bits, 6 frame quality display bits and 8 tail bits.

Figure 9n shows the 14.4 kbps blur and glitch frames used for half-speed primary and secondary transmission. The frame provides a de-display bit and a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 0100 to show that the data in the packet is half-speed primary traffic and secondary traffic. This frame has 124 main traffic bits, 137 secondary traffic bits, 12-frame quality display bits and 8 tail bits.

Figure 9o shows the 14.4 kbps blur and glitch frames used for the transmission of 1/4-speed primary and secondary traffic. The frame provides a de-display bit and a reserved bit. The mixed mode bit is set to 1.4. The frame mode bit is set to 0101 to show that the data in the packet is 1/4-speed main traffic and signal traffic. This frame has 54 main traffic bits, 207 secondary traffic bits, 12 frame quality display bits and 8 tail bits.

Figure 9p shows the 14.4 kbps ambiguity and glitch frame used for the transmission of frames containing 1/8-speed primary traffic and secondary traffic. The frame provides a de-display bit and a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 0110 to show that the data in the packet is 1/8-speed main traffic and signal traffic. The frame has 20 main traffic bits, 214 secondary traffic bits, 12 frame quality display bits and 8 tail bits.

Figure 9q shows the 14.4 kbps blank and glitch boxes used for the transmission of secondary traffic. The frame provides a de-display bit and a reserved bit. The mixed mode bit is set to 1.4 and the frame mode bit is set to 0111. This frame has 261 secondary traffic bits, 12 frame quality display bits and 8 tail bits.

Figure 9r shows the 14.4 kbps blur and glitch frame used for the transmission of 1/8-speed primary data, secondary and signal services. The frame provides a de-display bit and a reserved bit. The mixed mode bit is set to 1. The frame mode bit is set to 1000 to show that the data in the packet is 1/8-speed primary data, secondary and signal traffic. This frame has 20 main traffic bits. 221 signal service bit, 20 secondary service bit, 12 frame quality display bit and 8 tail bit.

Figure 9s shows the 7.2 kbps blur and glitch frame with 1/4-speed primary and secondary traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 011. This frame has 54 main traffic bits, 67 secondary traffic bits, 12 frame quality display bits and 8 tail bits.

Figure 9t shows the 7.2 kbps blur and glitch frame with 1/8-speed primary and secondary traffic. Provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 100. There are a total of 20 main traffic bits, 101 secondary traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9u shows the 7.2 kbps blank and glitch box with only secondary traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 101. This frame has 121 secondary traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9y shows the 7.2 kbps blur and glitch frame with 1/8-speed primary traffic, secondary and signal traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 110. The frame has 20 main traffic bits, 81 signal traffic bits, 20 secondary traffic bits, 10 frame quality display bits and 8 tail bits.

Figure 9w shows the 3.6 kbps blur and glitch frame with 1/8-speed primary and secondary traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 10. The frame has 20 main traffic bits, 32 secondary traffic bits, 8 frame quality display bits and 8 tail bits.

Figure 9x shows a 3.6 kbps blank and glitch box with only secondary traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 11. This frame has 52 secondary traffic bits, 8 frame quality display bits and 8 tail bits.

Figure 9y shows a 1.8 kbps blank and glitch box with only secondary traffic. The frame provides a removal display bit. The mixed mode bit is set to 1. The frame mode bit is set to 11. This frame has 20 secondary traffic bits, 6 frame quality display bits and 8 tail bits.

This case provides the foregoing description of preferred examples so that anyone familiar with the technical field can make or use the present invention. Various modifications to these examples will be very obvious to those familiar with the technical field, and the general principles defined herein are applicable to other examples without using original skills. Therefore, the present invention is not intended to be limited to the examples shown in this article, but should be in accordance with the maximum scope of the principles and novel features disclosed in this article.