Method and apparatus for the formatting of data for transmission
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20 claims: 2 independent, 18 dependent
- 1A method for formatting digital data in a data frame, for use in a digital communication system in which digital data is transmitted in data frames of a preselected time duration, comprising the steps of:providing a set of data bits of a first data type;generating a set of tail bits (T) for being appended to said set of data bits of said first data type;and providing in said data frame, in respective order said set of data bits of said first data type and said tail bits (T);characterized by: said set of data bits of said first data type having a bit count corresponding to one of a plurality of predetermined bit counts;when said bit count is a highest bit count or a next to highest bit count of said plurality of predetermined bit counts generating a set of parity check bits for said set of data bits of said first data type;and when said bit count is said highest bit count or said next to highest bit count providing in said data frame, in respective order, said set of data bits of said first data type, said parity check bits, and said tail bits (T).
- 2The method of Claim 1 further comprising the steps of:when said bit count of said set of data bits of said first data type is said highest bit count generating a mode bit (MM) of a first bit value (MM = 0);and providing said mode bit (MM) of said first bit value (MM = 0) in said data frame preceding said set of data bits of said first data type.
- 3The method of Claim 1 further comprising the steps of:when said set of data bits of said first data type are of said highest bit count providing a set of data bits of a second data type, generating said set of parity check bits for said set of data bits of said first data type and said set of data bits of said second data type;generating said set of tail bits (T) for being appended to said set of data bits of said first data type and said set of data bits of said second data type;and providing in said data frame, in respective order, said set of data bits of said first data type, said set of data bits of said second data type, said parity check bits, and said tail bits (T).
- 4The method of Claim 1 further comprising the steps of:when said set of data bits of said first data type are of said highest bit count providing a set of data bits of a second data type;generating a mode bit (MM) of a second bit value (MM = 1);generating said set of parity check bits for said set of data bits of said first data type and said set of data bits of said second data type;generating said set of tail bits (T) for being appended to said set of data bits of said first data type and said set of data bits of said second data type;and providing in said data frame, in respective order, said mode bit (MM) of said second bit value (MM = 1), said set of data bits of said first data type, said set of data bits of said second data type, said parity check bits, and said tail bits (T).
- 5A communication system for transmitting information in the form of a plurality of digital data types, comprising:a formatting means (18) responsive to at least a first type of digital data and a second type of digital data for producing a data frame including a set of data bits;a bit generator means (20) connected to the formatting means for: generating tail bits (T) for being appended to the set of data bits;providing in the data frame, in respective order, the set of data bits and the tail bits: modulation means (26) connected to the bit generator means (20) for producing a modulated data frame by modulating the data frame according to modulation procedure, and transmission means (56, 100) connected to the modulation means (26) for transmitting the modulated data frame;characterized by the bit generator means (20) being further for: in response to a first particular bit count of data bits of a first data type in the set of data bits, generating parity check bits for the set of data bits;and providing in the data frame, in respective order, the set of data bits, the parity check bits when the set of data bits includes the particular bit count of data bits of the first type and the tail bits (T).
- 6The communication system of Claim 5, wherein:the first particular bit count is a highest bit count or a next-to-highest bit count.
- 7The communication system of Claim 5, wherein the bit generator means (20) is further for:generating a mode bit (MM) in response to a second particular bit count, the mode bit (MM) indicating a type of data bits in the set of data bits;and providing in the data frame, in respective order, the mode bit (MM), the data bits, the parity check bits when the set of data bits includes the first particular bit count of data bits of the first data type, and the tail bits (T).
- 8The communication system of Claim 7, wherein the bit generator means (20) is further for setting the mode bit (MM) to a first state (MM = 0) when the set of data bits includes only data bits of the first data type.
- 9The communication system of Claim 8, wherein the bit generator means (20) is further for setting the mode bit (MM) to a second state (MM = 1) when the set of data bits includes data bits of a second data type.
- 10The communication system of Claim 9, wherein the bit generator means (20) is for setting the mode bit (MM) to a second state (MM = 1) when the set of data bits includes data bits of the first data type and data bits of the second data type.
- 11The communication system of Claim 9, wherein the bit generator means (20) is for setting the mode bit (MM) to the second state (MM = 1) when the set of data bits includes only data bits of the second data type.
- 12The communication system of Claim 9, wherein the bit generator means (20) is for setting the mode bit to the second state (MM = 1) when the set of data bits includes only data bits of the second data type and data bits of a third data type.
- 13The communication system of Claim 5, further including a vocoder means (16) connected to the formatting means (18) for generating the first type of digital data, the first type of digital data including data bits of the first data type.
- 14The communication system of Claim 9, wherein the data bits of the first data type represent voice information and the data bits of the second data type represent signalling information.
- 15The communication system of Claim 9, wherein the data bits of the first data type represent voice information and the data bits of the second data type represent user data.
- 16The communication system of Claim 5, wherein the modulation procedure is a CDMA procedure.
- 17A communication system according to Claim 5 which modulates and transmits data frames on forward and reverse channels, comprising a sub-system for producing data frames, the sub-system comprising:said formatting means (18) for generating data frames in which each data frame includes a set of traffic data bits, each set of traffic data bits including data bits of one or more data types;and said bit generator means (20) connected to the formatting means (18) for generating data frames, the bit generator means (20) being for: generating a mode bit (MM) indicating types of data bits for each data frame having a highest bit count;generating parity check bits for traffic bits for each data frame having a highest bit count or a next-to-highest bit count of data bits of a first data type;generating tail bits (T) for being appended to traffic data bits of each data frame;and providing in each data frame, in respective order: a mode bit, a set of traffic data bits, parity check bits and tail bits (T) for each data frame having the highest bit count;a set of traffic data bits, parity check bits, and tail bits (T) for each data frame having only the next-to-highest bit count;and a set of traffic data bits and tail bits (T) for all other data frames.
- 18The communication system according to Claim 17, wherein the data bits of the first data type are primary traffic data bits.
- 19The communication system according to Claim 17, wherein the mode bit (MM) indicates a set of traffic bits containing:only data bits of the first data type;or, only data bits of a second data type;or, only data bits of a third data type;or, only data bits of the first data type and data bits of the second data type;or only data bits of the first data type and data bits of the third data type.
- 20The communication system according to Claim 19, wherein:the data bits of the first data type represent voice data;the data bits of the second data type represent signalling data;and the data bits of the third data type represent user data.
Independent claims20
71 paragraphs in 4 sections, as filed
BACKGROUND OF THE INVENTION
I. Field of the Invention
0001The present application relates to the organization of data for transmission. More particularly, the present invention relates to a novel and improved method and apparatus for formatting vocoder data, non-vocoder data and signaling data for transmission.
II. Description of the Related Art
0002In the field of digital communications various arrangements of digital data for transmission are used. The data bits are organized according to commonly used formats for transfer over the communication medium.
0003It is therefore an object of the present invention to provide a data format which facilitates the communication of various-types of data, and data of various rates, to be communicated in a structured form.
0004US-A-4,291,409 discloses a method and apparatus employing spread spectrum techniques in a wide bandwidth communications system. A plurality of transmitting stations are each equipped to provide a transmission signal representing a pseudo-random coded, phase modulated, message signal. The transmission signal is directed through a bandwidth which encompasses otherwise dedicated, relatively narrow bandwidth repeater channels, employed in connection with a communications satellite, to a generally fixed receiver station. At the receiving station, the incoming signal is (a) code acquired and tracked, (b) carrier acquired and tracked, (c) phase locked to the receiver local oscillator and (d) coherently demodulated to extract the desired data. The receiving station advantageously employs plural receiving elements each having a pseudo-random sequence code matched filter which significantly reduces code acquisition time by obviating the necessity of exhaustively correlating the incoming signal with a replica of the pseudo-random code word at the receiver station.
0005EP-A2-0 412 583 discloses a time division multiple access (TDMA) communication device controller, which controls all signaling, synchronization and supervisory functions. In one embodiment, the invention operates to control a remote communication device having a vocoder and buffering means. The remote communication device is enabled to operate as a dispatch, full duplex or a combination dispatch/full duplex communication device. In another embodiment, a primary station (repeater) is controlled to operate as a single frequency repeater (SFR) or as a multi-frequency TDMA repeater. A communication channel is divided into time sub-slots which may be allocated to different users. The number of sub-slots allocated to a given user depends on the quality of speech required by the user. At the beginning of a call the user selects the required quality of speech. For the duration of the call the speech is encoded at that fixed rate. The encoded speech is provided to a buffer. The buffer is capable of holding enough encoded data to fill a time sub-slot. As soon as the buffer is filled the data is entered into the sub-slot for transmission. If the user wants to provide speech and digital data, this need is specified prior to transmission. The communication system then provides enough sub-slots to carry the fixed rate speech data and also provides additional sub-slots to carry the fixed rate digital data. When the call is completed the caller is billed in accordance with the number of sub-slots used.
0006WO 91/07030 discloses a distributed synchronization method for a wireless fast packet communication system. The distributed synchronization method provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic synchronization of packets. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions.
0007The method includes generating a set of tail bits for being appended to data in a frame.
SUMMARY OF THE INVENTION
0008The present invention is a novel and improved method and system for formatting digital data for communication over a transmission medium.
0009In communication systems it is important to utilize a data format which permits a full communication of data between users. In a communication system, such as a code division multiple access (CDMA) communication system, in which it is desirable to communicate various types of data, and at various rates, a data format must be selected which permits maximum flexibility within a predefined structure. Furthermore to maximize resources it is desirable to permit a sharing of the format to permit different types of data to be organized together. In such situations it is necessary to structure the data in a manner in which it may be readily extracted according to the corresponding type and rate.
0010A method and apparatus is provided for arranging various types of data, and at various rates, into a uniquely structured format for transmission. Data is provided as vocoder data or different types of non-vocoder data. The data is organized into frames of a predetermined time duration for transmission. The data frames are organized, depending on the data, to be at one of several data rates. Vocoder data is provided at one of several data rates and is organized in the frame according to a predetermined format. Frames may be formatted with a sharing of vocoder data with non-vocoder data to be at a highest frame data rate. Non-vocoder data may be organized so as to also be at a highest frame rate. Additional control data may be provided within the data frames to support various aspects of the transmission and recovery upon reception.
0011The invention in its widest aspect is set forth in Claims 1 and 5 written with regard to WO 91/07030 as nearest prior art.
BRIEF DESCRIPTION OF THE DRAWINGS
0012The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein: <ul id="ul0001" list-style="none"><li>Figure 1 is a block diagram illustrating an exemplary embodiment for a transmitter portion of a transceiver;</li><li>Figures 2a - 2h are a series of diagrams illustrating frame data formats for the various data rates, types and modes;</li><li>Figure 3 is a diagram illustrating an exemplary circuit implementation of the CRC and Tail Bit generator of Figure 1;</li><li>Figures 4a - 4e is a flow chart of the formatting of frames of data;</li><li>Figures 5a - 5d illustrate in a series of charts the ordering of code symbols in the interleaver array for transmission data rates of 9.6, 4.8, 2.4 and 1.2 kbps, respectively;</li><li>Figures 6a - 6c is a chart illustrating the Walsh symbol corresponding to each encoder symbol group;</li><li>Figure 7 is a block diagram illustrating the long code generator of Figure 1;</li><li>Figures 8a - 8c are a series of diagrams illustrating long code masks for the various channel type; and</li><li>Figure 9 is a graph illustrating the frequency response of the digital filters of Figure 1.</li></ul>
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
0013Referring now to the drawings, Figure 1 illustrates an exemplary embodiment of a transmit portion 10 of a CDMA mobile station transceiver or PCN handset. In a CDMA cellular communication system a forward CDMA channel is used to transmit information from a cell base station to the mobile station. Conversely a reverse CDMA channel is used to transmit information from the mobile station to the cell base station. The communication of signals from the mobile station may be characterized in the form of an access channel or a traffic channel communication. The access channel is used for short signaling messages such as call originations, responses to pages, and registrations. The traffic channel is used to communicate (1) primary traffic, typically includes user speech, or (2) secondary traffic, typically user data, or (3) signaling traffic, such as command and control signals, or (4) a combination of primary traffic and secondary traffic or (5) a combination of primary traffic and signaling traffic.
0014Transmit portion 10 enables data to be transmitted on the reverse CDMA channel at data rates of 9.6 kbps, 4.8 kbps, 2.4 kbps or 1.2 kbps. Transmissions on the reverse traffic channel may be at any of these data rates while transmissions on the access channel are at the 4.8 kbps data rate. The transmission duty cycle on the reverse traffic channel will vary with the transmission data rate. Specifically, the transmission duty cycle for each rate is provided in Table I. As the duty cycle for transmission varies proportionately with the data rate, the actual burst transmission rate is fixed at 28,800 code symbols per second. Since six code symbols are modulated as one of 64 Walsh symbols for transmission, the Walsh symbol transmission rate shall be fixed at 4800 Walsh symbols per second which results in a fixed Walsh chip rate of 307.2 kcps.
0015All data that is transmitted on the reverse CDMA channel is convolutional encoded, block interleaved, modulated by 64-ary modulation, and direct-sequence PN spread prior to transmission. Table I further defines the relationships and rates for data and symbols for the various transmission rates on the reverse traffic channel. The numerology is identical for the access channel except that the transmission rate is fixed at 4.8 kbps, and the duty cycle is 100%. As described later herein each bit transmitted on the reverse CDMA channel is convolutional encoded using a rate 1/3 code. Therefore, the code symbol rate is always three times the data rate. The rate of the direct-sequence spreading functions shall be fixed at 1.2288 MHz, so that each Walsh chip is spread by precisely four PN chips. <tables id="tabl0001" num="0001"><table frame="all"><title>TABLE I</title><tgroup cols="5" colsep="1" rowsep="1"><colspec colnum="1" colname="col1" colwidth="31.50mm" /><colspec colnum="2" colname="col2" colwidth="31.50mm" /><colspec colnum="3" colname="col3" colwidth="31.50mm" /><colspec colnum="4" colname="col4" colwidth="31.50mm" /><colspec colnum="5" colname="col5" colwidth="31.50mm" /><thead valign="top"><row rowsep="1"><entry namest="col1" nameend="col1" align="left">Bit Rate (kbps)</entry><entry namest="col2" nameend="col2" align="center">9.6</entry><entry namest="col3" nameend="col3" align="center">4.8</entry><entry namest="col4" nameend="col4" align="center">2.4</entry><entry namest="col5" nameend="col5" align="center">1.2</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">PN Chip Rate (Mcps)</entry><entry namest="col2" nameend="col2" align="center">1.2288</entry><entry namest="col3" nameend="col3" align="center">1.2288</entry><entry namest="col4" nameend="col4" align="center">1.2288</entry><entry namest="col5" nameend="col5" align="center">1.2288</entry></row><row><entry namest="col1" nameend="col1" align="left">Code Rate (bits/code symbol)</entry><entry namest="col2" nameend="col2" align="center">1/3</entry><entry namest="col3" nameend="col3" align="center">1/3</entry><entry namest="col4" nameend="col4" align="center">1/3</entry><entry namest="col5" nameend="col5" align="center">1/3</entry></row><row><entry namest="col1" nameend="col1" align="left">TX Cycle (%)</entry><entry namest="col2" nameend="col2" align="center">100.0</entry><entry namest="col3" nameend="col3" align="center">50.0</entry><entry namest="col4" nameend="col4" align="center">25.0</entry><entry namest="col5" nameend="col5" align="center">12.5</entry></row><row><entry namest="col1" nameend="col1" align="left">Code Symbol Rate (sps)</entry><entry namest="col2" nameend="col2" align="center">28,800</entry><entry namest="col3" nameend="col3" align="center">28,800</entry><entry namest="col4" nameend="col4" align="center">28,800</entry><entry namest="col5" nameend="col5" align="center">28,800</entry></row><row><entry namest="col1" nameend="col1" align="left">Modulation (code symbol/Walsh symbol)</entry><entry namest="col2" nameend="col2" align="center">6</entry><entry namest="col3" nameend="col3" align="center">6</entry><entry namest="col4" nameend="col4" align="center">6</entry><entry namest="col5" nameend="col5" align="center">6</entry></row><row><entry namest="col1" nameend="col1" align="left">Walsh Symbol Rate (sps)</entry><entry namest="col2" nameend="col2" align="center">4800</entry><entry namest="col3" nameend="col3" align="center">4800</entry><entry namest="col4" nameend="col4" align="center">4800</entry><entry namest="col5" nameend="col5" align="center">4800</entry></row><row><entry namest="col1" nameend="col1" align="left">Walsh Chip; Rate (kcps)</entry><entry namest="col2" nameend="col2" align="center">307.20</entry><entry namest="col3" nameend="col3" align="center">307.20</entry><entry namest="col4" nameend="col4" align="center">307.20</entry><entry namest="col5" nameend="col5" align="center">307.20</entry></row><row><entry namest="col1" nameend="col1" align="left">Walsh Symbol (µs)</entry><entry namest="col2" nameend="col2" align="center">208.33</entry><entry namest="col3" nameend="col3" align="center">208.33</entry><entry namest="col4" nameend="col4" align="center">208.33</entry><entry namest="col5" nameend="col5" align="center">208.33</entry></row><row><entry namest="col1" nameend="col1" align="left">PN Chips/Code Symbol</entry><entry namest="col2" nameend="col2" align="center">42.67</entry><entry namest="col3" nameend="col3" align="center">42.67</entry><entry namest="col4" nameend="col4" align="center">42.67</entry><entry namest="col5" nameend="col5" align="center">42.67</entry></row><row><entry namest="col1" nameend="col1" align="left">PN Chips/Walsh Symbol</entry><entry namest="col2" nameend="col2" align="center">256</entry><entry namest="col3" nameend="col3" align="center">256</entry><entry namest="col4" nameend="col4" align="center">256</entry><entry namest="col5" nameend="col5" align="center">256</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">PN Chips/Walsh Chip</entry><entry namest="col2" nameend="col2" align="center">4</entry><entry namest="col3" nameend="col3" align="center">4</entry><entry namest="col4" nameend="col4" align="center">4</entry><entry namest="col5" nameend="col5" align="center">4</entry></row></tbody></tgroup></table></tables>
0016Transmit portion 10, when functioning in mode in which primary traffic is present, communicates acoustical signals, such as speech and/or background noise, as digital signals over the transmission medium. To facilitate the digital communication of acoustical signals, these signals are sampled and digitized by well known techniques. For example, in Figure 1, sound is converted by microphone 12 to an analog signal which is then converted to a digital signal by codec 14. Codec 14 typically performs an analog to digital conversion process using a standard 8 bit/µlaw format. In the alternative, the analog signal may be directly converted to digital form in a uniform pulse code modulation (PCM) format. In an exemplary embodiment codec 14 uses an 8 kHz sampling and provides an output of 8 bit samples at the sampling rate so as to realize a 64 kbps data rate.
0017The 8-bit samples are output from codec 14 to vocoder 16 where a µlaw/uniform code conversion process is performed. In vocoder 16, the samples are organized into frames of input data wherein each frame is comprised of a predetermined number of samples. In a preferred implementation of vocoder 16 each frame is comprised of 160 samples or of 20 msec. of speech at the 8 kHz sampling rate. It should be understood that other sampling rates and frame sizes may be used. Each frame of speech samples is variable rate encoded by vocoder 16 with the resultant parameter data formatted into a corresponding data packet. The vocoder data packets are then output to microprocessor 18 and associated circuitry for transmission formatting. Microprocessor 18 generically includes program instructions contained with a program instruction memory, a data memory, and appropriate interface and related circuitry as is known in the art.
0018A preferred implementation of vocoder 16 utilizes a form of the Code Excited Linear Predictive (CELP) coding techniques so as to provide a variable rate in coded speech data. A Linear Predictive Coder (LPC) analysis is performed upon a constant number of samples, and the pitch and codebook searches are performed on varying numbers of samples depending upon the transmission rate. A variable rate vocoder of this type is described in further detail in WO 92/22891. Vocoder 16 may be implemented in an application specific integrated circuit (ASIC) or in a digital signal processor.
0019In the variable rate vocoder just mentioned, the speech analysis frames are 20 msec. in length, implying that the extracted parameters are output to microprocessor 18 in a burst 50 times per second. Furthermore the rate of data output is varied from roughly 8 kbps to 4 kbps to 2 kbps, and to 1 kbps.
0020At full rate, also referred to as rate 1, data transmission between the vocoder and the microprocessor is at an 8.55 kbps rate. For the full rate data the parameters are encoded for each frame and represented by 160 bits. The full rate data frame also includes a parity check of 11 bits thus resulting in a full rate frame being comprised of a total of 171 bits. In the full rate data frame, the transmission rate between the vocoder and the microprocessor absent the parity check bits would be 8 kbps.
0021At half rate, also referred to as rate 1/2, data transmission between the vocoder and the microprocessor is at a 4 kbps rate with the parameters encoded for each frame using 80 bits. At quarter rate, also referred to as rate 1/4, data transmission between the vocoder and the microprocessor is at a 2 kbps rate with the parameters encoded for each frame using 40 bits. At eighth rate, also referred to as rate 1/8, data transmission between the vocoder and the microprocessor is slightly less than a 1 kbps rate with the parameters encoded for each frame using 16 bits.
0022In addition, no information may be sent in a frame between the vocoder and the microprocessor. This frame type, referred to as a blank frame, may be used for signaling or other non-vocoder data.
0023The vocoder data packets are then output to microprocessor 18 and CRC and Tail Bit generator 20 for completing the transmission formatting. Microprocessor 18 receives packets of parameter data every 20 msec. along with a rate indication for the rate the frame of speech samples was encoded. Microprocessor 18 also receives, if present, an input of secondary traffic data for output to generator 20. Microprocessor 18 also internally generates signaling data for output to generator 20. Data whether it is primary traffic, secondary traffic or signaling traffic matter, if present, is output from microprocessor 18 to generator 20 every 20 msec. frame.
0024Generator 20 generates and appends at the end of all full and half rate frames a set of parity check bits or cyclic redundancy check bits (CRC Bits) which are used at the receiver as a frame quality indicator. For a full rate frame, regardless of whether the data is a full rate primary, secondary or signaling traffic, or a combination of half rate primary and secondary traffic, or a combination of half rate primary and signaling traffic, generator 20 preferably generates a set of CRC Bits according to a first polynomial. For a half rate data frame, generator 20 also generates a set of CRC Bits preferably according to a second polynomial. Generator 20 further generates for all frame rates a set of Encoder Tail Bits which follow the CRC bits, if present, or data if CRC bits are not present, at the end of the frame. Further details of the operation on microprocessor 18 and generator 20 are provided later herein with reference to Figures 3 and 4.
0025Reverse traffic channel frames provided from generator 20 at the 9.6 kbps rate are 192 bits in length and span the 20 msec. frame. These frames consist of a single Mixed Mode Bit, auxiliary format bits if present, message bits, a 12-bit frame quality indicator (CRC), and 8 Encoder Tail Bits as shown in Figures 2a - 2e. The Mixed Mode Bit shall be set to '0' during any frame in which the message bits are primary traffic information only. When the Mixed Mode Bit is '0', the frame shall consist of the Mixed Mode Bit, 171 Primary Traffic bits, 12 CRC Bits, and 8 Encoder Tail Bits.
0026The Mixed Mode Bit is set to '1' for frames containing secondary or signaling traffic. In these instances the first bit following the Mixed Mode Bit is a Burst Format Bit which specifies whether the frame is in a "blank-and-burst" or a "dim-and-burst" format. A "blank-and-burst" operation is one in which the entire frame is used for secondary or signaling traffic while a "dim-and-burst" operation is one in which the primary traffic shares the frame with either secondary or signaling traffic. If the Burst Format Bit is a '0', the frame is of the "dim and burst format", and if a '1' the frame is of the "blank and burst format".
0027The second bit following the Mixed Mode Bit is a Traffic Type Bit. The Traffic Type Bit is used to specify whether the frame contains secondary or signaling traffic. If the Traffic Type Bit is a '0', the frame contains signaling traffic, and if a '1', the frame contains secondary traffic. Figures 2b - through 2e illustrate the Burst Format Bit and the Traffic Type Bit.
0028When the Burst Format Bit is '0' denoting dim-and-burst, the two bits following the Traffic Type Bit are Traffic Mode Bits. These bits indicate the number of bits that are used for primary traffic information and the number of bits that shall be used for either signaling or secondary traffic information within that frame. For a default mode, only the Traffic Mode '00' is defined with all other traffic modes reserved for other bit type and numbers. Referring to Figures 2b and 2c, in the exemplary and preferred embodiment, 80 bits are used for primary traffic (half rate vocoder data packet) while 86 and 87 bits are respectively used for signaling and secondary traffic.
0029In frames where there is signaling traffic present the first bit of the frame's signaling portion is a Start of Message (SOM) Bit. The SOM Bit is a '1' if a reverse traffic channel message (signaling message) begins at the following bit. Generally the first bit of a reverse traffic channel message does not begin anywhere else in the frame other than following the SOM Bit. However should the frame contain part of a message that began in a previous frame the SOM Bit is a '0'. If the SOM Bit is a '0' the following bit is part of the message but it is not the first bit of the complete message.
0030In the preferred implementation only primary traffic is transmitted in frames at the 4.8 kbps, 2.4 kbps, and 1.2 kbps rates. Mixed mode operation is generally not supported at rates other than the 9.6 kbps rate, although it may be readily configured to do so. The frame formats for these particular rates are shown in Figures 2f - 2h. For the 4.8 kbps rate, the frame is 96 bits in length with the bits spaced over the 20 msec. time period of the frame as described later herein. The 4.8 kbps rate frame contains 80 primary traffic bits, an 8-bit frame quality indicator (CRC), and 8 Encoder Tail Bits. For the 2.4 kbps rate, the frame is 48 bits in length with the bits spaced over the 20 msec. time period of the frame as also described later herein. The 2.4 kbps rate frame contains 40 primary traffic bits and 8 Encoder Tail Bits. For the 1.2 kbps rate, the frame is 24 bits in length with the bits spaced over the 20 msec. time period of the frame as also described later herein. The 1.2 kbps rate frame contains 16 primary traffic bits and 8 encoder tail bits.
0031In a preferred embodiment the access channel data is generated by microprocessor 18 for transmission at a rate of 4.8 kbps. As such the data is prepared in a manner identical to that of 4.8 kbps frame format data, such as encoding, interleaving as Walsh encoding. In the encoding scheme i implemented for the 4.8 kbps data, whether reverse traffic channel data or access channel data, redundant data is generated. Unlike the reverse traffic channel where the redundant data is eliminated in the transmission, in the access channel all data including redundant data is transmitted. Details on the transmission aspects of frames of access channel data are provided later herein.
0032Figure 3 illustrates an exemplary implementation of the elements for formatting the data in accordance with Figures 2a - 2h. In Figure 3 data is transmitted from microprocessor 18 (Figure 1) to generator 20. Generator 20 is comprised of data buffer and control logic 60, CRC circuits 62 and 64, and Tail Bit circuit 66. Along with data provided from the microprocessor a rate command may optionally be provided. Data is transferred for each 20 msec frame from the microprocessor to logic 60 where temporarily stored. For each frame, logic 60 may for each frame count the number of bits transmitted from the microprocessor, or in the alternative use the rate command and a count of the clock cycles in formatting a frame of data.
0033Each frame of the traffic channel includes a frame quality indicator. For the 9.6 kbps and 4.8 kbps transmission rates, the frame quality indicator is the CRC. For the 2.4 kbps and 1.2 kbps transmission rates, the frame quality indicator is implied, in that no extra frame quality bits are transmitted. The frame quality indicator supports two functions at the receiver. The first function is to determine the transmission rate of the frame, while the second function is to determine whether the frame is in error. At the receiver these determinations are made by a combination of the decoder information and the CRC checks.
0034For the 9.6 kbps and 4.8 kbps rates, the frame quality indicator (CRC) is calculated on all bits within the frame, except the frame quality indicator (CRC) itself and the Encoder Tail Bits. Logic 60 provides the 9.6 kbps and 4.8 kbps rate data respectively to CRC circuits 62 and 64. Circuits 62 and 64 are typically constructed as a sequence of shift registers, modulo-2 adders (typically exclusive-OR gates) and switches as illustrated.
0035The 9.6 kbps transmission rate data uses a 12-bit frame quality indicator (CRC), which is transmitted within the 192-bit long frame as discussed with reference to Figures 2a - 2e. As illustrated in Figure 3 for CRC circuit 62, the generator polynomial for the 9.6 kbps rate is as follows:<maths id="math0001" num="(1)"><math display="block"><mrow><msup><mrow><mtext>g(x) = x</mtext></mrow><mrow><mtext>12</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>11</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>10</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>9</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>8</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>4</mtext></mrow></msup><mtext> + x + 1.</mtext></mrow></math><img file="EP0621998B1_D0001.tif" /></maths>
0036The 4.8 kbps transmission rate data uses an 8-bit CRC, which is transmitted within the 96-bit long frame as discussed with reference to Figure 2f. As illustrated in Figure 3 for CRC circuit 64, the generator polynomial for the 4.8 kbps rate is as follows:<maths id="math0002" num="(2)"><math display="block"><mrow><msup><mrow><mtext>g(x) = x</mtext></mrow><mrow><mtext>8</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>7</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>4</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>3</mtext></mrow></msup><mtext> + x + 1.</mtext></mrow></math><img file="EP0621998B1_D0002.tif" /></maths>
0037Initially, all shift register elements of circuits 62 and 64 are set to logical one ('1') by an initialization signal from logic 60. Furthermore logic 60 set the switches of circuits 62 and 64 in the up position.
0038For 9.6 kbps rate data, the registers of circuit 62 are then clocked 172 times for the 172 bits in the sequence of primary traffic, secondary traffic or signaling bits or a mixture thereof along with the corresponding mode/format indicator bits as input to circuit 62. After 172 bits are clocked through circuit 62, logic 60 then sets the switches of circuit 62 in the down position with the registers of circuit 62 then being clocked an additional 12 times. As a result of the 12 additional clockings of circuit 62, 12 additional output bits are generated which are the CRC bits. The CRC bits, in the order calculated, are appended to the end of the 172 bits as output from circuit 62. It should be noted that the 172 bits output from logic 60 which pass through circuit 62 are undisturbed by the computation of the CRC bits 5 and are thus output from circuit 62 in the same order and at the same value at which they entered.
0039For 9.6 kbps rate data bits are input to circuit 64 from logic 60 in the following order. For the case of primary traffic only, the bits are input to circuit 64 from logic 60 in the order of the single mixed mode (MM) bit followed by the 171 primary traffic bits. For the case of "dim and burst" with primary and signaling traffic, the bits are input to circuit 64 from logic 60 in the order of the single MM bit, a single burst format (BF) bit, a traffic type (TT) bit, a pair of traffic mode (TM) bits, 80 primary traffic bits, a start of message (SOM) bit, and 86 signaling traffic bits. For the case of "dim and burst" with primary and secondary traffic, the bits are input to circuit 64 from logic 60 in the order of the single MM bit, the single BF bit, the TT bit, the pair of TM bits, 80 primary traffic bits and 87 signaling traffic bits. For the case of "blank and burst" data format with signaling traffic only, the bits are input to circuit 64 from logic 60 in the order of the single MM bit, the single BF bit, the TT bit, the SOM bit and 168 signaling traffic bits. For the case of "blank and burst"data format with secondary traffic only, the bits are input to circuit 64 from logic 60 in the order of the single MM bit, the single BF bit, the TT bit and 169 signaling traffic bits.
0040Similarly for 4.8 kbps rate data, the registers of circuit 64 are clocked 80 times for the 80 bits of primary traffic data, or for the 80 bits of access channel data, as input to circuit 64 from logic 60. After the 80 bits are clocked through circuit 64, logic 60 then sets the switches of circuit 64 in the down position with the registers of circuit 64 then being clocked an additional 8 times. As a result of the 12 additional clockings of circuit 62, 12 additional output bits are generated which are the CRC bits. The CRC bits, in the order calculated, are again appended to the end of the 80 bits as output from circuit 64. It should again be noted that the 80 bits output from logic 60 which pass through circuit 64 are undisturbed by the computation of the CRC bits and are thus output from circuit 64 in the same order and at the same value at which they entered.
0041The bits output from either of circuits 62 and 64 are provided to switch 66 which is under the control of logic 60. Also input to switch 66 are the 40 and 16 bits of primary traffic data output from logic 60 for 2.4 kbps and 1.2 kbps data frames. Switch 66 selects between providing an output of the input data (up position) and tail bits at a logical zero ('0') value (down position). Switch 66 is normally set in the up position to permit data from logic 60, and from circuits 62 and 64 if present, to be output from generator 20 to encoder 22 (Figure 1). For the 9.6 kbps and 4.8 kbps frame data, after the CRC bits are clocked through switch 66, logic 60 sets the switch to the down position for 8 clock cycles so as to generate 8 all zero tail bits. Thus for 9.6 kbps and 4.8 kbps data frames, the data as output to the encoder for the frame includes appended after the CRC bits, the 8 tail bits. Similarly for the 2.4 kbps and 1.2 kbps frame data, after the primary traffic bits are clocked from logic 60 through switch 66, logic 60 sets the switch to the down position for 8 clock cycles so as to again generate 8 all zero tail bits. Thus for 2.4 kbps and 1.2 kbps data frames, the data as output to the encoder for the frame includes appended after the primary traffic bits, the 8 tail bits.
0042Figures 4a - 4e illustrate in a series of flow charts the operation of microprocessor 18, and generator 20 in assembling the data into the disclosed frame format. It should be noted that various schemes may be implemented for giving the various traffic types and rates priority for transmission. In an exemplary implementation, when a signaling traffic message is to be sent when there is vocoder data present a "dim and burst" format may be selected. Microprocessor 18 may generate a command to vocoder 16 for the vocoder to encode speech sample frames at the half rate, regardless of the rate at which the vocoder would normally encode the sample frame. Microprocessor 18 then assembles the half rate vocoder data with the signaling traffic into the 9.6 kbps frame as illustrated in Figure 2b. In this case, a limit may be placed on the number of speech frames encoded at the half rate to avoid degradation in the speech quality. In the alternative, microprocessor 18 may wait until a half rate frame of vocoder data is received before assembling the data into the "dim and burst" format. In this case, in order to ensure timely transmission of the signaling data, a maximum limit on the number of consecutive frames at other than half rate may be imposed before a command is sent to the vocoder to encode at half rate. Secondary traffic may be transferred in the "dim and burst" format (Figure 2c) in a similar manner.
0043Similar is the case for the "blank and burst" data formats as illustrated in Figures 2d - 2e. The vocoder may be commanded to not encode the frame of speech samples or the vocoder data is ignored by the microprocessor in constructing the data frame. Prioritizing between generating frame formats of primary traffic of various rate, "dim and burst" traffic, and "blank and burst" traffic is open to many possibilities.
0044Referring back to Figure 1, 20 msec. frames of 9.6 kbps, 4.8 kbps, 2.4 kbps and 1.2 kbps data are thus output from generator 20 to encoder 22. In the exemplary embodiment encoder 22 is a preferably a convolutional encoder, a type of encoder well known in the art. Encoder 22 preferably encodes the data using a rate 1/3 , constraint length k = 9 convolutional code. As an example encoder 22 is constructed with generator functions of g<sub>0</sub> = 557(octal), g<sub>1</sub> = 663(octal) and g<sub>2</sub> = 711(octal). As is well known in the art, convolutional encoding involves the modulo-2 addition of selected taps of a serially time-shifted delayed data sequence. The length of the data sequence delay is equal to k-1, where k is the code constraint length. Since in the preferred embodiment a rate 1/3 code is used, three code symbols, the code symbols (c<sub>0</sub>), (c<sub>1</sub>) and (c<sub>2</sub>), are generated for each data bit input to the encoder. The code symbols (c<sub>0</sub>), (c<sub>1</sub>) and (c<sub>2</sub>) are respectively generated by the generator functions g<sub>0</sub>, g<sub>1</sub> and g<sub>2</sub>. The code symbols are output from encoder 22 to block interleaver 24. The output code symbols are provided to interleaver 24 in the order of the code symbol (c<sub>0</sub>) being first, the code symbol (c<sub>1</sub>) being second and the code symbol (c<sub>2</sub>) being last. The state of the encoder 22, upon initialization, is the all-zero state. Furthermore the use of tail bits at the end of each frame provides a resetting of encoder 22 to an all-zero state.
0045The symbols output from encoder 22 are provided to block interleaver 24 which under the control of microprocessor 18 provides a code symbol repetition. Using a conventional random access memory (RAM) with the symbols stored therein as addressed by microprocessor 18, code symbols may be stored in a manner to achieve a code symbol repetition rate that varies with the data channel.
0046Code symbols are not repeated for the 9.6 kbps data rate. Each code symbol at the 4.8 kbps data rate is repeated 1 time, i.e. each symbol occurs 2 times. Each code symbol at the 2.4 kbps data rate is repeated 3 times, i.e. each symbol occurs 4 times. Each code symbol at the 1.2 kbps data rate is repeated 7 times, i.e. each symbol occurs 8 times. For all data rates (9.6, 4.8, 2.4 and 1.2 kbps), the code repetition results in a constant code symbol rate of 28,800 code symbols per second for the data as output from interleaver 24. On the reverse traffic channel the repeated code symbols are not transmitted multiple times with all but one of the code symbol repetitions deleted prior to actual transmission due to the variable transmission duty cycle as discussed in further detail below. It should be understood that the use of code symbol repetition as an expedient method for describing the operation of the interleaver and a data burst randomizer as discussed again in further detail below. It should be further understood that implementations other than those that use code symbol repetition may be readily devised that achieve the same result and remain within the teaching of the present invention.
0047All code symbols to be transmitted on the reverse traffic channel and the access channel are interleaved prior to modulation and transmission. Block interleaver 24, constructed as is well known in the art, provides an output of the code symbols over a time period spanning 20 msec. The interleaver structure is typically a rectangular array with 32 rows and 18 columns, i.e. 576 cells. Code symbols are written into the interleaver by columns, with repetition for data at the 9.6, 4.8, 2.4 and 1.2 kbps rate, so as to completely fill the 32 × 18 matrix. Figures 5a - 5d illustrate the ordering of write operations of repeated code symbols into the interleaver array for transmission data rates of 9.6, 4.8, 2.4 and 1.2 kbps, respectively.
0048Reverse traffic channel code symbols are output from the interleaver by rows. Microprocessor 18 also controls the addressing of the interleaver memory for outputting the symbols in the appropriate order. The interleaver rows are preferably output in the following order: At 9.6 kbps: 1 2 3 4 5 6 7 8 9 lo 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 At 4.8 kbps: 1 3 2 4 5 7 6 8 9 11 10 12 13 15 14 16 17 19 18 20 21 23 22 24 25 27 26 28 29 31 30 32 At 2.4 kbps: 1 5 2 6 3 7 4 8 9 13 10 14 11 15 12 16 17 21 18 22 19 23 20 24 25 29 26 30 27 31 28 32 At 1.2 kbps: 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 16 17 25 18 26 19 27 20 28 21 29 22 30 23 31 24 32.
0049Access channel code symbols are also output from interleaver 24 by rows. Microprocessor 18 again controls the addressing of the interleaver memory for outputting the symbols in the appropriate order. The interleaver rows are output in the following order at the 4.8 kbps rate for the access channel code symbols: 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 2 18 10 26 6 22 14 30 4 20 12 28 8 24 16 32.
0050It should be noted that other encoding rates, such as a rate 1/2 convolutional code used on the forward transmission channel, along with various other symbol interleaving formats may be readily devised using the basic teaching of the present invention.
0051Referring again to Figure 1, the interleaved code symbols are output from interleaver 24 to modulator 26. In the preferred embodiment modulation for the Reverse CDMA Channel uses 64-ary orthogonal signaling. That is, one of 64 possible modulation symbols is transmitted for each six code symbols. The 64-ary modulation symbol is one of 64 orthogonal waveforms generated preferably using Walsh functions. These modulation symbols are given in Figures 6a - 6c and are numbered 0 through 63. The modulation symbols are selected according to the following formula:<maths id="math0003" num="(3)"><math display="block"><mrow><msub><mrow><mtext>Modulation symbol number = c</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> + 2c</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> + 4c</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext> + 8c</mtext></mrow><mrow><mtext>3</mtext></mrow></msub><msub><mrow><mtext> + 16c</mtext></mrow><mrow><mtext>4</mtext></mrow></msub><msub><mrow><mtext> + 32c</mtext></mrow><mrow><mtext>5</mtext></mrow></msub></mrow></math><img file="EP0621998B1_D0003.tif" /></maths> where c<sub>5</sub> shall represent the last or most recent and c<sub>0</sub> the first or oldest binary valued ('0' and '1') code symbol of each group of six code symbols that form a modulation symbol. The period of time required to transmit a single modulation symbol is referred to as a "Walsh symbol" interval and is approximately equal to 208.333 µs. The period of time associated with one-sixty-fourth of the modulation symbol is referred to as a "Walsh chip" and is approximately equal to 3.2552083333... µs.
0052Each modulation or Walsh symbol is output from modulator 26 to one input of a modulo-2 adder, exclusive-OR gate 28. The Walsh symbols are output from modulator at a 4800 sps rate which corresponds to a Walsh chip rate of 307.2 kcps. The other input to gate 28 is provided from long code generator 30 which generates a masked pseudonoise (PN) code, referred to as the long code sequence, in cooperation with mask circuit 32. The long code sequence provided from generator 30 is at a chip rate rate four times the Walsh chip rate of modulator 26, i.e. a PN chip rate 1.2288 Mcps. Gate 28 combines the two input signals to provide an output of data at the chip rate of 1.2288 Mcps.
0053The long code sequence is a time shift of a sequence of length 2<sup>42</sup>-1 chips and is generated by a linear generator well known in the art using the following polynomial:<maths id="math0004" num="(4)"><math display="block"><mrow><msup><mrow><mtext>p(x) = x</mtext></mrow><mrow><mtext>42</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>35</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>33</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>31</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>27</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>26</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>25</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>22</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>21</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>19</mtext></mrow></msup><msup><mrow><mtext> +x</mtext></mrow><mrow><mtext>18</mtext></mrow></msup><mtext> +</mtext><mspace linebreak="newline" /><msup><mrow><mtext> x</mtext></mrow><mrow><mtext>17</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>16</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>10</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>7</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>6</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>5</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>3</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>1</mtext></mrow></msup><mtext> + 1</mtext></mrow></math><img file="EP0621998B1_D0004.tif" /></maths>
0054Figure 7 illustrates generator 30 in further detail. Generator 30 is comprised of a sequence generator section 70 and a masking section 72. Section 70 is comprised of a sequence of shift registers and modulo-2 adders (typically exclusive-OR gates) coupled together to generate a 42-bit code according to equation 4. The long code is then generated by masking the 42-bit state variables output from section 70 with a 42-bit wide mask provided from mask circuit 32.
0055Section 72 is comprised of a series of input AND gates 74<sub>1</sub>- 74<sub>42</sub> having one input for receiving a respective mask bit of the 42-bit wide mask. The other input of each of AND gates 74<sub>1</sub> - 74<sub>42</sub> receives the output from a corresponding shift register in section 70. The output of AND gates 74<sub>1</sub> - 74<sub>42</sub> are modulo-2 added by adder 76 to form a single bit output for each 1.2288 MHz clocking of the shift registers of section 70. Adder 76 is typically constructed as a cascaded arrangement of exclusive-OR gates as is well known in the art. Therefore, the actual output PN sequence is generated by the modulo-2 addition of all 42 masked output bits of sequence generator 70 as shown in Figure 7.
0056The mask used for the PN spreading shall vary depending on the channel type on which the mobile station is communicating. Referring to Figure 1, an initialization information is provided from microprocessor 18 to generator 30 and circuit 32. Generator 30 is responsive to the initialization information for initialization of the circuitry. Mask 32 is also responsive to the initialization information, which indicates the mask type to be provided, to output a 42-bit mask. As such, mask circuit 32 may be configured as a memory which contains a mask for each communication channel type. Figures 8a - 8c provide an exemplary definition of the masking bits for each channel type.
0057Specifically, when communicating on the Access Channel, the mask is defined as illustrated in Figure 8a. In the Access Channel mask, mask bits M<sub>24</sub> through M<sub>41</sub> are set to '1'; mask bits M<sub>19</sub> through M<sub>23</sub> are set to the chosen Access Channel number; mask bits M<sub>16</sub> through M<sub>18</sub> are set to the code channel for the associated Paging Channel, i.e, the range typically being 1 through 7; mask bits M<sub>9</sub> through M<sub>15</sub> are set to the registration zone for the current base station; and mask bits M<sub>0</sub> through M<sub>8</sub> are set to the pilot PN value for the current CDMA Channel.
0058When communicating on the Reverse Traffic Channel, the mask is defined as illustrated in Figure 8b. The mobile station uses one of two long codes unique to that mobile station: a public long code unique to the mobile station's electronic serial number (ESN); and a private long code unique for each mobile identification number (MIN) which is typically the telephone number of the mobile station. In the public long code the mask bits M<sub>32</sub> through M<sub>41</sub> are set to '0,' and the mask bits M<sub>0</sub> through M<sub>31</sub> are set to the mobile station ESN value.
0059It is further envisioned that a private long code may be implemented as illustrated in Figure 8c. The private long code will provide additional security in that it will only be known to the base station and the mobile station. The private long code will not be transmitted in the clear over the transmission medium. In the private long code the mask bit M<sub>40</sub> through M<sub>41</sub> are set to '0' and '1' respectively; while mask bits M<sub>0</sub> through M<sub>39</sub> may be set according to a predetermined assignment scheme.
0060Referring back to Figure 1 the output of gate 28 is respectively provided as one input to each one of a pair of modulo-2 adders, exdusive-OR gates 34 and 36. The other input to each of gates 34 and 36 are second and third PN sequences I and Q channel "short codes"respectively generated by I and Q Channel PN generators 38 and 40. The Reverse Access Channel and Reverse Traffic Channel is therefore OQPSK spread prior to actual transmission. This offset quadrature spreading on the Reverse Channel uses the same I and Q PN codes as the Forward Channel I and Q pilot PN codes. The I and Q PN codes generated by generators 38 and 40 are of length 2<sup>15</sup> and are preferably the zero-time offset codes with respect to the Forward Channel. For purposes of further understanding, on the Forward Channel a pilot signal is generated for each base station. Each base station pilot channel signal is spread by the I and Q PN codes as just mentioned. Base station I and Q PN codes are offset from one another, by a shifting of the code sequence, so as to provide distinction between base station transmission. The generating functions for the I and Q short PN codes shall be as follows:<maths id="math0005" num="(5)"><math display="block"><mrow><msub><mrow><mtext>P</mtext></mrow><mrow><mtext>I</mtext></mrow></msub><msup><mrow><mtext>(x) = x</mtext></mrow><mrow><mtext>15</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>13</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>9</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>8</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>7</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>5</mtext></mrow></msup><mtext> + 1</mtext></mrow></math><img file="EP0621998B1_D0005.tif" /></maths> and<maths id="math0006" num="(6)"><math display="block"><mrow><msub><mrow><mtext>P</mtext></mrow><mrow><mtext>Q</mtext></mrow></msub><msup><mrow><mtext>(x) = x</mtext></mrow><mrow><mtext>15</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>12</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>11</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>10</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>6</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>5</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>4</mtext></mrow></msup><msup><mrow><mtext> + x</mtext></mrow><mrow><mtext>3</mtext></mrow></msup><mtext> + 1.</mtext></mrow></math><img file="EP0621998B1_D0006.tif" /></maths> Generators 38 and 40 may be constructed as is well known in the art so as to provide an output sequence in accordance with equations (5) and (6).
0061The I and Q waveforms are respectively output from gates 34 and 36 where respectively provided as inputs to finite impulse response (FIR) filters 42 and 44. FIR filters 42 and 44 are digital filters which bandlimit the resulting I and Q waveforms. These digital filters shape the I and Q waveforms such that the resulting spectrum is contained within a given spectral mask. The digital filters preferably have the impulse response shown in the following Table II: <tables id="tabl0002" num="0002"><img file="EP0621998B1_D0007.tif" /></tables> Filters 42 and 44 may be constructed according to well known digital filter techniques and preferably provide a frequency response as illustrated in Figure 9.
0062The binary '0' and '1' inputs to digital filters 42 and 44, generated by the PN spreading functions, are mapped into +1 and -1, respectively. The sampling frequency of the digital filter is 4.9152 MHz = 4 × 1.2288 MHz. An additional binary '0' and '1' input sequence synchronous with the I and Q digital waveforms shall be provided to each of digital filters 42 and 44. This particular sequence, referred to as a masking sequence, is the output generated by a data burst randomizer. The masking sequence multiplies the I and Q binary waveforms to produce a ternary (-1, 0, and +1) input to the digital filters 42 and 44.
0063As discussed previously the data rate for transmission on the Reverse Traffic Channel is at one of the rates of equal 9.6, 4.8, 2.4, or 1.2 kbps and varies on a frame-by-frame basis. Since the frames are of a fixed 20 ms length for both the Access Channel and the Reverse Traffic Channel, the number of information bits per frame shall be 192, 96, 48, or 24 for transmission at data rates of 9.6, 4.8, 2.4, or 1.2 kbps, respectively. As described previously, the information is encoded using a rate 1/3 convolutional encoder and then the code symbols shall be repeated by a factor of 1, 2, 4, or 8 for a data rate of 9.6, 4.8, 2.4, or 1.2 kbps, respectively. The resulting repetition code symbol rate is thus fixed at 28,800 symbols per second (sps). This 28,800 sps stream is block interleaved as previously described.
0064Prior to transmission, the Reverse Traffic Channel interleaver output stream is gated with a time filter that allows transmission of certain interleaver output symbols and deletion of others. The duty cycle of the transmission gate thus varies with the transmit data rate. When the transmit data rate is 9.6 kbps, the transmission gate allows all interleaver output symbols to be transmitted. When the transmit data rate is 4.8 kbps, the transmission gate allows one-half of the interleaver output symbols to be transmitted, and so forth. The gating process operates by dividing the 20 msec frame into 16 equal length (i.e., 1.25 ms) periods, called power control groups. Certain power control groups are gated on (i.e., transmitted), while other groups are gated off (i.e., not transmitted).
0065The assignment of gated-on and gated-off groups is referred to as a data burst randomizer function. The gated-on power control groups are pseudo-randomized in their positions within the frame so that the actual traffic load on the Reverse CDMA Channel is averaged, assuming a random distribution of the frames for each duty cycle. The gated-on power control groups are such that every code symbol input to the repetition process shall be transmitted once without repetition. During the gated-off periods, the mobile station does not transmit energy, thus reducing the interference to other mobile stations operating on the same Reverse CDMA Channel. This symbol gating occurs prior to transmission filtering.
0066The transmission gating process is not used when the mobile station transmits on the Access Channel. When transmitting on the Access Channel, the code symbols are repeated once (each symbol occurs twice) prior to transmission.
0067In the implementation of the data burst randomizer function, data burst randomizer logic 46 generates a masking stream of 0's and 1's that randomly mask out the redundant data generated by the code repetition. The masking stream pattern is determined by the frame data rate and by a block of 14 bits taken from the long code sequence generated by generator 30. These mask bits are synchronized with the data flow and the data is selectively masked by these bits through the operation of the digital filters 42 and 44. Within logic 46 the 1.2288 MHz long code sequence output from generator 30 is input to a 14-bit shift register, which is shifted at a 1.2288 MHz rate. The contents of this shift register are loaded into a 14-bit latch exactly one power control group (1.25 ms) before each Reverse Traffic Channel frame boundary. Logic 46 uses this data along with the rate input from microprocessor 18, to determine, according to a predetermined algorithm, the particular power control group(s) in which the data is to be allowed to pass through filters 42 and 44 for transmission. Logic 46 thus outputs for each power control group a '1' or '0' for the entire power control group depending on whether the data is to be filtered out ('0') or passed through ('1'). The corresponding receiver, which also uses the same long code sequence and a corresponding rate determined for the frame, determines the appropriate power control group(s) in which the data is present.
0068The I channel data output from filter 42 is provided directly to a digital to analog (D/A) converter and anti-aliasing filter circuit 50. The Q channel data however is output from filter 44 to a delay element 48 which a one-half PN chip time delay (406.9 nsec) in the Q channel data. The Q channel data is output from delay element 48 to digital to analog (D/A) converter and anti-aliasing filter circuit 52. Circuits 50 and 52 convert the digital data to analog form and filter the analog signal. The signals output from circuits 50 and 52 are provided to Offset Quadrature Phase Shift Key (OQPSK) modulator 54 where they are modulated and output to RF transmitter circuit 56. Circuit 56 amplifies, filters and frequency upconverts the signal for transmission. The signal is output from circuitry 56 to antenna 108 for communication to the base station.
0069It should be understood that the exemplary embodiment of the present invention discusses the formatting of data for modulation and transmission with respect to a mobile station. It should be understood that the data formatting is the same for a cell base station, however the modulation may be different.
Contents4
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| Document | Relation | Office | Cited during |
|---|---|---|---|
| EP0381515A2 | Cites | European Patent Office (EPO) | Examiner |
| US5068849A | Cites | United States of America | Examiner |
| EP0412583A | Cites | European Patent Office (EPO) | – |
| EP0418865A | Cites | European Patent Office (EPO) | – |
| EP0444592A | Cites | European Patent Office (EPO) | – |
| WO9107030A | Cites | World Intellectual Property Organization (WIPO) | – |
| GB2022365A | Cites | United Kingdom | – |
| GB2182528A | Cites | United Kingdom | – |
| US4291409A | Cites | United States of America | – |
| US4951278A | Cites | United States of America | – |
225 members in 36 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 822164 | United States of America | – | |
| 82216492 | United States of America | A | |
| 9300406 | United States of America | W |
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Numbers
- Publication
- 0621998
- Application
- 939035416
Titles3
- German
- VERFAHREN UND EINRICHTUNG ZUR FORMATIERUNG VON ZU ÜBERTRAGENDEN DATEN
- English
- METHOD AND APPARATUS FOR THE FORMATTING OF DATA FOR TRANSMISSION
- French
- PROCEDE ET APPAREIL POUR LE FORMATAGE DE DONNEES EN VUE DE LEUR TRANSMISSION
Classification
- CPC, 19
- H04L1/0057
- C11D3/3788
- H04L27/30
- H04J3/1688
- H04J3/22
- H04J3/24
- H04J13/0048
- H04J13/18
- H04L1/0059
- H04L1/0065
- H04L1/0071
- H04L1/08
- C02F5/10
- C08L33/02
- C08L35/00
- C08L51/02
- C08L77/04
- C11D3/3757
- C11D3/3769
- IPC, 21
- H04L27 20
- C02F5 10
- C08L33 02
- C08L35 00
- C08L51 02
- C08L77 04
- C11D3 37
- H04B7 00
- H04J3 16
- H04J3 22
- H04J3 24
- H04J11 00
- H04J13 00
- H04J13 18
- H04L
- H04L1 00
- H04L1 08
- H04L12 00
- H04L27 30
- H04L29 06
- H04W72 04
Designated states1
- Contracting states, 1
- Sweden