PL172909B1 - METHOD OF FORMATTING DIGITAL DATA IN A DATA FRAME

4 claims: 2 independent, 2 dependent

1
Zastrzeżenia patentowe 1. Sposób formatowania danych cyfrowych w ramce danych, zwłaszcza w układzie przesyłania danych cyfrowych, w którym dane cyfrowe przesyła się w ramkach danych o uprzednio wybranym czasie trwania, i w którym na wstępie odbiera się zespół bitów danych pierwszego rodzaju danych i generuje się zespół bitów stopki, do dołączania do zespołu bitów danych pierwszego rodzaju, oraz następnie wprowadza się do ramki danych w określonym porządku zespół bitów danych pierwszego rodzaju i bitów stopki, znamienny tym, że stosuje się zespół bitów danych pierwszego rodzaju o liczbie bitów odpowiadającej jednej z wielu ustalonych uprzednio liczb bitów, przy czym gdy liczba bitów jest największą liczbą bitów albo drugą pod względem wielkości liczbą bitów z wielu ustalonych uprzednio liczb bitów, generuje się zespół bitów kontroli parzystości dla zespołu bitów danych pierwszego rodzaju, oraz gdy liczba bitów jest największą liczbą bitów albo drugą pod względem wielkości liczbąbitów, wprowadza się do ramki danych, w określonym porządku, zespół bitów pierwszego rodzaju, bity kontroli parzystości i bity stopki (T).
2
Sposób według zastrz. 1, znamienny tym, że gdy liczba bitów zespołu bitów danych pierwszego rodzaju jest największą liczbąbitów, generuje się bit trybu (MM) o pierwszej wartości bitu (MM=0), oraz wprowadza się bit trybu (MM) o pierwszej wartości bitu (MM=0) do ramki danych poprzedzającej zespół bitów danych pierwszego rodzaju.
3
Sposób według zastrz. 2, znamienny tym, że gdy zespół bitów danych pierwszego rodzaju ma największą liczbę bitów, wprowadza się zespół bitów danych drugiego rodzaju, generuje się zespół bitów kontroli parzystości dla zespołu bitów danych pierwszego rodzaju i dla zespołu bitów drugiego rodzaju, generuje się zespół bitów stopki, do dołączania do zespołu bitów danych pierwszego rodzaju i zespołu bitów danych drugiego rodzaju, oraz następnie wprowadza się do ramki danych, w określonym porządku, zespół bitów danych pierwszego rodzaju, zespół bitów danych drugiego rodzaju, bity kontroli parzystości i bity stopki (T).
4
Sposób według zastrz. 1, znamienny tym, że gdy zespół bitów danych pierwszego rodzaju ma największą liczbę bitów, wprowadza się zespół bitów danych drugiego rodzaju, generuje się bit trybu (MM) o drugiej wartości bitowej (MM=1), generuje się bity kontroli parzystości dla zespołu bitów danych pierwszego rodzaju i zespołu bitów danych drugiego rodzaju, generuje się zespół bitów stopki (T), do dołączenia do zespołu bitów pierwszego rodzaju i zespołu bitów drugiego rodzaju, oraz wprowadza się do ramki danych, w określonym porządku, bit trybu (MM) o drugiej wartości bitowej (MM= 1), zespół bitów pierwszego rodzaju, zespół bitów drugiego rodzaju, bity kontroli parzystości i bity stopki (T).

Independent claims4

430 paragraphs in 67 sections, as filed

The subject of the invention is a method of formatting digital data in a data frame, applicable in particular in digital data transmission systems in which digital data is transmitted in data frames of a predetermined duration.

The prior art solutions for formatting digital data sent in data frames of a previously selected duration, in which a set of first type data bits are received, a set of foot bits is generated in order to attach it to a set of first type data bits and are introduced into data frames, in a specific order, a set of first type data bits and footer bits.

In particular, in EP 0 418 865 regarding a wireless signal transmission system with direct access, the format of the signal transmitted over the system link in both directions is described. Signal sent in one direction,

172 909 that is, from the central station to the end stations, contains data blocks, each data block containing a first field, a second field and a third field. Each field contains a frame synchronization word, indicator signal and the correct data transmitted. The control bits are included at the end of the signal format to check for transmission errors. Each indicator signal then contains a bit indicating the permission or prohibition of new broadcasting of the next synchronization signals of the transmission from the end station and part of the signals transmitted from the end station, the bit indicating the correct signal reception or incorrect or no signal reception and the partial data received from the data received by the central station in accordance with with a predetermined rule. In turn, the signal sent in the other direction, i.e. one or several end stations to the central station, contains data blocks, each data block containing three fields. Each field contains a data stream signal from the link of a particular end station, the signal including a frame synchronization signal and data of that particular link. The data stream signal also includes transmitted signal length data belonging to the message structure. In addition, the data to be transmitted contains many fields, with the field numbers in the first field. Control bits for error detection are usually placed at the end of the signal format.

The signals formatted in this way are transmitted between the central station and the end stations as follows. At the beginning, the central station prepares and transmits data on the transmission format containing the bit indicating the permission or prohibition of new broadcasting of the next synchronization signal of the end stations, the bit indicating the reception or lack of reception by the central station of signals from the end stations and partial data created from data received by the central station according to a predetermined rule based on the signals that the central station received from the end stations. Signal length data is then generated for the transmission format at the end stations, the signal length data representing the signal length to be transmitted from the end station and transmission of signals or signals containing signal length data from one or more end stations to the central station begins. when a specific bit indicates a new broadcast permission, then it is determined and transmitted, at the central station a bit indicating the permission or prohibition of new broadcasting, a bit indicating the reception or lack of signal reception and partial data in accordance with the reception of the signal length data and the signal transmitted from one of the end stations. It is sequentially determined at one or more end stations that transmitted whether the signal was or was not received correctly by the central station, according to the bit indicating the reception or lack of reception of the signal and partial data from the central station, and the transmission of signals from one or more end stations for a specified period of time when it is determined that the signal was not received correctly by the central station.

From the publication of international application No. WO 91/07030 a method of distributed synchronization is known for a wireless communication system in which, in a transmitter, a frame indicator of the time of the frame that is transmitted is included in the frame synchronization packet, calculated in bytes from the beginning of the data field, the network interface to the first byte of the end of sequence of the synchronization packet. Then, in the receiver, a time indicator is separated, this indicator is compared with the reception time stamp, which is related to the reception time of this packet, propagation delays are set and when a significant error occurs, then the data fields of the network interface to get synchronization in the shortest possible time.

In turn, European Patent No. 0 412 583 discloses a method of transmitting information between the first communication device and multiple remote communication devices through a repeater, all working with time division multiplication (TDM). According to a known method, in the first communication device the activation code is transmitted to the repeater if the repeater is inactive, and the information signal is sent to the repeater in the first time interval through a communication channel at a specified data rate according to the TDM protocol. In the repeater, in turn, the activation code is received, the synchronization signal is sent to many remote communication devices and the information signal from the communication channel is received during the first time interval, after which the information signal in the second

172 909 in the time interval preceded by the data signal, and when none of the many remote devices sent information within the specified time interval, the repeater automatically deactivates after this time interval. However, in other remote communication devices or in their parts synchronization with the synchronization signal is carried out and a repeated information signal is received in the allocated time interval.

The essence of the method of formatting digital data in a data frame according to the invention, especially in a digital data transmission system in which digital data is transmitted in data frames of a previously selected duration, and in which the first set of data bits of the first type of data is received and generated a set of footer bits, for attaching to the first type of data bit set, and then introducing into the data frame in a particular order a set of first type data bits and footer bits, that is, a set of first type data bits having a number of bits corresponding to one of a plurality of predetermined number of bits is used, wherein when the number of bits is the largest number of bits or the second largest number of bits out of many predetermined number of bits, a set of parity check bits is generated for a set of first-order data bits, and when the number of bits is the largest number of bits or the number of bits in terms of the number of bits, a set of first type bits, parity check bits and footer bits are introduced into the data frame in a specific order.

Preferably, according to the invention, the number of bits of the first type data bit set is the largest number of bits, a mode bit with the first bit value is generated, and the mode bit with the first bit value is introduced into the data frame preceding the first type of data bit set.

It is also advantageous if, according to the invention, the first type of data bits set has the largest number of bits, a second type of data bits set is introduced, a parity set of bits is generated for the first type of data bits set and for the second type of bits set, a foot set of bits is generated, for attaching the first type of data bits and the second type of data bits to a set of data bits, and then entering the data frame in a specific order first type data bits set, second type data bits set, parity check bits and footer bits.

It is furthermore advantageous if, according to the invention, the first type of data bit set has the largest number of bits, the second type of data bit set is introduced, the mode bit with the second bit value is generated, the parity check bits are generated for the first type of data bit set and the data bit set of the second type, a set of footer bits is generated to be attached to the first type of bit set and the second type of bit set, and entered into the data frame, in a certain order, a mode bit with a second bit value, a set of first type bits, a set of second type bits, parity bits and footer bits.

The advantage of the solution according to the invention is that it facilitates the transmission of various types of data and data at different rates, transmitted in the form of frames.

The method of formatting digital data according to the invention is explained based on the embodiment shown in the drawing, in which Fig. 1 is a block diagram of the transceiver of the transceiver, Figs. 2a-2h are graphs of the frame data formats for different rates, types and modes of data Fig. 3 is a schematic diagram of the bit generator of Figs. 1, Figs. 4a-4e are a flowchart of formatting data frames, Fig. 5a-5d ordering of code symbols in an interlaced system for data rates of 9.6, 4.8, 2.4 and 1.2 kilobits per second (kbps), respectively, Figures 6a-6c - Walsh symbols corresponding to each group of symbolic encoders, Fig. 7 is a block diagram of the long code generator of Fig. 1, Figs. 8a-8c are diagrams of long code masks for different types of channels, and Fig. 9 is a frequency response graph of the digital filters of Fig. 1.

Figure 1 is a block diagram of the transmitting part 10 of a mobile station transceiver with a CDMA modulation procedure or a handset for the oso172 909 bista communication system (PCN). In a cellular transmission system with CDMA modulation, the target channel CDMA is used to send information from the cell base station to the mobile station. Alternatively, the CDMA return channel is used to send information from a mobile station to a cell base station. The communication signals from the mobile station may be in the form corresponding to connectivity of the access channel or the traffic channel. The access channel is used for short signaling messages such as call origins, page responses and registrations. The traffic channel is used for transmission / 1 / primary traffic, usually containing user speech, or / 2 / secondary traffic, usually user data, or / 3 / signaling traffic, such as command and control signals, or / 4 / combination of primary traffic and secondary traffic or / 5 / a combination of primary traffic and signaling traffic.

The transmitting portion 10 allows data to be transmitted via a reverse CDMA channel at data rates of 9.6 kbps, 4.8 kbps, 2.4 kbps or 1.2 kbps. Transmission via the reverse traffic channel can take place at any of these data rates, while transmission via the access channel takes place at a data rate of 4.8 kbps. The traffic cycle of the reverse traffic channel will change along with the speed of data transfer. The transmission duty cycle for each speed is detailed in Table I. When the transmission duty cycle changes in proportion to the data rate, the actual packet transmission rate is set to 28 800 code symbols per second. If six code symbols are modulated as one of 64 Walsh symbols, the Walsh symbol transmission rate will be set to 4800 Walsh symbols per second, resulting in a constant Walsh module speed of 307.2 kcps.

All data that is transmitted via the CDMA return channel is convolutional, block interleaved, modulated by system 64 modulation and set into a direct PN sequence prior to transmission. Table I then determines the relationships and data rates and symbols for different data rates on the reverse traffic channel. The number values are identical for the access channel except that the baud rate is set to 4.8 kbps and the duty cycle is 100%.

As described hereinafter, each bit transmitted on the reverse CDMA channel is convolutional encoded using a 1/3 speed code. So the code symbol speed is always three times faster than the data rate. The speed of the direct sequence spread function will be set at 1.2288 MHz so that each Walsh module is determined by exactly four PN modules.

Table I

<td>Transmission rate / kbps /</td><td> 9,6</td><td> 4,8</td><td> 2,4</td><td> 1,2</td>

<td>PN / Mcps / module speed</td><td> 1,2288</td><td> 1,2288</td><td> 1,2288</td><td> 1,2288</td>

<td>Code speed / bits / code symbol /</td><td> 1/3</td><td> 1/3</td><td> 1/3</td><td> 1/3</td>

<td>TX /% / duty cycle</td><td> 100,0</td><td> 50,0</td><td> 25,0</td><td> 12,5</td>

<td>Code symbol speed / sps /</td><td> 28800</td><td> 28800</td><td> 28800</td><td> 28800</td>

<td>Modulation / code symbol / Walsha symbol /</td><td> 6</td><td> 6</td><td> 6</td><td> 6</td>

<td>Symbol rate Walsha / sps /</td><td> 4800</td><td> 4800</td><td> 4800</td><td> 4800</td>

<td>Walsh module; speed / kcps /</td><td> 307,20</td><td> 307,20</td><td> 307,20</td><td> 307,20</td>

<td>Symbol Walsha / ps /</td><td> 208,33</td><td> 208,33</td><td> 208,33</td><td> 208,33</td>

<td>PN modules / code symbol</td><td> 42,67</td><td> 42,67</td><td> 42,67</td><td> 42,67</td>

<td>PN modules / Walsh symbol</td><td> 256</td><td> 256</td><td> 256</td><td> 256</td>

<td>PN modules / Walsh module</td><td> 4</td><td> 4</td><td> 4</td><td> 4</td>

The transmission part 10, when operating in a state in which primary traffic occurs, transmits acoustic signals, such as speech and / or background noise, as digital signals in the transmission medium. In order to facilitate the digital transmission of acoustic signals, these signals are sampled and

172 909 digitally processed by well-known techniques. For example, in Figure 1, the sound is converted by the microphone 12 into an analog signal, which is then converted into a digital signal by the codec 14. The codec 14 typically performs the analog-to-digital processing using the standard 8 bit / plaw format. Otherwise, the analog signal can be processed directly to digital form in a uniform code-pulse modulation / PCM / format. In the exemplary embodiment, the codec 14 uses 8 kHz sampling and outputs 8 bit samples at a sampling rate to provide a 64 kbps data rate.

8-bit samples are output from codec 14 to vocoder 16, where the ulaw / uniform code conversion process is performed. In vocoder 16, the samples are organized into input frames, where each frame is composed of a predetermined number of samples. In a preferred embodiment of vocoder 16, each frame is composed of 160 samples or 20 ms. speech at a sampling rate of 8 kHz. It should be understood that other sample rates and frame sizes can be used. Each frame of speech samples is encoded at a variable speed by vocoder 16 with the resulting parameter data formatted into a corresponding data packet. The vocoder data packets are then output to the microprocessor 18 and the corresponding formatting circuit for transmission. The microprocessor 18 usually includes program instructions contained in the program instruction memory, data memory and appropriate interface, and a corresponding arrangement as is known in the art.

The preferred embodiment of vocoder 16 employs some form of linear coding technique of the excited code so as to provide a variable rate of coded speech data. The analysis of the linear predictive coder / LPC / is carried out with a fixed number of samples and jumps are performed in the search for a character jump and a code book with variable numbers of samples depending on the transmission speed. Vocoder 16 can be made in an integrated circuit with a particular application / ASIC / or in a digital signal processor.

In a variable speed vocoder just mentioned, the speech analysis frames are 20 msec long, causing the secreted parameters to be output to microprocessor 18 in the packet 50 times per second. In addition, the output data rate is changed from roughly 8 kbps to 4 kbps to 2 kbps and up to 1 kbps.

At full speed, also referred to as speed 1, data transmission between the vocoder and the microprocessor occurs at a speed of 8.55 kbps. For full speed data, the parameters are coded for each frame and represented by 160 bits. The full speed data frame also includes an 11 bit parity check, resulting in a full speed frame of 171 bits. In the full speed data frame, the transmission rate between the vocoder and the microprocessor, in the absence of parity check bits, would be 8 kbps.

At half speed, also referred to as 1/2 speed, data transmission between the vocoder and the microprocessor is at 4 kbps, with parameters encoded for each frame using 80 bits. At the quarter rate, also referred to as 1/4 speed, data transmission between the vocoder and microprocessor occurs at 2 kbps, with the parameters encoded for each frame using 40 bits. At a rate of one-eighth, also referred to as 1/8, the data transmission between the vocoder and the microprocessor is slightly less than 1 kbps, with parameters encoded for each frame using 16 bits'.

In addition, no information can be transmitted in the frame between the vocoder and the microprocessor. This type of frame, referred to as blanking frame, can be used for signaling or non-vocoder data.

The vocoder data packets are then output to the microprocessor 18 and the CRC generator 20 and the foot bit to complete the transmission formatting. The microprocessor 18 receives parameter data packets every 20 msec. along with an indication that the frame rate of the speech samples was coded. The microprocessor 18 also receives, if present, secondary motion input data for the output of the generator 20. The microprocessor 18 also generates data internally.

172 909 signaling for generator output 20. Data, regardless of whether they relate to primary traffic, secondary traffic or signaling traffic, if present, are at the output of microprocessor 18 for each 20 msec frame.

Generator 20 generates and adds, at the end of all full and half speed frames, a set of parity check bits or cyclic redundancy check bits (CRC bits) that are used in the receiver as an indicator of the quality of the frame. For a full-speed frame, regardless of whether the data is primary, secondary or full-speed signaling, or a combination of primary and secondary motion at half-speed, or a combination of primary motion and half-speed signaling, the generator 20 preferably produces an assembly CRC bits according to the first polynomial. In the case of a half-speed data frame, the generator 20 also generates a set of CRC bits preferably according to the second polynomial. Generator 20 then generates for all frames a set of encoder foot bits that follow the CRC bits, if any, or data, if there are none, at the end of the frame. Further details of the operation of microprocessor 18 and generator 20 are hereinafter referred to in figures 3 and 4.

The reverse traffic channel frames supplied from the generator 20 at 9.6 kbps have a length of 192 bits and a frame spacing of 20 msec. These frames consist of a single mixed mode bit, auxiliary format bits, if any, message bits, 12-bit indicator / CRC / frame quality, and 8 encoder foot bits, as shown in Figures 2a-2e. The mixed mode bit will be set to "0" during any frame in which the message bits are mainly just traffic information. When the mixed mode bit is "0", the frame will consist of the mixed mode bit, 171 primary traffic bits, 12 CRC bits and 8 encoder foot bits.

The mixed mode bit is set to "1" for frames containing secondary traffic or signaling. In these cases, the first bit following the mixed mode bit is the packet format bit, which determines whether the frame is in "blank and packet" or "dimension and packet" format. The "blanking and packet" operation is one in which the entire frame is used for secondary traffic or signaling, while the "dimensioning and packet" operation is one in which primary traffic shares the frame with either secondary traffic or signaling. If the format bit is packet "0", the frame is "dimension and packet format", and if frame "1" is "blank and packet format".

The second bit following the mixed mode bit is the traffic type bit. The traffic type bit is used to determine if the frame includes secondary traffic or signaling. If the traffic type bit is "0", the frame includes signaling traffic, and if "1", the frame includes secondary traffic. Figures 2b-2e show the packet format bit and the traffic type bit.

When the format bit packet is "0", denoting dimension and packet, the two bits following the traffic type bit are traffic mode bits. These bits denote the number of bits that are used for primary traffic information and the number of bits that will be used for either signaling or secondary traffic information in this frame. For the default operating mode, only the "00" motion mode is specified, and all other motion modes are reserved for other types of bits and numbers. Referring to figures 2b and 2c, in the exemplary and preferred embodiment, 80 bits for primary traffic (half-rate vocoder data packet) are used, while bits 86 and 87 are used for secondary traffic and signaling, respectively.

In frames where signaling traffic occurs, the first bit of the signaling part of the frame is the start bit of the message / SOM /. The SOM bit is "1" if the reverse traffic channel message / signaling message / starts at the next bit. Usually the first bit of the reverse traffic channel message does not start anywhere else in the frame than after the SOM bit. However, if the frame contains part of the message that started in the previous frame, the SOM bit is "0". If the SOM bit is "0", the next bit is part of the message, but it is not the first bit of the complete message.

In a preferred embodiment, only primary traffic is transmitted in frames at 4.8 kbps, 2.4 kbps and 1.2 kbps. Mixed mode operation is usually not supportive 8

172 909 at speeds other than 9.6 kbps, although this can easily be done. Frame formats for these particular speeds are shown in figures 2f-2h. At a 4.8 kbps rate, the frame is 96 bits long, with bits 20 msec apart. for the frame as described hereinafter. The 4.8 kbps frame contains 80 bits of primary traffic, an 8-bit frame quality indicator / CRC / and 8 bits of encoder footer. At 2.4 kbps, the frame is 48 bits long, with bits 20 msec apart. frames, as also described hereinafter. The 2.4 kbps frame contains 40 bits of main traffic and 8 bits of encoder footer. At 1.2 kbps, the frame is 24 bits long, with bits 20 msec apart. frames, as also described hereinafter. The 1.2 kbps frame contains 16 bits of main traffic and 8 bits of encoder footer.

In a preferred embodiment, the access channel data is generated by the microprocessor 18 for transmission at a rate of 4.8 kbps. As such, the data is prepared in an identical manner to the 4.8 kbps frame format data, such as encoding, interleaving as Walsh encoding. In the coding scheme implemented for 4.8 kbps data, or with reverse traffic channel data or access channel data, redundant data is produced. Unlike the reverse traffic channel, where redundant data is eliminated during transmission, all data containing redundant data is transmitted on the access channel. Here are the details about the aspects of sending access channel data frames.

Figure 3 shows an exemplary embodiment of data formatting elements according to figures 2a-2h. In Figure 3, data is sent from the microprocessor 18 / Figure 1 / to the generator 20. The generator 20 is composed of the data control and buffering logic 60, the CRC systems 62 and 64 and the foot bit system 66. Along with the data provided from the microprocessor, an optional speed command may be provided. Data is sent for each 20 msec frame. from the microprocessor to the logic 60, where they are temporarily stored. For each frame, logic 60 may count for each frame the number of bits transmitted from the microprocessor or, in a different application, the speed command and the number of clock cycles when formatting the data frame.

Each traffic channel frame has a frame height indicator. For a 9.6 kbps 14.8 kbps transmission rate, the frame quality indicator is CRC. For 2.4 kbps and 1.2 kbps bit rates, the frame quality indicator is implied that no additional frame quality bits are transmitted. The frame quality indicator supports two functions in the receiver. The first function is to determine the frame rate, while the second function is to determine if the frame is incorrect. At the receiver, these determinations are made by combining decoder information and CRC checks.

At 9.6 kbps and 4.8 kbps, the / CRC / frame quality indicator is calculated for all bits in the frame except the / CRC / frame quality indicator itself and the encoder footer bits. Logic 60 provides data at 9.6 kbps and 4.8 kbps for CRC 62 and 64, respectively. Systems 62 and 64 are typically constructed as a sequence of shift registers, modulo 2 adders (usually ALBO components), and switches as shown.

The 9.6 kbps data rate uses the / CRC / 12-bit frame quality indicator, which is transmitted in a 192-bit frame, as discussed with reference to Figures 2u-2e. As shown in Figure 3 for CRC 62, generator polynomial for speed

9.6 kbps is as follows:

g (x) = Χ12Χ +Π+ χ1θΧ +9Χ +8Χ +4+ Χ + 1/1 /

The 4.8 kbps data rate data uses 8-bit CRC, which is transmitted in a 96-bit frame, as discussed with reference to figure 2f. As shown in Figure 3 for the CRC 64 system, the generator polynomial at 4.8 kbps is as follows: g (x) = Χ8Χ +7+ + Χ4 Χ3+ Χ + 1/2 /

172 909

Initially, all elements of the shift register of circuits 62 and 64 are set to logic one / "1" / by the initialization signal from logic circuit 60. In addition, logic circuit 60 sets the switches 62 and 64 in the upper position.

For 9.6 kbps data, system 62 registers are then synchronized 172 times for 172 bits in primary traffic, secondary traffic or signaling bits or a mixture thereof with the corresponding mode / format indicator bits as input to system 62. After synchronization 172 bits through system 62, logic 60 then sets system switches 62 to the lower position, wherein system 62 registers are then synchronized an additional 12 times. As a result of 12 additional synchronizations of system 62, 12 additional output bits are produced, which are CRC bits. CRC bits, in the calculated order, are appended to the end of 172 bits as output of system 62. It should be noted that 172 bits coming out of logic 60 that pass through system 62 are not disturbed by the calculation of CRC bits and are therefore output from system 62 in the same order and with the same value with which they entered.

For 9.6 kbps data, bits are input into system 64 from logic 60 in the following order. In the case of only primary traffic, the bits are input to system 64 from logic 60 in order first single bit / mm / mixed mode, then 171 bits primary traffic. In the case of "dimensioning and packet" with primary traffic and signaling, the bits are entered into system 64 from logic 60 in order: single MM bit, single bit / BF / packet format, bit / TT / traffic type, bit pair / TM / traffic mode, 80 bits of primary traffic, bit / SOM of the beginning of the message and 86 traffic bits of signaling. For the case of "dimensioning and packet" with primary and secondary traffic, the bits are input to system 64 from logic 60 in order: single MM bit, single BF bit, TT bit, TM bit pair, 80 primary traffic bits and 87 signaling traffic bits . For the "blanking and packet" data format only with signaling traffic, the bits are input to system 64 from logic 60 in the order: single MM bit, single BF bit, TT bit, SOM bit and 168 signaling traffic bits. For the "blanking and packet" data format only with secondary traffic, the bits are input to system 64 from logic 60 in the order: single MM bit, single BF bit, TT bit and 169 traffic signaling bits.

Similarly, for data with a speed of 4.8 kbps, registers of system 64 are synchronized 80 times for 80 bits of primary traffic data or for 80 bits of access channel data, as input to system 64 from logic system 60. After synchronization of 80 bits by system 64, system logic 60 then sets system switches 64 to the lower position, with system registers 64 then synchronized an additional 8 times. As a result of 12 additional synchronizations of system 62, 12 additional output bits are produced, which are CRC bits. The CRC bits, in the calculated order, are reconnected to the end of 80 bits as output 64. It should be noted again that 80 bits output from logic 60 passes through system 64, it is not disturbed by calculating CRC bits and is therefore output from system 64 in such same order and with the same value with which they fall.

The output bits of any of 62 and 64 are supplied to switch 66, which is controlled by logic 60. Also at the input of switch 66 is 40 and 16 bits of primary traffic data output from logic 60 for data frames of 2.4 kbps and 1 , 2 kbps. Switch 66 chooses between the supply of input data / upper position / and the foot bits with the logical value zero / "0" / / lower position /. Switch 66 is usually set in the upper position to allow data from logic 60 and from systems 62 and 64, if present, to derive from generator 20 to encoder 22 / figure 1 /. For 9.6 kbps and 4.8 kbps frame data, after the CRC bits are synchronized by the switch 66, logic 60 sets the switch in the down position to 8 clock cycles to produce 8 footer bits, all zeros. Thus, in the case of 9.6 kbps and 4.8 kbps data frames, the encoder output data for the frame includes 8 footer bits attached after the CRC bits. Similarly, for 2.4 kbps and 1.2 kbps frame data, after synchronizing the primary traffic bits from logic 60 by switch 66, logic 60 sets the switch to

172 909 down position for 8 cycles so as to generate 8 foot bits again, all zeros. Thus, in the case of 2.4 kbps and 1.2 kbps data frames, the data output to the frame encoder includes 8 footer bits attached after the primary traffic bits.

Figures 4a-4e illustrate sequential flowcharts for microprocessor 18 and generator 20 when assembling data into the disclosed frame format. It should be noted that different schemes can be used to achieve different types of traffic and bit rate priority. In the exemplary embodiment, when the signaling motion message is to be sent when vocoder data is present, the "dimension and packet" format may be selected. The microprocessor 18 can generate an order for vocoder 18 to encode the vocoder to encode half-rate speech sample frames, regardless of the speed at which the vocoder would normally encode the sample frame. The microprocessor 18 then assembles the half-speed vocoder data with 9.6 kbps frame traffic signaling as shown in Figure 2b. In this case, you can limit the number of speech frames encoded at half speed to prevent speech quality degradation. Alternatively, the microprocessor 18 may expect to receive the half-frame vocoder data frame before assembling the data into "dimension and package" format. In this case, to ensure timely signaling data transmission, a maximum limitation of the number of consecutive frames at a non-half speed can be introduced before sending the command to the vocoder for half speed coding. In a similar way, the secondary traffic can be transferred in the format and dimension / figure 2c /.

A similar case is for the "blanking and packet" data formats as shown in Figures 2d-2e. You can send an order to not encode the speech sample frame to the vocoder, or the vocoder data is ignored by the microprocessor when constructing the data frame. By choosing priority in producing primary motion frame formats at different speeds, the "dimension and packet" motion and the "blanking and packet" motion creates many possibilities.

Returning to figure 1, frames 20 ms. 9.6 kbps, 4.8 kbps, 2.4 kbps and 1.2 kbps data are then output from generator 20 to encoder 22. In the exemplary embodiment, encoder 22 is preferably a convolutional encoder, a type of encoder well known in the art. Encoder 22 preferably encodes data using a 1/3 rate convolutional code limited by length k = 9. As an example, encoder 22 is constructed with the functions of a g generator0= 557 / octal /, gj = 663 / octal / ig2 = 711 / octal /. As is well known in the art, convolutional coding adds a modulo of 2 selected leads in a time-shifted, delayed data sequence. The amount of data sequence delay is k-1, where k is the limited code length. If in a preferred embodiment a 1/3 code is used, three code symbols, symbols / Cq /, / Cj / and / c are generated for each data bit entering the encoder.2/ code. Funnel, tcf and / c symbols2/ are produced accordingly by the function g0, gj and g2 generator. Code symbols are output from encoder 22 to interleaving block 24. Output code symbols are supplied to interleaving block 24 in the order in which the Icf code symbol is first, the symbol / Cj / code is second and the symbol / c2/ code is last. The state of encoder 22, after initialization, is the state of all zeros. In addition, using footer bits at the end of each frame puts encoder 22 into all zeros.

Symbols output from encoder 22 are provided to interleaving block 24, which, when controlled by microprocessor 18, ensures the repetition of code symbols. Using ordinary random access memory / RAM /, with the symbols stored in it, addressed by the microprocessor 18, the code symbols can be remembered in a way that ensures the repetition rate of the code symbols, which changes with the data channel.

Code symbols are not repeated for a data rate of 9.6 kbps. Each code symbol at a data rate of 4.8 kbps is repeated once, i.e. each symbol appears twice. Each code symbol at a data rate of 2.4 kbps is repeated 3 times, i.e. each symbol appears 4 times. Each code symbol at a data rate of 1.2 kbps is repeated 7 times, i.e. each symbol appears 8 times. For all data rates / 9.6, 4.8, 2.4 and 1.2 kbps / code repetition results in a constant code symbol rate of 28 800 code symbols per second for data on output of interleaving block 249 909 In the reverse traffic channel repeated the code symbols are not transmitted many times all, but one of the repetitions of the code symbols is delayed before the actual transmission according to the variable transmission duty cycle, as discussed in more detail below. It should be understood that the use of code symbol repetition as a convenient way to describe interleaving operations and data packet optimization is discussed in more detail below. It should then be understood that embodiments other than those that use repetition of code symbols that achieve the same results and fall within the scope of the present invention can easily be invented.

All code symbols transmitted on the reverse traffic channel and the access channel are interleaved before modulation and transmission ^. Interleaving block 24 provides output code symbols at a time interval of 20 msec. The interleaving structure is usually a rectangular system with 32 rows and 18 columns, i.e. 576 cells. The code symbols are written into the interleaving block of the columns, with data repetition at 9.6, 4.8, 2.4 and 1.2 kpbs so as to completely fill the 32x18 matrix. Figures 5a-5d show the order of operations for writing repeated code symbols in an interleaving system for data rates of 9.6, 4.8, 2.4 and 1.2 kbps, respectively.

Reverse traffic channel code symbols are derived from the row interleaving block. The microprocessor 18 also controls the addressing of interleaving memory for outputting the symbols in the correct order. The interleaving block rows are preferably output in the following order:

At 9.6 kbps:

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

At 4.8 kbps:

3 2 4 5 7 6 8 9 11 10 12 13 15 14 16 17 19 18 20 21 23 22 24 25 27 26 28 29 31 30 32

At 2.4 kbps:

5 2 6 3 7 4 8 9 13 10 14 11 15 12 16 17 21 18 22 19 23 20 24 25 29 26 30 27 31 28 32

At 1.2 kbps:

192103 11-4125 13 614715 81617251826192720282129223023 312432.

Access channel code symbols are also output from interleaving block 24 through the rows. The microprocessor 18 again controls the addressing of the interleaving memory to output the symbols in the correct order. Interleaving block rows are output in the following order at 4.8 kbps for access channel code symbols:

17925 5 21 1329319112772315 31218102662214304201228 8241632.

It should be noted that other coding rates, such as the 1/2 rate of convolutional code used on the forward channel tr ^: n ^^ along with various other symbol interleaving formats, can easily be invented using the basic teachings of the present invention.

Referring again to Figure 1, interleaved code symbols are output from interleaving block 24 to modulator 26. In a preferred embodiment, modulation for the reverse CDMA channel uses orthogonal signaling 64. This means that one of the 64 possible modulation symbols is transmitted for every six code symbols. The 64 modulation symbol is one of 64 orthogonal waveforms produced preferably using the Walsh function. These modulation symbols are given in figure 6 and are numbered from 0 to 63. Modulation symbols are selected according to the following formula:

Modulation symbol number = c0+ 2c1 + 4c28c +3+ 16c4+ 32c5 / 3 / where c5 will represent the last or the latest and c0 the first or oldest code symbol with a given binary value / "0" and "1" / for each group of six code symbols that make up the modulation symbol. The period of time required to send a single modulation symbol is called the "Walsh symbol" period and is approximately 208 333 ps. Period

172 909 time associated with one sixty-fourth of the modulation symbol is called the "Walsh module" and is approximately equal to 3.25552083333 ... js.

Each modulation or Walsh symbol is output from modulator 26 to one input of modulo 2 adder, element OR 28. Walsh symbols are output from the modulator at a speed of 4800 sps, which corresponds to a Walsh module speed of 307.2 kcps. A second input on element 28 is provided from the long code generator 30, which produces the masked pseudo-noise / PN / code, called the long code sequence, in cooperation with the masking circuit 32. The long code sequence provided from generator 30 has a module speed, four times the speed of the Walsh module modulator 26, i.e. a module speed of PN 1.2288 Mcps. Element 28 combines two input signals to provide output at a module speed of 1.2288 Mcps.

The long code sequence is the time shift of the sequence module sequence length 242-1 and is produced by a linear generator well known in the art using the following poly titre:

p (x) = X42X +3SX +33X +31X +27X +26X +25X +22X +21X +19+

X18X +r7X +16X +10X +7X +6X +5X +3X +2X +1+1 /4/

Figure 7 shows generator 30 in further details. Generator 30 is composed of section 70 sequence generator and masking section 72. Section 70 is composed of a sequence of shift registers and modulo 2 / usually combiners / usually elements OR combined together to produce a 42-bit code according to equation 4. The long code is then generated by masking the 42-bit variable output from section 70, with a 42-bit mask provided by masking system 32.

Section 72 is composed of a series of input elements 1741 - 7442 having one input to receive a particular bit of the mask with a width of 42 bits. The second input of each item 1741-7442 receives the output of the corresponding shift register in section 70. The output of items 1741-7442 is added modulo 2 through the adder 76 to generate a single output bit for each synchronization of 1,2288 shift registers of section 70. Adder 76 is usually constructed as a cascade system of OR elements, which is well known in the art. Therefore, the actual PN output sequence is generated by adding modulo 2 of all 42 masked output bits of the sequence generator 70, as shown in Figure 7.

The mask used for PN scattering will change depending on the type of channel that the mobile station is communicating with. Returning to figure 1, the initialization information is provided from the microprocessor 18 to the generator 30 and the system 32. The generator 30 responds to the initialization information for starting the system. Mask 32 also responds to initialization information, which indicates the type of mask being provided, to obtain a 42-bit mask. Therefore, masking circuit 32 may have a memory configuration that includes a mask for each type of communication channel. Figures 8a-8c provide an exemplary determination of masking bits for each type of channel.

Especially for communication with the access channel, the mask is determined as shown in figure 8. In the access channel mask, the mask bits M24 to M41 are set to "1", bits M19 to M23 of the mask are set to the selected access channel number; bits MLC Houselg masks are set to the code channel for the appropriate paging channel, i.e. the range is usually 1 to 7; bits M9 to Min masks are set to the registration range for the current base station, and bits M0 to M8 the masks are set to the PN control value for the current CDMA channel.

For communication with the reverse channel, the mask is determined as shown in figure 8b. The mobile station uses one of two long codes unique for this mobile station: a long public code unique for the electronic serial number / ESN / mobile station and a long private code unique for each mobile identification number / MIN / which

172 909 is usually the number of a mobile station. In the long public code, the mask bits M32 to M41 are set to "0" and the bits Mabout to M31 the masks are set to the ESN value of the mobile station.

In addition, it has been found that the long private code can be executed as shown in figure 8c. The long private code will provide additional security in that it will only be known to the base station and the mobile station. A long private code will not be transmitted when being deleted in the transmission medium. In the long private code, the bits M4q to M41 masks are set to "0" and "1", respectively, while bits M() to M39 masks can be set according to a predetermined transfer pattern.

Returning to figure 1, the output of logic element 28 is made as the input of each of the pair of modulo 2 adders, element ALBO 34 and 36, respectively. At the second input of each of the elements 34 and 36 there are second and third PN sequences, there are respectively "short codes" of the channel I and Q, generated by PN 3 8 and 40 generators of the I and Q channels. The reverse access channel and the reverse traffic channel are therefore scattered OQPSK prior to actual transmission. This reverse quadrature scattering uses the same PN I and Q codes as the PN I and Q control codes of the target channel. PN I and Q codes generated by generators 38 and 40 have a length of 215and are preferably zero-shifted codes relative to the target channel. For further clarification, a control signal is generated on the destination channel for each base station. Each base station control channel signal is scattered by PN I and Q codes, as just mentioned. The base station PN I and Q codes are shifted relative to each other by shifting the code sequence so as to provide a distinction between base station transmission. The generation functions for short PN I and Q codes will be as follows:

Pj (x) = χ15Χ13 χ9 + + + χ8+ χ7+ χ5+1 / ^ / i

Pq (x) = χ15Χ12 χ11 + + + χ1θΧ +6Χ +5+ χ4 + χ3 + 1 / (^ /

Generators 38 and 40 can be constructed as is well known in the art to provide an output sequence according to equations /// and / 6 /.

I and Q waveforms are respectively at the outputs of logic elements 34 and 36, from where they are supplied to the filter / FIR / 42 and 44 inputs with finite impulse response, respectively. FIR filters 42 and 44 are digital filters that limit the bandwidth I and Q obtained. These digital filters shape the I and Q waveforms so that the spectrum obtained is contained in a given spectral mask. Digital filters preferably have an impulse response shown in the following table II:

Table II

172 909

Filters 42 and 44 may be constructed according to well known digital filter techniques and preferably provide a frequency response as shown in figure 9.

Binary "0" and "1" on digital filter inputs 42 and 44, produced by PN scatter functions, are converted to + 1 and -1, respectively. The sampling frequency of the digital filter is 4.9152 MHz = 4 x 1.2288 MHz. An additional binary input sequence "0" and "1", synchronous with the I and Q digital waveforms, is provided for each of the digital filters 42 and 44. This particular sequence, called the masking sequence, is the output quantity generated by the data packet randomizer. The masking sequence multiplies the binary I and Q waveforms to produce the ternary input / -1.0, + 1 / for digital filters 42 and 44.

As discussed previously, the reverse stream data rate has one of 9.6, 4.8, 2.4 or 1.2 kbps and varies for different frames. If the frames have the same length for both the access channel and the reverse traffic channel, the number of information bits per frame will be 192, 96, 48 or 24 for transmission at data rates of 9.6, 4.8, 2.4 or 1.2kbps respectively . As described previously, the information is encoded using a 1/3 convolutional encoder and then the code symbols will be repeated by a factor 1,2,4 or 8 for a data rate of 9.6, 4.8, 2.4 or 1.2, respectively. The obtained code symbol repetition rate is therefore set at 28 8000 symbols per second / sps /. This 28800 sps stream is interleaved as described previously.

Before transmission, the reverse flow interleaving output stream is controlled by a time filter that allows transmission of certain interleaving output symbols and deleting others. The work cycle of the transmission element therefore changes with the speed of the transmitted data. When the data transfer rate is 9.6 kbps, the transmission element allows all interleaving output symbols to be transmitted. When the data transfer rate is 4.8 kbps, the transmission element allows half of the interleaving output symbols to be transmitted, and so on. The control process takes place by dividing the 20 msec frame. for 16 periods of equal length / i.e. 1.25 ms./, called energy control groups. Some energy control groups are turned on / i.e. sent /, while other groups are turned off / i.e. not sent /.

The assignment of on and off groups is called the data packet randomizer function. Enabled energy control groups are pseudo-randomized in their positions within the frame so that the actual traffic load in the CdMa reverse channel is averaged, assuming a random distribution of frames for each duty cycle. The enabled energy control groups are such that each input code symbol for the repetition process will be sent once without repetition. During off periods, the mobile station does not transmit power, thereby reducing interference with other mobile stations operating on the same CDMA reverse path. This symbol control occurs before transmission filtering.

The transmission control process is not used when a mobile station transmits through an access channel. When transmitting via the access channel, the code symbols are repeated once / each symbol appears twice / before transmission.

When implementing the data packet randomizer function, the data packet randomizer logic 46 generates a stream of masking zeros and ones that randomly mask the redundant data generated by code repetition. The masking stream pattern is determined by the frame data rate and by a block of 14 bits taken from the long code sequence produced by generator 30. These mask bits are synchronized with the data flow and the data is selectively masked by these bits by the operation of digital filters 42 and 44. In logic 46, the long code sequence 1.2288 at the output of generator 30 is fed to the input of a 14-bit shift register, which is moved at 1.2288 MHz. The contents of this shift register are entered into a 14-bit lock, exactly one power control group / l, 25 ms./before each reverse frame of the reverse path. Logic 46 uses this data along with the input speed from microprocessor 18 to determine, according to a predetermined algorithm, a particular energy control group / s in which data is allowed to pass through filters 42 and 46 for transmission . Logic 46 thus outputs for each energy control group "1" or "0" for the entire energy control group, depending on whether the data is to be filtered / "O" / or passed / "1" /. In the appropriate receiver, which also uses the same long code sequence and corresponding frame rate, the proper energy control group (s) in which the data occurs are determined.

The output of channel I data from the filter 42 is fed directly to the digital-to-analog / C / A / converter and a filtering system 50 correcting image defects. However, Q channel data is output from filter 44 to delay element 48, which gives a half time delay / 406.9 sec./ PN module for Q channel data. Q channel data is output from delay element 48 to a digital-to-analog / C / A converter / and a filter system 52 correcting image defects. Circuits 50 and 52 convert the digital data to an analog form and filter the analog signal. The output signals of circuits 50 and 52 are supplied to the modulator 54 shift quadrature phase alignment, where they are modulated and output to the RF transmitting system 56. The circuit 56 amplifies, filters and processes the transmitted signal frequency. The signal is output from circuit 56 to antenna 58 for communication with the base station.

It should be understood that the exemplary embodiment of the present invention discusses data formatting for modulation and transmission relative to a mobile station. It should be understood that the data formatting is the same for a cellular base station, however the modulation may be different.

The previous description of preferred embodiments is provided to enable the skilled person to make and use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles set out herein may be applied to other embodiments without the use of inventive ability. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be within the broadest scope corresponding to the principles and new features disclosed herein.

172 909

DATA

ONLY

MOTION

DOWN

FRONT {9.6 KBPS)

DIMENSIONING AND PACKAGE WITH MOTION

FORWARD

AND SIGNALING (9.6 KBPS)

DIMENSIONING AND PACKAGE WITH MOTION

FORWARD AND RETURN (9.6 KBPS)

BLANKING AND PACKAGE

ONLY WITH SIGNAL TRAFFIC (9.6 KBPS)

BLANKING AND PACKAGE ONLY WITH REVERSING TRAFFIC (9.6 KBPS)

172 909

MM FORWARD MOVEMENT FT = 0

<td>"and-</td><td></td><td></td><td></td><td colspan="2">192 BITS-20MS</td><td></td><td></td><td>-about</td>

<td>MM</td><td>BF</td><td>TT</td><td>TM</td><td colspan="2">SOM MOTION</td><td>MOTION</td><td>F</td><td>T</td>

<td> =1</td><td> =0</td><td> =0</td><td> =00</td><td>FORWARD</td><td></td><td colspan="2">SIGNALING</td><td></td>

192 BITS-20MS -169 BITS

<td>BF = 1</td><td colspan="3">TT SOM = 0</td><td>MOTION SIGNALING</td><td>F</td><td>T</td>

MM BF TT RETURN MOTION FT = 1 = 1 = 1

172 909

4.8 KBPS FRAME FORMAT

96BITY-2OMS - 80 BITY80

FORWARD MOVEMENT

FIG.2 <

FORMAT 'FRAME 2.4 KBPS = -48 BITS - 20 MS - & = »o- 40BITS -gJ

FORWARD MOVEMENT

FIG.2I

FRAME FORMAT 1.2 KB PS

-24BITY-20MS

BITS

FORWARD MOVEMENT

T

172 909

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172 909

STATUS OF INITIALIZATION FROM THE MICROPROCESSOR

172 909

LONG MASK CODE OF ACCESS CHANNEL

41_29 28 24 23 21 20_98_0

<td>HEADING</td><td>ACN</td><td>PCN</td><td>STREFE_REJ.</td><td>STERUJĄCY_PN</td>

FIG. 8a

LONG PUBLIC CODE MASK 41_32 31_0

<td>HEADING</td><td>ESN / PERMUTATION ESN</td>

FIG. 8b

LONG PRIVATE CODE MASK

4039_0

HEADER | LONG PRIVATE CODE

FIG. 8c

FIG. 9

UP Department of Publications. Circulation of 90 copies Price PLN 6.00

Contents67

34 sheets

Sheet 1
Sheet 2
Sheet 3
Sheet 4
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225 members in 36 offices

This recordMember, by publication datePriority claim26 more offices are in the list below

Priority claims2

Priority claims
Document	Office	Kind	Date
82216492	United States of America	A	1992-01-16
9300406	United States of America	W	1993-01-19

Members225

Family members, oldest first
Document	Office	Kind
CA2085890A1	Canada	A1	1991-12-26
CA2360909A1	Canada	A1	1992-01-09
WO9200639A1	World Intellectual Property Organization (WIPO)	A1	1992-01-09
AU8401691A	Australia	A	1992-01-23
US5103459A	United States of America	A	1992-04-07
ZA914847B	South Africa	B	1992-04-29
CN1061312A	China	A	1992-05-20
IL98598D0	Israel	D0	1992-07-15
FI925812A	Finland	A	1992-12-21
FI925812A7	Finland	A7	1992-12-21
NO20032576L	Norway	L	1992-12-23
NO925019D0	Norway	D0	1992-12-23
NO925019L	Norway	L	1992-12-23
HU9204111D0	Hungary	D0	1993-03-29
EP0536334A1	European Patent Office (EPO)	A1	1993-04-14
BR9106592A	Brazil	A	1993-06-08
BRPI9106592A	Brazil	A	1993-06-08
KR930701880A	Republic of Korea	A	1993-06-12
CA2128327A1	Canada	A1	1993-07-22
WO9314588A1	World Intellectual Property Organization (WIPO)	A1	1993-07-22
AU3476793A	Australia	A	1993-08-03
PT98079A	Portugal	A	1993-08-31
CZ387192A3	Czechia	A3	1993-11-17
ZA93290B	South Africa	B	1993-11-22
EP0536334A4	European Patent Office (EPO)	A4	1993-12-01
CN1081040A	China	A	1994-01-19
HUT64657A	Hungary	A	1994-01-28
JPH06501349A	Japan	A	1994-02-10
IL98598A	Israel	A	1994-02-27
MX173818B	Mexico	B	1994-03-29
US5309474A	United States of America	A	1994-05-03
BG97222A	Bulgaria	A	1994-05-27
NO942670D0	Norway	D0	1994-07-15
SK387192A3	Slovakia	A3	1994-08-10
AU652956B2	Australia	B2	1994-09-15
FI943410A	Finland	A	1994-09-16
FI943410A7	Finland	A7	1994-09-16
NO942670L	Norway	L	1994-09-16
EP0621998A1	European Patent Office (EPO)	A1	1994-11-02
KR940704099A	Republic of Korea	A	1994-12-12
EP0621998A4	European Patent Office (EPO)	A4	1995-01-18
US5416797A	United States of America	A	1995-05-16
JPH07506469A	Japan	A	1995-07-13
TW253087B	Taiwan Province of China	B	1995-08-01
US5504773A	United States of America	A	1996-04-02
US5511073A	United States of America	A	1996-04-23
AU668378B2	Australia	B2	1996-05-02
IL116790D0	Israel	D0	1996-05-14
AU4791196A	Australia	A	1996-05-16
US5535239A	United States of America	A	1996-07-09
CA2210657A1	Canada	A1	1996-07-25
WO9622639A1	World Intellectual Property Organization (WIPO)	A1	1996-07-25
AU4760396A	Australia	A	1996-08-07
EP0730356A2	European Patent Office (EPO)	A2	1996-09-04
ZA96181B	South Africa	B	1996-10-14
US5568483A	United States of America	A	1996-10-22
IL118832D0	Israel	D0	1996-10-31
MY108626A	Malaysia	A	1996-10-31
IL104412A	Israel	A	1996-11-14
EP0730356A3	European Patent Office (EPO)	A3	1996-11-20
BR9305758A	Brazil	A	1997-01-28
TW301827B	Taiwan Province of China	B	1997-04-01
US5629955A	United States of America	A	1997-05-13
AR000423A1	Argentina	A1	1997-06-18
EP0621998B1	European Patent Office (EPO)	B1	1997-08-13
AT156954T	Austria	T	1997-08-15
ATE156954T1	Austria	T1	1997-08-15
US5659569A	United States of America	A	1997-08-19
FI972990A	Finland	A	1997-09-17
FI972990A7	Finland	A7	1997-09-17
DE69313098D1	Germany	D1	1997-09-18
BG61514B1	Bulgaria	B1	1997-10-31
MX9705396A	Mexico	A	1997-10-31
EP0804836A1	European Patent Office (EPO)	A1	1997-11-05
AU683597B2	Australia	B2	1997-11-13
ES2108260T3	Spain	T3	1997-12-16
BR9606833A	Brazil	A	1997-12-30
EA199700120A1	Eurasian Patent Organization (EAPO)	A1	1997-12-30
PL172909B1This record	Poland	B1	1997-12-31
CZ283123B6	Czechia	B6	1998-01-14
GR3025048T3	Greece	T3	1998-01-30
US5715236A	United States of America	A	1998-02-03
IL118832A	Israel	A	1998-03-10
DE69313098T2	Germany	T2	1998-03-12
DK0621998T3	Denmark	T3	1998-03-16
CN1178617A	China	A	1998-04-08
HK1000689A1	Hong Kong, China	A1	1998-04-17
KR0134390B1	Republic of Korea	B1	1998-04-27
AU694612B2	Australia	B2	1998-07-23
RU2116696C1	Russian Federation	C1	1998-07-27
SG52735A1	Singapore	A1	1998-09-28
JPH10512415A	Japan	A	1998-11-24
US5841806A	United States of America	A	1998-11-24
RU2125344C1	Russian Federation	C1	1999-01-20
KR100204160B1	Republic of Korea	B1	1999-06-15
US5103459B1	United States of America	B1	1999-07-06
US5943361A	United States of America	A	1999-08-24
EA000456B1	Eurasian Patent Organization (EAPO)	B1	1999-08-26
JP2958433B2	Japan	B2	1999-10-06
HU216989B	Hungary	B	1999-10-28

Showing 100 of 225

Numbers

Application: 30447293

Titles

English: METHOD OF FORMATTING DIGITAL DATA IN A DATA FRAME

Classification

CPC, 19: H04L1/0057
C11D3/3788
H04L27/30
H04J3/1688
H04J3/22
H04J3/24
H04J13/0048
H04J13/18
H04L1/0059
H04L1/0065
H04L1/0071
H04L1/08
C02F5/10
C08L33/02
C08L35/00
C08L51/02
C08L77/04
C11D3/3757
C11D3/3769
Filled: the office’s first classification
IPC, 21: H04L27 20
C02F5 10
C08L33 02
C08L35 00
C08L51 02
C08L77 04
C11D3 37
H04B7 00
H04J3 16
H04J3 22
H04J3 24
H04J11 00
H04J13 00
H04J13 18
H04L
H04L1 00
H04L1 08
H04L12 00
H04L27 30
H04L29 06
H04W72 04

Abstract

Term

DATA

ONLY

MOTION

DOWN

DIMENSIONING AND PACKAGE WITH MOTION

FORWARD

AND SIGNALING (9.6 KBPS)

DIMENSIONING AND PACKAGE WITH MOTION

FORWARD AND RETURN (9.6 KBPS)

BLANKING AND PACKAGE

ONLY WITH SIGNAL TRAFFIC (9.6 KBPS)

BLANKING AND PACKAGE ONLY WITH REVERSING TRAFFIC (9.6 KBPS)

192 BITS-20MS -169 BITS

4.8 KBPS FRAME FORMAT

96BITY-2OMS - 80 BITY80

FORWARD MOVEMENT

FORWARD MOVEMENT

FIG.2I

FRAME FORMAT 1.2 KB PS

-24BITY-20MS

BITS

FORWARD MOVEMENT

T

VI

VI

CN

CN

3J

ABOUT

CN

Q

ABOUT

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

AXIS

CN

ABOUT

CN

ABOUT

E

ABOUT

FM

ABOUT

PM

F-4

FM

OOOO

D

Q

ABOUT "

28S8

TH OMO

ABOUT

F-1 FF

STATUS OF INITIALIZATION FROM THE MICROPROCESSOR

LONG MASK CODE OF ACCESS CHANNEL

LONG PRIVATE CODE MASK

FIG. 9

Priority claims2

Members225

Numbers

Titles

Classification