Modem for telephone system

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Patent Board

The Netherlands © 192908 © C PATENT © Patent application: 8503399 © Submitted: 10.12.85 © lnt.CI.⁶

H04L27 / 18, H03H17 / 00, H04B7 / 24, H04J3 / 04 © Priority:

20.03.85 US 0000713923 © Laid out for inspection:

16.10.86 iE 86/20

Patent holder (s):

InterDigital Technology Corporation in Wilmington, Delaware, United States of America (US).

© Revealed:

01.12.97 IE 97/12 (47) Date:

02.04.98 (45) Issued:

02.06.98 IE 98/06 £ 4) Modem for subscriber telephone system.

Authorized representative:

Ir. LC de Bruijn et al. At 2517 KZ The Hague.

NL C 192908

Modem for subscriber telephone system

The invention relates to a modem including at least one multiple phase modulator for converting a phase modulated signal into a digitized bit stream, each given number of consecutive bits defines a symbol sequentially, which symbols are modulated in phase, digital filtering means for digital filtering or each phase modulated signal to form filtered, phase-representing, in-phase (I) and quadrature-phase (Q) components, and a digital-to-analog converter for converting the filtered, in-phase and qu adrature-phase components into an analog signal.

Such a modulator is known from British Patent Specification 2,092,864. The modem described in this patent is mainly directed to the modulation and transmission portions thereof and not to the receiving and demodulation portions thereof.

The invention now has for its object to provide a different and more complete embodiment of a modem in which use can be made in practical manner of a single combined l / Q signal, in which the parameters of this signal are both real and imaginary, and in which this modem is advantageously used. can be used in a base station or subscriber station of a high-frequency subscriber telephone system.

This is achieved with a modem of the type mentioned in the preamble according to the invention in such a way that the digital filter means comprise a multi-pole filter such that a single digital signal is formed in which the in-phase (I) and quadrature-phase (Q) components sequentially and overlapping time divided.

In this embodiment according to the invention, the 1 and Q components are combined, prior to their conversion into an analog signal, into a single time-divided current. A simplified embodiment is hereby obtained in which only one frequency signal is used for both the I and Q components. Advantageously, in the subsequent mixing, the single intermediate frequency can then be converted upwards, in which therefore the same gain is inherently applied for the I and Q samples. In this embodiment, therefore, no separate filters are required for the two components mentioned.

A modem is generally provided with a modulator section and a demodulator section. The transmitter section forms a system for converting a bit stream, in which each time a given number of consecutive bits defines a symbol, into a phase-modulated medium-frequency signal with a predetermined medium frequency. The modulator section provides phase modulation of each symbol, digitally filtering each phase modulated symbol to provide a filtered signal that upon conversion into an analog signal provides a modulation signal with a modulation frequency centered around a predetermined frequency and deviating from it in accordance with the value of the phase-modulated symbol; converting the filtered signal into an analog signal to provide the modulation signal; mixing the modulation signal with a quiescent state signal at a predetermined frequency to provide a phase modulated medium frequency signal that forms a frequency modulated (fm) signal with an intermediate frequency that is the modulation product of the modulation frequency and the predetermined frequency.

The demodulator section of the modem is provided with a demodulation system for converting a received phase modulated medium frequency signal into the bit stream from which the received phase modulated medium frequency signal was derived.

The described modem can function in a transmission mode, a reception mode, in a time-division multiplex transmission / reception mode or in a learning mode.

When operating in the transmit mode, the modulator section of the modem receives a digital binary bit stream of up to 4 bits per symbol and then converts the symbols into a phase modulated mid-frequency signal at a predetermined mid-frequency of 20.2 MHz. The modulated medium frequency signal is transmitted to a high frequency unit for up-conversion and transmission at the appropriate UHF frequency. When operating in the receive modes, the receiver section of the modem receives a phase modulated medium frequency signal from a high frequency receiver unit. The modem filters the received intermediate frequency signal and converts this signal into a baseband frequency signal and digitizes it into a complex (I, Q) sample with a predetermined symbol rate of 16 Ksps (kilo symbols per second). A digital FIR filter (finite response filter) performs further filtering and the complex samples are converted into a digital binary bit stream. The binary bit stream is then delivered to a base band unit.

The modem further performs functions for providing connection quality symbol synchronization measurements and various control and status reporting functions.

The modem can be placed in a learning mode at certain intervals. In this mode, the modulator and demodulator sections of the modem are fed back via the high-frequency unit to train the FIR filter in the demodulator section for changes in the system (mainly the filters in the high-frequency unit) that may occur with fluctuations in temperature, age, attenuation in adjacent channels or other environmental fluctuations. The FIR filter of the demodulator section learns its coefficients to counteract possible filter inaccuracies in order to achieve the best possible input signal. In this feedback mode the transmitter section of the modem outputs a fixed known training pattern to the demodulator section of the modem. The FIR filter of the demodulator section adjusts its coefficients (trains) in accordance with the signal itself, with delayed and leading signals, and with signals from adjacent bands.

Further features of the present invention are described with reference to a description of a preferred embodiment.

Figures 1A and 1B in combination show a block diagram of the preferred embodiment of a modem.

Figure 2 shows the signal constellation used in the Gray coding of the bit stream symbols.

Figure 3 is a block diagram of the digital FIR filter in the modulator section of the modem.

Figure 4 illustrates the multiple sample impulse response pattern of the digital FIR filter in the modulator section of the modem.

Figure 5 is a block diagram of the SIN / COS medium frequency generator in the demodulator section of the modem.

Figure 6 shows the waveforms of certain control time determining and data signals involved in the operation of the modem.

Overview of the abbreviations used in the description:

Abbreviation Definition

A / D analogue / digital converter

AGC automatic gain control

AM amplitude modulation

BPSK binary phase shift encryption modulation

BS base station

CCU channel control unit

D / A digital / analogue inverter dB decibel

DPSK differential phase shift encryption modulation

ECL emitter coupled logic

FCC the federal communication commission of the United States

FIFO first in first out of memory

FIR filter for impulse response with finite duration

Hz hertz (vibrations per second)

I in phase

MF middle frequency kHz kilohertz ksps kilo symbols per second

LSB least significance bit

MHz megahertz

MODEM combined modulator and demodulator

OCXO oven controlled crystal oscillator

Q quadrature

QPSK quadrature phase shift encryption modulation

RAM random access memory

RCC radio control channel

RELP rest-excited linear prediction

HF high frequency

HFU high frequency unit

ROM readout memory

<td>RX</td><td>receive</td>

<td>STIMU</td><td>time-determining unit of the system</td>

<td>SUB</td><td>subscriber station</td>

<td>TDMA</td><td>time division multiplex access</td>

<td>TX</td><td>send</td>

<td>UHF</td><td>ultra high frequency</td>

<td>VCXO</td><td>voltage controlled crystal oscillator</td>

A preferred embodiment of the modem is shown in Figures 1A and 1B. The modulator section of the modem is essentially provided with a read-out memory (ROM) 10 for digital phase shift encryption conversion (DPSK conversion), a learning mode switching unit 11, a digital filter 12 for finite duration pulse response (FIR), a digital / analog converter 13, a band pass filter 14 with a center frequency of 200 kHz, a mixing stage 15 and a high-frequency amplifier 16 centered at 20.2 MHz.

The demodulator section of the modem basically comprises a model TMS32010 digital microprocessor 17, a FIFO stack 18 (first in-first out of register), an analog / digital converter 19, an amplifier 20, and a mixing stage 21.

The modem further comprises various time-determining and controlling units which are essential for the modulation and demodulation functions performed by the modulator section and the demodulator section, respectively. These units include interface registers and a bus control unit 23, which is provided with a status register 24, a connection quality register 25 (Q-register), an AGC register 26, a receive frequency register 27, a subscriber fractional delay register 28 and a phase (I) register 29 , a quadrature (Q) phase register 30, the control unit 31 and a second fractional delay register 32.

The time-determining and controlling units of the modem are further provided with a buffer control circuit 34, a read / write decoding unit 35, a training pattern FIFO register 36, a data locking circuit 37, a generator 38 for generating internal time-determining and controlling signals, a transmit clock pulse delay unit 39, a fractional time delay generator 40, a VCXO interface unit 41, a sample time generator 42, a COS / SIN medium frequency signal generator 43, a 2 K random access memory (RAM) 44, a 2 K ROM 45, a 4 K ROM 46, a buffer / attenuator unit 47 and a buffer unit 48.

The modem is connected to a system time-determining unit (STIMU) 49.

The modem coupling circuits are shown in Figures 1A and 1B. The modem receives most of its input signals from the CCU. Other input signals come from the high-frequency unit and from the time-determining units. The modem input signals are the following:

To the modem from TX DATA (lines 50)

MOD BUS (51)

MOD WR (line 52) MOD RD (line 53)

MOD RESET (line 54) MOD ADD (line 55)

TX SOS (line 56)

RX SOS (line 57) the channel control unit (CCU):

A 4 bit symbol to be transmitted by the modem (4 bits for 16 worthy PSK, 2 bits for QPSK, 1 bit for BPSK).

a bi-directional microprocessor bus that provides control / status information to / from the modem.

The control signal for locking MOD BUS in the modem.

The control signal to bring the modem status and other information to the MOD BUS for transmission to the CCU.

This CCU control signal will reset the modem.

A control signal for defining different address locations and locked values ​​in the modem.

Signal from the CCU to the modem to start transmitting a transmit slot.

Signal from the CCU to the modem to start receiving a receive slot.

To the modem from the high-frequency unit (RFU):

IF RX (line 58) Medium frequency receive frequency from the RFU.

To the modem from the time-determining units (STIMU):

An 80 MHz ECL clock pulse signal! from the base station or from the STIMUs of the subscriber. Output signal from the XO in the base station and the VCXO in the subscriber station.

Master transmit clock pulse signal used in the base station from the STIMU.

Master frame start signal in the base station from the STIMU. Not used in the modem but forwarded to the CCU.

From the modem to the channel control unit (CCU):

MHz (line 59) kHz (line 60)

SOMF (line 61)

TX CLK (line 62)

RX CLK (line 63)

RX DATA (lines 64) MOD BUS (51)

MOD SOMF (line 61) AM STROBE (line 65)

A 16 kHz clock pulse signal that ensures the symbol transmission time determination in the CCU. The symbols are clocked into the modem on the rising edge of this clock pulse signal. In the base station, all slots have the same master TX CLK. All signals from the base station are therefore transmitted simultaneously. In the subscriber station, the TX CLK signal is shifted by the modem over the fractional path delay on information provided by the CCU.

The 16 kHz clock pulse signal that is derived from the received signal (always in the subscriber station and only during the control slot acquisition in the base station). This clock pulse signal will clock out the received symbol to the CCU and ensure the timing of the symbol in the CCU.

The 4 bit received symbol, clocked by RX CLK.

Status and data information from the modem.

Transfers SOMF / from the STIMU to the CCU in the base station.

A high-to-low transition on this line provides the CCU with a rough frame mark during the radio control channel acquisition (RCC) in the subscriber unit. This is a monostable line that is pulsed when the RX TMS 320 determines the approximate location of the AM opening.

From the modem to every high-frequency unit (RFU):

RF RX BUS (66)

RF TX BUS (67)

RX 80 MHz REF (line 59a)

TX 80 MHz REF (line 59b)

TX EN (line 68) RX EN (line 69) AGC WR (line 70) bit bus between the modem and the RF RX unit. The bus transports AGC and frequency selection information to the RFU receiver section. The modem controls the AGC values ​​to be transmitted and forwards CCU frequency selection information. The frequency selection information is supplied to the modem via the MOD BUS bus 51. In the learning mode, the modem will control the RF RX frequency selection.

bit bus between the modem and the RFU transmitter section. This bus transports TX power level and frequency selection information to the modulator section. The modem has nothing to do with this, so this information is only transferred to the RFU transmitter section.

ECL 80 MHz reference clock pulse to the RFU receiver section.

ECL 80 MHz reference clock pulse to the RFU transmitter section.

Line to RFU transmitter section to release the RF transmission.

Line to the RFU receiver section to release the RF reception. Write activation signal for locking AGC data in the RFU receiver section.

RXFREQ WR (line 71) Write activation signal for frequency registrations in the RFU receiver section. RXFREQ RD (line 71a) Read activation signal for reading back the receiving frequency of the RFU receiver section.

Write activation signal for locking power information in the RFU transmitter section.

Read activation signal for reading back power information from the RFU transmitter section.

TXFREQ RD (line 74) Read activation signal for reading back the transmission frequency of the RFU transmitter section.

TXFREQ WR (line 75) Write activation frequency registered in the RFU transmitter section.

IF TX (line 76) Broadcast signal on the center frequency to the RFU.

PWR WR (line 72)

PWR RD (line 73)

AGC RD (line 77) Read activation signal for reading back AGC data from the RFU receiver section.

From the modem to the system's determining unit (STIMU):

VCXO FDBK (line 78) A 10-bit data bus to the VCXO with control information for tracking the frequency.

VCXO WR (line 79) Write pulse to the VCXO circuit for locking VCXO BUS in the VCXO.

The modulator section of the modem transmits the information supplied to it on the TX DATA lines 50 by the CCU on 16 level PSK modulation. The modem broadcasts without knowledge of the modulation level of the received information.

The input control lines are decoded in the modem to select which register is to control the 8 bit MOD BUS 51 between the modem and the CCU. Control information regarding the receipt of a slot becomes active when the modem receives the RX SOS signal on the line 57 of the CCU. This line interrupts the microprocessor 17 to begin demodulation on an incoming slot. At that time, the RFU receiver section is released by the modem with the RX AND signal on the line 69.

At the end of each slot, the status information is updated to the registers 23 in order to be read by the CCU.

In the subscriber station, the CCU can instruct the modem to acquire the RCC signal from the base station. The most important acquisition characteristic of the RCC is the AM HOLE of eight symbols. In software, the modem scans the frequency selected by the CCU to detect the AM HOLE. The microprocessor 17 scans the frequency selected by the CCU to detect the AM HOLE. If an AM HOLE is present at this frequency, the microprocessor 17 will encrypt it. After the microprocessor 17 is sure that the AM HOLE is present, it will make the AM STROBE line 65 low via a pulse to communicate to the CCU two facts: (1) that the RCC signal has been found and (2) that the AM STROBE is a rough start for the frame mark. From there, the CCU will begin to look for the unique word in the RX data stream within a window of 0 to 3 symbols. Once the unique word is detected, the subscriber station's CCU can set its frame and slot counters to synchronize them with the base station's system frame.

The interface between the modem and the RFU receiver section makes it possible to control the frequency selection and the AGC levels in the RFU. The CCU controls the frequency selection and sends its instructions to the modem. The modem sends this information over the RF RX BUS 66 to the RFU. This bus 66 is also used to control AGC levels in the RFU receiver station. These AGC values ​​are updated in every symbol duration and transferred to the RFU receiver section.

The CCU modem interface is shown in Figure 1. The time relationships for the transmit interfaces are shown in Figure 6. These interfaces operate at a low speed and therefore only require standard TTL hardware interfaces. The modem provides the CCU with the 16 kHz symbol clock pulse. Four TX DATA bits are on a parallel bus to the modulator section. An 8 bit bus is available for exchange of control / status information. Control information is supplied to the modem by the CCU via asynchronous interface registers 23. The contents of the registers become valid if the TX SOS port signal on line 56 is received by the modem, indicating that the transmission of a slot can be started. The CCU provides the following control information to the modem: (1) freewheel mode; (2) transmit voice channel; (3) transmit control channel; (4) learning mode feedback; (5) TX CLK fractional symbol delay; (6) RF TX power level; and (7) RF / TX frequency selection. The RX frequency selection is stored in the RX frequency register 27.

The CCU has a direct coupling circuit with the high frequency TX unit from the MOD BUS 51 to the RF TX BUS 67 via the buffer control unit 34. The decoded addresses are supplied to the RFU as write gate signals for locking the TX power and TX frequency information . The modem must have control over the high frequency RX bus 66 for updating AGC data in the RFU. Therefore, the modem sends RX frequency information from the register 27 to the high frequency units at the beginning of each RX slot. This value is locked in the register 27 by the CCU. The modem can also change the RX frequency itself during the learning mode without the CCU having to do this.

The modulator section of the modem is fully implemented in hardware and requires no settings. The symbols of the CCU are received on the TX data lines 50 at a speed of 16 K symbols per second. The received symbols are phase modulated by the DPSK transform ROM 10 and the resulting waveforms are formed by the FIR filter 12 in order to obtain good interference characteristics and not to suffer from amplitude or group delay distortion. The justification for this concept follows from the assumption that in the frequency band closely adjacent to the band used (within 50-100 kHz) there are no strong interference signals (with power densities of 30-40 dB above the signal). The band pass filter 14 centered on 200 kHz provides a broad mid frequency filtering (100 kHz) so that the transmitted signal will not suffer from amplitude or group delay distortion and also filters out any harmonics that can be generated by the digital filter process and the D implemented in the base band / Aomation.

The main filtering operation is performed in the baseband by the digital FIR filter 12 with fixed coefficients. This filter 12 is a six-pole filter with a sampling rate of 50 samples per symbol per symbol duration in the FIR filter 12 in the modulator section.

Because no analog fitter operation is performed in the baseband, there is no need to implement two separate I and Q channels. In fact, the I and Q channels are implemented in the FIR filter 12. A time division channel, including the mixing stage 15, which multiplies by the center frequency, transforms this channel up to the center frequency. This channel inherently has the same gains for the I and Q samples. The I and Q sampling is now alternately performed over half a sampling period, but this is corrected in the FIR filter 12.

The Gray code is used for digital coding by the DPSK conversion ROM 10. This ensures that if a symbol was received incorrectly, it is most likely that the error in the decoded symbol will be only one bit. The signal constellation is shown in Figure 2. The phases, marked with "Q" and "B", are the QPSK and BPSK symbols, respectively.

The symbols are assumed to be Gray coded phase symbols. Each phase symbol is then converted to binary form from the Gray code and added to the binary form of the last phase symbol to form the DPSK symbol. As a result of the FIR filter algorithm, the other symbol is inverted prior to entry into the FIR filter 12. Therefore, the DPSK conversion is performed using the ROM 10. Four symbol bits, four bits of the preceding symbol and one bit for inversion control are input to the DPSK conversion ROM 10, which outputs the DPSK symbol to the input of the FIR filter 12.

After the DPSK conversion, the symbol is then delivered on the lines 80 to the FIR filter 12, which filter consists of an FIR filter with excessive sampling and six taps. The FIR filter 12 is provided with a ROM 81 and two three-stage 4-bit shift registers 82, 83 as shown in Figure 3. The FIR filter 12 serves to form the transmitted symbols in accordance with the specifications of the frequency channel. The sampling rate of the ROM 81 is determined by a timing signal provided on the line 84 by the time signal and control signal generator 38 to the counter 85 connected to the ROM 81. An input clock pulse signal is provided on the line 86 to two input switches 87 88, which allow data to be inserted into the shift registers 82, 83.

With reference to Figure 4, each of the six symbols in the two shift registers 82, 83 is sampled at a speed of 3/25 T (T = 1/16 kHz). This oversampling scheme ensures that the samples are skewed so that only two symbols are sampled during every 1/25 T sampling period. Therefore, two symbols are entered in the ROM 81 during every 1/25 T sampling period. Each 1/25 T sampling period is in turn divided into two parts: in phase (I) and quadrature (Q). During the first half of the 1/25 T period, the registers 82, 83 input the 3 bit in-phase component (I) of the symbol and during the second half of the period the quadrature component (Q) of the symbol is input to the ROM 81. The output signal from the FIR filter on line 89 thus forms the time-divided combination of digital I and Q waveforms of the waveform sent from. These samples are then supplied on lines 89 to the D / A converter 13 for conversion to an analog waveform. This waveform is then filtered through the bandpass filter 14 and supplied on the line 91 to the mixing stage 15 for upward transformation to a 20 MHz medium frequency signal on the line 92.

The two shift registers 82, 83 shift two of the stored symbols in the ROM 81 at a speed of 1/25 T for the required calculations. The symbols are converted to 3-bit I and Q-Gray code components by selecting either the fourth or the third symbol bit to the most significant bit (MSB) of the 3-bit component. The two least significant bits (LSBs) remain unchanged. This component selection is carried out at a speed of 1/50 T.

The ROM also requires five input signals from the counter 85 to indicate which of the 25 sampling periods is currently being calculated. An additional input signal from the counter 85 is required to indicate to the ROM 81 whether the three input bits are the I or Q components of the input symbols.

The output signals stored in the FIR filter ROM 81 of the transmitter are calculated to correct any errors that may occur due to the 1/50 T differences in the I and Q time values. Also, the center frequency filter in the RFU joins the two values ​​together to form the corrected waveform to be transmitted because its bandwidth is relatively small compared to the center frequency. The FIR filter ROM 81 provides an output signal consisting of 10 bit digital samples on line 89 at a speed of 800 kHz.

ZERO symbols can be injected into the FIR filter 12 to represent symbols with which no power is transmitted. These are used in the learning mode to enter a "pulse" into the FIR filter 12. These NULLS can also be used to deliver the AM HOLES and monitor the bands required on the radio control channel (RCC).

The D / A converter 13 receives the digital input signals from the digital FIR filter 12 and produces the requested spectrum at multiples of 33.33 kHz starting at 66.67 kHz.

The band pass filter 14 passes the 200 kHz spectrum with extremely small variations in band pass attenuation and group delay. The attenuation ripple is less than 0.1 dB and the delay variation less than 1.5 με. The aliasing spectra have been weakened to more than 20 dB.

The desired output signal from the D / A converter 13 is centered at 200 kHz with a bandwidth of approximately 32 kHz. This signal is filtered in the pass band by the band pass filter 14 prior to the mixing process to remove signal components at n times 133 kHz. By multiplying the 200 kHz waveform by 20 MHz, the mixing stage 15 mixes the I and Q samples with the SIN and COS components of the center frequency. The 20 MHz signal can thus be directly multiplied by the output waveform and the exact component multiplications will be performed automatically. It is therefore not necessary to use a discrete SIN (MF) / COS (MF) generator circuit to multiply the 1 / Q samples of the D / A as is the case in the demodulator section. This also prevents signal leakage through the mixing stage 15 from the base band to the output of the mixing stage 15.

The buffer attenuator unit 47 accepts a 20.00 MHz intermediate frequency ECL level signal on line 94 from the time and control signal generator 38 and translates this into a 350 mV peak / peak signal used as the local oscillator signal supplied on line 95 to the mixing stage

15. Another (not shown) voltage divider provides the +7.5 bias DC voltage of the mixer 15.

The mixing stage 15 is an active mixing stage of the MC1496 type. The I and Q component waveform on the line 91 is frequency frequency herein transformed into a 20.20 MHz medium frequency signal which is provided along with all other mixing products on the line 92. Third-order intermodulation products are lower than 40 dB. The mixer 15 is operated at a high level on the carrier input port and a low level on the modulation signal input port. This results in a saturated switching operation of the double differential carrier amplifier, and a linear operation of the differential modulation amplifier. No zero carrier is supplied because the carrier at 20.00 MHz is filtered out by a 20.20 MHz crystal filter in the RFU. The current sources are set to provide a current of 2 mA. An emitter degeneration resistance of 470 Ω (not shown) is provided to maintain the modulation input signal for linear operation at a peak of 1 volt.

The hf amplifier 16 is provided with an emitter follower buffer for isolating the tuned circuit of the mixer with respect to the hf unit and provides a 50 Ω output impedance. In order to eliminate the influences of the scattering capacity, the output capacity of the unit and the capacity of the emitter follower that buffers the input of the mixer, a parallel tuned circuit is used on the output of the mixer, which can be adjusted for maximum gain. The total gain of the mixer must be 10 dB because -10 dBm at 50 Ω is required at the modem's output. A fixed inductor instead of a variable can be used later in the mixing tank output tank circuit. The RF amplifier 16 amplifies the signal on the line 92 from the output of the mixer 15 and supplies the amplified signal to the RFU via the IF-TX line 76.

in free-idle mode, the modulator section of a base station modem sends a idle pattern that is offered by the CCU. Because in the subscriber station the modem works in half duplex, the CCU places the modem in the receive mode in all slots with the exception of the slot in which the subscriber station itself broadcasts. This makes it possible for the demodulator section of the subscriber station modem to monitor the AGC so that there is no surprise when a signal train enters from the base station.

The freeioop mode is used when there is a frequency for which at least one but not all locks are used. The empty slots are filled with the free-running pattern. If no conversation takes place on a frequency, the modulator section can be turned off.

Referring to the demodulator section of the modem, the mixer 21 presents a 50 Ω input impedance to the 20.00 MHz, -30 dBm signal received from the RFU over the MF-RX line 58. The basic function of the mixer 21 is to down transforming the MF signal from the RFU to the baseband and also amplifying it by 30 to 35 dB. A stable state signal is provided over line 22 at 20.00 MHz. The stable state signal on line 22 is the time-multiplexed SIN / COS / -SIN / -COS signal of the COS / SIN MF generator 43. An active mixer stage 21 of the MC 1496 model is used with the input signal of the local oscillator on line 22 on a high level and the modulated signal on line 58 at a low level. The output signal from the mixer on line 97 in the base band is alternatively coupled to alternating current with the amplifier 20, which is a differential amplifier. A high-pass filter is formed by the capacitive coupling from the mixing stage 21 and the input resistance from the differential amplifier 20 and has a cut-off frequency at approximately 1 Hz.

The buffer unit 48 provides the interface between the 20.00 MHz generator 43 at the ECL level and the mixing stage 21. The buffer unit 48 provides a 350 mV peak-peak signal for outputting the carrier input signal in the saturated switching state and also provides a bias voltage of +7.5 V DC for this input.

The MF SIN / COS generator 43 is shown in Figure 5. The generator 43 is provided with ECL components that function at four times the followed mf frequency in response to a 4 mf time signal on the line 98 from the timing and driving signal generator 38. With Referring to Figure 5, two flip-flops 99,100 serve as a four-divide counter with each of their outputs being 90 ° out of phase. A 4x1 multiplexer (MUX) 101 switches between the SIN, COS, -SIN, -COS outputs. The output of the MUX 101 is again clocked by another D flip-flop 102 and provides the output signal on line 103 to the mixing stage 21. This circuit provides a perfect 90 ° phase shift between the four components.

The single time multiplex channel also ensures that the i and Q components arrive with exactly the same gain factors.

The time diagram for the demodulator section is also shown in Figure 6. The modem supplies the CCU with the four data bits and their 16 kHz symbol clock pulse. The address lines and the 8-bit bus provide the status / control information exchange between the two units.

The amplifier 20 accepts the differential output signal from the mixer and amplifies it by approximately 25 dB. The amplifier 20 supplies an a.c. +10 volt peak-to-peak signal to the A / D converter 19 with a very low distortion.

The A / D converter 19, which consists of a TRW 12-bit A / D converter, is used to convert the baseband spectrum of the differential amplifier 20 into digital data to be processed by microprocessor 17. The sampling rate is four times per symbol (64 kHz).

During normal operation, digital processing is performed by the TMS 320 microprocessor

17. The microprocessor 17 operates at 20 MHz with 4 K bytes of memory from the 4 K ROM 46. The port address pins are used to address the I / O registers between the demodulator section and the CCU or the special diversity combination circuit.

The microprocessor 17 receives the 1 / Q data from the mixing stage 21 with a sampling rate of 64 kHz. The data is again time multiplexed over one frequency channel as happens in the modulation section. The microprocessor 17 takes care of filtering and demodulating the waveform. The microprocessor 17 then outputs the received symbol over the bus 104 to the data latch circuit 37 which provides the symbol to the CCU via the RX DATA lines 64 with a pulse of the RX CLK signal on line 63 at a speed of 16 kHz.

The receiver status is placed in the status register 24 and the I / Q samples are placed in the I-register 29 and the Q-register 30. The CCU will read the status while the I / Q samples are needed for an external diversity combination circuit. The control / status interface and functions are described below.

The operation of the base station modem is set at a fixed RF frequency. Communication in the base station is completely duplex. Therefore, the modulator and demodulator sections of the modem are operating simultaneously. If the modem is also designated as the control frequency channel modem, it will only send and receive information with the radio control channel format (RCC) during the assigned control slot period. In the base station, an OCXO present in the system time unit (STIMU) 49 is fixed and serves as the master clock pulse generator of the system. Therefore, no frequency deviations will occur during reception.

All transmissions from the base station modems are clocked by the master TX CLK (16 kHz) signal on line 60. The fractional time delay generator 40 in the base station modems supplies the CCU of the base station with the fractional portion of the symbol duration between the master TX CLK signal on line 60 and the derived RX CLK signal on line 63 in the modem. This information is then transmitted to the subscriber unit via the radio control channel so that the subscriber will delay his broadcast to ensure that his signal is received at the base station in synchronization with all other slots.

All operations in the subscriber station modem are derived from the received clock pulse signal (RX CLK) which is recovered from the received transmission by the time and control signal generator 38. This serves as master clock pulse generator of the subscriber station. The TX CLK signal on the line 62 from the transmit clock pulse delay circuit 39 to the CCU is not a master clock pulse signal as in the base station. It is derived from the RX CLK signal on line 63 and delayed by the transmit clock pulse delay circuit 39. The duration of this delay is provided by the CCU of the subscriber station, the fractional delay register (SUB) 28 and derived therefrom by the transmit clock pulse delay circuit 39. The CCU of the subscriber station receives the delay via the radio control channel from the base station CCU. The delay is determined by the distance between the base and the subscriber stations. The CCU of the subscriber station feeds this fractional time information to the fractional delay register (SUB) in the modem via the MOD BUS 50. The modem itself incorporates the fractional delay via the transmit clock pulse delay circuit 39. The CCU takes into account the integer symbol delay by inserting the TX SOS signal on line 56 to the modem delayed with the correct number of symbols. This process ensures alignment of the signals arriving at the base station from variations in the area of ​​all subscriber stations.

There are many sources of delay in the modem system that have a pronounced influence on system timing. This includes the analog filter delays, propagation delays, processing delays in the FIR filter 12, and so on. These delays cause skew between TX and RX frames and these skewed situations must be accurately taken into account.

The delay paths from the modulator section to the demodulator section are listed below together with their estimated values.

Tta TX analog delay, approximately 0.55 T.

Ttr Transitional delay between TX and RX in the hf unit. About 1.9 T.

Td Propagation delay. Maximum 1.2 T (one-way).

Tra RX analog delay. Approximately 5.77 T.

Th The time during sampling of the RX analog filter output signal for

A / D transformation. Approximately 0.03 T.

Tc A / D conversion time. Approximately 0.22 T.

Tf1, Tf2 RX FIR "window". To receive a peak at time t = 0, the sampling filter must start at t = - Tf1 and continue until Tf1 is approximately equal to 3.5 T and Tf2 is approximately equal to 3.25 T.

To TMS processing delay between '' peak and TMS output signal. Approximately 4.5 T.

Tw TX waveform length (6 T).

Tcrt Compensation delay between RX and TX (subscriber); minimum for the farthest subscriber and maximum for the nearest subscriber.

SBn Nearest subscriber.

SBf Remote subscriber.

The delay between the TX SOS in the base station and the first received analog peak ”symbol in the base station is +7.4 symbols. Therefore, there is a skew between the TX and RX slots. To correctly decode the incoming phase, the modem must start sampling about 3.5 symbols before the "peak" arrives. Therefore, the skew between the TX SOS and the start of the RX sampling covers approximately a length of four symbols.

In the base station the start of the RX slot takes place about 4 T after the start of the TX slot. The start of the RX slot is defined as the time when the first analog sample is taken to detect the first peak received.

The modem of the farthest subscriber station will start its TX slot 4 T before the start of the RX slot of the modem in the base station. Other subscribers can delay the start of their TX slots.

In the total hf telephone subscriber system, circular transmission delays can occur anywhere due to the distance with a time length between 0 and 3 symbols. Therefore, in order to ensure that the received communication in the base station is synchronous, the subscriber station must be able to shift its transmit clock pulse signal by 0 to 3 symbol times with respect to the derived received clock pulse signal (RX CLK). The time delays are calculated in the base station and transmitted via the control channel and interpreted by the CCU. The CCU then provides the fractional delay 5 constants to the modem of the subscriber station to delay the TX CLK. The fractional delay is an 8-bit value that is entered in the fractional delay register (SUB) 28. The entire symbol delay is controlled by the CCU. The TX SOS port signal on line 56 is generated with a delay of 0.1 or 2 symbols depending on the trajectory values ​​received from the base station.

During the reception of a random slot, the modem performs a frequency synchronization through acquisition and then continues with the tracking process. In the subscriber station, the VCXO is under direct control of the microprocessor 17 via a D / A converter in the VCXO interface 41. The frequency acquisition and voice algorithms in the microprocessor 17 calculate the c hangs that are needed in the VCXO to maintain synchronization.

During the receipt of a random slot, the microprocessor 17 also performs a bit synchronization on the bit synchronization pattern of the received data stream. An algorithm performs a bit tracking loop. The microprocessor 17 has control over a variable frequency divider or the 80 MHz VCXO or OCXO (only during the steering slot demodulation). Within the bit tracking loop, the microprocessor 17 modifies the frequency division to achieve bit synchronization. During the reception or a speech channel, the partial values ​​have step dimensions of 0.1% or 16 kHz, but during a control slot the values ​​can vary much more, even up to ± 50%.

Frame synchronization is handled in a completely different way in the base station and in the subscriber stations. In the base station, a master SOMF (start of modem frame) signal is sent on the line 61 to the CCU via the modem. This is the master SOMF signal that is used for all broadcasts from the base station. The CCU can derive all slot and frame time relationships from this signal and from the master system symbol clock pulse signal (16 kHz) on line 60.

During the initial acquisition, the microprocessor 17 searches in the subscriber station for the AM HOLE in the RCC. If the AM HOLE is detected, the microprocessor 17 will count it for a few frames and then cause the time and control signal generator 38 to place the AM STROBE / mark on the line 65 to the CCU at the AM HOLE frame location. The CCU uses this port marking to set initial frame mark counters (window formation) that can be modified by the CCU software for precise frame synchronization. This also indicates that the AM HOLE has been detected and the RCC has been acquired.

The slot synchronization is controlled by the CCU. The signals TX SOS on line 56 and RX SOS on line 57 are instructions to the t time and control signal generator 38 to start transmitting or receiving a slot. These signals are synchronized to the TX CLK signal on line 62 and RX CLK on line 63, respectively.

The modem demodulator section operates either in the off-line mode or in the on-line mode depending on bit 7 of the RX control word in the control word register 31. For switching the demodulation section from one mode to the other, the CCU then sends MOD RESET, necessary instruction in the RX control word register 31 via the MOD BUS 51, and then deactivates the MOD RESET signal.

In the offline mode, the external memory on the microprocessor is provided by 2 K words from the ROM 45 and 2 K words from the RAM 44. The CCU instructs the modem to enter into this mode after turning on the power and one times during any predetermined number of hours while the modem is not sending or receiving, in order to perform self-test and training routines primal.

The self-test routine tests the ROMs 45, 46, the internal RAM and the external RAM 44, and the link circuit to the CCU. It sends the test results to the CCU via the status register 24.

The training routine includes sending a training signal to the demodulator section and calculating the coefficients of the FIR fitter used in the microprocessor 17. This is done offline for any predetermined number of hours while the modem does not send data or receive data in the online mode, the modem receives signals from either the control channel or a voice lock, in accordance with the control word in the control word register 31 for the RX section. The online software performs the following routines.

An initialization routine is performed by the microprocessor 17 upon power-up or 55 after a reset signal is received. This routine reads the control word in the register 31 and calls other routines i n compliance with the control word.

This routine is performed when the CCU sends a MOD RESET signal to the modem on line 54 and an instruction via the MOD BUS 51 to the control register 31 to continue in the online mode. This routine performs a checksum test on an online PROM, initializes parameters, reads the control word register 31 and branches to the appropriate routine.

A frequency acquisition routine is performed only in the subscriber station modem upon reception of the control channel in order to synchronize the VCXO frequency of the subscriber station to the crystal frequency of the base station. Because the transmit, receive and mf frequencies are derived from the VCXO in the subscriber station or the OCXO in the base station, this will ensure that all frequencies are synchronized.

This routine is used only in the modem of the subscriber station. She is activated by an instruction from the CCU while the demodulato rsection is set to the control channel frequency. Its function is to synchronize the VCXO frequency with that of the OCXO in the base station. This is done by first looking at the AM HOLE, which is a small period of time during which no transmission takes place from the base station. The base station then transmits a non-modulated carrier wave. Upon receiving this waveform, the mf mixing stage will output another sine waveform whose frequency is proportional to the difference between the VCXO and the base station crystal oscillator frequency. The modem software samples the I and Q channels at specific intervals and performs a phase lock loop function, that is, determines the phase change for each interval, passes it through a low pass filter, and sends it as a correction word to the VCXO. The modem determines that the frequency acquisition is achieved if the phase change becomes lower than a certain level. If the AM HOLE is not detained ected during a certain period of time, the module will send an error message to the CCU indicating that the receiver is not tuned to the control channel.

The routine is called by the initialization routine and sends a status word from the status register 24 to the CCU indicating whether or not the frequency acquisition has been realized.

After being invoked by the initialization routine, the frequency acquisition routine samples the I and Q channels looking at the AM HOLE while simultaneously creating an AGC loop. If the AM gap is not detected during a predetermined number of samples, the routine transfers this information to the CCU via the status register 24. The CCU will then switch to another possible RCC frequency and reactivate the frequency acquisition routine.

After detection of the AM opening, this routine will provide a phase lock loop for the length of time in which an unmodulated learned carrier wave. In this loop, I and Q samples are taken and the phase angle of the sampled signal is calculated.

The calculated angle is subtracted from the previous phase and the result is low-pass filtered and sent as control word to the VCXO. The AGC is also calculated during the loop using the signal amplitude. At the end of the specified duration, the module places a 1 "in the status register 24, even if the phase deviations are smaller than a predetermined value, and if the deviations are still greater than this value, a" 2 "is placed in the status register 24. In the latter case, the frequency acquisition routine can be reactivated for more than one slot.

A bit synchronization routine is performed both in the subscriber station and base station modems, when the RCC is received and after completion of the frequency acquisition routine. In the subscriber status onmodem, its output signal will be used to synchronize the 16 kHz symbol clock pulse on the base station broadcast. In the base station modem, it is used to determine the fractional delay to be incorporated into the base station broadcast in order to achieve a coincidence with the base station modem clock pulse.

A slot receive routine is invoked when the modem is ready to receive data, i.e. after frequency and bit synchronization have been realized. Its main functions are (a) initializing parameters for the symbol receiving routine (described below); (b) activating the symbol receiving routine when the first symbol is sampled; and (c) determining the connection quality and other information upon receipt of all symbols in the slot.

This routine is called by the initialization routine at the start of each receipt key lock. Its most important function is to initialize the parameters for the symbol receiving routine. Upon completion of this task, she waits for all the samples of the first symbol in the slot to be stored in the FIFO stack 18 and then a branch to the symbol receiving routine takes place.

The processing tasks of this routine are:

1. reading the modulation level (ML of the control word register 31) in which ML can be 2, 4 or 16;

2. calculate the half symbol value given by the equation:

HS =

180

ML

O)

3. calculating a mask MASK that is used for truncating the LSBs of the decoded phase. The MASK depends on the ML and on the number of bits used to represent the decoded phase where as 2ⁿ represents a 22.5 degree phase angle then the following applies:

MASK = 8x2 for ML = 2

MASK = 12x2 for ML = 4 MASK = 15x2 for ML = 16

4. Previously reading the AGC for this slot from the AGC register 26 and transmitting it (only for the base station).

5. wait until the end of sampling the first symbol and then branch to the symbol receiving routine; and;

6. Upon receipt of all symbols in the slot, the transmission of the connection quality signal from the f5 connection quality register 25 to the CCU.

The symbol receiving routine is activated once per symbol duration while data is being received and its functions are: reading the I and Q samples for the symbol; (b) filtering the I and Q samples: (c) determining the transmitted symbol and sending it to the CCU; (d) outputting a phase lock loop to synchronize the VCXO on the incoming signal;

(e) executing a bit voice algorithm; (f) AG C calculation; and (g) accumulating information for the connection quality calculation.

The routine is activated once per symbol when all four samples relating to a symbol are stored in the external FIFO stack 18. This routine reads the samples in memory and then processes them to determine the transmitted symbol. The AGC is also calculated from the signal amplitude. The deviations in the received symbol from the transmitted symbol are used in the AGC, connection quality and bit tracking algorithms. The duration of this module is less than a symbol duration, that is 62.5 microseconds.

After receiving and storing the four I and Q samples for a given symbol, this routine performs the following tasks:

1. FIR filtering the samples received. The FIR coefficients are determined by the training routine discussed below;

2. determining the signal level and using it for the AGC;

3. determining the received phase angle, subtracting the preceding phase angle and rounding the result, Gray coding the rounded result and sending the coded result to the

CCU;

4. execute the bit voice algorithm. (Its output signal is accumulated for all symbols and transmitted at the end of the slot. It is used to synchronize the RX subscriber clock pulse on the basic transmission.);

5. performing a phase lock loop to synchronize the VCXO on the base station oscillator.

(The output signal is sent to the VCXO at the end of the slot, only in the subscriber station); and accumulating data for the connection quality and sending information to the CCU via the connection quality register 25 at the end of the slot.

Needed internal clock pulse signals in the modem are generated by the time and control signal generator 38 starting from the 80 MHz master clock pulse signal on the line 59. The modem uses the 16 kHz master clock pulse signal on the line 60 as the TX CLK for the broadcast. Therefore, all broadcasts by the base station are synchronous with each other.

The subscriber station clock pulse signals are derived entirely from an 80 MHz master VCXO in the time unit of the subscriber station. The VCXO is controlled by the VCXO FDBK signal on line 78 of the modem. All transmit and receive clock pulses are calculated from the VCXO FDBK signal on line 78. The time and control signal generator 38 then supplies the CCU with a 16 kHz RX CLK signal on line 63, derived from the incoming data stream. The CCU itself detects the unique word in the control channel and can determine frame and lock marks from the unique word and from the RX CLK signal on line 63. The AM STROBE signal on line 65 is derived from the sig by the time and control signal generator 38 signal demodulated by the microprocessor 17 and the CCU is informed where to look for the unique word.

In the subscriber station, the microprocessor 17 calculates the bit and frequency tracking parameters and adjusts the time relationships by outputting the VCXO FDBK and VCXO WR signals to the STIMU 49. To adjust the frequency, the microprocessor 17 outputs signals to a D / A converter in the VCXO interface 41 which supplies a voltage to the VCXO. This VCXO frequency is then divided by 5 to 16 MHz. The 16 MHz clock pulse is again divided by 5 to produce a 3.2 MHz clock pulse. The time and control signal generator 38 divides by 4 to produce the 800 kHz clock pulse signal required for the TX FIR filter 12. The sample time generator 42 divides a 3.2 MHz clock pulse signal by 50 to produce the 64 kHz sample clock pulse signal. The sampling time generator 42 is under the control of the microprocessor 17 to provide a trust aging during the steering channel acquisition. This allows large jumps of ± 16 kHz clock pulse periods for a fast acquisition.

The self-adjusting training mode is a feedback state in which the modem enters to train the digital FIR filter coefficients or the demodulator section stored in the microprocessor 17 as a correction for any analog filter degradations that may occur over time or as a result of temperature changes. The analysis is performed by feeding back transmission data via the RF unit and receiving a known pattern in the demodulator section of the modem. The coefficients are optimized about a Lagrange system with five determinations. These provisions are (1) the received data stream; (2) the data stream delayed by 0.05 T; (3) the data stream shifted forward by 0.05 T; (4) the data stream from the adjacent high-lying channel; and (5) the data stream from the adjacent lower channel.

During the training mode, the microprocessor 17 provides the FIR filter 12 of the modulator section with a series of 32 symbol-length training patterns on line 106 from the FIFO stack 36 that has been operated during the training mode. Shifts in the leading and slowing direction cause a skew between the two flows over 0.05 T.

The CCU places the modem in the training mode to allow the modulator section of the modem to read the special training pattern from the FIFO stack 36 by operating the training mode switch unit 11 via the control signal on line 107 of the control word register 31. The demodulator section also moves forward and shifted backwards for some tests. When the process is complete, the modem sends a status message to the CCU that the coefficients have been calculated. At that time, the CCU tests the modem by placing it in normal operating mode and issuing a setup pattern, instructing the RFU in the feedback situation, and reading the recurring data and testing for validity.

The learning mode is initiated by the CCU which sets the correct control register bits and transmits a MOD RESET signal on line 54 to the modem. This provides a reconfiguration of the microprocessor 17 to use 2 K of the ROM 45 and 2 K of the RAM 44 instead of 4 K ROM and no RAM. The 2 K ROM 45 contains the training mode algorithms and the 2 K RAM 44 provides the notepad memory when the filter coefficients are calculated.

An algorithm calculates the adjacent channel characteristics. To determine the adjacent channel interference, the modulator section of the modem must be able to transmit a frequency that is 25 kHz away from the received frequency. This is done because the CCU reads the status register in the modem. The information in the status register 24 is supplied to the CCU for changing the frequencies in the RFU receiver section as desired by the modem.

The microprocessor 17 performs the training routine. The function of the training routine is to calculate the FIR filter coefficients in the microprocessor 17. The modulator section is activated in the feedback mode to transmit a certain set of symbols. This sequence is transmitted to the demodulator section via the RFU in five different modes as follows: (1) normal mode; (2) forward time shift mode; (3) delayed time shift mode; (4 and 5) on the adjacent upper and lower channels. In the last two modes, the AGC setting is increased by 23 dB.

The demodulator section uses the samples on the incoming waveform to create a positive finite symmetrical matrix A of the order 28. Thus, a 28 word vector V is created from the input samples. The coefficient vector C is determined by:

C = A '¹ V (2)

An algorithm is used to determine B = A '¹ to be calculated for given A. Due to rounding errors, B will not be accurate, so an iterative method is used to calculate a more accurate C.

The calculation yields a vector of 28 complex FIR filter coefficients.

The modulator section is activated in training mode for transferring five similar sequence pairs. Each pair consists of the following two sequences: (a) an I sequence of 9 zero symbols, a "1" symbol and 22 zero symbols; and (b) a G sequence of 9 zero symbols, a "j" symbol and 22 zero symbols. The "1" can be any symbol. The j "is a symbol that differs from" 1 "by 90 degrees.

The processing tasks in the demodulator section are: (1) setting the AGC so that the signal peak in the normal mode is 50 to 70% of the maximum (the AGC is increased by 23 dB for the fourth and fifth modes); (2) reading and storing the input samples (the first 32 samples are disregarded and the following 64 samples are stored for each sequence): and (3) building the matrix A (28, 28). The following process is performed in normal mode (first mode):

A (1, J) = A (1, J) + Σ x (4N - 1) x (4N - J) (3)

The addition applies to all N that meet:

&lt;= 4N -1 &lt;64 and 0 &lt;= 4N - J &lt;64 (4)

For the forward and delayed modes (second and third modes), the same process is performed with the exception that the term resulting from N = 8 is not added. In the fourth and fifth modes (the transmission on the top and bottom adjacent channels) the following processes are performed:

A (1, J) = A (1, J) + Σ x (2N - I) x (2N - J) (5)

The addition applies to all N that meet:

&lt;= 2N -1 &lt;64 and 0 &lt;= 2N - J &lt;64 (6)

Further editing tasks of the demodulator section in training mode are:

4. Creating the vector V (1:28) from the samples of the first pair of sequences:

a. I {V (I)} = X (32 -1) (7) wherein X is the samples of the first (i) sequence; and

b. Q {V (I)} = X (32 -1) (8) wherein X is the samples of the second (Q) sequence; and

5. finding the coefficient vector C by resolving A x C - V = 0. This is done by first finding B that is equal to the inverse of A. Due to rounding errors, B will not be accurate. The following iterative method is used to find an accurate C.

C._O = W x V (9)

C._{n + 1}= C_n-bxB (AxC_n-V) (10) b is a predetermined value &lt;1.