Modem for telephone system

The present invention relates to a method for modulating a predetermined frequency in accordance with the information content of a digital input signal, the digital input signal representing a character stream which is polyphase shift keyed and then converted from digital form to analog form and finally analog mixed with the predetermined frequency , as well as an associated modem.

The embodiment shown in US Pat. No. 4,425,665 is a frequency modulated system rather than a phase modulated system. A sine synthesizer is required and the bandpass filters only serve to attenuate undesired sidebands.

US Pat. No. 4,253,067 proposes two separate circuits for the in-phase and quadrature-phase signals, each of these circuits being passed through a summing circuit to obtain a resulting output. This results in a not inconsiderable structure.

The same is true of U.S. Patents 3,204,029 and 4,253,067. According to U.S. Patent 4,481,640, the system splits the digital input signal into even and odd bit data streams, with each pair of even and odd bits forming a symbol. Furthermore, the patent specifications show that the resulting signal is phase-coded differentially twice, which is by no means necessary according to the invention. Also, in the known design, no symbols are transmitted, but the symbols are formed by signals in order to modulate a subcarrier by phase modulation. This phase-modulated subcarrier is then converted into a broadband signal and converted into an analog signal, which is then transmitted. Furthermore, the solution requires adapted low-pass filters and differentiators in order to form four signals.

In a method of the type mentioned, the polyphase shift keyed signal is broken down into an in-phase signal element and a quadrature-phase signal element, and these signal elements are converted from digital to analog form by a time-division multiplex process as a time-division multiplexed signal. Since the polyphase-shift keying-modulated signal is broken down first, there is no need to provide two separate filters for the in-phase signal element and the quadrature-phase signal element.

Further advantageous details of the method according to the invention are explained in the following description.

The present modem is provided with a transmitter unit, the digital input signal, which represents a character stream, being fed to the input of a digital phase shift keying modulator, the output of which is connected directly or indirectly to the input of an intermediate frequency mixer, the second input of which is connected to the output of a frequency generator .

According to the invention, the output of the phase shift keying modulator is connected to the input of at least one character memory, and the bit output of the highest order and the second highest order of the character memory is connected to the two inputs of a cycle-controlled switch whose output is connected to the highest order bit line and the other bit outputs of the Character memory connected to the lower order bit lines, these bit lines being connected directly or indirectly to the input of the digital-to-analog converter.

The transmitter part is a system for converting a bit stream, in which every given number of successive bits defines a symbol, into a phase-modulated intermediate frequency signal (IF) with a predetermined IF frequency. The modulator part phase modulates each symbol; digital filtering of each phase-modulated symbol provides a filtered signal which, when converted into an analog signal, provides a modulation signal with a modulation frequency that is averaged on a predetermined frequency and deviates therefrom in accordance with the value of the phase-modulated symbol, the filtered signal converts to an analog signal to provide the modulation signal; and mixing the modulation signal with a continuous signal having a predetermined frequency to provide a phase modulated IF signal which is a frequency modulated (FM) signal having an IF frequency that is the modulation product of frequency modulation with the predetermined frequency.

The demodulator part of the modem contains a demodulation system for converting a received phase-modulated IF signal into the bit stream from which the received phase2

AT 408 169 B modulated IF signal was derived.

The modem can work in transmission mode, in reception mode, in a time division multiplex transmission / reception mode or in training mode.

When working in transmission mode, the modulator part of the modem receives a binary digital bit stream of up to four bits per symbol and then converts the symbols into a phase-modulated IF signal with a specified IF frequency of 20.2 MHz. The modulated IF signal is transmitted to an RF unit for conversion to and transmission on the actual UHF frequency.

In the receiving mode, the modem receiving part receives a phase-modulated IF signal from an RF receiver unit. The modem filters and reduces the received IF signal to the baseband frequency and digitizes it into a complex (I, Q) sample with a given symbol rate of 16 Ksps (kilosymbols per second). A digital FIR filter carries out further filtering and the complex samples are converted into a binary digital bit stream. The binary bit stream is then output to a baseband unit.

The modem also performs functions for measuring symbol synchronization, connection quality and various controls and status reporting functions.

The modem can be put into training mode at certain times. In this operating mode, the modem modulator and demodulator part are connected via the RF unit via a loop in order to train the FIR filters of the demodulator part for changes in the system (mainly the RF filter units), which are related to temperature or aging damping the neighboring channel or other environmental fluctuations. The FIR filter of the demodulator part trains its coefficients to compensate for any filter deficiencies in order to achieve the best possible input signal. During the closing of the loop, the sender part! of the modem from a fixed training pattern that is known to the modem demodulator. The FIR filters of the demodulator part set (train) their coefficients according to the actual signal, delayed and leading signals, and signals from adjacent bands.

The modem is particularly useful in radio telephone systems such as that described in U.S. Patent 4,675863, filed March 20, 1985, issued June 23, 1987. The preferred embodiment of the modem described there is interposed between a channel control unit (CCU) and RF units, which are described in said patent specification, and the disclosure of the aforementioned patent specification is essential for this description and the content of this patent specification is incorporated into the present description by reference .

Additional features of the present invention will be discussed with reference to the description of a preferred embodiment.

Figures 1A and 1B together show a block diagram of the preferred embodiment of the modem according to the present invention.

FIG. 2 shows the signal constellation used in the Gray code, coding the symbols of a bit stream.

Figure 3 is a block diagram of the FIR filter in the modulator portion of the modem.

Figure 4 illustrates the response pattern of the multiple sampling pulses of the FIR digital filter in the modulator part of the modem.

Figure 5 is a block diagram of the SIN / COS IF generator in the demodulator portion of the modem.

Figure 6 shows the waveforms over time of certain control, clock and data signals that are involved in the operation of the modem.

GLOSSARY OF ACRONYMS

Glossary of acronyms used in the description

ACRONYM DEFINITION

A / D analog / digital converter

AGC automatic gain control

AM amplitude modulation

BPSK Binary phase-shifting key modulation

BS base station

CCU channel control unit

AT 408 169 Β

<td>THERE</td><td>Digital / analog converter</td>

<td>dB</td><td>decibel</td>

<td>DPSK</td><td>Differential phase shifting key modulation</td>

<td>ECL</td><td>Emitter-coupled logic</td>

<td>FCC</td><td>Unites States Federal Communications Commission</td>

<td>FIFO</td><td>First-in, first-out storage</td>

<td>FIR</td><td>Digital filter with a time-limited impulse response</td>

<td>Hz I.</td><td>Hertz (cycles per second) in phase</td>

<td>IF</td><td>Intermediate frequency</td>

<td>kHz</td><td>Kilohertz</td>

<td>Ksps</td><td>Kilo symbols per second</td>

<td>LSB</td><td>least significant bit</td>

<td>MHz</td><td>Megahertz</td>

<td>MODEM</td><td>Modulator and demodulator combined</td>

<td>OCXO</td><td>Thermostatically controlled crystal oscillator</td>

<td>Q</td><td>quadrature</td>

<td>QPSK</td><td>Quadrature phase rotating key modulation</td>

<td>R.A.M.</td><td>Random access storage</td>

<td>RCC</td><td>Radio control channel</td>

<td>RELP</td><td>remaining excited linear prediction</td>

<td>RF</td><td>High frequency</td>

<td>RFU</td><td>High frequency unit</td>

<td>ROME</td><td>Read-only memory</td>

<td>RX</td><td>Receive</td>

<td>STIMU</td><td>System clock unit</td>

<td>SUB</td><td>Subscriber station</td>

<td>TDMA</td><td>Multiple access time division</td>

<td>TX</td><td>Send</td>

<td>UHF</td><td>Ultra high frequency</td>

<td>VCXO</td><td>Voltage controlling crystal oscillator</td>

A preferred embodiment of the modem is shown in Figures 1A and 1B. The modulator part of the modem essentially contains a digital read-only memory (ROM) with digital phase-shifting conversion, i.e. phase shift keying modulator 10, a switch 11 for training operation, a digital filter stage (FIR) 12 with an impulse response of finite duration, a digital / analog converter ( D / A) 13, a bandpass filter 14 with a center frequency of 200 kHz, an intermediate frequency mixer 15 and an RF amplifier 16, tuned to 20.2 MHz.

The demodulator part of the modem essentially contains a digital microprocessor as phase shift key demodulator 17, model TMS 32010, a FIFO (first in first out) stack memory 18, an analog / digital converter (A / D) 19, an amplifier 20 and an intermediate frequency mixer 21 .

The modem also contains various clock generators and control units, which is essential for the modulation and demodulation function which are carried out by the modulator part and the demodulator part, respectively. These units contain interface registers and bus control units 23, a status register 24, a Q connection register 25, an AGC (automatic gain control) register 26, an RX frequency register 27, a partially delayed subscriber register (SUB) 28, an in-phase register (I) 29, a phase quadrature register (Q) 30, control unit 31 and a second partially delayed register 32. The modem timer and control unit further comprises a buffer control unit 34, a read / write decoder 35, a FIFO (first in first out) test pattern memory 36, a data acquisition memory 37, a frequency or frequency memory. Clock generator 38, a transmit clock delay unit 39, a partially delayed clock generator 40, a VCXO interface unit 41, a sampling time generator 42, a COS / SIN intermediate frequency generator 43, a 2K random access memory (RAM) 44, a 2K ROM 45, a 4K ROM 46, a buffer / damping unit and a buffer stage 48.

AT 408 169 B

The modem is connected to a system clock unit (STIMU) 49.

The modem interfaces are shown in Figures 1A and 1B. The modem receives most of its inputs from the CCU. Further inputs come from the RF unit and the clock units. The modem inputs are as follows:

To the modem from the channel control unit (CCU):

<td>TX data (line 50)</td><td>A 4-bit symbol to be transmitted by the modem (4 bits for 16 field PSK, 2 bits for the QPSK, 1 bit for BPSK)</td>

<td>MOD BUS (51)</td><td>A bi-directional microprocessor bus that provides control / status information to / from the modem.</td>

<td>MOD WR (line 52) MOD RD (line 53)</td><td>The control signal for locking the MOD BUS in the modem. The control signal to put the modem status and other information on the MOD BUS for transmission to the CCU.</td>

<td>MOD RESET (line 54) MOD ADD (line 55)</td><td>This CCU control resets the modem. Control signal to define different address memory locations and recorded sizes within the modem.</td>

<td>TX SOS (line 56)</td><td>Signal from the CCU to the modem at the beginning of the transmission of a TX slot.</td>

<td>RX SOS (line 57)</td><td>Signal from the CCU to the modem at the start of receiving an RX slot.</td>

To the modem from the RF unit (RFU):

IF RX (line 58) IF receive frequency input from the RFU

To the modem from the system clock unit (STIMU):

<td>80 MHz (line 59)</td><td>80 MHz ECL clock from the base station or the subscriber STIMUs. Output from the XO of the base station and the VCXP in the subscriber station.</td>

<td>16 kHz (line 60) SOMF (line 61)</td><td>TX CLK clock, used in the base station from STIMU. Start of the block in the base station from STIMU. Not used in the modem, but directed to the CCU</td>

From modem to channel control unit (CCU)

<td>TX CLK (line 62)</td><td>A 16 kHz clock signal that supplies the CCU with the symbol transmission timing. The symbols are clocked in the modem with the rising edge of this clock. In the base station all slots have the same TX CLK clock. Therefore, all signals from the base station are sent at the same time. In the subscriber station, the TX CLK is shifted by the subrange delay caused by the modem when information is fed from the CCU.</td>

<td>RX CLK (line 63)</td><td>The 16 kHz clock is derived from the received signal (always in the subscriber station, only during the acquisition of the control slot in the base station). This clock will blank the symbol received from the CCU and deliver the symbol time slot to the CCU.</td>

<td>RX DATA (line 64) MOD BUS (50) MOD SOMF (line 61) AM STROBE (line 65)</td><td>The received four-bit symbol, clocked by RX CLK. Status and data information from the modem Directed to SOMF / from the STIMU to the CCU in the base station. The conversion from high to low in this line gives the CCU an approximate frame marking during the acquisition of the radio frequency control channel (RCC) at the subscriber unit. This is a one-shot line that is pulsed when the RX TMS320 dies</td>

approximate position of the AM hole determined. From the modem to each RF unit (RFU):

<td>RF RX BUS (66)</td><td>8 bit bus between the modem and the RF RX unit. This bus sends AGC and frequency-selected information to the RFU of the receiving part. The modem controls the AGC values ​​to be sent, and also the CCU frequency selection information. The frequency selection information is transmitted to the modem via MOD BUS 50</td>

AT 408 169 B

RF TX BUS (67)

RX 80 MHz REF (line 59a) TX 80 MHz REF (line 59b) TX EN (line 68)

RX EN (line 69)

AGC WR (line 70) RXFREQ (WR) (line 71) RXFREQ RD (line 71a) PWR WR (line 72)

PWR RD (line 73) ZXFREQ RD (line 74)

TXFREQ WR (line 75)

IF TX (line 76)

AGC RD (line 77) supplied. During the training session, the modem controls the RF RX frequency selection.

Bit bus between the modem and the RFU transmitter part. This bus carries the TX power level and the frequency selection information to the modulator part. The modem has nothing to do with it, so the information is only directed to the RFU transmitter part. ECL 80 MHz reference clock to the RFU receiver.

ECL 80 MHz reference clock to the RFU transmitter part.

Line to the RFU transmitter part to enable the RF transmission. Line to the RFU receiver to enable RF reception. Write opening signal to lock the AGC data in the RFU receiving section

Write opening signal to write frequencies in the RFU receiving section.

Touch-up reading signal for reading back the received frequency from the receiving section.

Write activation signal for locking the power information in the RFU transmitter section.

Read push-button signal for reading back the power information from the RFU transmitter section.

Read push-button to read back the transmission frequency from the RFU transmission part.

Write frequency blanking signal, writes in the transmitter part. Transmitted signal on IF frequency to the RFU.

Read push-button to read back the AGC data from the RFU receiver.

From the modem to the system clock unit (STIMU):

VCXO FDBK (line 78) A 10-bit data bus to the VCXO with control information for frequency control.

VCXO WR (line 79) Write pulse to the VCXO holding circuit VCXO BUS in the VCXO:

The modulator part of the modem sends the information supplied to it on the TX data line 50 via the CCU with 16-level PSK modulation. The modem transmits without knowing the modulation level of the information received.

The input control lines are decoded within the modem in order to select which register has to put the 8 bit MOD BUS 50 between the modem and the CCU into operation. Control information regarding the receipt of a slot becomes active when the modem receives the RX SOS signal on line 57 from the CCU. This line interrupts the phase shift keying demodulator 17 to begin demodulation with an incoming slot. At this point in time, the RFU receiving section is enabled by the modem with the RX EN signal on line 69.

At the end of each slot, the status information of the register 23 for the reading CCU is brought up to date.

In the subscriber station, the CCU can cause the modem to detect the RCC signal from the base station. The main registration code of the RCC is the AM HOLE with 8 symbols. In the software, the modem queries the selected frequency for the AM HOLE via the CCU. The phase shift key demodulator 17 queries the selected frequency for the AM HOLE via the CCU. If there is an AM HOLE on this, the phase shift keying demodulator will lock onto it. After the phase shift key demodulator 17 is certain that an AM HOLE is present, it will pulse the AM STROBE line 65 to the CCU low, which means two things: (1) that the RCC signal is detected and (2) that the AM STROBE is an approximate start of the frame marker. From here on, the CCU begins looking for the only word in the RX data stream within a window of 0 to 3 symbols. When the single word is captured, the subscriber station's CCU can adjust its frames and slot counters to match the base station's frame.

The interface between the modem and the RFU receiving station allows control

AT 408 169 B of the frequency selection and the AGC level in the RFU. The CCU controls the frequency selection and sends its commands to the modem. The modem conveys this information to the RFU via the RX RF BUS 66. The bus 66 is therefore used to control the AGC level in the RFU receiving station. These AGC values ​​are updated every symbol time and sent to the RFU receiving section.

The CCU modem interface is shown in FIG. The timing for the transmitter interfaces is shown in FIG. These interfaces operate at low speed and therefore only require standard TTL hardware interfaces. The modem supplies the CCU with the 16 kHz symbol clock. Four TX DATA bits are on a parallel bus to the modulator part. An eight bit bus is provided for the exchange of control / status information. Control information is fed to the modem by the CCU via asynchronous interface registers 23. The contents of the registers become valid when the strobe signal TX SOS is received on the line 56 from the modem, which signifies the start of the transmission of a slot. The CCU provides the following control information to the modem: (1) idle operation; (2) send voice channels; (3) send control channel; (4) training operational loop; (5) TX CLK partial symbol delay; (6) RF TX power level; and (7) RF / TX frequency selection. The RX frequency selection is stored in the RX frequency register 27.

The CCU has a direct interface to the RF TX unit from the MOD bus 50 to the RF TX BUS 67 via the buffer control unit 34. The decoded addresses are fed to the RFU as written measuring marks in order to block the TX power and TX frequency information. The modem must have control of the RF RX in order to bring the AGC to the RFU up to date. Therefore the modem brings the RX frequency information from register 27 to the RF units at the beginning of each RX slot. This value is locked in register 27 by the CCU. In addition, the modem can change the RX frequency itself during the training session without the need for the CCU.

The modem modulator part is fully implemented in the hardware and does not require any adjustment. The symbols received by the CCU on the TX DATA line 50 are at a rate of 16K symbols / second. The received symbols are phase modulated by the DPSK converter ROM 10 and their resulting waveforms are shaped by the FIR filter to provide good interference characteristics and not suffer from amplitude or group delay distortion. The justification of this concept is based on the assumption that there are no strong interfering signals in the closely adjacent frequency band (within 50-100 kHz) to the band used (power density of 30-40 dB above the signal). The 200 kHz bandpass filter 14 provides a wide IF filtering (100 kHz) so that the transmitted signal does not suffer from amplitude or group delay distortion and also any harmonics generated by the digital filtering and D / A conversion and added to the baseband are filtered out .

The main filtering takes place at the baseband by a digital FIR filter stage 12. This filter stage 12 is a six-pole filter with a scanning speed of 50 samples per symbol per symbol duration in the FIR filter stage 12 in the modulator part.

Since no analog filtering is performed on the baseband, it is necessary to create two separate I and Q channels. In reality, the I and Q channels are integrated into the FIR filter stage 12. A multiplex channel, including the intermediate frequency mixer 15, which multiplies with the IF frequency, converts this channel to the IF. This channel inherently has equal gains for the I and Q samples. The I and Q sampling is now offset by half a sampling period, but this is corrected by the FIR filter.

The Gray code is used for digital coding by the phase conversion modulator 10. This ensures that if a symbol was received with an error, the likely greatest probability is that the error will only be one bit in a decoded symbol. The signal constellation is shown in FIG. The phases labeled Q and B are the QPSK and BPSK symbols, respectively.

The symbols are recorded as GRAY coded phase symbols. Any phase symbol is then converted to binary form from the GRAY code and added to the binary form of the last phase symbol to form the DPSK symbol. As a result of the FIR filter algorithm, each additional symbol is inverted before being entered in the digital FIR filter stage 12. Thus, the DPSK conversion is carried out through the use of the phase shift keying modulator 10.

AT 408 169 B

Four symbol bits, four bits from the previous symbol and one bit for the inversion control are input to the phase shift keying modulator 10, which outputs the DPSK symbol to the input of the FIR filter stage 12.

After the DPSK implementation, the symbol is then given to line 80 of the FIR filter stage 12, which is a six-stage, overloaded FIR filter. The FIR filter stage 12 comprises a ROM coefficient memory 81 and two three-stage four-bit latches 82, 83, as shown in FIG. The FIR filter stage 12 is used to shape the transmitted symbols in accordance with the specification of the frequency channel. The scanning speed of the ROM coefficient memory 81 is determined by a timing signal supplied via the line 84 from the frequency or clock generator 38 via a counter 85 which is connected to the ROM coefficient memory 81. An input clock signal is supplied via line 86 to two input switches 87, 88, which enables data to be input into shift register 82, 83.

Referring to Figure 4, each of the six symbols in the two buffers 82, 83 is scanned at a rate of 3/25 T (T01 / 16 kHz). This oversampling scheme reduces the samples so that only two symbols are sampled during every 1/25 T sampling period. Accordingly, two symbols enter the ROM coefficient memory 81 during every 1/25 T sampling period. Each 1/25 T sampling period is in turn divided into two parts: in-phase (I) and quadrature (Q). During the first half of the 1/25 T period, the latches 82, 83 receive the 3-bit in-phase component (I) of the symbol and during the second half of the period the quadrature component (Q) of the symbol is entered into the ROM coefficient memory. Therefore, the filter output on line 89 is the time-divided digital I and Q waveforms of the waveform to be transmitted. These samples are fed via lines 89 to the D / A converter 13 for conversion into an analog waveform. This waveform is then filtered by means of the bandpass filter 14 and fed via line 91 to the intermediate frequency mixer 15 for conversion into a 20 MHz IF signal via line 92.

The two buffers 82, 83 shift two of the stored symbols into the ROM coefficient memory 81 at a speed of 1/25 T for the required computational evaluations. The symbols are converted into 3-bit i and Q Gray code components by selecting either the fourth or third symbol bit as the most significant bit (MSB) of the three-bit component. The two least significant bits (LSBs) remain unchanged. This two-component selection is carried out at a speed of 1/50 T.

The ROM therefore requires five inputs from the counter 85 to designate which of the 25 sample periods is currently being calculated. An additional input from counter 85 is required to tell ROM coefficient memory 81 whether the 3 bit inputs are the I or Q components of the input symbols.

The output signals stored in the FIR ROM coefficient memory 81 are calculated to correct for any error that may occur due to the 1/50 T difference in the I and Q time values. Furthermore, the IF filter in the RFU adds the two values ​​together to form the correct transmitted waveform since its bandwidth is relatively narrow compared to the IF frequency. The FIR ROM coefficient memory 81 provides an output of 10 bit digital samples on line 89 at a frequency of 800 kHz.

ZERO symbols can be introduced into the digital FIR filter stage 12 in order to represent symbols without transmitter power. These are used in training operations to input a pulse into the digital FIR filter stage 12. These ZEROs can also be used to output AM HOLES and surveillance tapes that are required by the radio control channel (RCC).

The D / A converter 13 receives digital inputs from the digital FIR filter stage 12 and generates the required spectrum with multiples of 133.33 kHz, starting with 66.67 kHz.

The 200 kHz spectrum passes through the bandpass filter 14 with extremely small variations in the bandpass attenuation and the group delay. The attenuation ripple is less than 0.1 dB and the delay variation is less than 1.5 microseconds. The neighboring spectra are attenuated by more than 20 dB.

The desired signal from the D / A converter 13 is averaged over 200 kHz and has a bandwidth of approximately 32 kHz. This signal is band pass filtered by the pass band filter 14 before being mixed to remove the nx133 kHz signal components. By multiplying the

AT 408 169 B

200 kHz waveform at 20 MHz, the intermediate frequency mixer mixes the I and Q samples with the SIN and COS components of the IF frequency. Accordingly, the 20 MHz signal can directly multiply the output waveform and the exact component multiplication is done automatically. Therefore, there is no need for a discrete SIN (IF) / COS (IF) generator circuit to multiply the I / Q samples from the D / A as in the demodulator part. This also avoids a separate implementation of the baseband in the mixer to the output of the intermediate frequency mixer 15.

The buffer attenuator unit 47 receives an ECL level signal other than the IF frequency of 20.00 MHz on line 94 from the timing and control signal generator 38 and converts it to a peak-to-peak signal of 350 mV which is used as the local oscillator signal is supplied to the intermediate frequency mixer 15 via the line 95. Further voltage dividers (not shown) supply a +7.5 VDC bias voltage for the intermediate frequency mixer 15.

The intermediate frequency mixer 15 is an MC1496 active mixer. Its frequency translates the I and Q waveform on line 91 into a 20.20 MHz IF signal which is delivered on line 92 along with all other mixer products. Intermodulation products are more than 40 dB below this. The intermediate frequency mixer 15 operates at a high level at the carrier input and at a low level at the modulating signal input. This provides satisfactory switching performance of the dual differential amplifier of the carrier and linear operation of the modulating differential amplifier. A zero carrier is not emitted because the 20.00 MHz carrier is filtered out by a 20.20 MHz crystal filter in the RFU. A 470 ohm emitter negative feedback resistor (not shown) is provided to keep the modulation signal input at 1 volt peak for linear operation.

The RF amplifier contains an emitter train buffer stage to separate the tuned mixer circuit from the RF unit and to establish a 50 ohm output impedance. In order to eliminate the effects of stray capacitances, the output capacitance of the device and the capacitance of the emitter filter, which buffers the mixer input, are placed in a parallel resonant circuit at the mixer output, which can be tuned to maximum amplification. The total gain of the mixer must be 10 dB, since -10 dBm at 50 ohms are required at the output of the modem. A fixed coil, better than a variable one, can finally be used in the parallel resonant circuit of the intermediate frequency mixer 15. The RF amplifier 16 amplifies the signal on line 92 from the output of the mixer 15 and provides the amplified signal over the IF-TX line 76 to the RFU.

In the pause mode, the modulator part of the modem sends a base station an empty pattern issued by the CCU. Since the modem works in half-duplex mode, the CCU in the subscriber station sets all the slots in the subscriber station to the receiving state, with the exception of the slot in which the subscriber station itself transmits. This allows the demodulator part of the modem to monitor the subscriber station to the AGC so that it is not too surprised when a burst comes in from the base station. Pause operation is used when there is a frequency for which at least one, but not all, of the slots are used. The empty slots are filled with the empty pattern. If a frequency is not conducting any calls at all, the modulator part can be switched off.

Returning to the demodulator portion of the modem, the intermediate frequency mixer 21 has an input impedance of 50 ohms for the 20.00 MHz, -30 dBm signal received from the RFU on the IF-RX line 58. The basic function of the intermediate frequency mixer 21 is to reduce the IF signal from the RFU to the baseband and also to amplify it by 30 to 35 dB. A continuous signal at 20.00 MHz is applied to line 22. The continuous signal on line 22 is the time-division multiplexed SIN / COS / -SIN / -COS signal from the COS / SIN intermediate frequency generator 43. An active mixer, module MC 1496, with the local oscillator signal via line 22 at a high level, and the modulated A low level signal is applied via line 58. The baseband mixer output on line 97 is AC differential coupled to amplifier 20 which is a differential amplifier. A high-pass filter is formed by a coupling capacitor on the intermediate frequency mixer 21 and by the input resistance of the differential amplifier 20 and has a cutoff frequency of approximately 1 Hz.

The buffer stage 48 provides an interface between the ECL level of the 20.00 MHz generator 43 and the intermediate frequency mixer 21. The buffer unit provides a 350 mV peak-to-peak

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Signal to bring the carrier input into the saturated switching range and also provides a VDC bias voltage of 7.5 VDC for this input.

The SIN / COS intermediate frequency generator 43 is shown in FIG. The intermediate frequency generator 43 contains ECL parts which process the guided IF frequency at four times, corresponding to a 4 IF timing signal on line 98 from the timing and control signal generator 38. Referring to Figure 5, two 90 ° phase shifters 99, 100 operate as a divider with four counters, each of their outputs being 90 ° out of phase. A quadruple multiplexer (MUX) 101 switches between the SIN, COS, -SIN, -COS outputs. The output of the MUX 101 is clocked again by a D flop 102 and is output to the intermediate frequency mixer 21 via the line 103. This circuit provides a perfect 90 degree phase shift between the four components. The single time division multiplex channel also ensures that the I and Q components arrive with exactly the same gain.

The timing diagram for the demodulator part is shown in FIG. The modem supplies the CCU with the four data bits and their 16 kHz symbol clock. The address lines and an 8-bit bus ensure status / control exchange between the two units.

The amplifier 20 takes the differential output from the mixer and amplifies it by approximately 25 dB. The amplifier 20 provides an AC coupled ± 10 volts peak-to-peak signal to the A / D converter 19 with very little distortion.

The A / D converter 19, which is a TRW 12 bit A / D converter, is used to convert the baseband spectrum from the differential amplifier 20 into digital data for processing in the phase shift keying demodulator 17. The sampling rate is four times per symbol (64 kHz).

In normal operation, the digital processing is carried out by the TMS320 phase shift key demodulator 17. The phase shift key demodulator 17 operates at 20 MHz with 4K bytes of the memory from the 4K ROM 46. The address input pins are used to address the I / Q registers between the demodulator part and the CCU or the special diversity combiner circuit.

The phase shift keying demodulator 17 receives the I / Q data from the intermediate frequency mixer 21 at a sampling frequency of 64 kHz. The data are again time-multiplexed over a frequency channel, as was done with the modulator part. The phase shift keying demodulator 17 performs filtering and demodulation of the waveform. The phase shift key demodulator 17 then outputs the received symbol via the bus 104 to the data collector 37, which forwards the symbol to the CCU via the RX-DATA line 64, with a pulse of the RX CLK signal on line 63 and a frequency of 16 kHz.

The receiver state is placed in the state register 24 and the I / Q samples are placed in the I register 29 and the Q register 30. The CCU can read the status while the I / Q samples are requested for an external diversity combiner circuit. The control / status interfaces and functions are described below.

The operation of the base station modem is linked to a fixed RF frequency. The connection at the base station is full duplex. Accordingly, the modem modulator and demodulator work simultaneously. If the modem is also destined to be the control frequency channel modem, it will only send and receive information in the radio control channel (RCC) format during the allocated slot control period. In the base station, an OCXO is located in the timing control unit (STIMU) 49 of the system and operates as a clock. Accordingly, there will be no frequency deviation when receiving.

All transmissions from the modem of the base station are clocked by the clock signal TX CLK (16 kHz) via line 60. The part-time delay generator 40 in the modem of the base station supplies the CCU of the base station with a fraction of the symbol time between the clock signal on line 60 and the derived RX CLK signal! on line 63 in the modem. This information is then sent to the subscriber unit over the radio control channel so that the subscriber will delay its transmission so that its signal is received at the base station in synchronism with all other slots.

All processes in the modem of the subscriber station are derived from the received clock signal (RX CLK), which is recovered from the received transmission by the frequency or clock generator 38. This serves as a clock generator for the subscriber station. The TX CLK signal on line 62 from the transmitter clock delay circuit 39 to the CCU is not a clock as in the base 10

AT 408 1 69 Β

Station. It is derived from the RX CLK signal on line 63 and delayed by the transmit clock delay circuit 39. The duration of such a delay is determined by the CCU of the subscriber station, partial delay register (SUB) 28, and is retrieved therefrom by the transmit clock delay circuit 39. The CCU of the subscriber station receives the delay over the radio control channel from the CCU of the base station. The delay is determined by the distance between the base and the subscriber station. The CCU of the subscriber station feeds this part-time information into the partial delay register (SUB) 28 in the modem via the MOD BUS 50. The modem itself records the partial delay via the transmit clock delay circuit 39. The CCU books the entire symbol delay by receiving the TX SOS signal over line 56 to the modem delayed by the correct number of symbols. This procedure frees all signals arriving at the base station from changes in the area of ​​all subscriber stations.

There are many sources of delay in the modem system that have a significant impact on the timing system. Such include analog filter delays, propagation delays, FIR filter stage 12 processing delays, and so on. These delays shift the TX and RX frames mutually and these shifts must be factored into a careful calculation.

The delay paths from the modulator part to the demodulator part are listed below with their estimated values.

Tta TX analog delay. Approximately 55T.

Ttr Transfer delay between TX and RX in the RF unit. Approximately 1.9T.

Td propagation delay. 1.2T max. (One way).

Tra RX analog delay. Approximately 5.77T.

Th time during the sampling of the RX analog filter output before the A / D conversion. Approximately 0.03T.

Tc A / D conversion time. Approximately 0.22 T.

Tf1, Tf2 RX FIR window. To receive a peak at time t = 0, the filter must begin sampling at t = -Tf1 and continue until Tf1 is approximately 3.5T, Tf2 is approximately 3.25T.

To TMS processing delay between peak and TMS output. Approximately 4.5 T.

Tw TX waveform length (6T).

Tcrt compensation delay between RX and TX (subscriber); minimum for the most distant participant and maximum for the closest one.

SBn Closest participant.

SBf Farthest participant.

The delay between TX SOS in the base station and the first received analog symbol peak at the base station is +7.4 symbols. Therefore there is a shift between TX and RX slots. In order to correctly decode the incoming phase, the modem must begin scanning approximately 3.5 symbols before the tip arrives. Therefore, the offset between TX SOS / and the start of the RX scan is about four symbols long.

In the base station, the start of the RX slot occurs approximately 4 T after the start of the TX slot. The start of the RX slot is defined as the time at which the first analog sample is taken in order to detect the first peak that is received.

The modem of the most distant subscriber station starts its TX slot 4 T before the start of the RX slot of the modem of the base station. Other participants must delay the start of their TX slots.

Transmission delays of 0 to 3 times the symbol length may occur anywhere in the entire RF telephone subscriber system due to the distance there and back. Therefore, in order for the received message to become synchronous in the base station, the subscriber station must be able to shift its transmission clock in relation to the received derived clock (RX CLK) by 0 to 3 times the symbol time. The time delays are calculated in the base station and sent over the control channel and interpreted by the CCU. The CCU then supplies the partial delay constants to the modem of the subscriber station in order to delay the TX CLK. The partial delay is an 8-bit value that is written into the partial delay register (SUB) 28

AT 408 169 Β becomes. The full delay symbol is controlled by the CCU. The sampling signal TX SOS on line 56 is generated delayed by 0, 1 or 2 symbols, according to the range values ​​received from the base station.

While receiving a slot, the modem performs frequency synchronization by recording and then synchronizing. In the subscriber station, the VCXO is under the direct control of the phase shift key demodulator 17 via a D / A converter in the VCOX interface 41.

The phase shift key demodulator 17 uses frequency recording and synchronization algorithms to calculate the changes necessary in the VCXO in order to maintain synchronization.

During the reception of any slot, the microprocessor also carries out the bit synchronization of the bit synchronization characters of the received data stream. An algorithm creates a bit synchronization control loop. The phase shift key demodulator 17 has control over a variable frequency divider of the 80 MHz VCXO or OCXO (only during the control of the slot demodulation). Within the bit synchronization control loop, the microprocessor 17 modifies the frequency division in order to achieve bit synchronization. During the reception of a speech channel, the divider values ​​have font sizes of 0.1% of 16 kHz, whereas a control slot can change the values ​​much more drastically, as much as +/- 50%.

The frame synchronization is carried out in the base station and in the subscriber station in completely different ways. In the base station, a SOMF 8 (start of the modem block) main signal is sent via the modem on line 61 to the CCU. This is the main SOMF signal used for all transmissions from the base station. From this and the symbol clock signal (16 kHz) on line 60, the CCU can derive the entire timing of all slots and blocks.

In the subscriber station, the phase shift key demodulator 17 searches for the AM HOLE in the RCC during the beginning of the acquisition. When the AM HOLE is found, the phase shift keying demodulator 17 will count a few frames and cause the timing and control generator 38 to deliver the AM STROBE / flag over line 65 to the CCU in the frame memory location for the AM HOLE. The CCU uses this marker to build up (channel) the start frame marker counter, which can be modified by the CCU software for exact frame synchronization. This also means that the AM HOLE was detected and the RCC is occupied.

The slot synchronization is under the control of the CCU. The signals TX SOS on line 56 and RX SOS on line 57 are commands to the frequency or clock generator 38 to begin sending or receiving a slot. These signals are synchronized with the TX CLK signal on line 62 and the signal RX CLK on line 63, respectively.

The modem demodulator part works either in independent (off-line) mode or in dependent (on-line) mode, according to bit 7 of the RX control word in control word register 31. To switch the demodulator part from one operating mode to the other, the CCU sends MOD RESET, writes the required command into the RX control word register 31 via the MOD BUS 50 and then switches off the MOD RESET signal.

In off-line operation, the external memory of the microprocessor is supplied with 2K words from the ROM and 2K words from the RAM. The CCU controls the entry of this operating mode after switching on and once every specified number of hours during which the modem does not send or receive in order to carry out self-tests and training programs.

The self-test program tests the ROM 45, 46, the internal RAM and the external RAM 44 and the interface to the CCU. It sends the test results to the CCU via the status register 24.

The training program includes sending a training signal to the demodulator part and calculating the coefficients of the FIR filter contained in the phase shift keying demodulator 17. This is done off-line every predetermined number of hours while the modem is neither sending nor receiving data.

In on-line operation, the modem receives signals from either a control channel or a voice slot, corresponding to the RX part control word in control word register 31. The on-line software executes the following programs.

A preparatory program is from the phase shift key demodulator 17 when switching on or

AT 408 169 B executed after a received reset signal. This program reads the control word in register 31 and calls up further programs according to the control word.

This program is activated when the CCU sends the modem a MOD RESET signal via line 54 and a command via MOD BUS 50 to the control register in order to enter on-line operation. This program carries out a sum test on an on-line PROM, introduces parameters, reads the control word in word register 31 and jumps into the appropriate program.

A frequency acquisition program runs in the modem of the subscriber station only when a control channel is received in order to synchronize the VCXO frequency in the subscriber station with the crystal frequency in the base station. Since the transmission, reception and intermediate frequencies are derived from the VCXO in the subscriber station or from the OCXO in the base station, this will cause all frequencies to be synchronized.

This program is only used in the modem of the subscriber station. It is activated by a command from the CCU while the demodulator part is set to the control channel frequency. Its job is to synchronize the VCXO frequency with that of the OCXO in the base station. It does this by first looking for the AM hole, which is a short period of time during which there is no transmission from the base station. The base station then sends an unmodulated carrier signal. Upon receipt of this waveform, the mixer output will have a different sine waveform, the frequency of which is proportional to the difference between the VCXO and the base station crystal oscillator frequency. The modem software scans the I and Q channels at certain intervals and performs a phase lock loop function, ie it determines the phase difference for each interval, sends it through a low-pass filter and sends it to the VCXO as a correction word. The modem determines that frequency acquisition is complete when the phase difference is below a certain level. If the AM hole is not detected during a certain period of time, the module sends an error message to the CCU indicating that the receiver is not tuned to the control channel .

The program is called by the preparation program and sends a status word from the status register 24 to the CCU, which indicates whether a frequency detection has taken place or not.

When called by the preparation program, the frequency acquisition program scans the I and Q channels, looking for the I and Q channels and at the same time forming an AGC loop. If the AM fetch is not detected for a predetermined number of scans, this program sends this information via status register 24 to the CCU. The CCU will then switch to another possible frequency and reactivate the frequency acquisition program.

After determining the AM hole, this program provides a phase lock loop for the time during which an unmodulated carrier is being transmitted. In this loop, I and Q are sampled and the phase angle of the sampled signals is calculated.

The calculated angle is subtracted from the previous phase and the result is low-pass filtered and sent to the VCXO as a control word. The AGC is also calculated during the loop using the signal amplitude. At the end of the prescribed period, when the phase deviations are less than a predetermined amount, the module inserts 1 into the status register 24 and if the deviations are still greater than this amount, a 2 is inserted into the status register. In the latter case the frequency acquisition program can be reactivated for more than one slot.

A bit synchronization program runs both in the modem of the subscriber station and in that of the base station when the RCC is received and after the frequency detection program has been completed. In the modem of the subscriber station, its output is used to synchronize the 16 kHz symbol clock with the transmission from the base station. In the modem of the base station it is used to determine the partial delay that is contained in the transmission of the subscriber station in order to bring about a coincidence with the clock of the modem of the base station.

A slot receiving program is called when the modem is ready to receive data, ie after frequency and bit synchronization have been completed. Its main functions are (a) to introduce the parameters for the symbol receiving program (described below); (b) activate the symbol receiving program when the first symbol is scanned; and

AT 408 169 B (c) to determine the quality of the connection and further information after receiving all symbols in the slot.

This program is called by the preparation program at the beginning of each receiving slot. Its main function is to introduce the parameters for the symbol reception program. After completing this process, it waits until all samples of the first symbol in the slot are stored in the FIFO stack 18 and then jumps to the symbol receiving program.

The procedural steps of this program are:

1. Reading out the modulation level (ML from the control word register 31, where ML can be 2, 4 or 16);

2. Calculation of half the symbol value given by the equation:

180

HS = —— (Equation 1)

ML

3rd Calculation of a MASK to separate the LSB from the decoded phase. The MASK depends on the ML and the number of bits used to represent the decoded phase, where if 2ⁿ represent a phase angle of 22.5 °, then MASK = 8 x 2ⁿ for ML = 2 = 12x2ⁿfor ML = 4 = 15x2ⁿ for ML = 16

4th Previous reading of the AGC for this slot from the AGC register and sending it out (only for the base station).

5. Waiting for the first symbol to finish scanning and then jumping to the symbol receiving program; and

6th After all symbols in the slot have been received, the connection quality signal is sent from the connection quality register 25 to the CCU.

The symbol reception program is activated solely by the symbol time during data reception and its functions include: (a) reading out the I and Q samples for the symbol; (b) filtering the I and Q samples; (c) Determination of the symbols transmitted and their transmission to the CCU; (d) forming a phase lock loop to synchronize the VCXO with the incoming signal; (e) formation of a bit sequence algorithm; (f) AGC calculation; and (g) collecting the information for the calculation of the link quality.

The program is only activated by the symbol if all four samples belonging to a symbol are stored in the external FIFO stack 18. This program reads the samples in memory and processes them to determine the transmitted symbol. The AGC is also calculated from the signal amplitude. The deviations in the received symbol from the transmitted one are used in the AGC, the connection quality and the bit sequence algorithm. The runtime of this module is less than a symbol time, ie 62.5 microseconds.

After receiving and storing the four I and Q samples for a single symbol, this program does the following:

1. FIR filtering of the received samples. (The FIR coefficients are determined by the training program below);

2. Determination of the signal level and its use for the AGC;

3rd Determination of the received phase angle, subtraction of the previous one, rounding of the result, Gray coding of the rounded result and transmission of the encoded result to the CCU;

4th Execution of the bit sequence algorithm. (Its output is collected for all symbols and sent at the end of the slot. It is used to synchronize the subscriber's RX clock with the basic transmission.)

5. Formation of a phase lock loop in order to synchronize the VCXO with the oscillator of the base station (the output is sent to the VCXO at the end of the slot, only in the subscriber station); Collection of the data for the connection quality and transmission of the information via the connection quality register 25 at the end of the slot to the CCU.

Internal clock signals required by the modem are generated by the frequency or clock generator 38 from the 80 MHz clock signal on line 59. The modem uses the 16 kHz clock signal

AT 408 169 B

Line 60 as well as the TC CLK for transmission. Therefore, all transmissions from the base station are synchronized with each other.

The clock signals of the subscriber station are entirely derived from an 80 MHz clock generator in the subscriber time control unit. The VCXO is controlled by the VCXO FDBK signal on line 78 of the modem. All transmit and receive clocks are calculated from the VCXO FDBK signal on line 78. The timing control signal generator 38 then supplies the CCU with the 16 kHz RX CLK signal on line 63, derived from the incoming data stream. The CCU itself detects the single word in the control channel and can determine frames and slot markers from the single word and the RX CLK signal on line 63. The AM STROBE signal on line 65 is derived by the frequency or clock generator 38 from the signal demodulated by the phase shift keying demodulator 17 and informs the CCU where to look for the single word.

In the subscriber station, the phase shift keying demodulator 17 calculates the bit and frequency sequence parameters and controls the timing by outputting the VCXO FDBK and VCXO WR signals to the STIMU 49. In order to adjust the frequency, the output of the phase shift keying demodulator 17 is sent to a D / A converter in the VCXO interface 41, which supplies the voltage to the VCXO. This VCXO frequency is then divided by five to 16 MHz. The 16 MHz clock is again divided by 5 to produce a 3.2 MHz clock. The timing and control signal generator 38 divides this by 4 to generate the 800 kHz clock signal required for the TX FIR filter 12. The sample timing generator 42 divides a 3.2 MHz clock signal by 50 to generate the 64 kHz sample clock signal. The sampling timing generator 42 is under the control of the phase shift keying demodulator 17 to introduce a delay during channel acquisition. This enables the clock period to make large jumps of ± 16 kHz for fast detection.

The self-adaptive training mode is a feedback loop condition which instructs the modem to correct in the demodulator part the coefficients of the digital FIR filter stored in the phase shift keying demodulator 17 in the event of any analog filter drift occurring with time or temperature. The analysis is done by inserting the transmitter data backwards via the RF unit and receiving a known pattern in the demodulator part of the modem. The coefficients are optimized using a Lagrange system based on 5 constraints. These constraints are (1) the received data stream; (2) the data stream delayed by 0.05T; (3) the data stream advanced by 0.05 T; (4) the data stream of the adjacent upper channel; and (5) the data stream of the adjacent lower channel.

During the training operation, the phase shift keying demodulator 17 supplies the FIR filter stage 12 of the modulator part with a series of 32 symbol-length training patterns on line 106 from the FIFO stack 36, which is released during the training operation. Leading and decelerating twist the two currents by 0.05 T.

The CCU puts the modem in the training mode in order to enable the modulator part to read the special training pattern from the FIFO stack 36 by actuating the training mode switch unit 11 by a control signal on the line 107 from the control word register 31. The demodulator part is also advanced and then delayed for some tests.

When the process is complete, the modem sends a status message to the CCU that the coefficients have been calculated. At this point the CCU tests the modem by putting it into normal operation and writing out a pattern set that commands the RFU to switch back and read the reset data and the validity test.

The training operation is initiated by the CCU by setting suitable control register bits and sending a MOD RESET signal over line 54 to the modem. The phase shift key demodulator 17 calculates this again by using 4K of the ROM and no RAM until 2K from ROM 45 and 2K from RAM 44 are used. The 2K ROM 45 maintains the training operation algorithm and the 2K RAM 44 supplies the scratch pad memory while the filter coefficients are being calculated.

An algorithm calculates the characteristics of the neighboring channel. In order to determine the adjacent channel interference, the modulator part of the modem must be able to transmit on a frequency which is 25 kHz away from the frequency received. This is done by the CCU reading out the status register of the modem. The information in the status register 24

AT 408 169 Β determines the CCU to change the frequencies in the receiving part of the RFU after the command of the modem.

The phase shift key demodulator 17 executes the training program. The function of the training program is to calculate the filter coefficients of the FIR filter stage in the phase shift key demodulator 17. The modulator part is caused to send a certain sequence of symbols in a loop-back operation. This sequence is transmitted to the modulator part via the RFU in five different ways as follows: (1) normal operation; (2) advanced timing operation; (3) delayed time-out operation; and (4 and 5) to the higher and lower channel. In the latter two operating modes, the AGC is set, increased by 23 dB.

The demodulator part uses the samples of the input waveform to create a positively defined A-matrix 28, order. In addition, a 28 word vector is created from the input samples. The coefficient vector C is given by

C = A '¹V (equation 2).

Around B = A '¹ for a given A, an algorithm is used. As a result of the rounding off, B will not be accurate, so an iterative method is used to compute a more accurate C.

The calculation provides a vector with 28 complex FIR filter coefficients.

The modulator part is caused in the training mode to transmit five pairs of sequences of the same type. Each pair consists of the following two sequences: (a) an I sequence of 9 null symbols, one 1 symbol, and 22 null symbols; and (b) a Q sequence with 9 null symbols, one j symbol, and 22 null symbols. The 1 can be any symbol. The j is a symbol that is 90 degrees different from 1.

The process steps of the demodulator part are: (1) to regulate the AGC so that the signal peak in normal operation is 50 to 70% of the maximum (in modes 4 and 5 the AGC is increased by 23 dB); (2) read and store the input samples (the first 32 samples are discarded and the next 64 samples are stored for each sequence); and (3) building the A matrix (28, 28). The following process is carried out in normal operation (first operating mode):

Α (I, J) = Α (l, J) + X (4N -1) X (4N - J) (equation 3).

The addition applies to all N that satisfy:

&lt;= 4N -1 &lt;64 and 0 &lt;= 4N - J &lt;64 (equation 4)

The same procedure is carried out for the leading and delayed modes (second and third modes), except that the term that results for N = 8 is not added. In the fourth and fifth operating mode (transmission to adjacent higher and lower channels) the following procedure is carried out:

Α (I, J) = Α (I, J) + X (2N -1) X (2N - J) equation 5)

The addition applies to all N that satisfy:

&lt;= 2N -1 &lt;64 and 0 &lt;= 2N - J &lt;64 (equation 6).

Further process steps of the demodulator part in the training company are:

4th Creation of the vector V (1:28) from the samples of the first pair of sequences;

a) I (V (i)} = X (32-I), where X samples from the first (I)

Result are; and (equation 7)

b) Q {V (I)} = X (32-I); where X are samples from the second (Equation 8) (Q) sequence; and

5. Finding the vector C by solving A x CV = 0. This is done by first finding B, the inverse of A. Because of the rounding errors, B will not be accurate. That

AT 408 169 B the following iteration method is used to solve an exact C: C_O = BXV (equation 9)

C._n+ i = C_n - bx B (A x C_n - V) (equation 10) b is a predetermined value &lt;1.