Modem for telephone system

Description: TECHNICAL FIELD [Detailed description of the invention]

[Background of invention] The present invention relates generally to communication systems, especially to modems that convert bitstreams into phase-modulated intermediate frequency (IF) signals for RF subscriber telephone systems.

[Outline of Invention] The modem of the present invention has a modulation unit and a demodulation unit. A modulation unit is a system that converts a bit stream that defines one symbol in each of a predetermined number of pairs of bits that are continuous with each other into a phase-modulated IF signal of a predetermined intermediate frequency (IF). The modulation unit 1) phase-modulates each symbol, and 2) digitally filters each phase-modulated symbol to convert it into a filter wave output signal, that is, an analog signal. A filter wave output signal that produces a modulated signal having a modulation frequency that shifts according to the value of the modulation symbol is generated, 3) the filtered wave output signal is converted into an analog signal to generate the modulated signal, and 4) the modulated signal. Is mixed with a stationary signal of a predetermined frequency to produce a phase modulated IF signal, that is, a phase modulated IF signal which is a frequency modulated (FM) signal having an IF frequency which is the result of modulation between the modulated frequency and the predetermined frequency. The demodulation unit of the modem has a demodulation system that converts the received phase-modulated IF signal into the bit stream on which the phase-modulated IF signal is based. The modem of the present invention can operate in transmit mode, receive mode, time division multiplexing transmit / receive mode, or training mode. When operating in transmit mode, the modem's modulator receives a digital binary bitstream of up to 4 bits per symbol and converts these symbols into a phase-modulated IF signal with a given IF frequency of 20.2 MHz. This modulated IF signal is sent to the RF unit, up-converted to an appropriate UHF frequency, and transmitted. When operating in receive mode, the demodulator of the modem receives a phase-modulated IF signal from the RF receiver unit. The modem filters this received IF signal, downconverts it to the basehand frequency, and digitizes the signal into complex (I, Q) codewords at a given symbol speed of 16 Ksps. This digitized complex codeword is further filtered by an FIR filter and converted into a digital binary bit stream. This binary bit stream is output to the baseband device. The modem also has the ability to provide symbol synchronization, link quality measurement and various control and status reporting functions. The modem can be set to adjustment mode at regular time intervals, eg, every few hours. In this tuning mode, the modulator and demodulator of the modem are in a system (mainly RF unit filters) that changes with temperature or aging, adjacent channel attenuation, or other environmental changes. It is looped back via the RF unit to adjust the FIR filter of the demodulation section for the purpose of adapting to various changes. The FIR filter in the demodulator adjusts its coefficients and offsets all filter misalignment to achieve the best input signal state. During this loopback, the modem's transmitter outputs a known fixed adjustment pattern to the modem's demodulator. The FIR filter of this demodulator adjusts its coefficient according to the signal itself, the delay signal and the lead signal, and the signal from the adjacent band. The modem of the present invention is for performing multiple voice and / or data signal communication simultaneously by a single or multiple channels by Japanese Patent Application No. 61-39331 (Japanese Unexamined Patent Publication No. 61-218197) by the applicant of the present application on the same date as the present application. It is particularly useful in the radiotelephone system described in "Subscriber RF Telephone System". A preferred embodiment of the modem described herein is inserted between the channel control unit and the (CCU) and RF unit described in the patent application, and the description of the patent application relevant herein is here. And incorporate it into this specification. Other features of the invention will be described below in connection with preferred embodiments. The meanings of the symbols used in the present specification are as follows. A / D analog-to-digital converter AGC automatic gain adjustment AM amplitude modulation BPSK 2-Phase PSK (Phase Shift Keying Modulation) BS base station CCU channel control unit D / A digital-to-analog converter DPSK differential PSK ECL Emitter-coupled logic FCC Federal Communications Commission FIFO first-in first-out storage device FIR Finite time impulse response I homeomorph Ksps kilo symbol / sec LSB least significant bit OCXO constant temperature bath control crystal oscillator Q Quadrature phase QPSK 4-layer PSK RAM random access storage RCC wireless control channel RELP Residual Excitation Linear Prediction RF radio frequency RFU radio frequency unit (wireless communication device) ROM fixed storage device RX reception STIMU System Timing Unit SUB subscriber station TDMA time division multiple access TX transmission VCXO Voltage Control Crystal Transmitter Preferred embodiments of the modem of the present invention are shown in FIGS. 1A and 1B. The modulator of this modem is a fixed storage device (ROM) 10 for differential PSK (DPSK) modulation conversion, an adjustment mode switching unit 11, a FIR digital filter 12, a digital-to-analog converter (D / A) 13, and a center frequency of 200 KHz. The main components are a band filter 14, a mixer 15, and an RF amplifier 16 with a center frequency of 20.2 MHz. The demodulator of this modem includes a TMS32010 microprocessor 17, a FIFO stack memory 18, an A / D 19, an amplifier 20, and a mixer 21. The modem also has several timing and control units that are absolutely necessary for the modulation and demodulation functions performed by the modulation and demodulation units, respectively. These units include a state register 24, a link Q register 25, an AGC register 26, an RX frequency register 27, a subscriber minute delay register (SUB) 28, an in-phase (I) register 29, an orthogonal phase (Q) register 30, and a control unit. The interface register / bus controller 23, which includes 31 and a second minute delay register (BS) 32, is first included. The timing and control units also include a buffer control unit 34, a read / write decoder 35, an adjustment pattern FIFO stack 36, a data latch 37, an internal timing signal and control signal generator 38, a transmit clock delay unit 39, and a minute delay generation. Instrument 40, VCXO interface unit 41, sample time generator 42, COS / SIN IF signal generator 43, 2K random access storage (RAM) 44, 2K ROM45, 4K ROM46, buffer / attenuator unit 47, and buffer unit. 48 is included. The modem is also connected to System Timing Unit (STIMU) 49. The modem interface is shown in Figures 1A and 1B. Most of the input to this modem comes from the CCU. There are also inputs from RF units and timing devices. The input to the modem is as follows. From channel control unit (CCU) to modem TX DATA (Line 50): A symbol sequence of 4-bit symbols that the modem should send (4 bits for 16-ary PSK, 2 bits for QPSK, 1 bit for BPSK). MOD BUS (51): A bidirectional microprocessor bus that provides control / state information to and from the modem. MOD WR (Line 52): A control signal that latches the MOD BUS to the modem. MOD RD (line 53): A control signal sent to the MOD BUS to transfer modem status and other information to the CCU. MOD RESET (line 54): This CCU control line resets the modem. MOD ADD (Line 55): A control signal that defines various address positions and latched values within the modem. TX SOS (line 56): A signal from the CCU to the modem that initiates transmission of the TX slot. RX SOS (line 57): A signal from the CCU to the modem that initiates reception of the RX slot. From RF unit (RFU) to modem IF RX (line 58): Received IF frequency input from RFU. From system timing unit (STIMU) to modem 80 MHz (Line 59): 80 MHz ECL clock from the base station or subscriber STIMU. This is the output of XO at the base station and VCXO at the subscriber station. 16KHz (Line 60): Base station master TX CLK supplied by STIMU. SOMF (Line 61): Base station master frame start signal supplied by STIMU. It is sent to the CCU without being used by the modem. From modem to channel control unit (CCU) TX CLK (Line 62): A 16KHz signal that gives the CCU symbol transmission timing. The symbol synchronizes with the in-modem clock at the front edge of this signal. In the base station, all slots are the same master TX Has CLK. As a result, all the signals from the base station are transmitted at the same time. At the subscriber station, TX CLK is offset by a small distance delay from the modem based on the information from the CCU. RX CLK (line 63): The 16KHz clock is extracted from the received signal (always at the subscriber station, only when the control slot is captured at the base station). This clock clocks out the received symbol to the CCU and gives the CCU symbol timing. RX DATA (line 64): A 4-bit receive symbol clocked by RX CLK. MOD BUS (51): Status and data information from the modem. MOD SOMF (Line 61): Transfer SOMF from STIMU to the CCU in the base station. AM STROBE (Line 65): A change from high to low levels on this line becomes a coarse frame marker to the CCU during radio control channel (RCC) capture in the subscriber equipment. This is a one-shot line that is activated when the RX TMS 320 determines the approximate position of AM HOLE (note that AM). HOLE is the period of zero output for the first 16 symbols of RCC transmission from the base station, as described below). From modem to each RF unit (RFU) RF RX BUS (66): An 8-bit bus between the modem and the RF RX unit. This bus transmits AGC and frequency selection information to the RFU receiver. The modem controls the AGC value to be sent and transfers the CCU frequency selection information. Frequency selection information is supplied to the modem through MOD BUS 51. During the tuning mode, the modem controls the selection of RF RX frequencies. RF TX BUS (67): 8-bit bus between the modem and the RFU transmitter. This bus transmits TX power level and frequency selection information to the modulator. The modem has nothing to do with this information, and this information is simply transmitted to the RFU transmitter. RX 80MHz REF (line 59a): ECL 80MHz reference clock to the RFU receiver. RX 80MHz REF (line 59b): ECL 80MHz reference clock to the RFU transmitter. TX EN (Line 68): A line to the RFU transmitter to enable RF transmission. RX EN (line 69): A line to the RFU receiver to enable RF reception. AGC WR (Line 70): A write strobe for latching AGC data to the RFU receiver. RXFREQ WR (line 71): Write strobe for frequency writing to the RFU receiver. RXFREQ RD (line 71a): A read strobe for reading the receive frequency from the RFU receiver. PWR WR (Line 72): A write strobe for latching power information to the RFU transmitter. PWR RD (Line 73): A read strobe for reading power information from the RFU transmitter. TXFREQ RD (line 74): A read strobe for reading the transmit frequency from the RFU transmitter. TXFREQ WR (line 75): Write strobe for frequency writing to the RFU transmitter. IF TX (line 76): A signal transmitted to the RFU whose frequency is the IF frequency. AGC RD (line 77): A read strobe for reading AGC data from the RFU receiver. From modem to system timing unit (STIMU) VCXO FDBK (Line 78): 10-bit data bus to VCXO containing control information for frequency tracking. VCXO WR (line 79): A write pulse to the VCXO circuit that latches the VCXO BUS to the VCXO. The modulator of the modem transmits the symbol sequence supplied from the CCU via the TX DATA line 50 with 16-level PSK modulation. In this transmission, the modem does not sense the modulation level of the symbol sequence, i.e. the number of PSK phases. The input control line is decoded in the modem to select which register drives the 8-bit MOD BUS 51 between the modem and the CCU. When the modem receives the RX SOS signal on line 57 from the CCU, the control signal for slot reception is enabled. This line interrupts microprocessor 17 to initiate demodulation of incoming slots. At this point the RFU receiver is enabled by the RX EN signal from line 69. At the end of each slot, the state information is updated in register 23 to prepare for CCU reading. At the subscriber station, the CCU can issue a command to the modem to capture the RCC signal from the base station. The main capture feature of the RCC signal is AM HOLE, which is eight symbols long. The software causes the modem to scan the CCU's selected frequency for AM HOLE. That is, the microprocessor 17 scans the frequency selected by the CCU to search for AM HOLE. If AM HOLE is present at that frequency, microprocessor 17 will key in to it. After the microprocessor 17 confirms the existence of AM HOLE, it indicates to the CCU that () the RCC signal has been captured, and (2) AM STOROBE is approximately at the frame marker start point. From this point on, when a subscriber station CCU finds a unique word in the RX data stream in a window with a length of 0 to 3 symbols, it adjusts its frame counter and slot counter to base station them. Can be fitted to the system frame of. The interface between the modem and the RFU receiver allows frequency selection and AGC level control in the RFU. The CCU controls frequency selection and sends CCU commands to the modem. The modem sends this information to the RFU via the RX RF BUS 66. This bus 66 is also used to control the AGC level at the RFU receiver. These AGC values are updated for each symbol period and transmitted to the RFU receiver. The CCU modem interface is shown in Figures 1A and 1B. The timing diagram of the transmission interface is shown in Fig. 6. These interfaces are slow, so standard TTL hardware interfaces will suffice. The modem supplies the CCU with a 16KHz symbol clock. An 8-bit bus is provided for sending and receiving control information / status information. Control information is supplied from the CCU to the modem via the asynchronous interface register 23. The contents of these registers are the strobe TX on line 56. It is activated when the SOS signal is received by the modem and indicates the start of slot transfer. The CCU gives the modem the following control information: (1) hibernate mode, (2) transmit audio channel, (3) transmit control channel, (4) adjustment mode loopback, (5) TX CLK minute symbol delay, (6) ) RF / TX power level, and (7) RF / TX frequency selection. The RF frequency selection is stored in the RX frequency register 27. The CCU has a direct interface with the RF TX device from MOD BUS 51 through the buffer controller 34 to RF TX BUS 67. The decoded address is supplied to the RFU as a write strobe for latching TX power and TX frequency information. The modem must be able to control the RF RX bus 66 for AGC updates to RFU. Therefore, the modem transmits RF frequency information from register 27 to the RF unit at the start of each RX slot. This value is latched in register 27 by the CCU. Also, the modem can change the RF frequency itself during the tuning mode without the intervention of the CCU. The modulator of the modem is entirely composed of hardware and does not require any adjustment. A series of parallel 4-bit PSK symbols is fed from the CCU to TX DATA line 50 at a rate of 16K symbols per second. These symbols are DPSK converted with Gray coding by the DPSK conversion ROM 10, and the resulting waveform is shaped by the FIR filter 12 to obtain a waveform with excellent interference characteristics without harmful amplitude distortion or group delay distortion. To. Waveform shaping is performed by the FIR filter 12 on the assumption that there is no strong interference signal (power density is 30 to 40 dB or more of the signal) in the nearby frequency band (within the range of 50 to 100 KHz) close to the used band. (Ensuring interference resistance and amplitude / group delay strain resistance). The band filter 14 with a center frequency of 200 KHz performs wideband IF filter processing (100 KHz) so that the transmitted signal is not subjected to amplitude distortion or group delay distortion, and all harmonics associated with digital filter processing and D / A conversion in the baseband. Remove the waves. The digital filtering process is performed in the baseband with a fixed coefficient FIR digital filter 12. FIR filters are advantageous in facilitating the design of filters with accurate linear phase characteristics. In particular, in voice data processing and voice data transmission, a linear phase filter is required to suppress harmful frequency dispersion caused by non-linear phase, and the FIR filter is most suitable for this application. This FIR filter 12 samples each of the six consecutive symbols in the above 4-bit symbol symbol series at a rate of 50 times per symbol period T (1/16 KHz = 62.5 microseconds) as described later. This is a 6-symbol length oversampling FIR filter that produces a sequence of symbol sample values and adds the products obtained by multiplying those symbol sample values and the filter coefficients corresponding to those sample values to each other to produce a filter output. As is well known, the output Y of a 6-symbol length digital filter is obtained based on one symbol at the present time and five symbols preceding it. That is, the filter coefficients that are different from each other are h_ig, X the 6 symbol sample values corresponding to those filter coefficients_iExpressed in, the filter output sample value Y corresponding to each symbol sample value_iIs Y_i= X_ih_{o o}+ X_i-1h₁+ ... + X_i-5h₅ ...... (Equation a) Given in. Therefore, the above filter output sample value Y_iOne calculation must be done with six individual multiplications and the addition of the results of those multiplications. Moreover, since it is necessary to set a large number of symbol sample values for each symbol in order to utilize the oversampling, the calculation amount of this calculation becomes remarkably large, which hinders the miniaturization of the FIR digital filter and the reduction of manufacturing cost. In particular, it is an obstacle to miniaturization and cost reduction of base stations and subscriber stations that employ the modem of the present invention. Therefore, the FIR filter 12 in the present invention is configured so that the above calculation can be equivalently achieved by a very simple circuit. That is, using the approximate linearity of the FIR filter based on the finite symbol length operation, the above 6 symbol lengths are divided into two parts, the first half and the second half. X_ih_j+ X_i-3h_k ...... (Equation b) Is configured to equivalently obtain the output of the above equation (a) by repeating. Referring to FIG. 3, the FIR filter 12 passes through the first and second three-stage parallel 4-bit shift registers 82 and 83 arranged in series with each other and a series of 4-bit parallel symbol length T symbols via line 80. The first switch 87, which receives one of a pair of parallel four fixed contacts and connects the parallel four movable contacts to the first stage of the first shift register 82, and the final stage of the shift register 82, that is, the third stage. A second switch 88 in which the output is received by one of the parallel 4-piece fixed contacts and the parallel 4-piece movable contact is connected to the first stage of the second shift register 83, and the above fixed filter coefficient is stored in advance and a symbol described later. ROM81, which outputs the multiplication result of sample values and their filter coefficients, and four parallel outputs of each of the three register stages of shift registers 82 and 83, two directly and the other two I / The parallel output line set leading to the input of the ROM 81 via the Q component selector switch, and the filter coefficient stored in the ROM 81 in advance by receiving the timing signal and the timing signal from the control signal generator 38 (Fig. 1A) via the line 84. Is provided with an address counter 85 that enables multiplication with the symbol values from the read shift registers 82 and 83 at the timing described later. The movable contacts of the first and second switches 87 and 88 are interlocked to the upper fixed contact in the figure for each period T by the shift register drive pulse of period T supplied via line 86, thereby the period and time. The input symbols of width T are stored in the shift register 82 one by one, and the stored symbols are shifted to the right toward FIG. 3 (however, from the last stage of the shift register 82 to the first stage of the shift register 83). Let me. In this way, the six symbols stored in the register stages of shift registers 82 and 83, respectively, stay in those register stages for period T, respectively, and the next incoming symbol shifts one stage to the right toward the drawing, respectively. It will be updated symbol by symbol. On the other hand, as described above, the parallel output line sets of each of the three register stages of the shift register 82 are connected to the three input terminal sets on the input side of the ROM 81, and the ROM 81 is a set unit of these input terminal sets. The symbol sample values can be fetched one after another inside the ROM81 by scanning (that is, sampling) with. Similarly, each parallel output line set of the three register stages of the shift register 83 is also connected to each of the three input terminal sets different from the above on the input side of the ROM 81, and the ROM 81 is a set unit of these input terminal sets. The symbol sample values can be sequentially taken into the ROM81 by scanning with. Figure 3 shows only the parallel output line set between the final stages of each of the shift registers 82 and 83 and the ROM 81 for the sake of brevity. As described above, each of the symbols of the symbol series taken into the shift register 82 from the line 80 is Gray-encoded in the DPSK conversion ROM 10. That is, the output symbol sequence of the DPSK conversion ROM 10 keeps the Hamming distance between adjacent codes at 1 bit, and as is well known, even if there is an error in symbol transmission, the error can be suppressed to 1 bit. .. With reference to Fig. 2, the correspondence between the phase angle of the 16-level DPSK and the 4-bit codeword in the above Gray coding is the IQ that divides the in-phase (I) component axis I and the quadrature (Q) component axis Q. It is shown on the plane. In this IQ plane, the phase angle indicated by Q is the phase that the DPSK symbol can take in QPSK, and the phase angle indicated by B is the phase that the BPSK symbol can take. In Gray coding, a pair of points (1) and (1') that are symmetrical with each other on both sides of the Q axis as the axis of symmetry have the same Q coordinate value Q.₁Have. Similarly, a pair of points (1') and (2') that are symmetrical with each other on both sides of the I axis as the axis of symmetry have the same I coordinate value I.₂Have. The code values 0001 and 0101 corresponding to the above points (1) and (1') are equal to each other except for the second most significant bit. Therefore, when only the Q coordinate value of the point (1) or (1') is to be calculated, the second-order bit may be ignored and the other 3 bits may be extracted. Similarly, the code values 0101 and 1101 corresponding to points (1') and (2') are equal to each other except for the most significant bit. Therefore, when only the I coordinate value of the point (1') or (2') is to be calculated, the most significant bit can be ignored and the other 3 bits can be extracted. Utilizing this property of the Gray code, this embodiment simplifies the above operation and achieves the same channel operation of the I component / Q component. That is, each of the parallel output line sets that guides the output of each of the three register stages of the shift registers 82 and 83 to the ROM 81 is a parallel output line set between each of the shift registers 82 and 83 and the ROM 81 in FIG. As shown in, it includes an I / Q selector switch that selects the output line corresponding to the 2nd and most significant bits, and when the movable contact is at the position shown in Fig. 3, the Q coordinate value is taken into ROM81 and is movable. The I coordinate value is taken into ROM81 with the contact switched to the fixed contact at the bottom of the figure (note that the two output lines corresponding to the lower 2 bits are directly connected to ROM81). These I / Q changeover switches are switched in response to the timing pulse from the output line IQ at the right end toward the figure of the six output lines of the counter 85 described later. The reading of ROM81 and the acquisition of symbol sample values by scanning the output lines of the shift registers 82 and 83 synchronized with it are the 5-bit outputs of the address counter 85, that is, the addresses in ROM81 that can define different addresses of 25 (&lt;32). It is controlled by the output. That is, as shown in FIG. 4, the three symbols stored in the first shift register 82 and the three symbols stored in the second shift register 83 are placed in six register stages over the period T, respectively. While staying, the above scan of these shift register output lines by ROM81 is a sampling pulse with a pulse width of 1 / 25T, h in Figure 4.₀(For shift register 83, h₂₅, Same below), h₁₇(h₄₂), H₉(h₃₄), H₁(h₂₆), H₁₈(h₄₃), H₁₀(h₃₅), ... h₂₄(h₄₉), H₁₆(h₄₁), H₈(h₃₃), ..., and the corresponding filter coefficient stored in advance from ROM81 in synchronization with the scanning, that is, sampling (h in Fig. 4).₀, H₁, ... h₄₉Is a schematic representation of the analog corresponding values of those filter coefficients). That is, the three symbols stored in the first, second, and final stages of the shift registers 82 and 83 over the period T, respectively, are between these two registers 82 and 83, as shown in FIG. It is sampled in ROM81 while maintaining a synchronous relationship with, and in synchronization with this sampling, the filter coefficient stored in advance in ROM81 is read out and the two are multiplied. Sampling of the above three shift register storage symbol values by ROM81 (sampling pulse width is 1 / 25T as described above) actually consists of the first half (width 1 / 50T) and the second half (width 1 / 50T), and in the first half. Is the I component value, and in the latter half, the filter coefficient corresponding to the Q component value is read in ROM81 and multiplied by the symbol sample value of the corresponding time width. The I / Q switching corresponding to the first half and the second half is performed by the output pulse IQ at the right end of the address counter 85. That is, the sampling I / Q switching is performed in synchronization with the switching operation of the I / Q selector switch of the outputs of the shift registers 82 and 83. As described above, the import of the symbol sample value from the six register stages of the shift registers 82 and 83 into the ROM81 and the reading and multiplication of the corresponding filter coefficient in the ROM81 synchronized with this are performed by using two symbols each. It is divided into two shift registers 82 and 83, and the synchronization relationship between these shift registers is maintained and the period is 1 / 50T. That is, the multiplication of the parallel 3-bit symbol sample value from one register stage of the shift register 82 and the read corresponding filter coefficient, and the parallel 3-bit symbol sample value read from the corresponding register stage of the shift register 83 are read. The multiplication synchronized with the above multiplication with the corresponding filter coefficient is performed in parallel with a 1 / 50T period. Therefore, the two multiplications in the above equation (b) are performed with the pair of corresponding register stages of the shift registers 82 and 83 and the ROM 81. Can be achieved by the combination of. The two multiplications of equation (b) are performed at the same time, and the sum of the multiplication results, that is, the output representing the operation result of equation (b) is output from ROM81 in the form of parallel 10-bit digital data. The result of this operation only includes the multiplication 2 term of Eq. (B), but since the shift registers 82 and 83 have three pairs of register stages, every one cycle of the above sampling of the symbol values in these three pairs of register stages The multiplication 6 term is obtained by the equation (b), and the operation of the equation (a) can be achieved equivalently by the approximate linearity based on the finite symbol length operation of the FIR filter. As described above, the repetition frequency of this calculation result, that is, the parallel 10-bit digital data output of the ROM 81 is 800 KHz (16 KHz x 50). If the ROM 81 has a sufficiently large storage capacity and a sufficiently high operating speed in the embodiment of FIG. 3, it corresponds to all possible values of the parallel 3-bit symbol sample values supplied from each of the shift registers 82 and 83. Digital data representing the product of the filter coefficient of is stored in ROM81 in advance, and the corresponding stored digital data is read out using the pair of parallel 3-bit symbol sample values as the read address of ROM81 to be used as the parallel 10-bit digital data. You can also do it. The digital output from the FIR filter 12, that is, the digital data string from the ROM 81, is converted into an analog signal at the D / A 13. The digital data string performs the above calculation in ROM81, that is, the multiplication of the I component and the Q component and each corresponding filter coefficient for each width 1 / 50T and the addition of the multiplication results, so that the I component data and the Q component data are equalized for a long time. Including. Since the analog filter wave processing in the baseband is not performed as described above, it is not necessary to provide a separate signal path for the processing of the I component and the Q component, that is, both the I component and the Q component are simply from the FIR filter 12 to the mixer 15. It is processed with one signal path, that is, the same signal gain. The output signal from the D / A13 has a center frequency of 200 KHz and a bandwidth of about 32 KHz. This signal traverses the band filter 14, ie 200 KHz spectrum, with extremely small passband attenuation (attenuation ripple less than 0.1 dB) and group delay change (less than 1.5 microseconds) to remove the nx133 KHz mixture before mixing. The band is filtered by the band filter 14 passed through. By multiplying the output of 200 KHz from the D / A13 and the IF frequency of 20 MHz, the mixer 15 includes the alternately included I and Q components in the modulated output of the IF frequency of 20 MHz. In this way, the I component and the Q component are used as the modulated signal components for the 20 MHz IF signal via a common path to each other. Therefore, it does not require a separate SIN (IF) / COS (IF) generator to multiply the I / Q sample from the D / A as in the demodulation section below. This also eliminates the need for isolation within the mixer 15 from baseband to the output of the mixer 15. A NULL symbol can be injected into the FIR filter 12 to represent a symbol that does not involve transmission power. These symbols are used to input an "impulse" to the FIR filter 12 in adjustment mode. These NULLs are also used to output the AM HOLES and guard bands required by the Radio Control Channel (RCC). The buffer dampener 47 receives the ECL level signal differentially at the 20.00 MHz intermediate frequency of line 94 from the timing and control signal generator 38 and supplies this signal to line 95 to mixer 15 for local oscillation. Convert to a 350 mV peak / peak value signal as a signal. Another voltage divider (not shown) provides a + 7.5 VDC bias to the mixer 15. Mixer 15 is the MC 1496 Active Mixer. This mixer frequency-converts the I and Q component waveforms from line 91 into a 20.20 MHz IF signal, the IF signal supplied to line 92 along with all other mixer outputs. The third-order intermodulation product is attenuated by more than 40 dB. The mixer 15 operates at a high level for carrier input ports and at a low level for modulated signal input ports. This results in saturated switching operation of the carrier dual differential amplifier and linear operation of the modulated differential amplifier. The 20.00MHz carrier is removed by the 20.20MHz crystal filter in the RFU, so no carrier powerless output nulls occur. The current source is set to supply a current of 2mA. A 470 ohm emitter degenerate resistor (not shown) is provided to maintain the modulated signal input within a linear operating range of 1 volt peak. The RF amplifier 16 has an emitter follower buffer to avoid interference between the mixer tuning circuit and the RF unit and to provide an output impedance of 50 ohms. A parallel tuning circuit that can be tuned to the maximum gain is used for the mixer output to eliminate the negative effects of stray capacitance, device output capacitance, and emitter follower capacitance that weakens the mixer input. The total gain of the mixer should be 10 dB, as the output of the modem requires -10 dB at 50 ohms. Fixed inductors can be used in the mixer output tank circuit instead of variable inductors. The RF amplifier 16 amplifies the line 92 signal from the output of the mixer 15, and supplies the amplified signal to the RFU through the IF-TX line 76. During hibernation mode, the modulator of the base station modem transfers the hibernation pattern given by the CCU. At the subscriber station, the modem performs half-duplex transmission, so the CCU sets the modem to receive mode during all slot periods except the slot period during which the subscriber station itself is transmitting. This enables the demodulator of the subscriber station modem to monitor the AGC and prevent it from being hit unexpectedly by a burst signal from the base station. Hibernate mode is used when there is a frequency in which at least one slot is used instead of all slots. Empty slots are filled with a dormant pattern. If the frequency is not converted at all, the modulator becomes unused. With reference to the demodulator of the modem, the mixer 21 exhibits an input impedance of 50 ohms for the 20.00MHz-30dB signal received from the RFU on the IF-RX line 58. The basic function of the mixer 21 is to down-convert the IF signal from the RFU to the baseband and amplify it by 30 to 35 dB. A stationary signal is supplied to line 22 at 20.00 MHz. This stationary signal on line 22 is a time-multiplexed SIN / COS / -SIN / -COS signal from the COS / SIN IF generator 43. The model MC 1496 active mixer 21 uses the local oscillator input signal to line 22 at high level and the modulated signal to line 58 at low level. The mixer output of line 97 in the baseband is AC-coupled differentially to amplifier 20, which is a differential amplifier. A high-frequency filter is formed by the capacitive coupling from the mixer 21 and the input resistor of the differential amplifier 20, and the cutoff frequency of this high-frequency filter is about 1 Hz. The buffer device 48 forms an interface between the ECL level 20.00 MHz generator 43 and the mixer 21. The buffer device 48 provides a 350 mV peak peak value signal to pull the carrier input into saturation switching and biases this input by + 7.5 VDC. The IF SIN / COS generator 43 is shown in Figure 5. The generator 43 has an ECL component that operates at four times the tracked IF frequency in response to the timing signal and the 4IF timing signal of line 98 from the control signal generator 38. Referring to FIG. 5, the two flip-flops 99 and 100 act as quadrant counters, and their outputs are 90 degrees out of phase with each other. The 4X1 multiplexer (MUX) 101 switches between SIN, COS, -SIN, and -COS outputs. The output of MUX101 is reclocked by another D flip-flop 102 and output to line 103 to mixer 21. This circuit provides an exact 90 degree phase shift between the four components. This single time-multiplexed channel ensures that the I and Q components are input with exactly equal gain. The timing diagram of the demodulation unit is shown in Fig. 6. The modem sends the CCU four data bits per symbol and a 16KHz symbol clock. The address line and 8-bit bus perform state / control switching between the two devices. Amplifier 20 accepts the differential output from the mixer and amplifies it by about 25 dB. The amplifier 20 supplies an AC-coupled ± 10 volt peak peak value signal to the A / D converter 19 with almost no distortion. The TRW 12-bit A / D converter, A / D19, converts the baseband spectrum from the differential amplifier 20 into digital data for processing by the microprocessor 17. The sample speed is 4 times per symbol (64KHz). During normal operation, digital processing is performed by the TMS 320 microprocessor 17. The microprocessor 17 operates at 20 MHz using the 4K byte memory configured by the 4K ROM 46. Port address pins are used to address the I / O registers between the demodulator and the CCU or special diversity combiner circuitry. The microprocessor 17 receives I / Q data from the mixer 21 at a sampling rate of 64 KHz. This I / Q data is time-multiplexed to one frequency channel as in the processing in the modulator. The microprocessor 17 performs waveform filtering and demodulation processing. The microprocessor 17 then outputs the received symbol to the data latch 37 by bus 104, which data latch 37 to the CCU via the RX DATA line 64 with a pulse of the RX CLK signal on line 63 at a speed of 16 KHz. Send the lever symbol. The receiver status is stored in status register 24, and the I / Q sample is stored in I register 29 and Q register 30. The CCU will read the state if an I / Q sample is needed for the external diversity combiner circuit. The control / state interface and its functions are described below. Base station modem operations are assigned to fixed RF frequencies. Communication at a base station is full-duplex transmission. Therefore, the modulator and demodulator of the modem are operating at the same time. If the modem is also assigned to a control frequency channel, it will only send and receive RCC-formatted information during the allocation control slot period. At the base station, the OCXO at STIMU 49 is fixed and acts as the master clock for the system. Therefore, there is no frequency shift during reception. All transmissions from the base station modem are timed by the master TX CLK (16KHz) signals on lines 60 and 62. The micro-delay generator 40 in the base station modem gives the base station CCU a fractional part of the symbol time between it and the master TX CLK on line 60. This information is then given to the subscriber device via a radio control channel to delay transmission from the subscriber station so that the subscriber station signal is received synchronously at the base station to all other slots. Is sent to. All operations in the subscriber station modem are extracted from the received transmission content from the timing signal and the received clock (RX CLK) signal recovered by the control signal generator 38. This signal acts as the master clock of the subscriber station. The TX CLK signal on line 62 from the transmit clock delay circuit 39 to the CCU is not the master clock as in a base station. This signal is delayed by the transmit clock delay circuit 39 extracted from the RX CLK signal on line 63. The duration of such a delay is supplied by the subscriber station's CCU, the minute delay (SUB) register 28, and is read from this register 28 by the transmit clock delay circuit 39. The subscriber station CCU receives this delay from the base station CCU via the radio control channel. This delay is determined by the distance between the base station and the subscriber station. The subscriber station CCU supplies this minute time information to the minute delay (SUB) register 28 in the modem through the MOD BUS 50. The modem itself captures this minute delay via the transmit clock delay circuit 39. The CCU handles integer symbol delays by inserting the TX SOS signal on line 56 into a modem that is delayed by the exact number of symbols. This process synchronizes incoming signals from all subscriber stations at different distances to the base station. There are many sources of delay within a modem system, which can significantly affect the timing of the system. These delay sources include analog filter delay, propagation delay, processing delay of FIR filter 12, and the like. These delays skew the TX and RX frames from each other and must be carefully considered. The delay path from the modulation section to the demodulation section is shown below with its estimated delay value. Tta: TX analog delay. About 0.55T Ttr: Transmission delay between TX and RX in the RF unit. About 1.9T Td: Propagation delay. Maximum 1.2T (one way) Tra: RX analog delay. About 5.77T Th: Time during sampling of RX analog filter output before A / D conversion. About 0.03T Tc: A / D conversion time. About 0.22T Tf₁, Tf₂: RX FIR Window. The filter receives t = -Tf to receive the peak at time t = 0₁Sampling process is started at Tf₁(Approximately 3.5T), Tf₂Must last up to (about 3.25T). To: Processing delay between peak and TMS output. About 4.5T Tw: TX waveform length 6T Tcrt: Compensation delay between RX and TX (subscriber), minimum for farthest subscriber station, maximum for closest subscriber station. SBn: Recent subscribers station. SBf: Farthest subscriber station. The delay time between the TX SOS in the base station and the first received analog symbol "peak" in the base station is +7.4 symbols. Therefore, there is a skew between the TX slot and the RX slot. In order to correctly decode the incoming phase, the modem must start sampling about 3.5 symbol lengths before the arrival of the "peak". Therefore, the skew between the TX SOS and the starting point of RX sampling is about 4 symbols long. In a base station, the start of the RX slot occurs about 4T after the start of the TX slot. The point at which the first analog sample is captured to detect the first "peak" received is defined as the starting point of the RX slot. The modem of the farthest subscriber station starts its TX slot 4T before the start of the RX slot of the base station modem. Other subscriber stations can delay the start of that TX slot. Looking at the entire subscriber RF telephone system, distance-induced round-trip transmission delays occur at various values in the 0-3 symbol length range. Therefore, in order to synchronize the received call at the base station, the subscriber station must be able to shift its transmission clock by 0 to 3 symbol times with respect to the extraction reception clock (RX CLK). The time delay is calculated at the base station, sent by the control channel and decoded by the CCU. The CCU assigns a minute delay constant to the subscriber station's modem to delay TX CLK. The minute delay is an 8-bit value written to the minute delay (SUB) register 28. The integer symbol delay is controlled by the CCU. The strobe TXSOS signal on line 56 is delayed by 0, 1, or 2 symbol lengths according to the distance value received from the base station. When receiving any slot, the modem performs frequency synchronization by capturing the slot and keeps track of it. At the subscriber station, the VCXO is under the direct control of the microprocessor 17 via the D / A in the VCXO interface 41. The frequency capture and tracking algorithm of microprocessor 17 calculates the VCXO changes required to maintain synchronization. When receiving any slot, the microprocessor 17 performs bit synchronization on the bit synchronization pattern of the received data stream. The algorithm forms a bit tracking loop. Microprocessor 17 has control over the variable frequency divider of 80MHz VCXO or OCXO (only during control slot demodulation). Inside the bit tracking loop, microprocessor 17 modifies frequency division to achieve bit synchronization. When receiving an audio channel, the frequency division value has a step size of 0.1% at 16KHz, but when in the control slot, the frequency division value can be changed significantly to about +/- 50%. Frame synchronization is handled in a completely different way between the base station and the subscriber station. At the base station, the master SOMF (modem frame start) signal is transferred via the modem to line 61 to the CCU. This is the master SOMF signal used for all transmissions from the base station. From this signal and the line 60 master system symbol clock signal (16KHz), the CCU can derive all slot and frame timings. During the initial capture, in the subscriber station, microprocessor 17 searches for AM HOLE in the RCC. When AM HOLE is detected, microprocessor 17 counts AM HOLE for a few frames and puts the AM STROBE / marker on the timing and control signal generator 38 to line 65 to the CCU at the AM HOLE frame position. Supply. The CCU uses this strobe marker to set up an initial frame marker counter that can be modified by the CCU software for accurate frame synchronization (windowing). This is also AM Indicates that HOLE was detected and RCC was captured. Slot synchronization is under the control of the CCU. The signal TX SOS on line 56 and the signal RX SOS on line 57 are commands to the timing and control signal generator 38 to initiate transmission or reception of slots. Each of these signals is synchronized with the TX CLK signal on line 62. The demodulator of the modem operates in either offline mode or online mode according to bit 7 of the RX control word in control word register 31. To switch the demodulator from one mode to the other, the CCU sends a MOD RESET, writes the required command to the RX word register 31 via MOD BUS 50, and then invalidates the MOD RESET signal. .. In offline mode, the microprocessor's external memory consists of 2K words from ROM45 and 2K words from RAM44. The CCU commands the modem to input this signal after startup and at each predetermined number of hours during non-transmission or non-reception of the modem so that the modem performs self-testing and tuning routines. The self-test routine tests the interface to ROM 45, 46, internal and external RAM 44, and CCU. This routine sends the test results to the CCU through the status register 24. The tuning routine includes sending a tuning signal to the demodulator and calculating the coefficients of the FIR filter contained in the microprocessor 17. This routine is performed offline at each predetermined length of time during non-data transmission or non-data reception of the modem. In online mode, the modem receives a signal from either the control channel or the audio slot according to the RX section control word in the control word register 31. The online software executes the following routines. The initialization routine is performed by the microprocessor 17 at startup or after receiving the reset signal. This routine reads the control word in register 31 and calls other routines according to this control word. In this routine, the CCU sends a MOD RESET signal to line 54 to the modem and a MOD BUS to control register 31 for online mode input. Invoked when a command is sent by 50. This routine performs a checksum test on the online PROM, initializes the parameters, reads the control word register 31, and branches to the appropriate routine. The frequency acquisition routine is performed only on the subscriber station's modem when the control channel is received so that the subscriber station VCXO frequency is synchronized with the base station's crystal frequency. The transmit, receive, and IF frequencies are extracted from the subscriber station's VCXO or the base station's OCXO, so this routine synchronizes all frequencies. This routine is used only on subscriber station modems. This routine is invoked by a command from the CCU when the demodulator is set to the control channel frequency. The function of this routine is to synchronize the VCXO frequency with the OCXO frequency of the base station. This synchronization process is a short AM with no transmission from the base station. It starts with searching for HOLE first. After this search, the base station transmits an unmodulated carrier signal. Upon receiving this waveform, the output of the IF mixer becomes another sinusoidal waveform with a frequency proportional to the difference between the VCXO and the frequency of the base station crystal oscillator. Modem software Samples I and Q channels at certain time intervals and performs a phase lock loop function, i.e., determines the phase change for each time interval, guides this phase change to a reduction filter, and corrects it. Is sent to VCXO. The modem determines that frequency capture has been achieved when this phase change falls below a certain level. If AM HOLE is not detected within a certain amount of time, the modem sends an error message to the CCU indicating that the receiver is not tuned to the control channel. This routine is called by the initialization routine and sends a state word from status register 24 to the CCU, that is, a state word indicating whether frequency capture has been achieved. When called by the initialization routine, the frequency capture routine is AM Sample I and Q channels for HOLE search and at the same time form an AGC loop. If AM HOLE is not detected within a given number of samples, this routine propagates this information to the CCU via status register 24. The CCU switches to another possible RCC frequency and restarts the frequency capture routine. After detecting AM HOLE, this routine provides a phase-locked loop during the transmission of the unmodulated carrier. In this loop, I and Q samples are extracted and the phase angle of the sample output signal is calculated. The calculated phase angle is subtracted from the immediately preceding phase angle, the subtraction result is reduced and filtered, and sent to the VCXO as a control word. The AGC is also calculated during the loop using the amplitude of the signal. At the end of the specified duration, the modem sets status register 24 to "1" if the phase shift is less than or equal to a given amount, and to status register 24 if the phase shift is still greater than this amount. Set "2". In the latter case, the frequency capture routine can be restarted over one or more slots. The bit synchronization routine can be run on both the subscriber and base station modems when the RCC is received and after the frequency acquisition routine is complete. On a subscriber station modem, its output uses a 16KHz symbol clock for synchronization to base station transmission. In a base station modem, the output is used to determine the minute delay that should be incorporated into the subscriber station transmission to obtain synchronization with the base station modem clock. The slot receive routine is called when the modem is ready to receive data, i.e. after frequency synchronization and bit synchronization have been achieved. The main functions of this routine are (a) parameter initialization for the symbol receive routine (discussed below), (b) activation of the symbol receive routine when the first symbol is sampled, and (c) all of the slots. Judgment of link quality and other information after receiving the symbol. This routine is called by the initialization routine at the beginning of each receive slot. The main function of this routine is to initialize the parameters for the symbol receiving routine. After completing this task, the routine waits for all samples of the first symbol in the slot to be posted on the FIFO stack 18 before branching to the symbol receive routine. The processing tasks of this routine are as follows. 1. Read the modulation level ML from the control word register 31, where the value of ML can be 2, 4, or 16. 2. Calculate the half-symbol value given by the formula below.<img file="JP2543342B2_D0001.tif" />3. Calculate the MASK used to truncate the LSB from the demodulated phase. MASK depends on the number of bits used to represent the ML and demodulated phase, ie 2ⁿRepresents a phase angle of 22.5 degrees MASK = 8X2ⁿ(When ML = 2) = 12X2ⁿ(When ML = 4) = 15X2ⁿ(When ML = 16) 4. Read the previous AGC for this slot from AGC register 26 and send it out (only for base stations). 5. Wait until the end of sampling for the first symbol, then branch to the symbol receive routine. and 6. After receiving all the symbols in the slot, send them from the link quality register 25 to the CCU. The symbol reception routine is activated once every symbol cycle when data is received, and its functions are (a) reading the I and Q samples for the symbol, (b) filtering the I and Q samples, and (c) transmitting. Determine the symbol and send it to the CCU, (d) execute a phase lock loop to synchronize the VCXO with the incoming signal, (e) execute the bit tracking algorithm, (f) AGC To calculate, and (g) to accumulate information for link quality calculations. This routine is invoked once for each symbol when all four sample values from one symbol are stored on the external FIFO stack 18. This routine reads this sample value into memory and processes it to determine the send symbol. Also, AGC is calculated from the signal amplitude. The deviation between the receive and send symbols is used in AGC, link quality, and tracking algorithms. The execution time of this module is less than 1 symbol width or 65.5 microseconds. After receiving and storing I and Q samples for a particular symbol, this routine performs the following tasks: 1. FIR filtering of the received sample (FIR filter coefficients are determined by the adjustment routine described below). 2. Determine the signal level and use it for AGC. 3. Determine the received phase angle, subtract the previous phase angle, round the subtraction result, Gray-encode the rounded result, and send the coded result to the CCU. 4. Run the bit tracking algorithm. (This output is cumulative for all symbols and sent at the end of the slot, which is used to synchronize the subscriber RX clock with the transmission of the base station.) 5. Perform a phase lock loop to synchronize the VCXO with the base station oscillator. (This output is sent to the VCXO at the end of the slot, which is only used by subscriber stations.) And data accumulation for link quality and information to the CCU via the link quality register 25 at the end of the slot. Send. The internal clock signal required by the modem is generated by the timing signal and control signal generator 38 from the master 80 MHz clock signal on line 59. The modem uses the line 60 master 16KHz clock signal as a TX CLK for transmission. Therefore, all transfers from the base station are synchronized with each other. The subscriber station clock signal is extracted from the master 80MHz VCXO of the subscriber station timing device. This VCXO is controlled by the VCXO FDBK signal on line 78 from the modem. VCXO on line 78 All receive and transmit clocks are calculated from the FDBK signal. The timing signal and control signal generator 38 then feeds the CCU the 16KHz RX CLK signal on line 63 extracted from the input data stream. The CCU itself can detect unique words in the control channel and determine frame and slot markers from the unique words and the RX CLK signal on line 63. The AM STROBE signal on line 65 is derived from the signal demodulated by the microprocessor 17 by the timing and control signal generator 38, telling the CCU where to look for a unique word. At the subscriber station, microprocessor 17 calculates the bit and frequency tracking parameters for the VCXO FDBX signal and VCXO. Adjust the timing by outputting the WR signal to STIMU49. To adjust the frequency, the microprocessor 17 outputs to the D / A converter in the VCXO interface 41 that supplies voltage to the VCXO. This VCXO frequency is divided by 5 to 16MHz. This 16MHz clock is again divided by 5 to generate a 3.2MHz clock. The timing signal and control signal generator 38 divides this by 4 to generate the 800 KHz clock signal required for the TX FIR filter 12. The sample time generator 42 divides the 3.2 MHz clock signal by 50 to generate a 64 KHz sample clock signal. The sample time generator 42 is under the control of the microprocessor 17 and causes a delay when capturing the control channel. This enables a large jump of ± 16KHz clock width for high-speed acquisition. The self-adaptive adjustment mode is in a loopback state in which the modem enters the adjustment of the filter coefficient of the demodulator digital FIR filter stored in the microprocessor 17 to correct the deterioration of all analog filters due to aging or temperature changes. is there. This analysis is performed by looping back the transmitter data via the RF unit and receiving a known code pattern in the demodulator of the modem. The coefficients are optimized by the 5-constraint Lagrange method. The five constraint terms are (1) the received data stream, (2) the data stream delayed by 0.05T, (3) the data stream advanced by 0.05T, and (4) the adjacent upper channel. Data stream from (5) data stream from adjacent lower channel. During the tuning mode, the microprocessor 17 supplies the FIR filter 12 of the modulator with a series of 32-symbol length tuning patterns of lines 106 from the FIFO stack 36 that are enabled for the duration of that tuning mode. Time advance and time delay skew the two streams by 0.05T. The CCU sets the modem to adjustment mode by activating the adjustment mode switch 11 in response to the control signal on line 107 from the control word register 31 to set the modem's modulator to a special adjustment pattern from the FIFO stack 36. To read. The demodulator also receives advancement or delay depending on the test requirements. When the process is complete, the modem sends a status message to the CCU that the coefficients have been calculated. At this point, the CCU tests the modem by setting the modem to normal operation and writing a configuration pattern, ordering the RFU to establish a loopback, read the return data, and test the validity of that data. .. The tuning mode is initiated by the CCU setting the appropriate control register bits and sending a MOD RESET signal on line 54 to the modem. This reconfigures microprocessor 17 from ROM 4K usage and RAM OK usage to ROM 45 2K usage and RAM 44 2K usage. This 2K ROM 45 holds the tuning mode algorithm and the 2K RAM 44 acts as a scratchpad memory when calculating the filter coefficients. One algorithm calculates the adjacent channel characteristics. To determine adjacent channel interference, the modem's modulator must be capable of transmitting at a frequency 25KHz away from the receiving frequency. This is achieved by the CCU reading the modem's status register. The information in the status register 24 commands the CCU to change the frequency in the RFU receiver as instructed by the modem. The microprocessor 17 executes the tuning routine. The function of the tuning routine is to calculate the FIR filter coefficients in the microprocessor 17. The modulator activates in loopback mode and sends out a certain symbol sequence. This symbol sequence is transferred to the demodulator via RFU in the following five different modes. (1) Normal mode, (2) Forward timing mode, (3) Delay timing mode, and (4 and 5) Adjacent upper and lower channel modes. In the last two modes, the AGC setting is increased by 23dB. The demodulator uses a sample of the input waveform to generate a positive constant-eye symmetry matrix A of order 28. In addition, a 28 word vector V is generated from the input sample. The coefficient vector C is given by the following equation. C = A^-1 V ...... (Equation 2) B = A^-1Use the algorithm in the calculation of (given A). Since the value of B is not accurate due to the rounding error, a more accurate C is calculated using the iterative method. This calculation yields a complex FIR filter coefficient in the 28th order. The modulator activates in tuning mode and transfers five similar sequence pairs. Each of these pairs consists of the following two series. (a) I-series of 9 NULL symbols, 1 1 symbol, and 22 NULL symbols, (b) 9 NULL symbols, 1 j symbol, and 22 NULLs Q series consisting of symbols. The above "1" may be any symbol. Also, "J" is a symbol that is 90 degrees different from "1". The processing task of the demodulation section is (1) Adjust the AGC so that the signal peak in the normal mode is 50 to 70% of the maximum value (for the 4th and 5th modes, increase the AGC by 23 dB). (2) Read and memorize the input samples (discard the first 32 samples in each series and memorize the next 64 samples), and (3) construct matrix A (28, 28). In the normal mode (first mode), the following processing is performed. A (I, J) = A (I, J) + ΣX (4N-1) (4N-J) ...... (Equation 3) This addition is done for all Ns that satisfy the following equation. 0 4N-I &lt;64 and 0 4N-J &lt;64 ...... (Equation 4) With respect to the advance mode and the delay mode (the second and third modes), the same processing as above is performed except that the terms obtained from N = 8 are not added. In the fourth and fifth modes (transmission for upper and lower adjacent channels), the following processing is performed. A (I, J) = A (I, J) + ΣX (2N-1) (2N-J) ...... (Equation 5) This addition is done for all Ns that satisfy the following equation. 0 2N-I &lt;64 and 0 2N-J &lt;64 ...... (Equation 6) Other processing tasks of the demodulation unit in the adjustment mode are as follows. (4) Generate the vector V (1:28) from the sample of the first series pair. aI {V (I)} = X (32-I) ...... (Equation 7) Here X is a sample of the first (I) series, and bQ {V (I)} = V (32-I) ...... (Equation 8) Here X is a sample of the second (Q) series, and (5) Find the coefficient vector C by solving AxC-V = 0. This is done by first finding B, which is the inverse element of A. Due to the rounding error, B is likely to be inaccurate. The following iterative method is used to solve the exact C. Co = BxV ...... (Equation 9) C_{n + 1}= C_nbxB (AxC)_n-V) ...... (Equation 10) Here b is a predetermined value less than 1.

[Simple explanation of drawings]

1A and 1B show block diagrams of preferred embodiments of the modems of the invention, spliced together. Figure 2 shows a series of signals for Gray encoding a bitstream symbol. FIG. 3 is a block diagram of the FIR digital filter of the modulator of the modem. FIG. 4 is a diagram showing the time relationship between the symbols inside the FIR digital filter of the modulator of the modem and the read value of the filter coefficient to be multiplied by each of the symbols. FIG. 5 is a block diagram of the SIN / COS IF generator of the demodulator of the modem. FIG. 6 is a diagram showing a time relationship between a control signal, a timing signal, and a data signal related to the operation of the modem. Description of the sign of the main part 10 ...... Fixed storage device for differential PSK conversion 11 ...... Adjustment mode switching device 12 ...... FIR digital filter 13 ...... D / A converter 14 ...... Band filter, 15 ...... Mixer 16 ...... RF amplifier 17 ...... Microprocessor 18 ...... FIFO stack 19 ...... A / D converter 20 ...... amplifier, 21 ...... mixer 22 ...... Line, 23 ...... Interface register and bus controller 24 ...... Status register 25 ...... Link Q register 26 ...... AGC register 27 ...... RX frequency register 28 ...... minute delay register, 29 ...... common mode I register 30 ...... Quadrature phase Q register 31 ...... Control word register, 32 ...... Small delay (BS) register 34 ...... Buffer control device 35 ...... Read / Write Decoder 36 ...... FIFO stack, 37 ...... data latch 38 ...... Internal timing signal and control signal generator 39 ...... Transmission clock delay device 40 ...... Small delay generator 41 ...... VCXO interface device 42 ...... Sample time generator 43 ...... COS / SIN IF signal generator 44 ...... RAM, 45 ...... ROM 46 ...... ROM 47 ...... Buffer / Attenuator 48 ...... Buffer device 49 ...... System timing device