On-line storage with signature self-testing and analysis

The invention relates to the field of computer technology and microelectronics, and can be applied to the production and exploitation of superintegrated circuits with embedded means of testing and diagnostics.

A signature analyzer is known which contains a displacement register, о XOR logic gate, at which inputs are connected the outputs of the register positions corresponding to the structure of the polynomial p (x), о data entry and о synchronization input [1].

There is a well-known test method, called pseudo-self-testing or π-testing of operative memory devices with single-position logic cells, which consists in the number of test signals being chosen equal to that of the different stable states of a memory cell at the beginning of the iteration. test, the first and second test signals are properly recorded in the first two cells of the device of capacity m (m-number of cells), then repeat the following operations m-2 times: read and assemble module two (logical operation XOR) the contents of the cells, in which the current test signals are retained, then the second test signal is interpreted as the first test signal , and the result of the modulo two assembly is interpreted as the second test signal, the second test signal is entered in the greasing cell of the operative memory device; compare the resulting combination of test signals with the control one and in case of coincidence the test iterations are performed with other non-initial combinations of the values ​​of the test signals until the first non-coincidence of the resulting combination with the control one and in case of non-coincidence it is decided that the operating memory device is defective [2].

The disadvantage of this method is that it does not ensure detection of couple defects.

Also known is a self-test operative memory device, which contains a synchronization register, a group of three counters, о operative memory (RAM), a bistable group, an XOR logic element, the output of which is connected to the data input of the the memory, о one input is connected to the output of the second bistable of the group, and the other input - to the output of the first bistable of the group, the reset entry that is connected to the reset entry of the group's two-fold, the reset entries of the group counters, the reset entry of the synchronization register, and the reset entry of the device, the sync input is connected to the sync entry of the group's two folders, at the memory select entry, at the synchronization register synchronization entry, and at the device synchronization entry, the data entry is connected to the data entry of the second bistable of the group and to the data output of the memory, the address inputs of which are connected, respectively, to the informational outputs of the group counters, the read-write entry - to the pen entry the third counter of the group and the fourth output of the register, the third output of which is connected to the synchronization inputs of the group counters, the second output - at the inlet of the second meter of the group and at the inlet of the second flip of the group, the first output - at the inlet of the first meter of the group and at the inlet of the first of the group [3].

The disadvantage of the device is that it does not detect defects of the adjacent cell couple.

The problem solved by the invention is to increase the resolution of testing of operative memory devices.

The operative memory according to the invention removes the disadvantages mentioned above in that it contains a synchronization register 1, a counter 2, the increment-decrement input whose is joined with the fourth output of the synchronization register 1, о operative memory 3, the address entry. which is joined to the output of counter 2, a group of bistable 4.1, 4.2, reset inputs of bistable 4.1, 4.2 are connected to the reset input of counter 2, at the reset entry of the synchronization register 1 and at the reset entry 6 of the device, the synchronization inputs of the bistable 4.1, 4.2 are connected with the input of selecting the operating memory 3 and with the synchronization input 7 of the device, and the inputs of the pennant of the device. bistables 4.1, 4.2 are joined, respectively, with the first and second outputs of the synchronization register 1, further containing о logic gate XOR 5, the inputs to which are connected to the exits of the bistables 4.1,4.2. The novelty of the invention is that it further includes:

- a detent flip-flop 8, the setting input of which is connected to the reset input 6 of the device, the data input - to the logic signal source "0", and the synchronization input - to the output of the counter 2;

- five logic gates OR 9, 10, 11, 12, 13, the first inputs of the logical gates OR 9, 10, 12 are connected to the synchronization input 7 of the device; The output of the logic gate OR 9 is connected to the synchronization input of the synchronization register 1, the second input of the logical gate OR 10 - to the third output of the synchronization register 1, and its output - to the synchronization input of the meter 2; the first input of the logic gate OR 11 is connected to the fourth output of the synchronization register 1, and its output - to the input-read input of the operating memory 3 and to the second inverted input of the logic gate OR 12; the first input of the logic gate OR 13 is connected to the output of the operating memory 3;

- a multiplexer 14, the first input of which is joined with the output of the logical port XOR 5, its output - with the data input of the operating memory 3, and its control input - with the output of the detent bistable 8 and with the two inputs of the logic gates OR 9, 11, 13;

- a signature analyzer 15, the reset input of which is joined to the reset input 6 of the device, the synchronization input - with the output of the logical port OR 12, the data input - with the output of the logical port OR 13 and with the data inputs of the bistable ones 4.1, 4.2, and the output - with the second input of the multiplexer 14.

The result of the invention consists in the self-testing of the operative memory device with the absolute resolution of 100% for the couple defects. This result is obtained due to the fact that some of the defects are detected by πMD 3870 G2 2009.03.31_{W + 1} 2^w“^/+1 testing with R resolution_n - Σ daily the rest of the defects (which were not detected by π-testing) are detected by the signature analyzer with the known resolution and equal to R_s..\⁼l-2 'per irritation, where m is the binary of the virtual register in the π-test method, η - the binary of the register of the signature analyzer. With each iteration, the number of defective burns decreases by 1^m or T times, so that at the end of the test the absolute value of 100% of the resolution is reached.

At the same time, in each iteration of the π-testing and analysis of signatures there are о sub-indications of jointly detected defects.

The invention is explained by the drawings in FIG. 1 ... 5, which represents:

FIG. 1, the structure diagram of the proposed device;

FIG. 2, the electrical diagram of the synchronization register;

FIG. 3, device operating time charts;

FIG. 4, the diagram of a bistable;

FIG. 5, the stereo diagram of the signature analyzer.

The device is composed of synchronization register 1, counter 2, operative memory 3, a group of bistables 4, о XOR logic gate 5, reset inputs 6 and synchronization 7, retention bistable 8, five logic gates OR 9, 10, 11, 12 and 13, multiplexer 14, signature analyzer 15 (see fig. 1).

The synchronization input 7 is connected with the selection input of the operating memory 3, with the synchronization inputs of the bistable group 4, with the first inputs of the logic gates OR 9, 10 and 12, the reset input 6 is connected with the reset entries of the register 1 , the meter 2, the analyzer 15 and the input of the bistable setting 8, the data input of which is connected to the logic source "0", the synchronization input - at the output of the counter 2, and the output - with the control input of the multiplexer 14, with the second input of the logic gate OR 13, of the logic gate OR 11 and of the logic gate OR 9, the output of which is connected with the synchronization input of register 1, the first output of which is connected with the inlet of the first bistable 4.1 of group 4, the second output - with the incoming of the bistable of the second bistable 4.2 of group 4, the third output - with the second input of the logic gate OR 10 and the fourth output - with the first output of the logic gate OR 11 and with the increment-decrement (±) input of the counter 2, whose synchronization input is connected to the output of the gate logical OR 10, the output of the report - with the input of synchronization of the detent bistable 8, and the output of data - with the input of addresses of the memory 3, the read-write input whose connection is connected to the output of the logic gate OR 11 and the second input of the reverse of the logic gate OR 12, the output of which is connected to the synchronization input of the analyzer 15, the output of which is connected to the second input (of data) of the multiplexer 14, the first input (data) of which is connected with the output of the XOR port 5, and the output is connected with the data input of memory 3, the output of which is connected with the first input of the logic gate OR 13, the output of which is connected with the data inputs of the signature analyzer 15, of the bistables of group 4, the outputs of which are connected to the inputs of the logic gate XOR 5.

The synchronization register realizes the cyclical displacement of the logical unit (against the zeros background) and can be implemented, for example, according to the scheme presented in fig. 2 and confines four bistables: 1.1, 1.2, 1.3, 1.4, the outputs of which are the outputs of register 1, at the same time, the output of the flip-flop 1.4 is connected with the data input of the flip-flop 1.1, the output of which is connected with the data input of the flip-flop 1.2, the output of which is connected with the data input of the bistable 1.3, the output of which is connected with the data input of the bistable 1.4, the synchronization input of which is connected with the synchronization inputs of the bistable 1.1, 1.2, 1.3 and with the synchronization input of register 1, and the reset entry - with the reset inputs of bistables 1.2 and 1.3, with the input of setting the bistable 1.1 and with the reset entry of register 1.

As bistables 1.1, 1.2, 1.3, 1.4 and the detent bistable 8 can use D-bistables from the microcircuit K1531TM2 (see: Нефедов AB Интегральные микросхемы ТТЛ.-M. Аргус, 1999).

Counter 2 is a well-known device and can be constructed on the basis of microcircuits KI531 HE 17 (see: Нефедов AB Интегральные микросхемы ТТЛ.-M .: Аргус, 1999).

Operational memory 3 with the binary of 1-bit cells is the unit that is tested and represents a known (static) operating memory microcircuit, for example, the microcircuit К537РУ14 (see: Микросхемы памяти, ЦАП и АЦП: СправовечеЛ.А. .-Й.К.Марцинкявичюс, Э.-А.К.Багданскис и др. - М.: КубК-а, 1996).

Bistables 4.1 and 4.2 of group 4 save (record) the data from the memory output 3. the data recording takes place at the transition of the synchronization signal C from "0" to "1" and of the logger value. "1" at the pennant entry E. The bistables of group 4 can be implemented, for example according to the scheme presented in fig. 4. A flip-flop with boundary о carries logic OR 16 and a flip-flop 17, the output of which is the output of the flip-flop, the reset and data inputs - respectively the reset and data inputs of the flip-flop, and the synchronization input is connected to the output logical gates OR 16, the direct input of which is the synchronization input of the flip-flop, and the reverse - the flip-in input of the flip-flop.

As the bistable 17 the D-bistable from the component of the microcircuit K1531TM2 can be used (see: Нефедов AB Интегральные микросхемы ТТЛ.-M .: Аргус, 1999); as logical gates OR 9, 10, 11, 12, 13 and 16 - logical gates OR of the microcircuit component KI 531 ЛЛ1 (see: Нефедов AB Интегральные микросхемы ТТЛ.-M .: Аргус, 1999); as an inverter - the inverter from the KI 531 microcircuit component

MD 3870 G2 2009.03.31

ЛН1 (see: Нефедов AB Интегральные микросхемы ТТЛ.-M .: Аргус, 1999); as multiplexer 14 multiplexer ^ with two inputs of the composition of the microcircuit К 1531 КП1 (see: Нефедов AB Интегральные микросхемы ТТЛ.-M .: Аргус, 1999).

The logic analyzer is a known device and can be built, for example, according to the diagram, shown in FIG. 8.2 from Ярмолик BH Контроль и диагностика цифровых ЭВМ. Мн .: Наука и техника, 1988. The analyzer reset input is used to set the analyzer to a non-zero initial state.

The synchronization register 1 is intended for generating control signals for the components of the self-test device. Counter 2 is intended for generating memory addresses 3. The binary of the counter equals the binary of the address lines of memory 3. The signature analyzer 15 is intended for generating the initialized states of the cells of the memory matrix 3 and for recording (compressing) the reactions of the tested unit, ie of the operating memory 3. The flip-flop 8 is intended for maintaining the enrollment signal in the active state, at the input of memory 3 during its initialization period.

The device works in the non-dense mode.

When connecting the power supply, the states of the bistable, register, counter and memory cells can be arbitrary.

At the initial time point at the synchronization input 7, the logic level "1" is set and at the reset input 6 the logic level "0" (see fig. 3). The logic level "0" of the reset signal resets the counter 2, the bistables of the group 4 and the bistables 1.2, 1.3, and 1.4, sets the bistables 1.1, 8 and the signature analyzer 15 in the initiated state Init, where Initial ·. The logic signal "1" from the output of the bistable 8 includes the logic gates OR 9 and 13, installs the log. "1" at the output of the gate OR 11 and at the input of read-write memory 3; opens (via gate OR 11) gate OR 12, allowing the synchronization signals to be passed to analyzer 15, switches the second input of the multiplexer 14 to its output.

The logic signal "0" at the output 3 of register 1 keeps the gate OR 10 open, allowing the synchronization signals to be passed to counter 2.

Thus, the test device is installed in the initiated state. By generating the synchronization pulses at the input 7 (see fig. 1), the π-test of memory 3 is executed.

π-testing consists of the iteration of initialization of the memory matrix cells and the test iterations (see: MD 1240 G 1999.05.31). ''

It is known that the structure of the signature analyzer follows the structure of the irreducible polynomial p (x) (νο, Α. Ярмолик BH Контроль и диагностика цифровых ЭВМ. Мн .: Наука и техника, 1998). The degree of the polynomial deg р (х) is chosen equal to the binary of the address bus of memory 3, that is / <= deg p (x). Then the period of the polynomial p (x) will be equal to T = N1, where N = 2^Um'is the capacity of the memory array. In the initialization iteration, N synchronization touches are executed. The bits (the logical values ​​"0" or "1") generated at the output of the analyzer 15 are sequentially entered in the cells of the memory array 3 - the write-read signal of the memory 3 is in the "write" state (see fig. 3) .

For example, if k = 3 and p (x) = 1 + x + x³ and Init = <xj x₂ x₃> = <100>, then the general sequence of analyzer will be the one presented in line 8 column Out of fig. 5. The logical values ​​are entered in the cells of the memory matrix with the addresses generated by the counter 2. The addresses follow the natural string 0, 1, ..., 2 ^ -1.

After executing T synchronization tactics at the output of the counter 2, the logical signal "0" appears, which at the end of the tact passes into the logical signal "1" (see fig. 3). This transition resets the bistable 8 and thus opens the logic gates OR 9, 11, 13 and switches the first input to the output of the multiplexer 14.

Thus, the test device is prepared for performing test iterations.

According to MD 1240 G 1999.05.31 there are 3 test iterations. The test iterations are executed sequentially (nonstop). Because the capacity of the memory array N is an even number, and the period T - an odd nunter, at the beginning of each iteration of the test, the virtual machine (of the π-tester) will have о initiated state (nine) different from the previous states, which provides the necessary condition for π-testing.

The test iteration consists of test subtitles of four synchronization tactics each.

The test subtitle is performed in humidifier mode.

In the first synchronization tact, the logic signal "1" from the first output of the synchronization register 1 allows the entry in the first bistable 4.1 of the value from the memory output 3; the value (saved) is the contents of memory cell 3 with the current address, ie 0.

In the second tact (counter 2 was increased by о unit) the logical unit moved to the second position of register 1, and the logical signal "1" from the second output of the synchronization register 1 allows the value of 0 to be entered in the second bistable 4.2. at the output of memory 3, which is read from the cell with the current address equal to 1.

In tact three the counter 2 increased with о unit (and became equal to 2), the logical unit moved to the third position of register 1 and at the output of the XOR 5 port the result of the modulo 2 of the read values ​​from the memory cells 3 is fonned.

In tact four the logic signal "1" from the fourth output of register 1 changes the direction of counter 2 towards decrementation, opens gate OR 12 (passing through gate OR 11) and passes memory 3 in the registration state. At the arrival of the positive front of the synchronization signal, the data from the output of memory 3 takes place in the analyzer 15, the value from the output of the XOR portion 5 in the memory cell 3 to the address indicated by the meter 2, ie

MD 3870 G2 2009.03.31 to address 2, and the decrement with о unit of meter 2 (the current state of meter 2 is equal to 1). This will test the subtitle of the test.

The test subtitles are repeated N times, and the test iterations, according to MD 1240 G 1999.05.31, - 3 times. At the end of the test iterations, the status of the register of the signature analyzer 15 and the bistable ones of group 4 takes place, which is compared with the expected ones. In case of non-coincidence it is accepted the hypothesis that the test unit, that is to say the operative memory 3, is defective.

To estimate the expected signal combination, read from the bistables of group 4, the iterative fonnula can be used:

v (/ + l) = v (/> 4, / = 0, ..., 7, (1) where v = <x₁... x_I> represents the states of the respective bistables at the moment /; and the characteristic matrix A is:

<td></td><td> &gt;1</td><td> 1</td><td> 0 ··</td><td> • 0</td>

<td>A =</td><td>gl</td><td> 0</td><td> 1 ··</td><td> • 0</td>

<td>RXR</td><td></td><td></td><td></td><td></td>

<td></td><td>_gr</td><td> 0</td><td> 0 ··</td><td> • ⁰</td>

(2) where g_b g₂, ..., g_r are the coefficients of the polynomial g (x) that describe the structure of the virtual machine of the π-test. Note'. the operations in relation (1) apply to the Galois GF field according to the matrix (2).

According to MD 1240 G 1999.05.31 is sufficient that r = 2, then g (x) = \ + xAx² and the matrix (2) becomes equal to:

At the moment / = 0 the components of the vector v (0) are equal to the states of the first r = 2 cells of memory 3. In particular, for the analyzed example, we have v (0) = &lt;0 1&gt; and ν (Γ) = v (0 ) A^r (3) or v (7) = (0 1)

<img file="MD3870G2_D0001.tif" />

(4)

The determination of the expected state of the analyzer 15 can be performed either by simulating the self-test device or by a complex calculation.

In calculating the expected signature, first, the signature is estimated after the initialization iteration of the operating memory and then the test iterations signatures. The signature of the initialization iteration is calculated according to the formula:

S (/ + 1) = S (/) B, / = 0, ..., 7, (5) where S = &lt;Xj ... x_k &gt; represents the states of the signature analyzer 15 at the moment /, / = 0, ..., 7, and the characteristic matrix В is equal to:

~ ρ_γ 1 0 ··· 0'

<img file="MD3870G2_D0002.tif" />

Pt 0 о ··· о undeр_ь ... р_к are coefficients of the polynomial p {x) - Σ

For the calculation of test iterations signatures will be used the modified version of the formula (5), namely:

S (/ + l) = v * (/) + S (/) B, / = r, ..., 7, '(6) where V_uk = (d 0 · · · 0 ^ is the vector of data d read from memory 3 at time /.

The value d is the first component of the vector v (z) of formula (1) at times z = r, ..., 7. For the example analyzed cup (x) = \ + xAx³ we have the matrix:

в = о 0

MD 3870 G2 2009.03.31

Accepting that S (0) = &lt;1 0 0&gt;, for those. \ - 2³= 8 synchronization tactics, according to the formula (5) at the end of the initialization iteration we have the following expected signature value:

oT

S (8) = S (0) -B⁸ =(1

0) 0 = (0 I 0) ·

For the first test iteration I, for which Vi (0) = &lt;0 1&gt;, at the output of memory 3, the logical values ​​D = [l, 0, 1, 1,0, 1] are expected, respectively, at the time moments z -2, ..., 8. The expected value of the signature for this bit string will be calculated according to formula (6). Taking into account the result (7), we obtain:

οΊ '¹ эд = (4

0) + (0 1 0), / = 2, ..., 8, (8) where it gives values ​​in the Dp string Applying the relation (8) for the first iteration of the test we have the following signature:

Sj = &lt;1 1 1&gt;.

Similarly, the expected value of the signature will be calculated at the end of the second iteration of test II. We have: v "(0) = &lt;l 0&gt;, D" = [l, 1, 0, 1, 1,0] and j S_II(I) = &lt;d_andA&gt; + S_I-B^{i + 1}, where the dj takes values ​​from D_n, i = 2, ..., 8. The result of the calculations is obtained:

S_n=&lt; 0 0 0 &gt;.

For the calculation of the signature of test iteration III, the data initiated are:

v, n (0) = &lt;1 1&gt;, Dni = [0, 1,1,0, 1, 1] and S_m(i) = &lt;diO&gt; + S „· B^{i + 1}, where the dj takes values ​​from D_m, i = 2, ..., 8. We have the signature:

Sin— &lt;1 0 0&gt;.

Let's analyze how to detect the (interference) defects of the (adjacent) memory cell pair_of and c_v, where c_of is the address of the aggressor cell, and c_v - address of the victim cell. Coupling failure is defined (specified) by the transition (jump) of the cell stereo c_v when performing the read or write operation on the cell c_of. There are two cases: c_of&lt;c_v and c_of&gt; c_v.

Case c_of&lt;c_v, that is, the address of the aggressor cell is smaller than the address of the victim cell. Cell c_v is the one in which the data is entered. In the fourth tact of the test subtitle the data read from c_v in the signature analyzer 15. That is why it influences c_of on c_v is recorded by the analyzer 15.

If the data is read from the victim cell c_v, then the wrong cell transition c_v will be recorded by the π-testing mechanism when reading the data in the first two synchronization tactics of the test subtitle.

Case c_of&gt; c_v, that is, the address of the aggressor cell is greater than the address of the victim cell. The victim cell c_v is the one in which the data is entered. In the first two synchronization tactics of the test subtitle in the aggressor cell c_of erroneous data will be read, which will bring the status of the bistables of group 4 different from the expected one (calculated previously). If the data is read from the victim cell c_v, then the wrong cell transition c_v will be recorded by both the signature analyzer 15 and the π-testing mechanism.

Therefore, the application of the proposed device allows pseudo-self-testing with the simultaneous signature analysis of the operating memory microcircuits. The resolution of the test in relation to the defects of the memory cell couple is equal to 100%, and the complexity of the self-testing algorithm, estimated for each of the 3 test iteraphs, is 4. Synchronous tactile speeds, where N is the capacity of the operating memory matrix.