Method of testing the correct operation of memory and method of testing the content of memory
Abstract
The invention relates to the computer engineering and microelectronics and may be used in the intellectual boards for testing the information recorded in the memory merged with a microprocessor.The process includes comparison of the output information from the memory (2), fed through the reading channel (10) with the preset data signals generated from without, and fed by way of the port (7) through the reading channel (9).The comparison is made by means of the comparison device (3), which may be, for example, a microprocessor programmed to carry out the comparison. At the output of the comparison device (3) appears a common checking signal launched into the port (5). The stored data, recorded in the memory (2), can permanently be stored in the memory, for example, in a read-only memory (ROM) or can (if the memory is electrically modified) especially be recorded in the memory for testing.The result consists in protecting the memory content from direct access.

Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
16 claims: 8 independent, 8 dependent
- 1Method of testing the correct functioning of the memory, electrically modified, joined with an integrated circuit, the method consisting of recording the data of the test in memory, debiting the preset data at the input of the integrated circuit, comparing the preset data inside the integrated circuit with the test data, recorded in memory, and the output of the verification signal from the integrated circuit, characterized in that it encrypts the default data before comparing the default data with the test data. 1. Metodă de testare a funcționării corecte a memoriei, modificate in mod electric, unite cu un circuit integrat, metoda constând in inregistrarea datelor testării in memorie, debitarea datelor prestabilite la intrarea circuitului integrat, compararea datelor prestabilite in interiorul circuitului integrat cu datele testării, inregistrate in memorie, și emiterea semnalului verificării din circuitul integrat, caracterizată prin aceea că se efectuează cifrarea datelor prestabilite inainte de compararea datelor prestabilite cu datele testării.
- 4Method according to one of the preceding claims, characterized in that the verification signal is output at the delayed output. 4. Metodă, conform uneia din revendicările precedente, caracterizată prin aceea că semnalul verificării se emite la ieșire cu întârziere.
- 5Method according to one of the preceding claims, characterized in that the microprocessor, located in the integrated circuit, is programmed to perform the data comparison. 5. Metodă, conform uneia din revendicările precedente, caracterizată prin aceea că microprocesorul, amplasat in circuitul integrat, este programat pentru executarea comparării datelor.
- 6Method according to one of claims 1-4, characterized in that the integrated circuit is used as part of the module, including one or more integrated circuits and the microprocessor. 6. Metodă, conform uneia din revendicările 1-4, caracterizată prin aceea că circuitul integrat este utilizat ca о parte a modulului, incluzând unul sau mai multe circuite integrate și microprocesorul.
- 8Method of testing the content of the memory, unified with a microprocessor in a module, the method consisting of cutting the preset data at the module input, comparing the preset data inside the module with the data recorded in the memory and issuing the verification signal from the module, which indicates the positive or negative result. of the comparison, characterized in that the encryption of the preset data is performed before the comparison with the test data. 8. Metodă de testare a confinutului memoriei, unificate cu un microprocesor intr-un modul, metoda constând in debitarea datelor prestabilite la intrarea modulului, compararea datelor prestabilite in interiorul modulului cu datele inregistrate in memorie și emiterea semnalului verificării din modul, care indică rezultatul pozitiv sau negativ al comparării, caracterizată prin aceea câ cifrarea datelor prestabilite se efectuează inainte de compararea cu datele testării.
- 15Method according to one of claims 8-14, characterized in that the module includes one or more integrated circuits, which include memory and microprocessor. 15. Metodă, conform uneia din revendicările 8-14, caracterizată prin aceea că modulul include unui sau mai multe circuite integrate, care includ memorie și microprocesor.
Independent claims8
36 paragraphs in 2 sections, as filed
The invention relates to the technique of calculation and microelectronics and can be applied in intellectual boards for testing information recorded in unified memory with a microprocessor. This can be о memory, the contents of which cannot be changed for example (device with constant memory or ROM) or о memory, information to which can be changed, for example the device with electrically programmable constant memory (EPROM) or the device with operative memory (RAM) ).
There are о many cases when memory testing is required, which confines pre-recorded information. For example, the use of unified credit cards, also known as intellectual cards. Usually, the memory of the intellectual boards is tested by connecting them to a reading device, which reads the contents of the memory, checks for the result, possibly, by checking the control amount or by comparing the output data with the data that must be in reality.
It is known the method of testing the memory, realized with the help of the device [1] input / output for the transmission of the data from о external source, together with the programmable memory electrically, independent from the energetic point of view, through the circuit of steering of the selection. The commands from the input / output device are decoded and compared with the memory output, and if the comparison result is correct, the output signal must be identical after the bifi with the expected memory content.
The closest is the test method performed using the device [2]. The given device gives the possibility of testing the correct functioning of the memory, changed by an electrical procedure and / or a method of testing the content of the memory, consisting of transmitting the preset data at the input, comparing the preset data with the test data, that is with the data entered in the memory, and issuing the control signal, indicating a positive or negative result.
It is often the case that memory confines confidential information and unauthorized access to this information can be obtained by giving the simple command to test the memory.
The problem solved by the invention is the removal of the aforementioned shortcoming, that is, ensuring the protection of the memory confinement against unauthorized access during the testing.
According to the first aspect of the invention, a method of testing the correct functioning of the memory, electrically modified, unified with an integrated circuit is proposed, the method consisting of recording the test data in memory, debiting the preset data at the input of the integrated circuit, comparing the data preset inside the integrated circuit with the test data, recorded in memory, and the output of the verification signal from the integrated circuit, fact that allows to verify the correctness of the function of the recording function and the characteristics of the memory, the encryption of the preset data being made before their comparison with the test data.
The method is further characterized by the fact that the preset data is relayed to the first input of the comparison device, it being part of the integrated circuit, in which the memory content is relayed to the second entry in the comparison device to compare the data from two inputs and output the test signal.
Also, according to the invention , the test data is retransmitted at the recording input and temporarily stored in memory before relaying at the second recording input of the comparator.
Additionally, in the method, the verification signal is output at the delayed output.
The method is also characterized by the fact that the microprocessor, located in the integrated circuit, is programmed to perform the data comparison.
In addition, according to the invention, the integrated circuit is used as part of the module, including one or more integrated circuits and the microprocessor.
Moreover, the method is characterized in that the circuit or integrated circuits are made on the intellectual board.
Using this method you can test the function of the recording and the characteristics of the electrically editable memory.
According to the second aspect of the invention, a method of testing the confinement of memory, unified with a microprocessor in a module, is proposed. and emitting the verification signal from the module, which indicates the positive or negative result of the comparison, characterized in that the encryption of the preset data is performed before their comparison with the test data.
MD 1844 B2 2002.01.31
This method, according to the invention, is characterized! by that c! the default data is debited! at the first input of the comparison device, forming part of the module, the memory content is debited! at the second input of the comparator, compare! the data charged to the two! device inputs and the verification signal is output.
In addition, the data recorded in memory includes the stored data in memory.
Also, according to the invention, the test data, charged at the module input, include the data that must be recorded in the memory before comparison.
The method, outside! therefore, it is characterized! by that c! memory changes! electrically the test data is charged! at the entrance of the registration and will be released! temporarily in memory before being transmitted to the second input of the comparison device.
In addition, the verification signal is output at the delayed output.
The method is also characterized! by that c! the microprocessor is programmed to perform the data comparison.
Additionally, the module includes one or more integrated circuits, including memory and microprocessor.
The method is still characterized! by that c! the circuit or integrated circuits are located on the intellectual board!
According to the second aspect of the invention, the data may be permanently stored in memory or may be renewed, such as program data and / or initialization data, or these may be data recorded in memory as a first command! Testing. By the last method! you can test the recording area and the characteristics of the electrically editable memory.
The module can be an integrated circuit, which includes о memory and a microprocessor, or it can be a set of integrated circuits, physically connected by means of hermetic or similar. Usually!, The module is an integrated circuit to your liking! intellectual!.
It is possible that the cross-over attempts to determine the contents of the memory s! can! be achieved by successive introduction! automatic! of the test data sets, methodically modified after! confined to! at the moment the output signal will c! the memory data coincides with the data charged at the input. I exist! different procedures to solve this problem.
According to one feature of the invention, the microprocessor is programmed so that s! refinance! output of each confirmation or unconfirmation signal. Refining between consecutive signals can take a few microseconds or seconds. In this case a methodical control will require a very long time.
Another procedure for preventing excruciating attempts to test memory const! in encoding data before comparing them, for example, with the help of a secret algorithm. And then the output data will have no connection! express! with the memory contained. The algorithm or key can be different from one control of the intellectual board to another.
Using the methods described above for internal comparison! of data makes it impossible to directly access the contents of the memory, which is precisely the result of the invention. All that is confined to the output is the test signal.
The invention will be described further with reference to a single explanatory drawing, the one representing о schem! -Block, which describes the method according to the invention.
In the figure! shown are integrated circuit 1 with memory 2 (EPROM), which confines some data, and a comparator 3, for example, a microprocessor programmed for comparing data. Link interface! with external devices is presented! with dotted line! 4. Interface 4 has three access ports 5, 6 and 7, through which it is achieved! transmission of signals in integrated circuit 1 and from it. The internal access channel from port 7 is divided! in two !: recording channel 8, which leads to memory, and reading channel 9, which leads to the comparator. Testing is done! by entering the program data into the integrated circuit and performing the internal comparison using the comparator 3. The program data is generated! by the external devices (not shown) and transmitted to the comparison device through the data input port 10 and the reading channel 9. The tested data, recorded in memory 2, are transmitted to the comparison device 3 through channel 10. In the comparison device, the data from two channels 9 and 10 are compared, and the result of the comparison is transmitted to the external environment through port 5 through the verification signal 3, which shows! the result of the comparison. This! method! it excludes the possibility of extracting the information from integrated circuit 1, thus ensuring a high degree of protection. The address of the reading and the steering signals can be generated by the external devices (not shown) and their introduction can be made through the address port! / Steering 6 of the interface 4.
MD 1844 B2 2002.01.31
The address / routing signals are transmitted to memory and direct the transmission of data from memory 2 to the comparator 3 by a standard method.
In the alternative embodiment of the invention (not shown), ports 5 and 7 are unified into a multiplex port for reading / recording, and port 6 is removed. The address and routing signals, which previously came to port 6, are transmitted through the multiplex port 7 of the unified port 5/7 and through the access channel 8.
The given scheme also gives the possibility to test the function of the recording in the program memory by electrically testing the data recorded in memory 2 through the data entry port 7 of the interface 4 and through the recording channel 8. The correct recording can then be verified by the method described above, also, under the direction of the address / direction signals. In this method, such properties can be tested, such as wear resistance, retention time, memory cell reliability.
It is possible to obtain unsanctioned access to the contents of memory 2 by testing all possible combinations of memory. It can be shown that this complicates the generation of several error signals. For example, if the error is generated after reading a single byte, which consists of eight bifi, then for the full byte test it must be read 256 times. However, if the error signal is generated only after a 16-bit word, for word testing it will have to be read 65536 times. Thus, for testing a word from 32 bifi, it will have to be read 4294967296 times. By applying the given scheme, exhaustive testing to obtain very simple memory content can be made unattainable.
An additional means of protection is the following: the words tested must exceed the limits of the memory page, possibly with the help of variable values.
Contents2
1 sheet
Sheet 1
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| MD3870G2 | Cited by | Republic of Moldova | Search report |
| EP0215464A2 | Cites | European Patent Office (EPO) | Search report |
| EP0215464A2 | Cites | European Patent Office (EPO) | Search report |
| EP0267114A1 | Cites | European Patent Office (EPO) | Search report |
| EP0276114A2 | Cites | European Patent Office (EPO) | Search report |
34 members in 24 offices
Priority claims8
| Document | Office | Kind | Date |
|---|---|---|---|
| 9414266 | United Kingdom | A | |
| 9414266 | United Kingdom | A | |
| 9501642 | United Kingdom | W | |
| 9501642 | United Kingdom | W | |
| 94142668 | – | – | – |
| GB19940014266 | – | – | – |
| PCTGB95001642 | – | – | – |
| WO1995GB01642 | – | – | – |
Members34
| Document | Office | Kind | |
|---|---|---|---|
| GB9414266D0 | United Kingdom | D0 | |
| CA2194289A1 | Canada | A1 | |
| WO9602917A1 | World Intellectual Property Organization (WIPO) | A1 | |
| AU2895595A | Australia | A | |
| ZA955806B | South Africa | B | |
| NO970112D0 | Norway | D0 | |
| NO970112L | Norway | L | |
| GB9626477D0 | United Kingdom | D0 | |
| GB2303950A | United Kingdom | A | |
| EP0770256A1 | European Patent Office (EPO) | A1 | |
| PL318166A1 | Poland | A1 | |
| EE9700015A | Estonia | A | |
| BR9508279A | Brazil | A | |
| JPH10503038A | Japan | A | |
| MX9700366A | Mexico | A | |
| AU692573B2 | Australia | B2 | |
| NZ289190A | New Zealand | A | |
| US5841786A | United States of America | A | |
| GB2303950B | United Kingdom | B | |
| EP0770256B1 | European Patent Office (EPO) | B1 | |
| AT176741T | Austria | T | |
| ATE176741T1 | Austria | T1 | |
| DE69507809D1 | Germany | D1 | |
| ES2126908T3 | Spain | T3 | |
| SI0770256T1 | Slovenia | T1 | |
| DE69507809T2 | Germany | T2 | |
| GR3029918T3 | Greece | T3 | |
| MD970057A | Republic of Moldova | A | |
| DK0770256T3 | Denmark | T3 | |
| TW371339B | Taiwan Province of China | B | |
| GEP19991885B | Georgia | B | |
| PL178997B1 | Poland | B1 | |
| RU2155996C2 | Russian Federation | C2 | |
| MD1844B2This record | Republic of Moldova | B2 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Pending applicationPD99 | PD99 |
Numbers
- Publication
- 0000001844
- Publication, DOCDB
- 1844
- Publication, EPODOC
- MD1844
- Application
- 970057
- Application, DOCDB
- 970057
- Application, EPODOC
- MD19970000057
Titles3
- English
- Method of testing the correct operation of memory and method of testing the content of memory
- Romanian
- Metodă de testare a funcţionării corecte a memoriei şi metodă de testare a conţinutului memoriei.
- Russian
- Способ тестирования правильной работы памяти и способ тестирования содержимого памяти
Classification
- CPC, 1
- G11C29/52
- IPC, 11
- G06F12 16
- G06F12 14
- G06F21 60
- G11C29 52
- G06F21 62
- G06F21 64
- G06K19 07
- G06K19 073
- G11C29 00
- G11C29 02
- G11C29 08