Device for on-line storage pseudoannular diagnostication

Description:

The invention relates to the technique of calculation and microelectronics and can be applied to the production and operation of superintegrated circuits with compact means inserted for testing and diagnostics.

The test method, known as pseudoinelial self-testing of operative memory devices with unipositive logic cells, is known, in that the number of test signals is chosen equal to that of the different stable states of a memory cell at the beginning of the test iterophy, first and second. test signals, are properly recorded in the first two cells of the device of the capacity m (m - the number of cells), then repeat the following operap m-2 times: read and assemble module two contained cells, in which the current test signals are retained, then the second test signal is interpreted as the first test signal, and the result of the modulo two assembly is interpreted as the second test signal, insert the second test signal into the next cell of the operating memory device; the combination of test signals with the control one is compared and in case of coincidence, the test iterations are performed with other non-initial combinations of the test signal values ​​until the first non-coincidence of the resultant combination with the control one and if there is such an incidence, decides that the operating memory device is defective [1].

The shortcoming of this method is that it does not ensure the diagnosis of operative memory devices.

The closest solution after the essence and the effect obtained is the self-test device of the operative memory that confines a synchronization register, the synchronization input of which is the synchronization input of the device, о group of three counters, operative memory (RAM), о bistable group, a logical addition element (adder) modulo 2 (OR EXCLUSIVE), the output of which is connected to the memory data input, or the input is connected to the output of the second bistable of the group, and the other input - at the output of the first bistable of the group, the data input of which is connected to the data input of the second bistable of the group and to the output of memory data, the address entries of which are connected respectively to the information outputs of the group counters, read-write entry - at the permission of the third meter of the group and at the fourth exit of the register, the third output of which is connected to the allowance input of the second meter of the group and to the synchronization (tact) input of the second bistable of the group, the second output - to the allowance input of the first meter of the group and to the tact input of the first bistable of the group, the first output - with the tact inputs of the group counters, whose tact input is connected to the device synchronization input [2].

The shortcoming of the device is that it does not contain the necessary means for diagnosing operating memory, including memory microcircuits.

The problem solved by the invention is to extend the functional performances of the device.

The essence of the invention is that in the pseudo-annular diagnostic device of the operative memory that confines a group of к counters (2 <к <r + 1), о operative memory, a modulo 2 adder (OR EXCLUSIVE), the output of which is connected to the input of memory data, a counter, a shift register, two multiplexers, three porphyries OR and a bistable are introduced, the tactile input which constitutes the device synchronization input and is joined with the third input of the three porphyry OR, the indirect output is connected to its data input, and the direct output - at the first input of the first porphyry OR, at the second input information of the first multiplexer, at the input of memory selection, at the first input of the porphyry OR OR and at the first (direct) entry of the porphyry OR, the output of which is connected to the tact input of the register, The outputs of which from 1 to r constitute the group of outputs of the device and are connected to the inputs of the modulo 2 adder, and the data input - to the memory output, the read-write input which is connected to the output of the three OR, and the address inputs - respectively at the outputs of the multiplexer two, the group of inputs from 1 to к which are connected respectively to the information outputs of the meters in the group, and the group of control inputs - respectively at the outputs of the group meters, whose tact input is united with the output of the first porphy OR, and the (indirect) output of the report - with the tact inputs of the meters in the group from 2 to k, with the input the second of the porphyry OR, with the second (indirect) entry of the porphyry OR, and with the first informational input of the first multiplexer, the control input whose connection is connected to the output of the counter к in the group and to the second input of the first porphy OR, and the output - at the tact input of the first meter in the group, the output of which is the STOP indication output of device.

The result of the invention consists in diagnosing the operative memory by recognizing and locating the defective memory cell (for constant defects).

At the same time, this technical result is obtained by executing the predefined r + 1 test iteraphs, as a result of which the defective cell will be determined, where r = Log₂ η, n - the capacity of the memory array. In fact, the result of the test iteration is the fact that memory confines ("yes") or does not confine ("no") о failure. And the combination of answers or decision of length r + 1, consisting of "yes" and "no", is unique for each case of failure (singular constant).

Figure 1 shows the structure diagram of the proposed device; in figure 2 - the electrical circuit of the multiplexer two; in fig.3 - the device operating time diagrams.

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The proposed device is composed of meter 1, group of meters 2, operating memory 3, modulo two adder 4, register 5, bistable 6, logic gates OR 7, 8 and 9, multiplexers 10 and 11, tact input 12, indication output 13 and the output group 14 (fig. 1).

The tact input 12 is connected to the third input of port three OR 9 and with the tact input of the bistable 6, the indirect output of which is joined with its data input, and the direct output - with the first input of the first port OR 7, with the second informational input of the first multiplexer 10, with the input of memory selection 3, with the first input of port three OR 9 and with the first (direct) input of port two OR 8, the output of which is connected to the tact input of the register 5 , the outputs of which 1 to r constitute the group 14 outputs of the device and at the same time, the outputs from 1 to к (2 <к <г +1) are connected to the inputs of the modulo two adder 4, and the data input - to the output of the unit memory 3, the read-write input whose connection is connected to the output of port three OR 9, and the inputs - respectively to the outputs of the multiplexer two 11, groups of inputs whose 1 to к are connected respectively to the information outputs of the meters of group 2, and the group of control inputs respectively to the group of outputs of meter 1, whose tact input is joined with the output of the first port OR 7, and the (indirect) output of the report - with the tactile inputs of the meters from 2.2 to 2.к in the group 2, with the second entry of the third gate OR 9, with the second (indirect) input of the second gate OR 8 and with the first informational input of the first multiplexer 10, the control input of which is connected with the output of the counter 2.к in group 2 and with the second input of the first gate 7 OR, and the output - with the tactile input of the first meter 2.1 in group 2, the output of the output which is output 13 indicating the STOP of the device.

Counter 1 can be built based on the microcircuits К155ИЕ7 [Шило В.Л. Популярные микросхемы ТТЛ, M., Аргус, 1993], ensuring the generation of values ​​in the range {0,1 ... к -1}; output of the report ТС_и of the respective microcircuit.

The counters of group 2 can be built on the basis of the microcircuits К155ИЕ7, ensuring the generation of values ​​in the range {0 ... n}; the output TCu of the microcircuit of the meter 2.к in group 2, connected to its output of the report, is reversed through a gate NO of the composition of the microcircuit К155ЛН1 [ШилоВ.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993].

Operational memory 3 of capacity n is the unit being tested and represents a known (static) operating memory microcircuit, for example the microcircuit К537РУ6 (or К132РУ5) [Микросхемы памяти ЦАП и АЦП. Справочник, 2-е изд., Стереотип. Лебедев О.Н., Марцинкявичюс А-И.К., Богданскис Э-А.К. и др., М „КУБК-а, 1996].

The adder module two 4 (OR EXCLUSIVE) can be built based on the microcircuit К555ЛП5 [Шило В.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993].

As a bistable 6, the type D bistable from the K155TM2 microcircuit [Шило В.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993]. The R and S inputs, not involved in the operation of the device, will be connected (for certainty) through a 1 kHom resistor to the log source. ' Г.

gates OR 7 and 8 can be used OR gates in the microcircuit К155ЛЛ1 [Шило В.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993], where the second input of the gate OR 8 is reversed through a gate NOT of the composition of the microcircuit К155ЛН1 [Шило В.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993], and the gate OR 9 with three entrances can be constructed on the basis of two gates OR with two entrances of the same microcircuit.

Multiplexer 10 is a switching element and can be constructed, for example, based on three I-NO logic gates with two inputs according to the standard circuit of multiplexers [Каган Б.М. Электронные вычислительные машины и системы, Учеб, пособие для вузов. М., Энергоатомиздат, 1985].

Multiplexer 11 is a switch, which unites the outputs of one of the group 2 counters with the address entries of memory 3; the number of the chosen meter is indicated by the output value of the meter 1. The multiplexer 11 can be made, for example, according to the circuit in fig. 2 and contains a group of multiplexers r 15.1 ... 15.r, the outputs of which are respectively the outputs of the multiplexer 11, the control inputs of which are connected respectively together and constitute respectively the control inputs of the multiplexer 11; the inputs 1 to r in the groups 1 to k of the inputs of the multiplexer 11 are connected respectively to the inputs 1 to k of the multiplexers in the group 15, ie the inputs of the first group are connected to the first inputs of the multiplexers in the group 15, the inputs of the group of two inputs - to the inputs of the multiplexers of group 15 etc., the inputs of the group of inputs k - to the inputs k of the multiplexers of group 15. As multiplexers of group 15, for example, the multiplexers in the microcircuit К155ИДЗ [Шило В.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993].

As a travel register 5, for example, the register in the microcircuit К555ИР11 [ШилоВ.Л. Популярные микросхемы ТТЛ, М., Аргус, 1993].

The device operates as follows.

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When connecting the sterile power supply to the register, counters, bistable and memory cells can be arbitrary.

The initial state of the bistable 6 can be set using the inputs set (S) and reset (R), for example, by applying the signals log.O and log.l respectively to the inputs S and R of the bistable in the microcircuit К155 TM2. After setting the bistable in the state log.l (at the direct output Q - log.l), the set and reset entries are established in the storage state, which does not influence the operation of the bistable D.

The initial states of the meter 1 and the meter group 2 are recorded using, for example, the parallel register input and applying the command signals required for the asynchronous setting. For example, in the microcircuits К155ИЕ7 for this purpose, the reset control inputs R, parallel permitting PE and data inputs D will be used.

The pseudo-annular diagnosis of the memory device 3 consists of performing ar +1 test iterations. The test hysteresis, according to the pseudo-test method [1], starts with the initiation of the first r cells with predetermined о state, executing linear transformations on the data from the memory cells by simulating the linear LFSR automatic and comparing the final LFSR states with the expected ones, previously calculated.

Initiation of memory cells with default status can be performed in the following mode. Counter 2.1 is reset. Counter 1 is set to state к -1, so its output is reset. The 2.к meter in group 2 is set to the maximum allowable state, ie n. In this case, the report output of the 2.к meter will be set in the log state. 1, which will close the gate OR 7 and connect the second input of the multiplexer 10 at its output, thus permitting the passage of the tactile signals from the output of the bistable 6 to the tact input of the meter 2.1. The value to be entered in the cell and memory 3 is provided by the sterile register 5 0 <i <r. The state of register 5 is initiated by the combination of the data inputs, which is inscribed with the back front of the tact signal.

The registration of the initial values ​​of the LFSR virtual register - the first r cells of memory 3, is performed within the sub-items of the initiated setting interval. At first the counters of group 2 are set in a predefined (default) initiated state. О subtitle consists of к tact - tact signals (the front front) reached from the direct output of the bistable 6. With each passing (apart from touch k) of the tact signal from log.O to log.l the data entry in register 5 takes place.

According to the known method [1] the pseudo-annular test of memory 3 consists of r +1 test iterations. At the beginning of each iteration in the first cells of the memory matrix, one of the combinations 0..00, 0..01, 0..011, 1..11 of length r is written. The number к of counters of group 2 is determined by the number of non-zero terms of the irreducible polynomial_r , φ (χ) = 1+ Σ^αί^χ> а, е {0,1}, which describes the structure (of the automatic) LFSR. For example, for the operating memory microcircuit K537 РУ 6 (or К132РУ5) of the capacity 12 Kbit the degree deg φ (.ν) of the polynomial (pfv) is equal to r = 12, and for this size the polynomial can be chosen, for example irreducible φ (.ν) 1 + jv³+ U · x¹+ jr¹² (Ярмолик BH, Демиденко С.H. Генерирование и применение псевдослучайных сигналов в системах испытаний и котроля. Мхнка So, к -1 = 4, that is (pfv) confines 4 non-zero terms - x³, x \ x¹ and _v¹².

At the same time, the powers of the terms of the polynomial (pfv) determine at the beginning of the test iteration the initiated state of the counters of group 2. For example, the initiated state of the counter 2.1, which corresponds to the term of the highest degree r, that is r = 12, is equal to no, that is 4096-12 = 4084, of counter 2.2 - with 4096-7 = 4089, of counter 2.3 - with 4092, of counter 2.4 - with 4093 and of counter 2.5 (that is, 2.к) - with 0. These stresses are initialized when applying the reset signal (the reset input is not shown in fig. 1).

The initialization of memory 3, that is, of the first r = 12 cells (from 0 to 11), proceeds in the following way. The subtitles are executed. Within these subheadings register 5, which is constructed as mentioned above based on the universal register K155 ИР11 (for the analyzed example it is necessary to connect in series 3 microcircuits К155ИР11), is set in the parallel recording (registration) mode (inputs S0 = log.O and Sl = log.l - are not shown in fig. 1). The data inputs (not shown in Fig. 1) of the К155ИР11 register will be used to record the data in register 5. The combination of data is selected in such a way as to ensure at the output of the adder 4 the required value of the current position of the LFSR virtual register. For example, if 0 is needed at the output of the adder 4, the combination can be from 0s, and if 1 is required at the output of the adder 4, in the input combination it must be о unit in one of the к positions of the combination and the rest - 0.

The address of the cell, in which the value from the output of the sum 4 will be written, will be indicated (discounted) by the counter 2.k. At the end of each test subtitle, when the signal from the output of the report of the meter 1 passes from log.O to log.l, it occurs incrementally to the meters of group 2.

Thus, at the end of the initialization subheadings, the required values ​​of the group 2 counters and the pre-declared status of the LFSR virtual register are ensured. For the example analyzed, we will have the following states of the group 2 meters: meter 2.1 - in state 0, meter 2.2 - in state 5, meter 2.3 - in state 8, meter 2.4 - in state 9 and meter 2.5 - in state 12.

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Although within the initialization subtitle the reading of memory 3 takes place, it will not influence the state of the register 5, because the output of memory 3 is connected to the data entry on the right, DSR.

After exhausting the initialization subheadings of the memory, the register 5 is switched to the right-shift mode (S0 = log.l and Sl = log.0), allowing data to be recorded from memory output 3.

This is how the test iteration proceeds (fig. 3).

The test hysteria consists of test subtitles that are executed in к tact: in к tact read and record sequentially in register 5 the cells of memory 3, located at the addresses indicated by the first к -1 counters in group 2, and in tact к the result of the sum of the module 2 on the read values ​​is entered in the memory cell, indicated by the counter 2.k. At the end of the sub-entry, when passing the report signal of meter 1 from log.0 to log.l, the increment of the counters of group 2 takes place, thus simulating the movement of the virtual LFSR register in the memory array 3.

After n test subtitles, that is, at the time when the meter 2.k goes to state n, the signal output log.l appears at its output, which closes the gate OR 7 and switches the second input of the multiplexer 10 to its output and the reading stage of the LFSR virtual register states is started, which is in the last cells of the memory array 3. Since the status of counter 1 is 0, the address entries of memory 3 are connected with the outputs of counter 2.1, which is touched (through the multiplexer 10) by the bistable 6; the reading input of the memory register 3 is in the log.l state, that is in the "reading" state. With each tact, the state of the meter 2.1 executes the increment from no to the value n, that is until the last cell of memory 3 is read; the values ​​from the memory output 3 are recorded in register 5. The signal, which appears at the report output of the meter 2.1 (fig. 3) and at the indication output 13 can be used as an indicator of the completion of the test iteration. In this case, the output value of register 5, ie from output 14, is compared with the expected (predefined) value. The result of the comparison is recorded.

As a whole, as mentioned above, r +1 test iteraphs will be executed. The decision vector, consisting of the results of the test iterations, univocally indicates the defective cell and the type of defect (if the defect is present in the memory matrix!). For this purpose, the decision table that confines the decision vectors and the defective cells with the indication of the type of defect corresponding to these vectors is constructed (for example, by simulation).

The pseudo-annular diagnostic procedure was considered, considered о memory matrix of capacity n = 7 bif. In this case r = \ Log₂ n | = 3, for which the polynomial φ (χ) = I + jF + x is selected³ . The result of the simulation of the r + 1 = 4 test iteraphs with the initial (binary) values ​​respectively 000, 001, 011, 111 are presented in table 1.

Table 1 a₅ of₄ of₃ of₂ oh yeah

RAM:

θι

<td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td> 0</td><td> .0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

<td> 1</td><td> 1</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 1</td>

<td> 1</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 1</td><td> 1</td>

<td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 1</td><td> 1</td><td> 1</td>

Init θι .. .θ₄ - test iteraphs.

The decision vectors are presented in table 2. In this table the note a (.) = 0 times a₍.) = 1 specifies the state of the cell that is locked in 0 or 1.

In case memory 3 will be the microcircuit К537РУ6 (К132РУ5) the diagnosis of pseudoin width will require r + 1 = 13 test iteraphs, and the decision table will contain 4094 decision vectors.

Thus, the application of the proposed device allows to diagnose the devices, including the microcircuits, of operative memory for the failures of type "locked 0" and "blocked 1".

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Table 2

<td>The hysteria that has not passed</td><td>Cell address and type of defect</td><td>The decision vector, 6) 626364</td>

<td>Θ1</td><td>of₀= 1</td><td> 1000</td>

<td>Θ2Θ3Θ4</td><td>of₀=0</td><td> 0111</td>

<td>Θ1Θ2</td><td>aj = 1</td><td> 1100</td>

<td>Θ3Θ4</td><td>a ^ 0</td><td>ООП</td>

<td> 6)6263</td><td>of₂= 1</td><td> 1110</td>

<td> 04</td><td>of₂= 0</td><td> 0001</td>

<td> 6)6364</td><td>of₃= 1</td><td> 1011</td>

<td> 02</td><td>of₃= 0</td><td> 0100</td>

<td> 6)6264</td><td>of₄= 1</td><td> 1101</td>

<td> 0₃</td><td>of₄= 0</td><td> 0010</td>

<td>Θ1Θ3</td><td>of₅= 1</td><td> 1010</td>

<td> 6₂6₄</td><td>of₅= 0</td><td> 0101</td>

<td> 6)64</td><td>of₆= 1</td><td> 1001</td>

<td>Θ2Θ3</td><td>of₆=0</td><td> 0110</td>

- test iteration passed, 1 - the test iteraph is not passed.