On-line self-testing memory

Description:

The invention relates to the technique of calculation and microelectronics and can be applied to the production and exploitation of the superintegrated circuits equipped with compact means of testing and diagnostics.

It is known the memory device with self-testing that contains address counter, memory (tested), two registers - one data and another output, two bistables - first and second, о synchronization input, о reset input, inputs and outputs information [1].

The disadvantage of the method lies in the complexity of the test due to the long duration and the low resolution compared to the interaction defects (inter-influence) of the memory cells.

The test method, known as pseudo-annular self-testing of operative memory devices with unipositioned logic cells, is known, in that the number of test signals is chosen equal to that of the different stable states of a memory cell, at the beginning of the first iteration and of the test iteration. the second test signals are properly recorded in the first two cells of the device of the capacity m (m - the number of cells), then repeat the following operations m-2 times: read and assemble module two contained cells, in which the current test signals are kept, then the second test signal is interpreted as the first test signal, and the result of the module assembly 2 is interpreted as the second test signal , the second test signal is entered in the next cell of the operative memory device; compare the combination of test signals with the control one and in case of coincidence, the test iterations are performed with other non-zero combinations of the values ​​of the test signals until the first mismatch of the result combination with the control one and in this case it is decided that the device the working memory is defective [2].

The disadvantage of this method (and of the device in question) is that the testing of the operative memory devices, including the memory circuits, with multi-position logic cells, ie with the binary of the word n> \, is not ensured.

The closest solution according to the essence and the result obtained is the self-test device of the operative memory that confines a synchronization register, the synchronization input which is the synchronization input of the device, a group of three counters, the reset inputs which are connected with the input for resetting the synchronization register and at the device reset entry, the operating memory (RAM), a group of bistables, one adder (summation logic element) modulo q, q = 2 (- or exclusively), the output of which is connected to the data input of the memory, о input is connected to the output of the two flip-flops, and the other input - to the output of the first flip-flops, the input of data which is connected to the data entry of the two flip-flops and to the data output of the memory, the address entries of which are connected respectively to the information outputs of the counters, read-write input - at the allowance of the counter three and at the fourth output of the register, the third output whose connection is connected to the allowance of the counter two and to the synchronization input (tact) of the bistable two, the second output - at the input of permitting the first meter and at the tact input of the first bistable, the first output - at the tact inputs of the meters [3].

The disadvantage of the device is that it does not allow the testing of the operating memory, including the memory microcircuits, with cells of binary n greater than 1, that is, with multiposition cells.

The problem that the invention solves is the extension of the functional performances of the device.

The essence of the invention is that in the self-test operating memory, which contains a synchronization register, whose tact input is connected to the tact input of the device, a counter with the reset input connected to the reset input of the synchronization register and to device reset input, decrement input - at the second output of the synchronization register, and the information outputs of the meter are joined with the address entries of the operating memory, a modulo adder q, additionally a group of two registers are included, the outputs of the first register being connected respectively to the first group of entries of the adder, the outputs of the second register being connected respectively to the two input group of the adder, a switch, Outputs - bidirectional inputs whose connections are connected respectively to outputs - bidirectional inputs of memory data, inputs - respectively to the outputs of the modulo summator q, outputs - respectively to the data inputs of the group registers, о logic gate and, the output of which is connected to the input memory selection, the first logic gate OR, the output of which is connected to the increment input of the counter, the second input - at the tact input of the second register in the group and at the fourth output of the synchronization register, the second logic gate OR, the output of which is connected to the read-register memory input, the first input - the first input of the gate AND also at the tact input of the device, and the second input - at the second input of the gate AND, at the switch input of the switch and at the second output of the synchronization register, the third logic gate OR, о whose input is connected to the counter output of the counter, the other input - at the first input of the first gate OR or at the third output of the synchronization register, and the output - at the tact input of the first register in the group.

The result that can be obtained by carrying out the invention consists in self-testing the operative memory device with the absolute resolution of 100% for the constant defects of the memory matrix cells.

MD 1995 G2 2002.08.31

At the same time, this result is obtained due to the fact that the process (algorithm) of self-testing is performed in three test iteraphs, and as demonstrated in the generated Analysis of the resolution of the RAM pseudo-ring test. [Acta Academia, 1999, p. 169], g will be detected initially²/ (G²+ g + l) defects, then q / (q²+ q + Y defects and finally l / (g²+ g + l) defects from burn defects, q = 2ⁿ presents the characteristic of the Galois (extended) field. Thus the total amount of defects will be equal to 1, ie 100%.

In FIG. 1 shows the structural diagram of the proposed device; in FIG. 2 - the electric circuit of the synchronization register; in FIG. 3 - device operating time diagrams.

The proposed device is composed of the synchronization register 1, the counter 2, the operating memory 3, the modulo summator q 4, a register group 5, the reset inputs 6 and tact 7, the switch 8, о logic gate AND 9, three logic gates OR 10, 11, 12 (fig. 1).

The tact input 7 is joined by the tact input of the synchronization register 1 and with the first gate entries ȘI 9 and OR 11, the reset entry 6 communicates with the reset entries of the synchronization register 1 and the counter 2, the decrement input of which is coupled with the second output of the synchronization register 1, with the two inputs of the gates AND 9, OR 11 and with the switching input of the switch 8, the incremental input with the output of the gates OR 10, the output of the report - with the first entry of the porphyry OR 12, and the informational outputs respectively with the address entries of the memory 3, the selection entry, which is connected to the exit of the porphyry AND 9, the reading-recording entry - at the exit of the porphyry OR 11, and Outputs - bidirectional data inputs respectively to outputs - bidirectional inputs of switch 8, the outputs of which are joined respectively with the data inputs of registers 5, and the inputs - respectively with the outputs of the adder modulo q 4, the first group of inputs whose communicates respectively with the outputs of the first register 5.1, and the second group of inputs - respectively with the outputs of the second register 5.2, whose tact input is connected to the second input of porphyry OR 10 and at the fourth exit of register 1, the third exit of which is connected to the first entrance of porphyry OR 10 and to the second entrance of porphyry OR 12, the output of which is joined to the tact input of register 5.1.

The synchronization register 1 can be made, for example, according to the circuit in fig. 2, containing four bistables 1.1, 1.2, 1.3 and 1.4, the outputs of which are the outputs of register 1, at the same time the output of bistable 1.4 is connected to the data input of bistable 1.1, the output of which is connected to the data input of bistable 1.2, whose output communicates with the data input of the bistable 1.3, the output of which is coupled with the data input of the bistable 1.4, the tactic input whose is combined with the tactic input of the bistable 1.1, 1.2, 1.3 and with the tact input of register 1, and the reset input - with the setting inputs of bistables 1.2, 1.3, the reset input of bistable 1.1 and with the reset entry of register 1.

As bistables I can use RS bistables from KI microcircuit 55 micr2 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993]. The R and S inputs, not involved in the operation of the device, will be connected (for certainty) through a 1 kQ resistor to the logic source 'Г.

Counter 2 is a well-known device and can be built on the basis of microcircuits К155ИЕ7 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993], ensuring the generation of values ​​in the range {0,1, ..., m-1}; TC report output_D of the respective microcircuit, which is connected to the output of the counter 2, is reversed by means of a porphyry NO from the component of the microcircuit К155ЛН1 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993].

Operational memory 3 with the binary words of n bifi (n> l and q = 2ⁿ) is the unit being tested and represents a known (static) operating memory microcircuit, for example, the microcircuit К537РУ13 [Микросхемы памяти. ЦАП и АЦП: справочник. 2-е изд., Стереотип. О.Н. Лебедев, А-Й.К. Марцинкявичус, Э-А.К. Богданскис и др., М, КУБК-а, 1996].

As registers in group 5 I can use, for example, registers from the microcircuit К155ИР11 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993], in which the reset input and the SO and SI inputs are logically connected (through a 1 kQ resistor).

Modulo q 4 adder is a specialized device, which for the two input words of binary n (each) properly presents a word of binary n. PT1 of 256 x 4 capacity [Микросхемы памяти. ЦАП и АЦП: справочник. 2-е изд., Стереотип. О.Н. Лебедев, А-Й.К. Марцинкявичус, Э-А.К. Богданскис и др., М, КУБК-а, 1996]. The memory microcircuit is programmed to produce the polynomial modulus assembly table q (Z) in the extended Galois GF field (2).ⁿ) of the tenons of the generating polynomial φ (Χ), q (Z) - irreducible polynomial of degree n, that is deg </ (Z) = ii and the coefficients in the field GF (2). The polynomial φ (Χ), according to the test method [2], is a primitive irreducible polynomial of the structure cp (X) = l + ax + bx², where a, be {0,1, ..., 2ⁿ-l} are representations of the polynomials of degree n in the field GF (2), n - the binary of the cells of the memory matrix.

For the inverse structure of the polynomial φ (Χ) in the field GF (2⁴) can be chosen, for example, the irreducible polynomial subset: φ (Χ) = 1 + χ + 9χ² with the minimal polynomial g (Z) = l + z + z⁴. Assembly table x + 9x² (mod 1 + z + z⁴), go ft:

MD 1995 G2 2002.08.31

Table 1

<td>^ \ Xx^r9\^</td><td> 0</td><td> 1</td><td> 2</td><td> 3</td><td> 4</td><td> 5</td><td> 6</td><td> 7</td><td> 8</td><td> 9</td><td> 10</td><td> 11</td><td> 12</td><td> 13</td><td> 14</td><td> 15</td>

<td> 0*9=0</td><td> 0</td><td> 1</td><td> 2</td><td> 3</td><td> 4</td><td> 5</td><td> 6</td><td> 7</td><td> 8</td><td> 9</td><td> 10</td><td> 11</td><td> 12</td><td> 13</td><td> 14</td><td> 15</td>

<td> 1*9=9</td><td> 9</td><td> 8</td><td> 11</td><td> 10</td><td> 13</td><td> 12</td><td> 15</td><td> 14</td><td> 1</td><td> 0</td><td> 3</td><td> 2</td><td> 5</td><td> 4</td><td> 7</td><td> 6</td>

<td> 2*9=1</td><td> 1</td><td> 0</td><td> 3</td><td> 2</td><td> 5</td><td> 4</td><td> 7</td><td> 6</td><td> 9</td><td> 8</td><td> 11</td><td> 10</td><td> 13</td><td> 12</td><td> 15</td><td> 14</td>

<td> 3*9=8</td><td> 8</td><td> 9</td><td> 10</td><td> 11</td><td> 12</td><td> 13</td><td> 14</td><td> 15</td><td> 0</td><td> 1</td><td> 2</td><td> 3</td><td> 4</td><td> 5</td><td> 6</td><td> 7</td>

<td> 4*9=2</td><td> 2</td><td> 3</td><td> 0</td><td> 1</td><td> 6</td><td> 7</td><td> 4</td><td> 5</td><td> 10</td><td> 11</td><td> 8</td><td> 9</td><td> 14</td><td> 15</td><td> 12</td><td> 13</td>

<td> 5*9=11</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 15</td><td> 14</td><td> 13</td><td> 12</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td>

<td> 6*9=3</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 15</td><td> 14</td><td> 13</td><td> 12</td>

<td> 7*9=10</td><td> 10</td><td> 11</td><td> 8</td><td> 9</td><td> 14</td><td> 15</td><td> 12</td><td> 13</td><td> 2</td><td> 3</td><td> 0</td><td> 1</td><td> 6</td><td> 7</td><td> 4</td><td> 5</td>

<td> 8*9=4</td><td> 4</td><td> 5</td><td> 6</td><td> 7</td><td> 0</td><td> 1</td><td> 2</td><td> 3</td><td> 12</td><td> 13</td><td> 14</td><td> 15</td><td> 8</td><td> 9</td><td> 10</td><td> 11</td>

<td> 9*9=13</td><td> 13</td><td> 12</td><td> 15</td><td> 14</td><td> 9</td><td> 8</td><td> 11</td><td> 10</td><td> 5</td><td> 4</td><td> 7</td><td> 6</td><td> 1</td><td> 0</td><td> 3</td><td> 2</td>

<td> 10*9=5</td><td> 5</td><td> 4</td><td> 7</td><td> 6</td><td> 1</td><td> 0</td><td> 3</td><td> 2</td><td> 13</td><td> 12</td><td> 15</td><td> 14</td><td> 9</td><td> 8</td><td> 11</td><td> 10</td>

<td> 11*9=12</td><td> 12</td><td> 13</td><td> 14</td><td> 15</td><td> 8</td><td> 9</td><td> 10</td><td> 11</td><td> 4</td><td> 5</td><td> 6</td><td> 7</td><td> 0</td><td> 1</td><td> 2</td><td> 3</td>

<td> 12*9=6</td><td> 6</td><td> 7</td><td> 4</td><td> 5</td><td> 2</td><td> 3</td><td> 0</td><td> 1</td><td> 14</td><td> 15</td><td> 12</td><td> 13</td><td> 10</td><td> 11</td><td> 8</td><td> 9</td>

<td> 13*9=15</td><td> 15</td><td> 14</td><td> 13</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td>

<td> 14*9=7</td><td> 7</td><td> 6</td><td> 5</td><td> 4</td><td> 3</td><td> 2</td><td> 1</td><td> 0</td><td> 15</td><td> 14</td><td> 13</td><td> 12</td><td> 11</td><td> 10</td><td> 9</td><td> 8</td>

<td> 15*9=14</td><td> 14</td><td> 15</td><td> 12</td><td> 13</td><td> 10</td><td> 11</td><td> 8</td><td> 9</td><td> 6</td><td> 7</td><td> 4</td><td> 5</td><td> 2</td><td> 3</td><td> 0</td><td> 1</td>

In this case, as the first group of addresses of adder 4, for example, the address entries A can be selected₀... A₃ of the K541PT1 microcircuit, and as the second group of addresses - entries A₄... A₇of the same microcircuit. The first group of addresses will indicate (mean) the number of the column, and the second group of addresses - the row number of the table analyzed. At the preparatory stage, for the groups of addresses indicated by successively selecting the values ​​of the addresses - from 0 to 15, in the respective cells of the programmed memory K541PT1 the corresponding sizes from the tab will be written. 1.

As a result of gathering the input sizes, for example, 12, which comes from register 5.2 - the position of the virtual register x, and 14, which comes from register 5.1 - the position x² of the virtual register, at the output of the adder 4, according to the table, the size 11 will appear (see column 12 and row 14 of table 1). This size corresponds to the combination of four 1011 bars₂.

As a switch 8 can be used, for example, the microcircuit К589АП16 [Микропроцессоры и микропроцессорные комплекты интегральных микросхем: справочни В / Б.Б. Абрайтис, Н.Н. Аверьянов, А.И.Белоусов, под ред. В.А.Шахнова, М, Радио и связь, 1988. Tl], the selection input (CS) to which it is connected! logic 0.

As a bear! And 9 can be used! gate AND from the component of the microcircuit К155ЛИ1 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993]; and as porphyry OR 10, 11 and 12 - the pores OR of the microcircuit К155ЛЛ1 [Шило В.Л. Популярные микросхемы ТТЛ. М, Аргус, 1993].

The synchronization register 1 is intended for the cyclical displacement of the zeros to the bottom of the units (that is, the binary combination 0111₂). Counter 2 is intended for generating memory cell addresses for reading and recording operations. The registers in group 5 are destined to store (keep) the current values ​​of the test signals (memory cell states) of characteristic 2ⁿ”.

The device works! in unn! tor mode.

When connecting the sterile power supply to the registers, the meter and the memory cells can be arbitrary.

The initial tailings of registers 5 are registered using, for example, the entry of serial registration and applying command signals! required. For example, for the characteristic q = 2⁴= 16 to 0₁₆ and 1₁₆ they will correspond to the binary sequences of length n = 4, respectively, 0000₂ and 0001₂. (In registers 5 these sequences are written from left to right).

The combinations of initial stresses that must! either recorded in registers 5, according to the test method [2], must! ensures the combinations of initial test signals of the virtual register of the LFSR structure. These combinations for each iteration of the test are 00, 01 and 10 (in the positive computation system based on q).

In the initial moment of time the positions of the virtual register, which correspond to the ten x¹ and x² of the polynomial φ (Χ), I am the first one respectively! of memory 3 (in the analyzed case it is at address 0) and the first register 5.1. Inifial status! the first memory cell is entered! as a result of the modulo sum the polynomial q (Z) on the contents of registers 5. In this case, obviously c! inifial state! of register two 5.2 must! be chosen! so that at the output of the sum of 4 s! be assured! the inifial value! predetermined! for the first one! of memory.

To obtain the default initial sterile of the first memory cell, which are 0, 0 and 1 (while those of register 5.1 are respectively 0, 1 and 0), in register two 5.2, according to tab. 1, in each test iteration the values ​​0, 9 and 1 must be entered initially.

MD 1995 G2 2002.08.31 в

At the initial moment of time at input 6 of the device reset the log level is set. 0. Log level. 0 of the reset signal resets the counter 2 and installs the synchronization register 1 in the state '0111'.

Thus the test device is installed in the initiated state.

After deactivation of the reset pulse (ie, return to log. 1 level) from the input 1, the synchronization pulses 1a input 7 is generated (fig. 3) and the test iteration begins. The test iteration confines the subtitles to four tactics.

The first test subtitle consists of greasers.

The first tact is preparatory and executed "empty".

In the second tact, according to the diagrams presented in fig. 3, the signal log. 0 from the second output of the synchronization register 1 sets the memory selection input 3 in the active state, ie SELECTED, switches the inputs of the switch 8 to its inputs-outputs and opens the gate OR 11 for passing the tactile impulse to the read-recording input. of memory 3. When passing the positive front of the tactile impulse, the data from the output of the adder 4 in the first cell (with address 0) of the memory 3 takes place, the decrements of the counter 2 (its value becomes equal to m-1) and, as a result, the output of the report of counter 2 is set in the log state. 'Г, which does not allow the passage of signals through the gate OR 12.

In the third tact the switching of the bidirectional inputs-outputs of switch 8 to its outputs takes place (DC = 'U), memory 3 is other in read state (W / R = l), and state' 0 'from the third output register 1 allows the passage of the tact signal to the incremental input of the meter 2, which leads to the restoration of the meter status, that is to say "0", and the status of the report output, which is set in the log. '0'.

Finally, the fourth tact, when the tact signal goes through the log. '0' in log. '1', includes the registration (fixing) of the confinement of the respective cell (address = 0) of memory 3 in the second register 5.2 increments of the meter 2 and the conclusion of the selection operation of memory 3.

In the next subtitle, in the second tact the registration of the modulo q from the output of the adder 4 in the actuated cells of the memory 3 and the decrements of the meter 2, ie the passage of the previous cell, takes place. In the third tact, because the report state of the meter 2 is equaled with '0', the current state of the respective cell of the memory 3 m takes place the register 5.1 and increments of the meter 2. The operations in the fourth tact are the same as in the previous subtitle.

Thus, in this subtitle according to [2], о virtual displacement of the {virtual) linear automaton is realized (ie, read and assembled specifically (according to the structure of the generating polynomial φ (Χ)) modulo the polynomial q {Z) contained of two memory cells, and the result of the assembly is entered in another memory cell (the greaser), which together with the memory cells preceded by the greased pair of processed cells.

The subtitle, described above, is repeated until the last 1a memory cells with the address m-1 are reached (fig. 3). In this case, the iteration of the test is finalized in the undo mode.

The final subtitle (the zeros are in the second position of the register 1) begins with the registration of the result - the modular sum of the polynomial q {Z) in the last cell of memory (address = 'т-Г). Counter 2 is in the maximum permissible state, therefore its (direct) report output is set to the 1 log level. 0. Then, in the non-tactile zero, the zero being in the third position of the register 1, the value of the meter 2 decreases by 1, that is, it decreases, indicating the address 'm-2' of the penultimate cell m-1 of memory, and the output of the report of the meter 2 is restores 1a log level. 1. The passage from Ό'm Ί 'of the tactile signal causes the passage of 0 from the third position to the fourth position of the register 1 and, as a result, the confinement of the respective memory cell in register 5.1 and the increase of the meter 2. In the fourth tact the contents of the memory cell with the address 'm-1' are entered in register 5.2, and the status of meter 2 is equal to 0, which can be used as an indicator for completing the test iteration.

At the end of the last sub-entry, the states of the registers 5 are compared with the preset ones and in case of non-coincidence it is accepted the hypothesis that the test unit, that is the operative memory 3, is defective. Otherwise, according to [2], other test iteraphs are performed with other initial combinations of the declared ones.

Next, it will be analyzed the self-test iteration considering the microcircuit К537РУ13 as tested operating memory. This microcircuit has binary memory cells equal to 4, characteristic q = 2⁴; capacity = IK.

Let the test iteration start with the combination of test signals equal to 10₁₆, ie in the first register 5.1 the value 1 will be entered₁₆(=0001₂), and in the second register 5.2 - value 9₁₆(= 1001₂).

At the output of adder 4, the sum of the mod (7 + z + z⁴) of these values ​​which, according to tab. 1, equals 0 (see column 9, row 1), or at the exits of adder 4 will be the binary combination 0000₂ (from the 1st right to the left - at the exits of the group of 1 1 1a 4 of the adder 4). The value from the additions of the sum 4 will be entered in the cells with the address 0 (see the first tact of the first iteraph, fig. 3) of the memory 3, which ensures the establishment of the initial state in the first position (x¹) of the virtual register.

In the fourth tact of the first sub-entry, the cell with the address 0 and the registration of its confinement in the second register 5.2 takes place. From this moment, for the following test subtitles, the first register 5.1 will be the "carrier" of the states of the first test signal (according to [2]), that is, in the virtual machine register 5.1 will play

MD 1995 G2 2002.08.31 the role of the second position of the virtual register, and the second register 5.2 - the role of the first position of the virtual register (the positions of the virtual register are numbered from left to right).

(This leads to the fact that the states of the first register 5.1 will indicate the number of the row, and the states of the second register 5.2 - the number of the column m table 1).

Suggestively these tactics can be presented abstractly in the following way:

<img file="MD1995G2_D0001.tif" />

where: RAM - the cells (from 0 to m-1) of the operating memory matrix 3; Rgl - first register 5.1; Rg2 the second register 5.2; Θ - sum of the polynomial modulus g (Z).

In the second sub-entry the registration of the amount 9® Ιξ | will take place (or 9 + 1 (mode l + z + z⁴) = l) in the following memory cell with address 1 and the contents of the previous cell with address 0 and the current cell with address 1. will be read. At the abstract level, after two subtitles, the following picture is outlined:

<img file="MD1995G2_D0002.tif" />

Voter. In the line "RAM" is presented the sequence 9, 0, 1 which represents the successive (correct) states of the virtual register positions.

After the third sub-entry the painting will be the following:

<img file="MD1995G2_D0003.tif" />

At the end of the last sub-entry the first register 5.1 will confine the state of the penultimate cell, with the address m-2, and the second register 5.2 - the state of the last cell, with the address m-1. These states will represent the combination of final (test) signals that must be compared to the control.

<img file="MD1995G2_D0004.tif" />

MD 1995 G2 2002.08.31

For example, m the case analyzed for combination 10₁₆ of test signals the combination of control is 10₁₆.

It is known that for complete pseudo-annular self-testing (with 100% resolution), when the register of the linear machine consists of two positions, ie Deg φ (Χ) = 2, three test iteraphs are required. As default values ​​of the automatic register, the combinations 00, 01 and 10 (based on q) are sufficiently chosen.

Thus, the application of the proposed device allows to perform the self-testing of the memory microcircuits with the n arbitrary binaries of the memory cells (n&gt; l). The resolution of the test in relation to the constant defects of the memory cells is absolute and equal to 1 (100%).