On-line memory with compact self-testing

Invenfia refer! to the calculation and microelectronic techniques! and it can be applied! to the production and exploitation of microcircuits with compact means incorporated for testing and diagnostics.

It's known! the compact self-test method of working memory devices! with single-position logic cells that consist! in that c! The number of test signals is chosen equal to that of the different stable states of a memory cell. At the beginning of the test iteration, the first and second test signals are properly registered in the first two! device cells with the capacity m (m is the cell number), then repeat! m-2 times all the operations: read and gather! module two (the logical operation! XOR) the cells contained in which they are stored! the current test signals, then the second test signal is interpreted as the first test signal, and the result of the modulo two assembly is interpreted as the second test signal, the second test signal is inscribed in the no. cellulite! of the operating memory device! compare! The resulting combination! of test signals with the one of selection and in case of coincidence it is performed! test iteraphs with other initial combinations of test signal values ​​up to! the first incident! of the resulting combination with the one of selection and in case of non-coincidence! it is decided c! the operative memory device! is defective [1].

The disadvantage of this method is const! in that c! I'm not sure! detection of dynamic defects.

The closest! Solution is the self-test device for operating memory that confines о reset input, о synchronization input, a group of select inputs, о indication output, a synchronization register, a group of three counters, operational memory! (RAM), a group of bistables, an XOR logic element, the output of the battery is connected! at the data entry of the memory, its input is connected! at the exit of the group's two-seater, and the other! input - at the output of the first bistable of the group, the reset input of the device is connected! at the registry and meter reset entries, the indication output - at the output of the group number three report, the selection entries - respectively at the synchronization register selection entries, and the input synchronization - at the synchronization entry of the synchronization register, the first output is connected! at the synchronization inputs of the group counters, the second output - at the pen entry of the first number of the group and at the synchronization entry of the first bistable of the group, the third output - at the pen entry of the number the second output of the group and at the synchronization input of the second bi-fold of the group, and the fourth output - at the pen entry of the third digit of the group and at the read-write memory entry, the address entries of the company are connected respectively to the information outputs of the group counters, and the data output - to the data entries of the group bistables [2].

The disadvantage of the device is! in detecting dynamic defects in memory cells.

The problem I solve! invention const! in improving the resolution of testing of operative memory devices!

The device, according to the invention, is removed! the disadvantages mentioned above in that c! confine a synchronization register, the synchronization input is connected! at the device synchronization input, a counter, the reset input is connected! at the registry reset input and the device reset input, and the report output is the indication output of the connected device! at the counter, о working memory !, the entry of access addresses is connected! at the output of the meter, a group of bistables, consisting of the first and second bistables, an XOR adder, the entrances of the group are connected to the exits of the bistables of the group. The novelty of the invention consists! in that c! the device additionally contains:

- a group of multiplexers, consisting of the first and second multiplexers, and a selection input, which is connected! at the selection inputs of the group multiplexers; first informational entry! of the second multiplexer of the group is connected! at the first output of the synchronization register, and the second informational entry! his - at the third output of the synchronization register; first informational entry! of the first multiplexer of the group is connected! at the second output of the synchronization register, and the second informational entry! his - at the fourth output of the synchronization register;

- a group of XOR logical portfolios, consisting of the first and second gates! logical! XOR, and о pair of negation entries, о negation input is connected! at one of the entrances of the first XOR logical portfolios of the group, the other! the access entry is connected! at the output of the XOR adder, and its output - at the data entry of the operating memory, о another! The business entrance is connected! at one of the entrances of the two logical XORs of the group, the other! being connected! at the output of the operating memory;

- an additional multiplexer, the first informational input! home is connected! at the exit of the XOR adder, the second informational entry! - at the output of the second XOR logic port of the group, the output - at the data entry of the first bistable of the group, and the selection input - at the data entry of the synchronization register, at the output of the first multiplexer of the group, at the synchronization input of the counter and at the entry of read-write the operative memory;

- I'm wearing it! logical! OR, о the input of the access is connected! at the output of the second multiplexer of the group, the other! input - at the selection input of the operating memory and at the input of the device synchronization, and the output - at the synchronization inputs of the bistable group, at the same time! the output of the first bistable of the group is connected! at the data entry of the second bistable of the group.

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The result obtained by carrying out the invention consists in self-testing the operative memory device with the absolute resolution of 100% for dynamic defects. This result is obtained by the fact that by dynamically reconfiguring (during testing) the reaction links and applying the appropriate test combinations initiated, the conditions of sensitization of the defects and of their transport to the primary outputs of the device are ensured, so that at the end of the test, after the execution of the 15 test iteraphs, the absolute value of 100% of the resolution is reached.

The invention is explained by the drawings in fig. 1-4, which represents:

FIG. 1, the structure diagram of the proposed device;

FIG. 2, the electrical diagram of the synchronization register;

FIG. 3, the device operating time diagram;

FIG. 4, the device operating time diagram.

The proposed device is composed of synchronization register 1, counter 2, operating memory 3, a group of bistables 4, о XOR logic gate 5, reset inputs 6 and synchronization 7, indication output 8, a group 9 of multiplexers (9.1 and 9.2), о logic gate OR 10, a group 11 of XOR logic portfolios (11.1 and 11.2), the additional multiplexer 12, the selection input 13, a group of negation inputs 14 (fig. 1) · '

The reset input 6 is connected to the register 1 reset input and the meter reset input 2, the output of which is the device output indication 8, the information output is connected to the memory address input 3; the selection input 13 is connected to the selection inputs of the multiplexers 9.1 and 9.2, the first information input of the second multiplexer 9.2 is connected to the first output of the synchronization register 1, and the second information input - to the third output of the synchronization register 1, the second output of which is connected to the first informational input of the first multiplexer 9.1, the fourth output - to the second informational input of the first multiplexer 9.1, the output of which is connected to the data entry of the synchronization register 1, to the input of synchronization of the meter 2, to the input of selecting the multiplexer 12 and to the input of read-write memory 3, the data input of which is connected to the output of the first XOR 11.1 porphyry, and the output - at one of the two logical XOR 11.2 porphyry inputs, the other inputs of which are connected to the inlet of the negation group 14 of the device, the other negation input of the group 14 being connected to one of the inputs of the first XOR 11.1 logical port, the other input which is connected to the output of the XOR 5 logical port and to the first information input of the multiplexer 12, the second information input of which is connected to the output XOR 11.2 logical second porphyry, and the output - at the data entry of the first bistable 4.1, the output of which is connected to the data input of the second bistable 4.2 and to the о input of the logical port XOR 5, the other input which is connected to the output of the two bistable 4.2, the synchronization input of which is connected to the synchronization input of the first bistable 4.1 and at the output of the logical gate OR 10, о whose input is connected to the output of the two multiplexer 9.2, and the other input - at the input of selecting memory 3, at the synchronization entry of the register 1 and at the synchronization entry 7 of the device.

The synchronization register 1 performs the cyclic displacement of the logical unit log. 1 (against the zeros background) and can be implemented, for example, according to the scheme presented in fig. 2 and confines four bistables: 1.1, 1.2, 1.3, 1.4, the outputs of which are the outputs of register 1, at the same time, the data entry of the bistable 1.1 is connected to the data entry of the register 1, the output - to the data entry of the bistable 1.2, the output of which is connected to the input of bistable data 1.3, the output of which is connected to the data input of bistable 1.4, the synchronization input of which is connected to the synchronization inputs of the bistable 1.1, 1.2, 1.3 and at the synchronization entry of register 1, and the reset entry - at the reset inputs of the bistables 1.2 and 1.3, at the setting entry of the bistable 1.1 and at the reset entry of the synchronization register 1.

As bistables 1.1, 1.2, 1.3, 1.4 can be used D-bistables from the microcircuit component K1531TM2 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус, 1999]).

Counter 2 is a well-known device and can be built on the basis of microcircuits К1531ИЕ10 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус, 1999]).

Operating memory 3 with 1-bit cell binary is the unit being tested and represents a known (static) operating memory microcircuit, for example, the К537РУ14 microcircuit (see [Микросхемы памяти, ЦАП и АЦП. -Й.К. Марцинкявичус, Э.-А.К. Багданскис и др., Москва, КубК-а, 1996]).

Bistables 4.1 and 4.2 record the data from the memory output 3. The data recording takes place at the timing of the synchronization signal C from '0' in 'Г. At the same time, when the selection signal of the multiplexer 12 is in the log state. 'O', a linear reaction link (from which XOR 5 logic component is part) is formed and the bistables of group 4 play the role of the cells of the corresponding linear automaton's shift register. As bistables 4.1 and 4.2, the D-bistables from the K1531TM2 microcircuit component can be used, and as the XOR 5 logic gate - the XOR logic gate from the К1531ЛП5 microcircuit component (see [Нефедов AB Интегральныу, микрор, Микров, Микр .

The first multiplexer 9.1 of the group is intended for configuring the feedback link of the register

1. The second multiplexer 9.2 of the group is intended to block the passage of the synchronization signal at the time of the transition from the recording mode to the memory reading mode or vice versa. Into the

MD 3984 G2 2009.11.30 as the group 9 multiplexers can be used, for example, the two input multiplexers from the microcircuit component of the К1531КП11 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус), 1999)

As logical gate OR 10 - о logical gate OR from the microcircuit component К1531ЛЛ1 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус, 1999]); as XOR logical portfolios of group 11 - XOR logical pores from the microcircuit component of the К1531ЛП5 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус, 1999]); as multiplexer 12 - multiplexer with two inputs of the microcircuit component of the К1531КП11 (see [Нефедов AB Интегральные микросхемы ТТЛ. Москва, Аргус, 1999]).

The synchronization register 1 is intended for generating the synchronization signals of the components (units) of the self-test device. Counter 2 is intended for generating memory addresses 3. The number of cells in the counter equals the binary of the address lines of memory 3. The logic gate OR 10 is intended for blocking (log. 1) or allowing (log. 0) to pass the synchronization signal. . The XOR logical pores of group 11 are intended for inverting (negating) the signal at the data entry and / or at the memory output 3.

The device operates in the non-greasing mode.

When connecting the power supply, the states of the bistable ones, the register, the meter and the memory cells can be arbitrary.

At the initial time point at the reset input 6, the logic level '0' is set and at the synchronization input 7 - the logic level 'Г (fig. 3), and at the negation entries 14 the combination targeted by the self-test algorithm is set. At the selection input 13, the value defining the feedback link of the synchronization register 1 is set. The logic level '0' of the reset signal resets counter 2, the output of which is set in the log state. 0, set the bistable 1.1 and reset the bistable from 1.2 to 1.4 (fig. 3). The bistables of group 4 are set in the predefined state by the respective self-test algorithm 00, 0, 10 or 11 (the setting-reset entries of the bistables of group 4 are not shown in fig. 1).

Thus the test device is installed in the initiated state. By generating the synchronization pulses at input 7 (fig. 1), the memory test 3 is passed.

The dynamic defects self-test consists of executing the test iterations (see source [1]), in which on each memory cell 3 is executed a sequence (called subiteration) of the read and write operations. The class of dynamic defects (analyzed) confines 2 types of models of functional defects (single-cell) - transient (dynamic Transition Fault, dTF) and destructive (dynamic Write Destructive Fault, dWDF), summing 12 primitives (see [S. Hamdioui, GN Gaydadjiev, and Ad J. Van de Goor. A Primitive Fault Based Analysis of Dynamic Memory Faults, Proc. PRORISC 2003, Veldhoven, Nov. 2003, pp. 84-89]).

Over a memory cell 3 must be executed successively and repeatedly more than о read and / or write operation to detect о dynamic failure. in most cases it is limited by the execution of two or three successive operafions. Next we analyze the operation of the test device for the dynamic defects mentioned - dTF, which confines 6 primitives, namely: <w0w0wl / 0 / ->, <ulul w0 / l / ->, <μ'0μΊ w0 / 1 / -> , <w 1 ν-τθν-г 1/0 / ->, <w0w0wl / 0 / ->, <vr 1 rl w0 / 1 / ->; and dWDF which confines the primitive 6 humers: <w0w0w0 / 1 / ->, <и4и4и4 / 0 / ->, <w0wl wl / 0 / ->, <w 1 wOwO / 1 / ->, <w0w0w0 / l /> and <wlrlwl / 0 / ->, here w means the inscription operation, and r - the read operation. We note that the first 4 primitives of the dTF and dWDF defects have the same structure of the sequence of operands, applied successively to one and the same memory cell 3: wwwr, and the last 2 primitives to the wrwr structure.

Let, for example, the primitive defect defect dTF: <vr 1 w 1 w0 / 1 / ->. From the description of this defect it results that for the activation (detection) they must execute (repeated) three registration operations - vtl vtl vtO. Then you need to urinate the reading operation to record dynamic failure (locked 1). These 4 operas (the essence of a sub-entry) - three of inscription and one of reading, are executed on each memory cell 3. Therefore, the required number of synchronization tactics will be equal to the length of the sequence, that is to say 4. To ensure this sequence of operations, the logic input 1 is applied to the selection input 13, ie the multiplexers 9.1 and 9.2 will connect the second input to the output. saddle.

The self-test iteration scheme is selected, according to which, at the initial time, the bistables of group 4 are set in the humid mode: bistable 4.1 - in log. 0, bistable 4.2 - in log. 1. At the negation entries of group 14, the combination of log signals is installed. 0.

After performing the device reset - the reset signal at input 6 goes into the log state. 1 (Fig. 3), the test device is ready for performing the test iteration.

In FIG. 3 is presented the time diagram of the execution of the test iteration subtitles. The test subtitle is executed for 4 synchronization touches in humid mode.

In the first three tactics of the subtitle at the output of the first multiplexer 9.1 is the log status. 0, which connects the first input of the multiplexer 12 to its output, sets the memory 3 in the write mode and, with each synchronization pulse, the value of the signal is entered, which comes from the output of the XOR 5 logic gate and passes through the gate. XOR logic 11.1. the leasing of the multiplexer 9.2 has the value of the state of the cell 3 of the register 1, that is in the first two tactics, being in the log state. 0, while passing the synchronization signal through the logic gate OR 10, and in tact three, being in the log state. 1, blocks the passage of the synchronization signal through the logic gate OR 10.

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With each synchronization pulse, the data in the bistables of group 4 and the calculation of the XOR amount (modulo 2) of the contents of these bistables takes place. Thus, because the (initial) states of bistable 4.1 and 4.2 are log. 0 and log. 1, before applying the first tactile impulse at the exit of the XOR gate 5, the log signal is fused. 1 (0®l = 1).

In the first tact of the subtitle at the arrival of the positive front of the synchronization signal the log value. 1 from the output of the logical gate XOR 5 is entered in the corresponding cell of memory 3; takes place the movement of data in the bistables of group 4 with the registration of the exit status of the XOR gate 5 in the first bistable 4.1. Thus, bistable states become greasers: bistable 4.1 is in log state. 1, the hinged 4.2 is in the log state. 0, and at the output of the logic gate XOR 5 we have the log status. 1 (1 ®0 = 1).

In the second tact of the subtitle at the arrival of the positive front of the synchronization signal the log value. 1 from the output of the logical gate XOR 5 is entered in the corresponding cell of memory 3; it takes place the data movement in the bistables of group 4 with the registration of the log status. 1 from the output of the logical gate XOR 5 in the first bistable 4.1 (its state becomes log. 1), and in the second bistable 4.2 the log is moved. 1 of the flip-flop 4.1 and at the output of the XOR 5 logic gate, the log value will be set. 0 as a result of the XOR sum of the bistable states of group 4 (l®l = 0).

In the third tact of the subtitle at the output of the second multiplexer 9.2 the log signal appears. 1, which closes the logic gate OR 10, thus blocking the passage of the synchronization signal to the bistables of group 4; at the arrival of the positive front of the synchronization signal the log value. 0 from the output of the logic gate XOR 5 is entered in the corresponding cell of memory 3.

In the fourth tact of the subtitle the output of the multiplexer 9.1 goes into the log state. 1, transferring the memory 3 in the read mode and connecting the second input of the multiplexer 12 at its output. At the same time the output of the multiplexer 9.2 appears the log signal. 0, unlocking the synchronization signal passing through logic gate OR 10. At the arrival of the positive front of the touch signal the data from the bistable 4.1 is transcribed into the bistable 4.2, and the bistable 4.1 the data is written, read from the memory cell 3, the address of which is specified by the state of the meter 2. Thus, the bistable state 4.2 comes log . 1, and at the output of the logical gate XOR 5 will be the result of the XOR sum of the bistable states of group 4: if the bistable state 4.1 is log. 0, ie the correct expected state, then at the output of the logical port XOR 5 will be log. 1 (0®l = 1) and the next subtitle will start with the same initiated state; otherwise, at the output of the logical port XOR 5 will be log. 0, ie the memory cell is defective and the incorrect log value has been read. 1 (1 ®1 = 0) and the next subtitle will start with о another incorrectly initiated state, which will be retained until the end of the test iteration. This incorrect state of the bistables of the group 4 is the indicator of the presence of the dynamic defect in memory 3. At the end of the fourth tact, when the signal from the output of the multiplexer 9.1 (or the fourth output q4 of the register 1) executes the transition 1—> 0 (the negative front), it has place increment (+1) of counter 2.

Test subtitles are repeated N times. At the end of the test iterations the reading of the bistable tailings of group 4 takes place, which is compared with the expected ones (initial ones in the analyzed example). In case of non-coincidence, it is accepted the hypothesis that the test unit, ie the operating memory 3, is defective. The transition of the report signal 1—> 0 (negative front) can be used as an indicator of the test iteration.

Table 1

<td rowspan="2">Dynamic failure</td><td colspan="2">Bistables of the group 4</td>

<td>The first 4.1</td><td>The second 4.2</td>

<td>dTF &lt;vt · 1 vt '1 w0 / 1 / -&gt;</td><td> 0</td><td> 1</td>

<td>dTF &lt;vt '1 vt'O vt' 1/0 / -&gt;</td><td> 1</td><td> 0</td>

<td>d WDF &lt;vt'O vt'O w0 / 1 /&gt;</td><td> 0</td><td> 0</td>

<td>d WDF &lt;vt'O vv 1 vt '1/0 / -&gt;</td><td> 1</td><td> 1</td>

For detecting dynamic defects the self-test iteration, described above, according to [1] is performed with different initial values. Table 1 presents the dynamic defects and the initial values ​​(states) in which the bistable group 4 must be set at the beginning of each iteration of the test.

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Table 2

<td rowspan="2">Dynamic failure</td><td colspan="2">Bistables of the group 4</td>

<td>The first 4.1</td><td>The second 4.2</td>

<td>dTF &lt;w0w0wl / 0-&gt;</td><td> 1</td><td> 0</td>

<td>dTF &lt;u'O M'l w0 / 1 / -&gt;</td><td> 0</td><td> 1</td>

<td>d WDF &lt;it '1 u'O м'О / 1 / -&gt;</td><td> 0</td><td> 0</td>

Let now, for example, the failure of dTF &lt;w0w0wl / 0 / -&gt;. To generate the wOwOwl sequence, the value from the output of the XOR 5 logic gate must be inverted. Therefore, at the initial time point the negation entry 14.1 is set in the log state. 1. Table 2 presents the dynamic defects and the initial states in which the bistables of group 4 must be set; the other input parameters remain unchanged compared to the self-test parameters for the previous example (fig. 3).

For the self-test of the dWDF failure &lt;wl wlwl / 0 / -&gt; the iteration similar to the one shown in fig. 3, but with the (double) reversal of the value entered and the value read from memory 3 - the entries of group 14 are set in log. 1 during the execution period of the test iteration, and the initial states of the bistables of group 4 are set in log. 0.

Thus with the help of 8 iterations of compact self-testing of 4N complexity, 8 out of 12 dynamic defects are detected.

Let's look at how dynamic dynamic defects are detected. The list of these defects is: dTF &lt;w0r0wl / 0 / -&gt;, dTF &lt;wl rlw0 / l / -&gt;, dWDF &lt;w0r0w0 / l / -&gt;, dWDF &lt;wlrlwl / 0 / -&gt; with the structure of the sequence of read and write operations wrwr . in this sequence of operations the pair is repeated. Execution of this pair is ensured by setting the selection entry 13 in the log. 0. Two test iterations must be performed to detect the failure in the lists.

Let, for example, the failure of dTF &lt;w0r0wl / 0 / -&gt;. In the first test iteration, subtitles are executed containing о logging operation μΌ of the log value. 0 and о read operation rO, and in the second test iteration, subtitles will be executed containing о register operation ula of the log value. 1 and о read operation of the contents of the memory cells 3. Accepting the same criterion for detecting the defect - comparing the final state with the initiated state of the bistables of group 4, in both test iterations the initiated state of the bistables of group 4 is set to 0, where in the first iteration of the test the data is written and read from memory 3 third in salt salt (negation entries of group 14 are set in log. 0), and in the second test iteration the data is written and read from memory 3 with inverted (negation entries of group 14 are set in log. 1). The time diagram of the execution of a test iteration is shown in fig. 4.

In the first tact the log value. 0 from the second output q2 of the synchronization register 1 passes through the multiplexer 9.1 and sets the memory 3 in the recording mode, and the signal log. 1 from the first output ql of the synchronization register 1, passing through the multiplexer 9.2, blocks the logic gate OR 10. Upon the arrival of the synchronization pulse, the output stereo of the logic gate XOR 5 is entered in the memory cell 3, the address of which is indicated by current status of meter 2 (fig. 4).

In the second tact the log value. 1 from the output of the multiplexer 9.1 sets the memory 3 in the read mode, and the signal log. 0 from the output of the multiplexer 9.2 allows the synchronization signals to be passed through the logic gate OR 10. At the moment of the synchronization pulse, the current memory cell 3 is read and the value read in the bistable group 4 is entered. At the end of the second tact, when the signal from the output of the multiplexer 9.1 executes the transition 1—&gt; 0 (the negative front), the increment (+1) of the counter 2 (fig. 4) takes place.

The test subtitles are repeated N times and the second test iteration is executed, in which the negation entries of group 14 are set in the log state. 1. If the memory cell 3 is defective, then the state of the bistables changes. At the end of the second iteration, the reading of the bistable tailings of group 4 takes place, which is compared with the expected ones. In case of non-coincidence it is accepted the hypothesis that memory 3 is defective. The time diagrams of the second iteration are identical to those shown in fig. 4.

In order to detect the failure of the dTF &lt;wl rlw0 / l / -&gt;, two self-test iterations, described above, are performed, but in reverse order: the second test iteration is performed first, then the first test iteration of the previous test is performed.

To detect the dWDF &lt;w0r0w0 / l / -&gt; defect, two self-test iterations are performed identical to the first test iteration of the dTF &lt;wl rlw0 / l / -&gt; defect test, and to detect the dWDF &lt;wlrlwl / 0 / -&gt; defect. two iterations of self-testing identical to the second iteration of the dTF defect test test &lt;w0r0wl / 0 / -&gt;.

Thus, with the help of 7 compact iterations of 2tV compact self-testing, 4 dynamic list failures are detected.

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Thus, the test of the 12 dynamic defects of the type dTF and dWDF altogether confers 15 test iteraphs with the 46.V summary complexity.

Thus the application of the proposed device allows the compact self-testing of the operating memory microcircuits. The resolution of the test in relation to the dynamic single-cell failures of the memory cells is equal to 100%, and the complexity of the self-test algorithm is 46 / V units of synchronization tactics, where .V is the capacity of the operating memory matrix.