Device and method for through-hole via stackable semiconductor device

BACKGROUND ART Device and method for through-hole via stackable semiconductor device

<p>FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to through hole via stacked semiconductor devices.</p>

<p>BACKGROUND OF THE INVENTION [0002] As a trend, semiconductor manufacturers are increasingly adopting three-dimensional (3D) interconnects and packings for semiconductor devices. 3D interconnects have advantages such as small size, short interconnect length and integration of devices with different functions within each package.</p><p>One of the various ways to implement a three-dimensional interconnect involves the use of a so-called "through-hole via" technique. The location of the through-hole vias may be located either on the semiconductor chip, on the "die" or outside the die (ie along so-called "saw street" guides).</p><p>However, the current through-hole via technology has several limitations. Vias located within the semiconductor chip limit the degree of freedom for having additional circuitry within the chip. As is conceivable, each position of the through-hole via interferes with the circuit arrangement at that position. As a result, the functions of the chip and the devices using the chip are limited.</p><p>Vias located outside the semiconductor chip (ie, along the saw street guide) require a wider saw street to accommodate the product of the through-hole. As a result, the yield (ie, chips per wafer) is reduced.</p>

<solutionproblem><p>SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a through-hole via stackable semiconductor device free from the above-mentioned limitations.</p></solutionproblem><meansproblemsolution><p>Accordingly, in one embodiment, the present invention provides a first die having upper, lower and peripheral surfaces; a bond pad formed on the upper surface; an organic material coupled to the first die and positioned about the peripheral surface; a via hole formed in the organic material; a metal trace connecting the via hole to the bond pad; and a conductive material deposited in the via hole.</p><p>In another embodiment, the present invention provides a method comprising: providing a wafer designated as a saw street guide; taping the wafer with dicing tape; singulating the wafer to a plurality of dies having a plurality of gaps between each of the plurality of dies along a saw street guide; stretching the dicing tape to expand the plurality of gaps by a predetermined distance; depositing an organic material into each of the plurality of gaps, the top surface being flush with a first die top surface of the plurality of dies; forming a plurality of holes in the organic material; patterning each of the plurality of via holes at each of the plurality of bond pad locations on the plurality of dies; depositing a conductive material in each of the plurality of via holes; A method of manufacturing a semiconductor device comprising singulating each of a plurality of dies from a dicing tape.</p><p>In another embodiment, the present invention provides a method comprising: providing a wafer designated as a saw street guide; taping the wafer with a first dicing tape; singulating the wafer into a plurality of dies having a first plurality of gaps therebetween each of the plurality of dies along a saw street guide; picking a plurality of dies from the dicing tape; positioning the plurality of dies on the first wafer support system to obtain a plurality of second gaps of a predetermined width between each of the plurality of dies; depositing an organic material having a top surface coplanar with a top surface of a first die of the plurality of dies into each of the plurality of gaps to form a recoated wafer; transferring the recoated wafer onto a second wafer support system; forming a plurality of via holes in the organic material; patterning each of the plurality of via holes at each of the plurality of bond pad locations on the plurality of dies; depositing a conductive material in each of the plurality of via holes; conveying the recoated wafer onto a second dicing tape; A method of manufacturing a semiconductor device comprising singulating each of a plurality of dies from a second dicing tape.</p><p>In another embodiment, the present invention provides a method comprising: providing a first die having a top surface, a bottom surface and a peripheral surface; providing a bond pad formed on the upper surface; providing an organic material coupled to the first die and positioned about the peripheral surface; providing via holes formed in the organic material; providing a via hole formed in the organic material; A method of manufacturing a semiconductor device comprising the step of depositing a conductive material in a via hole.</p></meansproblemsolution><effectiveness><p>While one or more embodiments of the present invention have been described, those skilled in the art will appreciate that modifications and variations of the embodiments are possible without departing from the scope of the present invention as set forth in the appended claims that follow.</p></effectiveness>

<p>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is described in one or more embodiments through the following description with reference to the drawings in which like numbers indicate like or like elements. While the present invention is described by an optimal method for achieving the object of the present invention, the scope and spirit of the invention defined by the appended claims and their equivalents while supported by the following specification and drawings It is intended that the invention be construed in terms of the functions of the elements of the invention, which are intended to cover alternatives, modifications and equivalents which may be contained therein.</p><p>1 is a diagram illustrating an example 100 of a conventional manufacturing method of a wafer level chip scale package. A number of chips 102 are cut from the wafer. Each chip 102 has a protruding bonding pad 104 located on the active side of the chip 102 .</p><p>A plurality of chips 102 are positioned on the top surface of the stretchable film 106 . The stretchable film 106 is secured by a frame 108 . The frame 108 is fixed by a fixture 110 and the stretchable film 106 is placed on a work platform 112 and stretched a certain distance.</p><p>The platform 112 may move upward in correspondence with the fixing unit 110 . The wafer is cut into a number of chips 102 as shown by a cutter, which are then sawed by a cutter 118 after being encapsulated into a semiconductor package. The shaft 114 rises to lift the platform 112 in response to the fixing portion 110 .</p><p>The present invention, in some embodiments, improves upon example 100 of conventional fabrication methods for through-hole via semiconductor devices that are stacked together for special applications and practices.</p><p>2A and 2B are side and plan views, respectively, illustrating a first embodiment according to a through-hole via stackable semiconductor device 200 . The device 200 has a embodied die 202 . The device 200 includes a plurality of bond pads 204 deposited on an active side of a semiconductor die 202 . The bond pads 204 may be deposited on the electrode terminals of the die 202 by a plating process or other process. The material of the bond pad 204 may be made of a conductive metal such as aluminum (Al). The bond pad 204 may be joined to the substrate by a soldering process.</p><p>A series of metal traces 206 electrically connect the bond pads 204 to vias 208 . As shown in FIG. 2B , the via 208 is formed with a surrounding material 210 that matches the through-hole via configuration in the active top surface 212 and the surrounding material 210 of the die 202 . It extends vertically to the lower surface of the die.</p><p>For purposes of the present invention, the surrounding material 210 is referred to as an "organic material" that is deposited around the peripheral surface 214 of the die 202 as shown. The organic material 210 is an improvement over and based on the prior art, as further described below. The organic material includes materials such as benzocyclobutene (BCB), polyimide (PI) materials, or similar materials. As shown, vias 208 are formed in organic material 210 and are organized in rows. In this embodiment 200 , vias 208 are formed on each side of organic material 210 (ie, sides 216 and 218 ) to completely surround the perimeter of die 202 . A plurality of bond pads 204 are electrically connected to each of the plurality of vias 208 .</p><p>As shown, the through-hole vias 208 may be formed in various structures along multiple rows, for example. In addition, half-cut vias (shown as illustrative figures) or fully uncut vias 208 may be formed in various embodiments to suit individual implementations. The semiconductor device 200 may be stacked on or coupled to an additional die 202 in various structures.</p><p>3A and 3B are a side view and a plan view showing a first step of the first embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A wafer 300 is provided. A series of bond pads 204 are formed on the active side of the wafer as shown. The wafer has a saw street guide 302 .</p><p>4A and 4B are a side view and a plan view showing a second step of the first embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The wafer 300 is singulated into a marked piece 400 during the first step by a cutting source 402 . The cutting source 402 may include a saw or laser cutting tool.</p><p>Prior to singulation, wafer 300 is placed on dicing tape 404, which holds various segments 400 in place during the singulation process. . After the singulation process, a series of gaps 406 are formed between each segment as shown.</p><p>5A and 5B are a side view and a plan view showing a third step of the first embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In each segment shown, the wafer 300 undergoes an expansion process. The dicing tape 404 is stretched by various techniques (eg, an expansion table) to form a series of gaps 502 having a distance 504 . The illustrated arrows 506 represent the various expansion directions traversed by the wafer expansion process.</p><p>As a next step, FIGS. 6A and 6B are a side view and a plan view showing a fourth step of the first embodiment according to the through-hole via stacked semiconductor device manufacturing method shown in FIGS. 2A and 2B, respectively. Various gaps 502 as shown in FIGS. 5A and 5B are filled with the organic material 602 described above. The plane 604 coincident with the upper surface of the filled segment 600 is flush with the plane 606 coincident with the upper surface of the organic material 602 .</p><p>Application of the organic material 602 may be performed by methods such as spin coating, needle dispensing, or similar applications.</p><p>7A and 7B are a side view and a plan view showing a fifth step of the first embodiment according to the method for manufacturing a through-hole via stacked semiconductor device as shown in FIGS. 2A and 2B, respectively. The segment 700 is subjected to a process to form a plurality of via holes 702 in the illustrated organic material 602 . The via hole may be formed in various processes, including a laser via drilling process or an etching process. As shown, each via hole is shaped in the organic material 602 such that the via hole coincides with the respective pump pad 204 with which it is associated.</p><p>Next, FIGS. 8A and 8B are a side view and a plan view showing a sixth step of the first embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. 8A and 8B illustrate a metal patterning process that connects a series of metal traces 206 from the bond pad 204 to the via hole 702 . Metal traces 206 also electrically connect the bond pads to each of via holes 702 as shown.</p><p>9A and 9B are diagrams showing a seventh step of the first embodiment according to the method of manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A via hole metal deposition process is performed in assembly 900 to deposit a conductive material into each via hole 702 while forming a series of metal vias 902 . The conductive material may be a material such as aluminum (Al), copper (Cu), tungsten (W), or another conductive material or any combination thereof. Again, a metal via 902 is formed in the organic material 602 . Various methods and techniques for forming metal vias may be used, such as plating or plugging processes.</p><p>10A and 10B are views showing an eighth step of the first embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Wafer assembly 300 , 900 is singulated during a second step by cutting source 402 to form gap 904 . As will be appreciated by those of ordinary skill in the art, the various dies 202 shown in FIGS. 10A and 10B and the example shapes described above represent a small fraction of the overall chip yielded from an individual wafer 300 . Following the end of the second singulation phase, most of the die 202 becomes as in the embodiment shown in FIGS. 2A and 2B , in which the organic material 210 covers the peripheral surface of the die 202 . Fully enclosed, through-hole vias 902 are arranged in rows along each side of the die as described above.</p><p>In a first embodiment, after the singulation step shown in FIGS. 10A and 10B , the individual die 202 are die pick and place for removing each die 202 from the dicing tape 404 . pick and place) process.</p><p>11A and 11B are plan and side views, respectively, illustrating a second embodiment according to a through-hole via stacked semiconductor device 906 including a plurality of complete through-hole vias. Here again, the elements shown in the preceding figures are shown including die 202 , bond pads 204 , and metal tracing formed on active surface 212 of die 202 . In the present embodiment 906, each through-hole via 908 is "complete" instead of the half-cut shown in the foregoing embodiment. The illustrated finished through-hole vias 908 may be formed by the individual shapes of the saw street guides 302 shown in FIGS. 3A and 3B . The wider saw street guide 302 cuts the organic material 602 as shown and holds the finished via hole 908 .</p><p>12A and 12B are a plan view and a side view showing a third step of the second embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. It includes the first two steps of the first embodiment (ie, providing a wafer and singulating each into segments on a dicing tape 404). In addition, various elements (ie, bond pads 204) are implemented.</p><p>As a next step, a wafer 300 segment 550 is picked from a first dicing tape 404 and placed on the so-called "wafer support system" shown. The wafer support system necessarily includes a second dicing tape 405 . However, the wafer support system may also be a temporary wafer support system such as a glass, ceramic, laminate or silicon (Si) substrate. In one embodiment, the sawn die 202 is picked from the dicing tape 404 and placed on the wafer support system 405 using a pick and place apparatus. The pick and place process forms a gap 406 having a predetermined width or distance 412 between each segment 550 .</p><p>13A and 13B are a plan view and a side view illustrating a fourth step of the second embodiment according to the method of manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Organic material 602 is again applied to segment 650 by spin coating, needle dispensing, or other methods similar to those described above. A plane 642 of the segment 650 is substantially coplanar with a plane 642 of the organic material 602 .</p><p>Next, FIGS. 14A and 14B are a plan view and a side view illustrating a fifth step of the second embodiment according to the method for manufacturing the through-hole via stacked-layer semiconductor device shown in FIGS. 2A and 2B. A recoated wafer 300 is transferred onto a second wafer support system 408 . The second wafer support system may again comprise glass, silicon (Si) substrate material, ceramic and laminate material.</p><p>15A and 15B are a plan view and a side view illustrating a sixth step of the second embodiment according to the method of manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In a step 750 similar to that shown in FIGS. 7A and 7B , multiple via holes 702 are formed in the organic material 602 to mate with the bond pads 204 .</p><p>16A and 16B are a plan view and a side view illustrating a seventh step 850 of the second embodiment according to the method of manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Step 850 is again similar to that shown in FIGS. 8A and 8B of metal patterning of metal traces 206 electrically connecting bond pad 204 locations to via 702 locations.</p><p>17A and 17B are a plan view and a side view illustrating an eighth step 950 of the second embodiment according to the method of manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Vias 702 are plugged, plated, or otherwise deposited with a conductive material to fill via holes 702 and form metal vias 902 as shown.</p><p>After the metal via 902 forming process, the via hole wafer 960 is transported onto the additional dicing tape 410 shown in FIGS. 18A and 18B which represents the ninth step shown.</p><p>19A and 19B are a plan view and a side view illustrating a tenth step of the second embodiment according to the method for manufacturing the through-hole via stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The cutting source 402 is again used to singulate the via hole wafer 960 into the illustrated segment 970 , resulting in a gap 904 . As a final step, after the second singulation process, a die pick and place device may be used to remove each device 200 from the dicing tape 410 .</p><p>20 is a side view showing an eighth step of the third embodiment according to a method of manufacturing a through-hole via stacked semiconductor device 910 using a die-to-die stacked configuration. A series of devices 200 can be stacked as shown to achieve special applications. Each of the metal vias 902 may be connected 912 using a direct via metal bonding process. One of ordinary skill in the art can imagine any number of devices 200 that can be loaded as shown to realize a desired implementation.</p><p>21 is a side view illustrating a fourth embodiment according to a method of manufacturing a through-hole via stacked semiconductor device 910 using a die-to-die stacked configuration including a solder paste 916 . Solder paste 916 contains a mixture of small solder particles and a flux. Various solder pastes of various materials may be included. Solder paste 916 may be applied using a reflow soldering method to form a strong metallic bond between each of the stacked devices 914 .</p><p>A fifth embodiment according to a through-hole via stackable semiconductor device is shown in FIG. This embodiment includes multiple flows of bond pads 204 suitably connected with metal tracings 206 and multiple flows of via holes 902 as shown in the plan view. Each via hole 902 is deposited in an organic material 602 as shown. Multiple die 202 configurations may be implemented with multiple flows of bond pads 204 and multiple flows of via holes 902 . In addition to the present embodiment 918 , other embodiments may be realized, in which the illustrated half-cut outer vias 902 are not located on the active side of the die 202 , but the additional die 202 . ) or elsewhere where special implementations are required, to bond pads 204 located on additional surfaces.</p><p>A sixth embodiment according to a through-hole via stackable semiconductor device 920 is shown in FIG. The device 920 shows a bond pad 204 , a trace 206 , and a series of half-cut vias 902 positioned on opposite sides of the die 202 . Here again, a die 902 is formed in an organic material 602 located on each peripheral surface of the illustrated die 202 . In a variation on the illustrated embodiment 902 , one configuration may include a full via 902 .</p><p>A seventh embodiment according to a through-hole via stackable semiconductor device 922 is shown in FIG. The device 922 includes a so-called "dummy" via hole 924 located on the opposite side of the illustrated die 202 . The vias 902 are positioned on the left and right hand sides shown. Derby via hole 924 provides electrical connection through device 924 for special applications. The dummy via hole 924 may be used to connect other devices 922 or packages using a wire bonding process. The hole 924 may also act as a ground or circuit for input/output (I/O) signals.</p><p>The dummy hole 924 may be of the same configuration as the via 902 in various implementations. For example, multiple flow or full or half-cut holes 924 may be implemented. 25 illustrates such an embodiment of an apparatus 926 , with a row of half-cut vias 924 on the left side of the die 202 and through-hole vias 902 on the right side of the die 202 . , which is again placed in organic material 602 .</p><p>26 is a through-hole via stack, showing two stacking dies 202 and 203 using the dummy via holes 902 shown in Figures 24 and 25 to connect the top die 203 with a wire bonding process. A ninth embodiment according to a semiconductor device 928 is shown. A series of bond pads 205 are located on the active side of the die 203 . Wire bonds 207 connect bond pads 204 to vias 902 . A dielectric, insulator or bonding material is placed between the dies 202 , 203 to provide structural support for the device/package 928 .</p><p>A semiconductor device such as device 200 including a series of through-hole vias 208 , 902 may provide a variety of functionality and flexibility in a variety of applications. The use of the organic material 210 may allow the vias 208 to be located outside the die 202 and allow additional circuitry within the die 202 to enhance the functionality of the device 200 . Also, by using the organic material 210 instead of the wafer 300 material, the yield per wafer is increased. The organic material may be constructed to any thickness required to accommodate the various vias 208 in any number of applications.</p><p>While one or more embodiments of the present invention have been described, those skilled in the art will appreciate that modifications and variations of the embodiments are possible without departing from the scope of the present invention as set forth in the appended claims that follow.</p>