Package-on-package using through-hole via die on saw streets

PACKAGE-ON-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS

<p>This invention is a continuation-in-part (CIP) of U.S. Patent Application Serial No. 11/744,657, filed May 4, 2007, entitled "Through-Hole Via on Saw Street," and Claims priority to earlier applications. </p><p>This application is filed concurrently with this application and is entitled Patent Attorney Docket No. 125155.00022, titled "Package-in-Package Using Through-Hole Via Die on Saw Street," Co-Pending United States Partial Serial Application No. (pending) ) and some co-pending United States Serial Application No. have.</p><p>FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to through-hole via (THV) stacked semiconductor devices.</p>

<p>BACKGROUND OF THE INVENTION [0002] As a trend, semiconductor manufacturers are increasingly adopting three-dimensional (3D) interconnects and packings for semiconductor devices. 3D interconnects have advantages such as small size, short interconnect length and integration of devices with different functions within each package.</p><p>One of the various ways to implement a three-dimensional interconnect involves the use of THV technology. The THV may be located either on the semiconductor chip, or within the die or outside the die along the saw street guide.</p><p>However, various limitations exist in the current THV. Vias located within the semiconductor chip limit the degree of freedom for having additional circuitry within the chip. As is conceivable, each position of the THV interferes with the circuit arrangement at that position. As a result, the functions of the chip and the devices using the chip are limited.</p><p>Vias located outside the semiconductor chip (ie, along the saw street guide) require a wider saw street to accommodate the product of the through-hole. As a result, the yield (ie, chips per wafer) is reduced.</p>

<solutionproblem><p>In view of the foregoing, it is an object of the present invention to provide a THV stacked semiconductor device without any accompanying limitations described above. The device may be included in the various package-on-package (PoP) configurations described below.</p></solutionproblem><meansproblemsolution><p>Accordingly, in one embodiment, the present invention provides a first die comprising a through-hole via (THV) positioned along a peripheral surface of a first die positioned on a substrate or leadframe structure, the THV of the first die. A semiconductor PoP device comprising: a first semiconductor package electrically connected to or electrically connected to the substrate or leadframe structure; and an encapsulation body formed on the first die and a portion of the first semiconductor package. </p><p>In another embodiment, the present invention provides a second bumped die positioned over a first die comprising a through-hole via (THV) positioned along a peripheral surface of the first die. , providing a single bump located on the THV, encapsulation covering the top of the THV and bumped die but exposing a portion of the bump and the bottom of the first die that constitute the first package of a plurality of packages A method of manufacturing a semiconductor device, comprising: providing a sieve; and stacking a first package and a second package of a plurality of packages by connecting the bumps of the first package to the THV of the second package. </p><p>In another embodiment, the present invention provides a method comprising the steps of providing a first die comprising a through-hole via (THV) positioned along a peripheral surface, the first die positioned on the top surface or positioned on the THV. providing a bump, providing an encapsulant covering the first die and a portion of the bump, exposing the bump by removing a portion of the encapsulant, and a second die or first and laminating a package onto the exposed bumps. </p><p>In another embodiment, the present invention provides a first die comprising a through-hole via (THV) positioned along a peripheral surface and connected to bond pads by metal traces on the top surface of the first die. positioning an interconnect pad; providing an encapsulant covering the THV, metal traces and bond pads but exposing a portion of the bottom surface of the interconnect pad and the first die; and a second die or first die. and laminating a package on the interconnect pad. </p></meansproblemsolution>

<p>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is described in one or more embodiments through the following description with reference to the drawings in which like numbers indicate like or like elements. While the present invention is described by an optimal method for achieving the object of the present invention, the scope and spirit of the invention defined by the appended claims and their equivalents while supported by the following specification and drawings It is intended that the invention be construed in terms of the functions of the elements of the invention, which are intended to cover alternatives, modifications and equivalents which may be contained therein.</p><p>In the following description and claims, the terms "comprise" and "include", together with their derivatives, may be used and intended as synonyms for each other. Also, in the following descriptive claims, the terms "coupled" and "connected" may be used together with their derivatives. "Connected" can be used to indicate that two or more elements are in physical or electrical contact with each other, respectively. "Coupled" may refer to direct physical or electrical contact of two or more elements. However, "coupled" can also mean that two or more elements cooperate or interact with each other, although not each in direct contact with each other. For example, "coupled" may mean that two or more elements are not each in contact with each other, but are indirectly coupled together through another element or intermediate elements. Finally, the terms "On", "Overlying" and "Over" may be used in the following description or claims: "On", "Overlying" "on" and "Over" may be used to indicate that two or more elements are each in direct physical contact with each other. However, "Over" also means that there is no direct contact. For example, "over" means that one element is on top of the other but not in contact with each other, and can have another element or elements between the two elements. do. </p><p>1 is a diagram illustrating an example 100 of a conventional manufacturing method of a wafer level chip scale package. A number of semiconductor devices 102 are cut from the wafer. Each semiconductor device 102 has a protruding bonding pad 104 located on the active side of the semiconductor device 102 .</p><p>A plurality of semiconductor devices 102 are positioned on the top surface of the stretchable film 106 . The stretchable film 106 is secured by a frame 108 . The frame 108 is fixed by a fixture 110 and the stretchable film 106 is placed on a work platform 112 and stretched to a certain distance.</p><p>The platform 112 may move upward in correspondence with the fixing unit 110 . The wafer is cut into a plurality of semiconductor devices 102 as shown by a cutter, and the chips are then saw by a cutter 118 after being encapsulated into a semiconductor package. The shaft 114 rises to lift the platform 112 in response to the fixing portion 110 .</p><p>The present invention, in some embodiments, improves upon example 100 of conventional fabrication methods for THV semiconductor devices that are stacked together for specific applications and practices.</p><p>2A and 2B are a side view and a plan view of a THV stackable semiconductor device 200 according to the first embodiment, respectively. The device 200 has a embodied die 202 . The device 200 includes a plurality of bond pads 204 deposited on an active surface of a semiconductor die 202 . The bond pads 204 may be deposited on the electrode terminals of the die 202 by a plating process or other process. The material of the bond pad 204 may be made of a conductive metal such as aluminum (Al). The bond pad 204 may be joined to the substrate by a soldering process.</p><p>A series of metal traces 206 electrically connect the bond pads 204 to vias 226 . As shown in FIG. 2B , via 226 is formed between the active top surface 212 of die 202 and the surrounding material 210 matching the THV configuration in the surrounding material 210 of the die. extends vertically to the bottom.</p><p>For purposes of the present invention, the surrounding material 210 is referred to as an "organic material" that is deposited around the peripheral surface 214 of the die 202 as shown. The organic material 210 is an improvement over and based on the prior art, as further described below. The organic material includes materials such as benzocyclobutene (BCB), polyimide (PI) materials, or similar materials. As shown, vias 226 are formed in organic material 210 and are organized according to rows. In this embodiment 200 , vias 226 are formed on each side of organic material 210 (ie, sides 216 and 218 ) to completely surround the perimeter of die 202 . A plurality of bond pads 204 are electrically connected to each of the plurality of vias 226 .</p><p>As shown, the THV 226 may be formed in various structures, for example, along multiple rows. In addition, half-cut vias (shown as illustrative figures) or finished uncut vias 226 may be formed in various embodiments to suit individual implementations. The semiconductor device 200 may be stacked on or coupled to an additional die 202 in various structures.</p><p>3A and 3B are a side view and a plan view showing a first step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A wafer 300 is provided. A series of bond pads 204 are formed on the active side of the wafer as shown. The wafer has a saw street guide 302 .</p><p>4A and 4B are a side view and a plan view showing a second step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The wafer 300 is singulated into a marked piece 400 during the first step by a cutting source 402 . The cutting source 402 may include a saw or laser cutting tool.</p><p>Prior to singulation, wafer 300 is placed on dicing tape 404, which holds various segments 400 in place during the singulation process. . After the singulation process, a series of gaps 406 are formed between each segment as shown.</p><p>5A and 5B are a side view and a plan view showing a third step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In each segment shown, the wafer 300 undergoes an expansion process. The dicing tape 404 is stretched by various techniques (eg, an expansion table) to form a series of gaps 502 having a distance 504 . The illustrated arrows 506 represent the various expansion directions traversed by the wafer expansion process.</p><p>As a next step, FIGS. 6A and 6B are a side view and a plan view showing a fourth step of the first embodiment according to the THV stacked semiconductor device manufacturing method shown in FIGS. 2A and 2B, respectively. Various gaps 502 as shown in FIGS. 5A and 5B are filled with the organic material 602 described above. The plane 604 coincident with the top surface of the filled segment 600 is flush with the plane 606 coincident with the top surface of the organic material 602 .</p><p>Application of the organic material 602 may be performed by methods such as spin coating, needle dispensing, or similar applications.</p><p>7A and 7B are a side view and a plan view illustrating a fifth step of the first embodiment according to the method for manufacturing a THV stacked semiconductor device as shown in FIGS. 2A and 2B, respectively. The segment 700 is subjected to a process to form a plurality of via holes 702 in the illustrated organic material 602 . The via hole may be formed in various processes, including a laser via drilling process or an etching process. As shown, each via hole is shaped in the organic material 602 such that the via hole coincides with the respective pump pad 204 with which it is associated.</p><p>Next, FIGS. 8A and 8B are a side view and a plan view showing a sixth step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. 8A and 8B illustrate a metal patterning process that connects a series of metal traces 206 from the bond pad 204 to the via hole 702 . Metal traces 206 also electrically connect the bond pads to each of via holes 702 as shown.</p><p>9A and 9B are diagrams illustrating a seventh step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A via hole metal deposition process is performed in assembly 900 to deposit a conductive material into each via hole 702 while forming a series of metal vias 902 . The conductive material may be a material such as aluminum (Al), copper (Cu), tungsten (W), or another conductive material or any combination thereof. Again, a metal via 902 is formed in the organic material 602 . Various methods and techniques for forming metal vias may be used, such as plating or plugging processes.</p><p>10A and 10B are views showing an eighth step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Wafer assembly 300 , 900 is singulated during a second step by cutting source 402 to form gap 904 . As will be appreciated by those of ordinary skill in the art, the various dies 202 shown in FIGS. 10A and 10B and the example shapes described above represent a small fraction of the overall chip yielded from an individual wafer 300 . Following the end of the second singulation phase, most of the die 202 becomes as in the embodiment shown in FIGS. 2A and 2B , in which the organic material 210 covers the peripheral surface of the die 202 . Fully enclosed, THVs 902 are arranged in rows along each side of the die as described above.</p><p>In a first embodiment, after the singulation step shown in FIGS. 10A and 10B , the individual die 202 are die pick and place for removing each die 202 from the dicing tape 404 . pick and place) process.</p><p>11A and 11B are plan and side views, respectively, showing a second embodiment according to a through-hole stacked semiconductor device 906 including a plurality of complete THVs. Here again, the elements shown in the preceding figures are shown including die 202 , bond pads 204 , and metal tracing formed on active surface 212 of die 202 . In this embodiment 906, each THV 908 is "complete" instead of the half-cut shown in the previous embodiment. The finished THV 908 shown may be formed by the individual shapes of the saw street guide 302 shown in FIGS. 3A and 3B . The wider saw street guide 302 cuts the organic material 602 as shown and holds the finished via hole 908 .</p><p>12A and 12B are a plan view and a side view showing a third step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The example includes the first two steps (ie, providing a wafer and singulating each into segments on the dicing tape 404). In addition, various elements (ie, bond pads 204) are implemented.</p><p>As a next step, a wafer segment 550 is picked from the first dicing tape 404 and placed on the so-called "wafer support system" shown. The wafer support system necessarily includes a second dicing tape 405 . However, the wafer support system may also be a temporary wafer support system such as a glass, ceramic, laminate or silicon (Si) substrate. In one embodiment, the sawn die 202 is picked from the dicing tape 404 and placed on the wafer support system 405 using a pick and place apparatus. The pick and place process forms a gap 406 having a predetermined width or distance 412 between each segment 550 .</p><p>13A and 13B are a plan view and a side view illustrating a fourth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Organic material 602 is again applied to segment 650 by spin coating, needle dispensing, or other methods similar to those described above. A plane 642 of the segment 650 is substantially coplanar with a plane 642 of the organic material 602 .</p><p>Next, FIGS. 14A and 14B are a plan view and a side view illustrating a fifth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B . A recoated wafer 300 is transferred onto a second wafer support system 408 . The second wafer support system may again comprise glass, silicon (Si) substrate material, ceramic and laminate material.</p><p>15A and 15B are a plan view and a side view illustrating a sixth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In a step 750 similar to that shown in FIGS. 7A and 7B , multiple via holes 702 are formed in the organic material 602 to mate with the bond pads 204 .</p><p>16A and 16B are a plan view and a side view illustrating a seventh step 850 of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Step 850 is again similar to that shown in FIGS. 8A and 8B for metal patterning of metal traces 206 electrically connecting bond pad 204 locations to via 702 locations.</p><p>17A and 17B are a plan view and a side view illustrating an eighth step 950 of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Via 702 is plugged, plated, or otherwise deposited with a conductive material to fill via hole 702 and form metal via 902 as shown.</p><p>After the metal via 902 forming process, the via hole wafer 960 is transported onto the additional dicing tape 410 shown in FIGS. 18A and 18B which represents the ninth step shown.</p><p>19A and 19B are a plan view and a side view illustrating a tenth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The cutting source 402 is again used to singulate the via hole wafer 960 into the illustrated segment 970 , resulting in a gap 904 . As a final step, after the second singulation process, a die pick and place device may be used to remove each device 200 from the dicing tape 410 .</p><p>20 is a side view showing an eighth step of the third embodiment according to the manufacturing method of the THV stacked semiconductor device 910 using a die-to-die stacked configuration. A series of devices 200 may be stacked as shown to achieve special applications. Each of the metal vias 902 may be connected 912 using a direct via metal bonding process. One of ordinary skill in the art can imagine any number of devices 200 that can be stacked as shown to realize a desired implementation.</p><p>21 is a side view illustrating a fourth embodiment according to a method of manufacturing a THV stacked semiconductor device 910 using a die-to-die stack configuration including a solder paste 916 . Solder paste 916 contains a mixture of small solder particles and a flux. Various solder pastes of various materials may be included. The solder paste 916 may be applied using a reflow soldering method to form a strong metallic bond between each of the stacked devices 914 .</p><p>A fifth embodiment according to a THV stacked semiconductor device is shown in FIG. This embodiment includes multiple flows of bond pads 204 suitably connected with metal tracings 206 and multiple flows of via holes 902 as shown in the plan view. Each via hole 902 is deposited in an organic material 602, as shown. Multiple die 202 configurations may be implemented with multiple flows of bond pads 204 and multiple flows of via holes 902 . In addition to the present embodiment 918 , other embodiments may be realized, in which the illustrated half-cut outer via 902 is not located on the active side of the die 202 , but the additional die 202 . ) or elsewhere where special implementations are required, to bond pads 204 located on additional surfaces.</p><p>A sixth embodiment according to a THV stacked semiconductor device 920 is shown in FIG. The device 920 shows a bond pad 204 , a trace 206 , and a series of half-cut vias 902 positioned on opposite sides of the die 202 . Here again, a die 902 is formed in an organic material 602 located on each peripheral surface of the illustrated die 202 . In a variation on the illustrated embodiment 902 , one configuration may include a completed via 902 .</p><p>A seventh embodiment according to a THV stacked semiconductor device 922 is shown in FIG. The device 922 includes a so-called "dummy" via hole 924 located on the opposite side of the illustrated die 202 . Vias 902 are located on the left and right hand sides shown. Dummy via hole 924 provides electrical connection through device 924 for special applications. The dummy via hole 924 may be used to connect other devices 922 or packages using a wire bonding process. The hole 924 may also act as a ground or circuit for input/output (I/O) signals.</p><p>The dummy hole 924 may be of the same configuration as the via 902 in various implementations. For example, a multiple flow or complete pre- or half-cut hole 924 may be implemented. 25 depicts such an embodiment of an apparatus 926 , with a row of half-cut vias 924 on the left side of the die 202 and a row of THV 902 on the right side of the die 202 . , and again placed on the organic material 602 .</p><p>26 is a THV stacked semiconductor device ( 928) shows a ninth embodiment. A series of bond pads 205 are located on the active side of the die 203 . Wire bonds 207 connect bond pads 204 to vias 902 . A dielectric, insulator or bonding material is placed between the dies 202 , 203 to provide structural support for the device/package 928 .</p><p>A semiconductor device such as device 200 comprising a series of THVs 226 and 902 may provide a variety of functionality and flexibility in a variety of applications. The use of the organic material 210 may allow the vias 226 to be located outside the die 202 and allow additional circuitry within the die 202 to enhance the functionality of the device 200 . Also, by using organic material 210 instead of wafer 300 material, each yield per wafer is increased. The organic material may be constructed to any thickness required to accommodate the various vias 226 in any number of applications.</p><p>The device 200 using the THV 226 may be included in a variety of PoP configurations. Such a device may include a semiconductor die having an integral THV 226 . Such a semiconductor die may be referred to as a THV die. Current Package-in-Package (PiP) packaging techniques use wire and/or bump interconnections to provide electrical signals between dies, interposers and packages. . There is a growing need to provide stronger, more efficient, space-saving interconnects. The use of a THV structure, such as 226, to provide such an interconnect, and thus a THV die, may provide a stronger, more efficient space saving interconnect.</p><p>Referring to FIG. 27A , a tenth exemplary embodiment of the THV stacked semiconductor device 220 is shown. Device 220 includes a die 202 . An organic material 210 is positioned about a peripheral surface 214 of the die 202 . The organic material is positioned, for example, along sides 216 , 218 of die 202 . A bond pad 204 is formed on or integrated into the top surface of the die 202 . A bond pad 204 on which a conductive material is located via a metal trace is connected to the THV 226 . A series of RDL and interconnect pads are either located in the structure shown above or integrated within the top surface of the die 202 . The RDL and interconnect pads provide additional electrical contact terminals for the die stacked on the THV die device 220 .</p><p>27B shows a side view of a THV die structure 220 including a second semiconductor die 224 mounted on the THV die 220 described above. The RDL/interconnect pads are connected to a series of bumps 222 for electrically connecting the die 224 . The THV die 220 includes the THV structure 226 described above, which is integrated into an organic material 210 positioned about the peripheral surface of the die 202 as shown. A series of bond pads 204 and metal traces 206 provide an electrical path for sending signals through vias 226 to the top surface of THV die 220 .</p><p>28A depicts a first stage apparatus 228 of an exemplary method for manufacturing a PoP semiconductor device to illustrate encapsulation and package stacking techniques. The device 228 includes a THV die 202 that again includes a THV 226 integrated into an organic material 210 . A series of bumps 222 electrically connect a second die or package 224 , such as a bumped die or flip chip die, to the THV die 202 . In one embodiment, bumps 222 are connected to the RDL and interconnect pads, as shown in FIG. 27A .</p><p>A next step device 230 in an exemplary encapsulation and package lamination process is shown in FIG. 28B . A next step device 234 is shown in FIG. 28C . An encapsulant 235 is positioned over the THV die 202 and a portion of the die 204 . A portion of the bump 232 is exposed, such as the bottom of the THV die 202 . Various sub-components such as THV die 202, bump 232, die 224, and bump 222 are referred to as being located within an integrated circuit package as shown.</p><p>As the next step device 238 shown in FIG. 28D , a first package 234 is stacked on a second package 234 . The top surface of the exposed bump 232 of the second package 234 is connected to the bottom surface of the THV 226 of the first package, and hence the THV die 202 of the first package. As such, vias 226 of different packages 234 may be connected using a series of partially exposed bumps 232 . An encapsulant 235 may be positioned on the THV die 202 and a portion of the die 204 .</p><p>29A-32B illustrate a series of steps in an exemplary method for semiconductor device fabrication using an exposed ball and die on package or using a PoP configuration. . 29A, 30A, 31A and 32A illustrate a first selection of an exemplary method, and similarly, FIGS. 29B, 30B, 31B and 32B illustrate a second selection of an exemplary method.</p><p>29A illustrates a process for providing a series of bumps 222 positioned on a THV die 202 . In one embodiment, bumps 222 may be connected to various RDL and associated interconnect pads, as shown in FIG. 27A . The bumps 222 provide an electrical connection path between the THV die 202 and the second die or package. 29B illustrates an additional option for forming bumps 222 on the top surface of vias 226 of THV die 202 .</p><p>As a next step, FIG. 30A illustrates the process of forming an encapsulant 236 on a portion of the THV die 202 and on the bump 222 . In a similar step, an encapsulant is formed on the bumps of the configuration shown in Fig. 30B.</p><p>A portion of the encapsulant is then removed to remove some of the bumps 222 , as indicated by arrow 240 in FIG. 31A for the first selection and FIG. 31B for the second selection. The encapsulant is removed by a wet etching or chemical-mechanical polishing (CMP) process.</p><p>As a final step, a second die 224 or second package 224 is deposited over the exposed bumps, where the bumps 222 send signals to or from the THV die 202 to the die or package 224 . transmit it to As shown in FIG. 32A , the die 224 is sized appropriately for each given bump 222 configuration. Similarly, a larger die or package 224 that extends to the peripheral edges of the THV die 202 may be used, as shown in FIG. 32B . Vias 226 may be used as ground or as a path for I/O signals to or from the die or package. The die or combination of package 224 , THV die 202 , encapsulant 236 , and bumps 222 is referred to as an integrated circuit package, which can be stacked again in various configurations to suit a particular setup.</p><p>33A-36 illustrate another example method of making a PoP configuration including a fan-in package-on-package (Fi-PoP) implementation. In a method similar to FIGS. 29A-32B, FIGS. 33A, 34A and 35A show the first option, while FIGS. 33B, 34B, 35B and 36 show the second option.</p><p>Referring to FIG. 33A , a THV die 202 is provided. In an alternative embodiment, a series of bumps 241 may be deposited on vias 226 , as shown in FIG. 33B . 34A illustrates the processes of forming a capsule covering some of the vias 226 , metal traces 206 and bond pads 204 as shown. Encapsulant 244 leaves the top of THV die 202 exposed to expose RDL 242 and/or interconnect pads 242 . Also, the bottom of the THV die 202 remains exposed. 34B depicts a similar step, wherein the encapsulant 244 is again formed on a portion of the THV die, but the interconnect pads and/or RDL 242 remain exposed, resulting in bumps 241 . ), provide electrical connectivity as indicated by arrow 243 .</p><p>35A illustrates a process for stacking a die or package 224 onto a THV die 202, wherein a series of bumps 222 connects the package or die 224 via interconnect pads and/or RDLs. Electrically connected to the THV die 202 . In a similar example, a package or die 224 is attached on the embodiment having bumps as shown in FIG. 35B. Bumps 222 electrically connect die or package 224 to THV die 202 via RDL or interconnect pads.</p><p>Fig. 36 shows the last step in the second alternative method described in Figs. 33b, 34b and 35b. The integrated circuit package 246 is stacked with an additional package 246 , as shown in FIG. 35B , where vias 226 are electrically connected using bumps 241 . A gap 248 may result between the two packages, which may be reduced by the use of an optional underfill material.</p><p>In some PoP arrangements, the top and bottom packages are ball grid array (BGA) packages with the top package stacked on the bottom package. The top package is connected to the bottom package via bumps between the top and bottom packages. These bumps are located about the perimeter of the bottom package.</p><p>Fi-PoP refers to embodiments having an inverted package such as 260 connected to a base substrate via a wire. The wire is encapsulated by a molding material and has an exposed middle cavity. As the electrical signal from the top surface second package is transmitted into the bottom package via the central cavity area, the exposed cavity area can receive the second package. Also, Fi-PoP may have a pre-encapsulated package. The Fi-PoP is attached with an interposer. Wires are added to accommodate the second package and the capsule with the intermediate cavity is exposed.</p><p>37 shows a first exemplary embodiment for a Fi-PoP configuration including a THV die 202 positioned on an inverted package 26 . The THV die 202 is oriented with its integral circuit layers facing upward. The THV die 202 may be placed on a circuit carrier substrate 252, or may also be placed on a leadframe material. In the illustrated embodiment, substrate 252 includes a series of bumps 254 that provide electrical connectivity. An additional die or package 256 is placed on and electrically connected to the THV die 202 . An encapsulant 244 is positioned over a portion of the THV die 202 , the inverted package 260 and the wire bonds 207 connecting the THV die 202 to the substrate 252 . The encapsulation is formed so as to terminate approximately midway between the via 226 and the bond pad 204 , ie, the illustrated metal traces 206 . The vias 226 may be used to connect to the top surface integral circuit or package 256 using wire and/or bump interconnects. In the illustrated embodiment, bumps 258 are used to provide interconnection.</p><p>38 shows a second exemplary embodiment for a Fi-PoP configuration, wherein the THV die 202 is on a standard package 264, which is located on a circuit carrier substrate or leadframe package 252. is located The THV die 202 is again wire-bonded directly to the substrate 252 . An additional package or die 256 is again shown electrically connected to the THV die 202 via bumps 258 .</p><p>As shown in many Fi-PoP embodiments throughout, package or die 256 is a flip chip bare die, quad flat nonlead (QFN) package, small Small outline nonlead (SON) package, quad flat package (QFP), land grid array (LGA), ball grid array (BGA) and The same device, or similar device or packaging configurations, includes a known preferred die. </p><p>39 shows a third embodiment 266 for a Fi-PoP implementation, wherein a THV die 202 is included in a top-side up flip chip die 268 and located on top of it. A top die 256 or package 256 is electrically connected to the THV die 202 via bumps interconnect 258 . An underfill material positioned under the THV die 202 is optional.</p><p>40 shows a fourth embodiment 268 for a Fi-PoP implementation, wherein the THV die 202 is wire-bonded to the vias 226 using a wire 207 as shown. -bonded) located under the inverted package. The illustrated embodiment also illustrates the flexibility of the implementation of the THV die 202 .</p><p>In a fifth embodiment, the THV die is wire bonded to an interposer device 272, as shown in FIG. The interposer acts as an interface providing a signal path between the THV die 202 and the top die or package 256 . The interposer 272 is wire-bonded to vias 226 similar to the method shown in FIG. 40 .</p><p>A sixth embodiment 274 of a Fi-PoP implementation is shown in FIG. 42 , showing an inverted device 276 that may be placed back on a circuit carrier substrate 252 or placed on a leadframe. A second encapsulant 278 may optionally be positioned between the gap formed between the THV die 202 and the encapsulant 244 . In the illustrated embodiment, the THV die is oriented such that the integral circuit layer remains facing down for electrical contact with the device 276 .</p><p>A similar embodiment 282 is shown in FIG. 43 , where additional packaging 280 is placed on the THV die 202 . Here, the wire bonds of the package 280 are connected through the vias 226 of the THV die 202 to electrically connect the package 280 to the integral circuit layers facing the top surface of the device 276 . The die 280 may include a flip chip bare die, QFN, QFP, SON, LGA, BGA, or other implementations including a known preferred die. The flexibility of the THV die 202 allows for a variety of such devices to be implemented in combination with the THV die 202 to suit particular applications, conform to certain performance requirements, or conform to certain dimensional requirements.</p><p>One embodiment 284 of Fi-PoP shows a THV die 202 using the set of exposed bumps 290 shown. Bumps 290 connect to leadframe 288, die 286, or similar device of package 286, which may again include various devices such as those shown in device 280, BGA, LGA, etc. do. In the illustrated embodiment, the THV die 202 overhangs the package 264 . The encapsulation body 244 covers a portion of the THV die 202 and the package 264 and bumps 290 to provide structural support. In a similar embodiment 297 shown in FIG. 45 , the die 286 mounted directly to the THV die 202 shown in FIG. 44 is removed and replaced with an additional encapsulant 244 . 44 and 45 , THV die 202 is wire-bonded to substrate 252 directly from vias 226 using wire 207 as shown.</p><p>46 , a further embodiment of a Fi-PoP configuration in which a THV die 202 is positioned on a substrate 252 having an open cavity 295 formed in a portion of the substrate 252 ( 298) is shown. The integral circuit layers of the THV die 202 abut the open cavity of the substrate. An additional die 286 is placed on the inverted package 260 , where the die 286 uses a series of bumps 258 to electrically connect the die 286 to the integrated circuit layer of the package 260 . connect The package 260 is connected to a THV die 202 using a die attach (D/A) attachment material. Similarly, an additional die 224 is positioned below the active surface of the THV die and is also connected to the integral circuit layers of the THV die using a series of bumps 258 . An underfill material 299 is optionally positioned between the bottom die 224 and the THV die 202 to provide additional structural support. </p><p>27-46, the use of a THV die 226 incorporated into a THV die 202 provides a flexible variety of choices for incorporating a variety of dies and packages. Various dimensional requirements, such as footprint size or height or depth requirements, may be satisfied through the use of THV die 202 in various stack configurations. The use of a THV die in various embodiments provides an efficient, effective and robust solution in many cases.</p><p>While one or more embodiments of the present invention have been described, those skilled in the art will appreciate that modifications and variations of the embodiments are possible without departing from the scope of the present invention as set forth in the appended claims that follow.</p>