A semiconductor device and a method of making a semiconductor device

A semiconductor device and its manufacturing method

<p>FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to through hole via (THV) stacked semiconductor devices.</p>

<p>BACKGROUND OF THE INVENTION [0002] As a trend, semiconductor manufacturers are increasingly adopting three-dimensional (3D) interconnects and packings for semiconductor devices. 3D interconnects have advantages such as small size, short interconnect length and integration of devices with different functions within each package.</p><p>One of the various ways to implement a three-dimensional interconnect involves the use of THV technology. The location of the THV may be located either outside the die along the semiconductor chip, the "die" or the saw street guide.</p><p>However, the current THV technology has several limitations. Vias located within the semiconductor device limit the degree of freedom for having additional circuitry in the semiconductor device. As is conceivable, each position of the THV interferes with the circuit arrangement at that position. As a result, the functions of the semiconductor device and the devices using the semiconductor device are limited.</p><p>Vias located outside the semiconductor device (ie, along the saw street guide) require a wider saw street to accommodate the product of the through-hole. As a result, the yield of the semiconductor device from wafer to wafer is reduced.</p>

<solutionproblem><p>SUMMARY OF THE INVENTION In order to solve the above problems, it is an object of the present invention to provide a through-hole via stackable semiconductor device free from the above-mentioned limitations.</p></solutionproblem><meansproblemsolution><p>Accordingly, in one embodiment, the present invention is a semiconductor device comprising a first die having a top surface, a bottom surface, and a peripheral surface. One bond pad is formed on the upper surface. An organic material is coupled to the first die and positioned about the peripheral surface. One via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is fused to the via hole. A redistribution layer (RDL) has interconnection pads located on the top surface of the first die.</p><p>In another embodiment, the present invention provides a semiconductor package-in-package comprising one THV (THV) positioned along a perimeter of a first die and comprising a first die positioned on a substrate or leadframe. (PiP) device. The second die is placed on a substrate or leadframe structure. The second die is electrically connected to the THV of the first die or electrically connected to the substrate or leadframe structure. An encapsulant is formed over the first and second dies.</p><p>In another embodiment, the present invention provides a method comprising the steps of providing a first die having a top surface, a bottom surface and a peripheral surface, providing a bond pad formed on the top surface, coupled to the first die and around the peripheral surface providing an organic material positioned at and providing a redistribution layer (RDL) having interconnect pads positioned on a top surface of the first die.</p><p>In another embodiment, the present invention provides a first die positioned on a substrate or leadframe comprising one THV (THV) positioned along a perimeter of a first die, comprising the steps of: A semiconductor package-in comprising the steps of providing a second die electrically coupled to the THV or electrically coupled to the substrate or leadframe structure, and providing an encapsulation body formed over the first die and the second die. - A method of manufacturing a package device. </p></meansproblemsolution><effectiveness><p>While one or more embodiments of the present invention have been described, those skilled in the art will appreciate that modifications and variations of the embodiments are possible without departing from the scope of the invention as set forth in the appended claims that follow.</p></effectiveness>

<p>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is described in one or more embodiments through the following description with reference to the drawings in which like numbers indicate like or like elements. While the present invention is described by an optimal method for achieving the object of the present invention, the scope and spirit of the invention defined by the appended claims and their equivalents while supported by the following specification and drawings It is intended that the invention be construed in terms of the functions of the elements of the invention, which are intended to cover alternatives, modifications and equivalents which may be contained therein.</p><p>In the following description and claims, the terms "comprise" and "include", along with their derivatives, may be used and intended as synonyms for each other. Also, in the following descriptive claims, the terms "coupled" and "connected" may be used together with their derivatives. "Connected" can be used to indicate that two or more elements are in physical or electrical contact with each other, respectively. "Coupled" may refer to direct physical or electrical contact of two or more elements. However, "coupled" can also mean that two or more elements cooperate or interact with each other, although not each in direct contact with each other. For example, "coupled" may mean that two or more elements are not each in contact with each other, but are indirectly coupled together through another element or intermediate elements. Finally, the terms "On", "Overlying" and "Over" may be used in the following description or claims: "On", "Overlying" "on" and "Over" may be used to indicate that two or more elements are each in direct physical contact with each other. However, "Over" also means that there is no direct contact. For example, "over" means that one element is on top of the other but not in contact with each other, and can have another element or elements between the two elements. do. </p><p>1 is a diagram illustrating an example 100 of a conventional manufacturing method of a wafer level chip scale package. A number of semiconductor devices 102 are cut from the wafer. Each semiconductor device 102 has a protruding bonding pad 104 located on the active side of the device 102 .</p><p>A plurality of semiconductor devices 102 are positioned on the top surface of the stretchable film 106 . The stretchable film 106 is secured by a frame 108 . The frame 108 is fixed by a fixture 110 and the stretchable film 106 is placed on a work platform 112 and stretched to a certain distance.</p><p>The platform 112 may move upward in correspondence with the fixing unit 110 . The wafer is cut into a plurality of semiconductor devices 102 as shown by a cutter, which are then sawed by a cutter 118 after being encapsulated into a semiconductor package. The shaft 114 rises to lift the platform 112 in response to the fixing portion 110 .</p><p>The present invention, in some embodiments, improves upon example 100 of conventional fabrication methods for THV semiconductor devices that are stacked together for specific applications and practices.</p><p>2A and 2B are a side view and a plan view illustrating a first embodiment according to a THV through-hole via stackable semiconductor device 200, respectively. The device 200 has a embodied die 202 . The device 200 includes a plurality of bond pads 204 deposited on an active surface of a semiconductor die 202 . The bond pads 204 may be deposited on the electrode terminals of the die 202 by a plating process or other process. The material of the bond pad 204 may be made of a conductive metal such as aluminum (Al). The bond pad 204 may be joined to the substrate by a soldering process.</p><p>A series of metal traces 206 electrically connect the bond pads 204 to vias 226 . As shown in FIG. 2B , vias 226 are formed between the active top surface 212 of the die 202 and the surrounding material 210 matching the THV configuration in the surrounding material 210 and of the die. extends vertically to the bottom.</p><p>For purposes of the present invention, the surrounding material 210 is referred to as an "organic material" that is deposited around the peripheral surface 214 of the die 202 as shown. The organic material 210 is an improvement over and based on the prior art, as further described below. The organic material includes materials such as benzocyclobutene (BCB), polyimide (PI) materials, or similar materials. As shown, vias 226 are formed in the organic material 210 and are organized in rows. In this embodiment 200, vias 226 are formed on each side of organic material 210 (ie, sides 216 and 218 ) to completely surround the perimeter of die 202 . A plurality of bond pads 204 are electrically connected to each of the plurality of vias 226 .</p><p>As shown, the THV 226 may be formed in various structures, for example, along multiple rows. In addition, half-cut vias (shown as illustrative figures) or complete uncut vias may be formed in various embodiments to suit individual implementations. The semiconductor device 200 may be stacked on or coupled to an additional die 202 in various structures.</p><p>3A and 3B are a side view and a plan view showing a first step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A series of bond pads 204 are formed on the active side of the wafer 300 as shown. The wafer has a saw street guide 302 .</p><p>4A and 4B are a side view and a plan view showing a second step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The wafer 300 is singulated into a piece 400 indicated by a cutting source 402 . The cutting source 402 may include a saw or laser cutting tool.</p><p>Prior to singulation, wafer 300 is placed on dicing tape 404, which holds various segments 400 in place during the singulation process. . After the singulation process, a series of gaps 406 are formed between each segment as shown.</p><p>5A and 5B are a side view and a plan view illustrating a third step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In each segment shown, the wafer 300 undergoes an expansion process. The dicing tape 404 is stretched by using an expansion table to form a series of gaps 502 having a distance 504 . The illustrated arrows 506 represent the various expansion directions traversed by the wafer expansion process.</p><p>As a next step, FIGS. 6A and 6B are a side view and a plan view showing a fourth step of the first embodiment according to the THV stacked semiconductor device manufacturing method shown in FIGS. 2A and 2B, respectively. Various gaps 502 as shown in FIGS. 5A and 5B are filled with the organic material 602 described above. The plane 604 coincident with the top surface of the filled segment 600 is flush with the plane 606 coincident with the top surface of the organic material 602 .</p><p>Application of the organic material 602 may be performed by methods such as spin coating, needle dispensing, or similar applications.</p><p>7A and 7B are a side view and a plan view showing a fifth step of the first embodiment according to the method for manufacturing a THV stacked semiconductor device as shown in FIGS. 2A and 2B, respectively. The segment 700 is subjected to a process to form a plurality of via holes 702 in the illustrated organic material 602 . The via hole may be formed in various processes, including a laser via drilling process or an etching process. As shown, each via hole is shaped in the organic material 602 such that the via hole coincides with the respective pump pad 204 with which it is associated.</p><p>Next, FIGS. 8A and 8B are a side view and a plan view showing a sixth step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. 8A and 8B illustrate a metal patterning process that connects a series of metal traces 206 from the bond pad 204 to the via hole 702 . Metal traces 206 also electrically connect the bond pads to each of the via holes 702 as shown.</p><p>9A and 9B are views showing a seventh step of the first embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. A via hole metal deposition process is performed in assembly 900 to deposit a conductive material into each via hole 702 while forming a series of metal vias 902 . The conductive material may be a material such as Al, copper (Cu), tungsten (W), or another conductive material or any combination thereof. Again, a metal via 902 is formed in the organic material 602 . Various methods and techniques for forming metal vias may be used, such as plating or plugging processes.</p><p>10A and 10B are views showing an eighth step of the first embodiment according to the method of manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Wafer assembly 300 , 900 is singulated during a second step by cutting source 402 to form gap 904 . The various dies 202 shown in FIGS. 10A and 10B , and the example shapes described above, represent a small portion of the overall semiconductor device produced on an individual wafer 300 . Following the end of the second singulation phase, most of the die 202 becomes as in the embodiment shown in FIGS. 2A and 2B , in which the organic material 210 covers the peripheral surface of the die 202 . Fully enclosed, THVs 902 are arranged in rows along each side of the die as described above.</p><p>In a first embodiment, after the singulation step shown in FIGS. 10A and 10B , the individual die 202 are die pick and place for removing each die 202 from the dicing tape 404 . It is removed by the pick and place) process.</p><p>11A and 11B are plan and side views, respectively, showing a second embodiment according to a THV stacked semiconductor device 906 including a plurality of complete THVs. Here again, the elements shown in the preceding figures are shown including die 202 , bond pads 204 , and metal tracing formed on active surface 212 of die 202 . In this embodiment 906, each THV 908 is "complete" instead of the half-cut shown in the previous embodiment. The finished THVs 908 shown may be formed by the individual shapes of the saw street guides 302 shown in FIGS. 3A and 3B . The wider saw street guide 302 cuts the organic material 602 as shown and retains the finished via hole 908 .</p><p>12A and 12B are a plan view and a side view showing a third step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The first two steps of the example include providing the wafer and singulating each into segments on the dicing tape 404 . In addition, various elements such as bond pads 204 are implemented.</p><p>As a next step, wafer segments 550 are picked from dicing tape 404 and placed on the so-called "wafer support system" shown. The wafer support system necessarily includes a second dicing tape 405 . However, the wafer support system may also be a temporary wafer support system such as a glass, ceramic, laminate or silicon (Si) substrate. In one embodiment, the sawn die 202 is picked from the dicing tape 404 and placed on the wafer support system 405 using a pick and place apparatus. The pick and place process forms a gap 406 having a predetermined width or distance 412 between each segment 550 .</p><p>13A and 13B are a plan view and a side view illustrating a fourth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Organic material 602 is again applied to segment 650 by spin coating, needle dispensing, or other methods similar to those described above. A plane 642 of the segment 650 is substantially coplanar with a plane 642 of the organic material 602 .</p><p>Next, FIGS. 14A and 14B are a plan view and a side view illustrating a fifth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B . A recoated wafer 300 is transferred onto a second wafer support system 408 . The second wafer support system may again comprise glass, silicon (Si) substrate material, ceramic and laminate material.</p><p>15A and 15B are a plan view and a side view illustrating a sixth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. In a step 750 similar to that shown in FIGS. 7A and 7B , multiple via holes 702 are formed in the organic material 602 to mate with the bond pads 204 .</p><p>16A and 16B are a plan view and a side view illustrating a seventh step 850 of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Step 850 is again similar to that shown in FIGS. 8A and 8B for metal patterning of metal traces 206 electrically connecting bond pad 204 locations to via 702 locations.</p><p>17A and 17B are a plan view and a side view illustrating an eighth step 950 of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. Vias 702 are plugged, plated, or otherwise deposited with a conductive material to fill via holes 702 and form metal vias 902 as shown.</p><p>After the metal via 902 formation process, the via hole wafer 960 is transported onto the additional dicing tape 410 shown in FIGS. 18A and 18B , which represents the ninth step shown.</p><p>19A and 19B are a plan view and a side view illustrating a tenth step of the second embodiment according to the method for manufacturing the THV stacked semiconductor device shown in FIGS. 2A and 2B, respectively. The cutting source 402 is again used to singulate the via hole wafer 960 into the illustrated segment 970 , resulting in a gap 904 . As a final step, after the second singulation process, a die pick and place device may be used to remove each device 200 from the dicing tape 410 .</p><p>20 is a side view showing an eighth step of the third embodiment according to the manufacturing method of the THV stacked semiconductor device 910 using a die-to-die stacked configuration. A series of devices 200 may be stacked as shown to achieve special applications. Each of the metal vias 902 may be joined by a connector 912 as shown using a direct via metal bonding process. One of ordinary skill in the art can envision a number of devices 200 that can be stacked as shown to realize a desired implementation.</p><p>21 is a side view illustrating a fourth embodiment according to a method of manufacturing a THV stacked semiconductor device 910 using a die-to-die stack configuration including a solder paste 916 . Solder paste 916 contains a mixture of small solder particles and a flux. Various solder pastes of various materials may be included. The solder paste 916 may be applied using a reflow soldering method to form a strong metallic bond between each of the stacked devices 914 .</p><p>A fifth embodiment according to a THV stacked semiconductor device is shown in FIG. This embodiment includes multiple flows of bond pads 204 suitably connected with metal tracings 206 and multiples of via holes 902 as shown in the plan view. Each via hole 902 is deposited in an organic material 602, as shown. Multiple die 202 configurations may be implemented with multiples of bond pads 204 and multiples of via holes 902 . In addition to the present embodiment 918 , other embodiments may be realized, in which the illustrated half-cut outer via 902 is not located on the active side of the die 202 , but the additional die 202 . ) or elsewhere where special implementations are required, to bond pads 204 located on additional surfaces.</p><p>A sixth embodiment according to a THV stacked semiconductor device 920 is shown in FIG. The device 920 shows a bond pad 204 , a trace 206 , and a series of half-cut vias 902 located on opposite sides of the die 202 . Die 902 is formed in organic material 602 located on each peripheral surface of die 202 shown. In a variation of the illustrated embodiment 902 , one configuration may include a completed via 902 .</p><p>A seventh embodiment according to a THV stacked semiconductor device 922 is shown in FIG. The device 922 includes a series of dummy via holes 924 located on opposite sides of the illustrated die 202 . Vias 902 are located on the left and right hand sides shown. Dummy via hole 924 provides electrical connection through device 924 for special applications. The dummy via hole 924 may be used to connect other devices 922 or packages using a wire bonding process. The hole 924 may also act as a ground or circuit for input/output (I/O) signals.</p><p>The dummy hole 924 may be of the same configuration as the via 902 in various implementations. For example, a multiple flow or complete pre- or half-cut hole 924 may be implemented. 25 depicts such an embodiment of a device 926 , with a row of half-cut vias 924 on the left side of the die 202 and a row of THV 902 on the right side of the die 202 . , and again placed on the organic material 602 .</p><p>26 is a THV stacked semiconductor device ( 928) shows a ninth embodiment. A series of bond pads 205 are located on the active side of the die 203 . Wire bonds 207 connect bond pads 204 to vias 902 . A dielectric, insulator or bonding material is placed between the dies 202 , 203 to provide structural support for the device/package 928 .</p><p>A semiconductor device such as device 200 comprising a series of THVs 226 and 902 may provide a variety of functionality and flexibility in a variety of applications. The use of the organic material 210 may allow the vias 226 to be located outside the die 202 and enable additional circuitry within the die 202 to enhance the functionality of the device 200 . Also, by using the organic material 210 instead of the wafer 300 material, the yield per wafer is increased. The organic material may be constructed to any thickness required to accommodate the various vias 226 in any number of applications.</p><p>The device 200 using the THV 226 may be included in a variety of Package-on-Package (PoP) configurations. Such a device may include a semiconductor die having an integral THV 226 . Such a semiconductor die may be referred to as a THV die. Current Package-in-Package (PiP) packaging techniques use wire and/or bump interconnections to provide electrical signals between dies, interposers and packages. . There is a growing need to provide stronger, more efficient, space-saving interconnects. The use of a THV structure, such as 226, to provide such an interconnect, and thus a THV die, may provide a stronger, more efficient space saving interconnect.</p><p>Referring to FIG. 27A , a tenth exemplary embodiment of the THV stacked semiconductor device 220 is shown. Device 220 includes a die 202 . An organic material 210 is positioned around the peripheral surface 214 of the die 202 . The organic material is positioned along sides 216 , 218 of die 202 . A bond pad 204 is formed on or integrated into the top surface of the die 202 . Bond pads 204 on which conductive material is located are connected to THVs 226 via metal traces 206 . A series of RDL and interconnect pads are either located in the structure shown above or integrated within the top surface of the die 202 . The RDL and interconnect pads provide electrical contact terminals for additional die stacked on die 202 .</p><p>27B shows a side view of a THV die structure 220 including a second semiconductor die 224 stacked on the THV die 202 . The RDL/pads are connected to a series of bumps 222 to electrically connect the die 224 . The THV die 202 includes the THV structure 226 described above, which is integrated into an organic material 210 positioned about the peripheral surface of the die 202 as shown. A series of bond pads 204 and metal traces 206 provide an electrical path for sending signals through vias 226 to the top surface of die 202 .</p><p>28 depicts a first exemplary embodiment of a series of package-in-package (PiP) structures using a THV structure. In some cases, such as in the illustrated example, the package-in-package structures are formed on a circuit carrier substrate 230 . Also, however, the underlying base material may include such a structure as a leadframe. The structure 226 may be used to connect top-side integrated circuits or top-side integrated packages using wire and/or bump interconnects. Vias 226 as described above. It can act as ground or to pass input/output (I/O) signals.</p><p>The illustrated package 228 includes a die 202 . An attachment material, such as a die attach (D/A) attachment 209 , connects the die 202 to the wire bond die 224 . Bond pads 205 on wire bond die 224 use wires 207 to connect die 224 to vias 226 at terminal locations 213 . A wire bond die 224 and a THV die 202 are placed on a substrate 230 having a series of bumps 232 . An encapsulant 211 is formed on the THV die 202 and the wire bond die 224 .</p><p>29 illustrates an additional wire bond embodiment of a package 234 , wherein a wire bond die 224 is wire bonded to a bond pad 204 integrated on the top surface of the die 202 . The bond pads 204 are connected to vias 226 using metal traces 206 .</p><p>In a similar embodiment, FIG. 30 shows a wire bond embodiment of a package 236 , wherein a series of bond pads 205 have a die 224 connected to a via 226 at a terminal location 213 and a terminal location ( 238 to bond both to the substrate 230 . </p><p>31 shows one exemplary package 238 , where wire bond die 224 overhangs THV die 202 , as indicated by distance arrow 240 . Bond pads 205 connect die 224 directly to substrate 230 .</p><p>32 shows one Package-in-Package (PiP) 242 , where a flip chip die 244 is positioned over the THV die 202 and uses bumps 248 . electrically connected to the RDL/interconnect pads. An optional underfill material 246 is positioned between the flip chip die 244 and the THV die 202 .</p><p>An overhanged third wire bond die 245 is positioned over the flip chip die 244 of the exemplary PiP 250 shown in FIG. 33 . Overhang wire bond die 245 is wire bonded from bond pad 252 to via 226 at terminal location 213 . again. D/A 209 attaches overhang die 245 to flip chip die 244 .</p><p>In the PiP 254, a leadframe package 256 is attached to the THV die 202, as shown in FIG. Package 256 includes an integrated die 258 and die paddle 260 that are attached using D/A 209 . Lead terminals 262 allow wires 207 to connect to both bond pads 204 and vias 226 . Package 256 is attached to THV die 202 using D/A 209 . Package 256 includes devices such as a quad flat nonlead (QFN) package, small outline nonlead (SON) and quad flat package (QFP), or It may contain similar package configurations.</p><p>The leadframe package 256 has been replaced by an array package 266 in FIG. 35 which shows an exemplary PiP 264 . The package 266 also includes a die 268 positioned on the substrate, whose bumps 270 connect the array package 266 to the THV die 202 and the RDL/pads. The package 266 may include a device such as a land grid array (LGA), a ball grid array (BGA), or a similar package configuration. Again, optional underfill material 208 connects package 266 to die 202 .</p><p>FIG. 36 shows a PiP 272 comprising an inverted top package 274 . The inverted package 274 also includes a die 276 and a die paddle 278 . Lead terminals 282 connect package 274 to vias 226 . The inverted upper package 274 may include devices such as QFN, SON, QFP, LGA, BGA, or a similar package configuration.</p><p>FIG. 37 shows another package 284 including an inverted top package 286 similar to package 274 . Package 286 is attached to THV die 202 using D/A material 288 . A flip chip die 244 is positioned over the package 286 , as shown using bumps 248 and an optional underfill 246 . The flip chip die 244 may include wire bond dies or additional semiconductor integrated circuit packages.</p><p>38 shows the configuration of a PiP 290 where the THV die 202 is inverted to connect the top surface of the package 286 to the bottom surface of the via 226 using a number of bumps. is located on Again, the inverted bottom package 286 includes devices such as QFNs, SONs, QFPs, LGAs, BGAs, flip chip bare dies and wafer level packages (WLPs) 286 . may include Package 286 is attached to substrate 230 with D/A 288 and wire-bonded as shown.</p><p>FIG. 39 shows the configuration shown in FIG. 38 or a configuration with additional stacking. Package 292 includes an additional flip chip die 244 that is positioned on top of THV die 202 using bumps 248 and underfill 246 similar to the method shown in FIG. 32 . do. Other semiconductor devices, such as wire bond dies, may also be used in place of flip chip dies 244 .</p><p>Referring to FIG. 40 , an exemplary PiP 296 includes an inverted bottom package 286 . In the illustrated embodiment, a series of THV dies 202 are stacked one on top of the other as shown. The bottom of the top THV die via 226 is connected to the top of the bottom THV die via 226 . The top THV die 202 is wire-bonded from the via location 283 to a location on the adjacent THV die via.</p><p>In a similar embodiment, THV dies 202 are stacked adjacent to each other on a package 286, as shown in FIG. 41 . PiP 298 includes an inverted bottom package 286 attached to substrate 230 as shown again. In the illustrated embodiment, an additional flip chip die 304 , or similar die 304 or integrated circuit package 304 is placed on the THV die 202 using bumps 306 .</p><p>42 shows a package 308 including an inverted bottom package 286 . A solder paste 310 is connected to the bottom surface of the via 226 . A passive device 312 , such as an inductor, filter, capacitor, resistor, or similar passive device 312 is coupled to the solder paste 310 to provide additional functionality to the package 308 . In the illustrated embodiment, the THV die 202 overhangs the package 286 to allow room for the passive device 312 . Encapsulant 211 covers a portion of all elements of package 308 as shown to provide structural support. Bond pad 314 connects THV die 202 to substrate 230 at terminal location 294 .</p><p>43, the PiP 316 again comprises a THV die 202 with a passive device 312 attached using a solder paste material 310, the device 312 comprising: It is attached to the top surface of the via 226 . The inverted bottom package 318 may in turn include devices such as QFN, SON, QFP, LGA, BGA, flip chip bare die and WLP configuration 318 . A bond pad 314 connects the THV die 202 to the substrate using a wire 209 through a passive device 312 . Again encapsulant 211 is then provided for structural support of package 316 .</p><p>As various PiP embodiments are shown, various innovative, strong, flexible and efficient PiP configurations may be implemented using the THV 226 of the THV die 202 . </p><p>While one or more embodiments of the present invention have been described, those skilled in the art will appreciate that modifications and variations of the embodiments are possible without departing from the scope of the invention as set forth in the appended claims that follow.</p>