Nova Patents
EP1563608A2

Digital signal to pulse converter

Abstract

A system is disclosed for controlling a plurality of pulse-width-modulated switching power converters. The system includes a sample and hold circuit which is configured to receive information at time-separated intervals. The information the sample and hold circuit receives includes information which is indicative of the performance of the power converters. In some embodiments, the sample and hold circuit takes samples of data from each of the switching power converters and provides information to an analog to digital conversion circuit coupled to the sample and hold circuit. In one embodiment, the plurality of pulse-width-modulated switching power are configured to independently provide power to unrelated loads.

EP1563608A2, drawing sheet 1
Sheet 1 of 44

Term

Term ended

Projected expiry passed 13 November 2023, 2.9 years ago.

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29 claims: 8 independent, 21 dependent

  1. 1
    Claims of equivalent WO 2004047266 A2 I claim:1. A digital signal to pulse converter comprising: a content addressable memory having at least a write port and a read port, wherein the write port is used to write a first set of data into the content addressable memory as stored data, and the read port is used to receive a second set of data, with the content addressable memory comparing the stored data with the second set of data and, if a match occurs, providing an output signal that determines a beginning or an end of a pulse.
  2. 2
    The digital signal to pulse converter of Claim 1, further comprising a Grey counter, coupled to the content addressable memory, adapted to provide the second set of data, and wherein the stored data in the content addressable memory is Grey coded.
  3. 3
    The digital signal to pulse converter of Claim 2 , further comprising a phase lock loop, coupled to the Grey counter, adapted to increment the Grey counter to provide the second set of data.
  4. 4
    The digital signal to pulse converter of Claim 3, further comprising a spreader divider, coupled between the phase lock loop and the Grey counter, adapted to receive a signal from the phase lock loop and provide spread spectrum clocking to the Grey counter.
  5. 5
    The digital signal to pulse converter of Claim 1, wherein the pulse is used to control a transistor for power regulation.
  6. 6
    The digital signal to pulse converter of Claim 1, wherein the pulse is used to control analog to digital signal conversion.
  7. 7
    The digital signal to pulse converter of Claim 1, 5 wherein the output signal is not encoded. .
  8. 8
    The digital signal to pulse converter of Claim 1, wherein the output signal activates one or more address lines to set or reset a latch that determines the beginning or the end of the pulse.
  9. 9
    10 9. A circuit comprising:means for generating a reference frequency;means for providing a first set of data at a rate based on the reference frequency;means for ' storing a second set of data;and 15 means for comparing the first set of data and the second set of data and providing an output signal if a match occurs that determines an edge of a pulse. 10. The circuit of Claim 9, further comprising means for providing the second set of data. 20
  10. 10
    11. The circuit of Claim 9, wherein the pulse is used to control a transistor for power regulation.
  11. 11
    12. The circuit of Claim 9, wherein the pulse is used to control analog to digital signal conversion.
  12. 12
    13. The circuit of Claim 9, wherein the output signal , 25 is not encoded.
  13. 13
    14. A method of generating a pulse, the method comprising:storing a first set of data in a content addressable memory;receiving a second set of data;comparing the first set of data to the second set of data;and providing an output signal if a match occurs as a result of the comparing of the first set of data and " the second set of data.
  14. 14
    15. The method of Claim 14, wherein the output signal determines a beginning or an end of the pulse.
  15. 15
    16. The method of Claim 14, wherein the pulse is used to control a transistor for power regulation.
  16. 16
    17. The method of Claim 14, wherein the pulse is used to control analog to digital signal conversion.
  17. 17
    18. The method of Claim 14, wherein the output signal activates one or more address lines to set or reset a latch that determines the beginning or the end of the pulse.
  18. 18
    19. A digital signal to pulse converter, comprising:a spectral spreader for receiving a first clock signal and providing an adjusted clock signal, wherein the adjusted clock signal cycles according to the first clock signal except for selected cycles of the first clock signal, and wherein the adjusted clock signal does not cycle during these selected cycles;a counter configured to cyclically count through • N counts responsive to the adjusted clock signal and provide the current _ count as an output signal;and a content addressable memory having at least a write port and a read port, wherein the write port is used to write a first set of data into the content addressable memory as stored data, and the read port is used to receive the current count, with the content addressable memory comparing the stored data with current count and, if a match occurs, providing output signals that determine a beginning or an end of a pulse, whereby each pulse is defined in a frame having a frame rate of the count rate divided.by N;wherein the spectral spreader is configured to vary the number of selected cycles to adjust the frame rate as desired.
  19. 19
    20. The digital signal to pulse converter of claim , wherein the frame rate is varied nonlinearly.
  20. 20
    21. The digital signal to pulse converter of claim , wherein the frame rate is varied linearly.
  21. 21
    22. The digital signal to pulse converter of claim , wherein the counter is a Grey counter.
  22. 22
    23. The digital signal to pulse converter of claim , further comprising:a phase locked loop for providing a second clock signal;and a divider configured to receive the second clock signal and divide this clock signal to form the first clock signal.
  23. 23
    24. The digital to signal pulse converter of claim 23, wherein the pulse is used to control a power switch for power regulation.
  24. 24
    25. The digital to signal pulse converter of claim 24, wherein the output signal activates one or more address lines to set or reset a latch that determines the beginning or end of a pulse.
  25. 25
    26. A method of digital to signal pulse conversion;comprising receiving a first clock signal and providing an adjusted clock signal based on the first clock signal, wherein the adjusted clock signal cycles according to the first clock signal except for selected cycles of the first clock signal, and wherein the adjusted clock signal does not cycle during these selected cycles;(a) cyclically counting through N counts responsive to the adjusted clock signal comparing the current count from act (a) with stored data in a content addressable memory and, if a match occurs, providing output signals that determine a beginning or an end of a pulse, whereby each pulse is defined in a frame having a frame rate of the count rate used in act (a) divided by N;and varying the number of selected cycles to adjust the frame rate as desired.
  26. 26
    27. The method of claim 26, wherein the frame rate is varied nonlinearly.
  27. 27
    28. The ' ethod of claim 27, wherein the frame rate is varied linearly.
  28. 28
    29. The method of claim 28, wherein the counting in act (a) occurs according to a Grey count.
Independent claims28