Photoelectric conversion apparatus and imaging system having revision with multiple impurity densities

TECHNICAL FIELD

0001The present invention relates to a photoelectric conversion apparatus and an imaging system.

BACKGROUND ART

0002Japanese Patent Laid-Open No. 2005-197674 (called “Patent Document 1” hereinafter) discloses a photoelectric conversion apparatus in which a P-type well to be disposed below an N-type charge accumulating area is described as being configured of multiple impurity areas 4A to 4D having differing depths, as shown in FIG. 1 of that document. The density of the impurity area 4A, which is the deepest of the multiple impurity areas 4A to 4D, is greater than the densities of the other impurity areas. Therefore, according to Patent Document 1, a potential barrier for electrons can be formed in the depth direction of the substrate, which makes it possible to guide the carrier to a photodiode in the depth direction efficiently and without loss, which in turn makes it possible to improve the sensitivity.

0003Incidentally, there is demand for pixel miniaturization and pixel sensitivity improvement in photoelectric conversion apparatuses. It is conceivable that miniaturizing the pixels in the photoelectric conversion apparatus disclosed in Patent Document 1 will also bring adjacent photodiodes closer to each other.

0004Patent Document 1 discloses forming the multiple impurity areas 4A to 4D by implanting boron, first in deep areas and moving sequentially to shallow areas, and then executing a heat treatment of 950° C. or less. When executing such heat treatment after forming the multiple impurity areas 4A to 4D, boron tends to diffuse even under heat treatments of 950° C. or less, and therefore the impurity density peaks in the respective impurity areas 4A to 4D drop easily. As a result, the slope of the potential along the substrate depth direction broadens, resulting in the possibility that the electrons will not reach the photodiodes of pixels in which electrons are produced and will instead reach adjacent pixels based on the mechanics of diffusion. In color sensors whose pixels have different spectral transmission characteristics from one another, this phenomenon results in a problem called “color mixture”, whereby light of a certain color leaks into pixels that respond to a different color. In monochromatic sensors, this phenomenon appears as a drop in the MTF. This problem is apparent particularly when the distance between adjacent photodiodes (photoelectric conversion portions) is low.

DISCLOSURE OF INVENTION

0005It is an object of the present invention to efficiently collect holes, which make up a signal charge produced by a photoelectric conversion portion, in a charge accumulating area.

0006A photoelectric conversion apparatus according to a first aspect of the present invention includes multiple photoelectric conversion portions disposed in a semiconductor substrate. Each photoelectric conversion portion has a P-type charge accumulating area containing a first impurity and an N-type well portion that, along with the P-type charge accumulating area, configures a photodiode. Each well portion has an N-type first semiconductor region containing arsenic at a first density, an N-type second semiconductor region disposed below the first semiconductor region and containing arsenic at a second density that is lower than the first density, and an N-type third semiconductor region disposed below the second semiconductor region and containing a second impurity at a third density that is higher than the first density.

0007An imaging system according to a second aspect of the present invention includes: the photoelectric conversion apparatus according to the first aspect of the present invention; an optical system that forms an image upon an imaging area of the photoelectric conversion apparatus; and a signal processing unit that generates image data by processing a signal outputted from the photoelectric conversion apparatus.

0008According to the present invention, it is possible to efficiently collect holes, which make up a signal charge produced by a photoelectric conversion portion, in a charge accumulating area.

0009Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).

BRIEF DESCRIPTION OF DRAWINGS

0010<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating the overall configuration of a photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention.

0011<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating the configuration of a pixel P according to an embodiment of the present invention.

0012<figref idref="DRAWINGS">FIG. 3</figref> is a diagram illustrating the cross-sectional structure of the photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention.

0013<figref idref="DRAWINGS">FIGS. 4A through 4C</figref> are cross-sections illustrating steps of a photoelectric conversion apparatus manufacturing method according to an embodiment of the present invention.

0014<figref idref="DRAWINGS">FIGS. 5A through 5C</figref> are cross-sections illustrating steps of a photoelectric conversion apparatus manufacturing method according to an embodiment of the present invention.

0015<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are cross-sections illustrating steps of a photoelectric conversion apparatus manufacturing method according to an embodiment of the present invention.

0016<figref idref="DRAWINGS">FIGS. 7A through 7C</figref> are diagrams illustrating the results of a simulation of the effects of thermal diffusion.

0017<figref idref="DRAWINGS">FIGS. 8A through 8C</figref> are diagrams illustrating the results of a simulation of the effects of thermal diffusion (a variation).

0018<figref idref="DRAWINGS">FIG. 9</figref> is a diagram illustrating the cross-sectional structure of a photoelectric conversion apparatus according to a second embodiment of the present invention.

0019<figref idref="DRAWINGS">FIG. 10</figref> is a diagram illustrating the results of a simulation of the effects of thermal diffusion according to the second embodiment.

0020<figref idref="DRAWINGS">FIG. 11</figref> is a diagram illustrating the cross-sectional structure of a photoelectric conversion apparatus according to a third embodiment of the present invention.

0021<figref idref="DRAWINGS">FIG. 12</figref> is a diagram illustrating the configuration of an imaging system in which the photoelectric conversion apparatus according to an embodiment of the present invention has been applied.

BEST MODE FOR CARRYING OUT THE INVENTION

0022In the present specification, disposing a second area “above” a first area includes cases where the second area is disposed upon another area that is itself disposed upon the first area, in addition to cases where the second area is disposed directly upon the first area. Similarly, disposing a second area “below” a first area includes cases where the second area is disposed below another area that is itself disposed below the first area, in addition to cases where the second area is disposed directly below the first area.

0023The overall configuration of a photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention shall be described using <figref idref="DRAWINGS">FIG. 1</figref>. <figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating the overall configuration of the photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention.

0024The photoelectric conversion apparatus <b>1</b> includes a pixel array PA, a vertical scanning circuit <b>10</b>, a holding circuit <b>20</b>, a horizontal scanning circuit <b>30</b>, and an output amplifier <b>40</b>.

0025Multiple pixels P (see <figref idref="DRAWINGS">FIG. 2</figref>) are arranged one- or two-dimensionally in the pixel array PA. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, each pixel P includes a photoelectric conversion portion <b>51</b>, a transfer unit <b>52</b>, a charge-voltage conversion unit <b>53</b>, a reset unit <b>54</b>, and an output unit <b>55</b>. Note that <figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating the configuration of the pixel P according to an embodiment of the present invention.

0026The photoelectric conversion portion <b>51</b> produces a charge based on light and stores the charge. Here, the signal charge is holes. The photoelectric conversion portion <b>51</b> is, for example, a photodiode whose cathode is connected to a ground potential and whose anode is connected to the transfer unit <b>52</b>.

0027The transfer unit <b>52</b> transfers the signal charge produced by the photoelectric conversion portion <b>51</b> to the charge-voltage conversion unit <b>53</b>.

0028The transfer unit <b>52</b> is, for example, a PMOS transfer transistor, and transfers the signal charge produced by the photoelectric conversion portion <b>51</b> to the charge-voltage conversion unit <b>53</b> by turning on when an active-level transfer control signal is supplied from the vertical scanning circuit <b>10</b>.

0029The charge-voltage conversion unit <b>53</b> converts the transferred charge into a voltage. The charge-voltage conversion unit <b>53</b> has, for example, a P-type floating diffusion.

0030The reset unit <b>54</b> resets the charge-voltage conversion unit <b>53</b> and places the pixel P in a selected/non-selected state based on a supplied reset potential. The reset unit <b>54</b> is, for example, a PMOS reset transistor, and resets the charge-voltage conversion unit <b>53</b> by turning on when an active-level reset control signal has been supplied from the vertical scanning circuit <b>10</b>. The reset unit <b>54</b> places a pixel in a selected state by resetting the potential of the charge-voltage conversion unit <b>53</b> to a first reset potential in response to a supplied first reset potential (for example, L level). Meanwhile, the reset unit <b>54</b> places a pixel in a non-selected state by resetting the potential of the charge-voltage conversion unit <b>53</b> to a second reset potential in response to a supplied second reset potential (for example, H level).

0031The output unit <b>55</b> outputs a signal based on the voltage of the charge-voltage conversion unit <b>53</b> to a signal line SL. The output unit <b>55</b> is, for example, a PMOS amplifying transistor, and outputs a signal based on the voltage of the charge-voltage conversion unit <b>53</b> to the signal line SL by performing a source-follow operation with a constant current source CS connected to the signal line SL. In other words, the output unit <b>55</b> outputs a noise signal to the signal line SL based on the voltage of the charge-voltage conversion unit <b>53</b> in a state where the charge-voltage conversion unit <b>53</b> has been reset by the reset unit <b>54</b>. The output unit <b>55</b> outputs, to the signal line SL, an optical signal based on the voltage of the charge-voltage conversion unit <b>53</b> in the state when the signal charge of the photoelectric conversion portion <b>51</b> was transferred to the charge-voltage conversion unit <b>53</b> by the transfer unit <b>52</b>.

0032Note that each pixel P may be configured so as to include a selection unit (not shown). In this case, the selection unit switches the pixel P between the selected/non-selected states. The selection unit is, for example, a PMOS select transistor, and puts the pixel P in a selected state by turning on when an active-level selection control signal has been supplied from the vertical scanning circuit <b>10</b>. The selection unit also puts the pixel P in a non-selected state by turning off when a non-active level selection control signal has been supplied from the vertical scanning circuit <b>10</b>.

0033The vertical scanning circuit <b>10</b> selects a readout row in the pixel array PA from which signals are to be read out by scanning the pixel array PA in the vertical direction, and outputs the signals from the readout row to multiple signal lines SL.

0034The holding circuit <b>20</b> temporarily holds signals (noise signals, optical signals) of multiple columns outputted from the readout row via the multiple signal lines SL.

0035The horizontal scanning circuit <b>30</b> sequentially transfers, to the output amplifier <b>40</b>, the signals (noise signals, optical signals) of the multiple columns held in the holding circuit <b>20</b> by scanning the holding circuit <b>20</b> in the horizontal direction.

0036The output amplifier <b>40</b> generates an image signal based on the transferred signals (noise signals, optical signals). For example, the output amplifier generates an image signal by finding the difference between a noise signal and an optical signal. The output amplifier <b>40</b> outputs the generated image signal to a later stage (an imaging signal processing circuit <b>95</b>, described later).

0037Next, the cross-sectional structure of the photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention shall be described using <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 3</figref> is a diagram illustrating the cross-sectional structure of the photoelectric conversion apparatus <b>1</b> according to an embodiment of the present invention. A pixel region PR, corresponding to a single pixel, is shown in <figref idref="DRAWINGS">FIG. 3</figref>.

0038The photoelectric conversion apparatus <b>1</b> includes multiple photoelectric conversion portions <b>51</b>, multiple device isolation areas <b>103</b>, a well portion <b>102</b>, and multiple channel stop portions CS.

0039The multiple photoelectric conversion portions <b>51</b> are disposed in a semiconductor substrate SB. The semiconductor substrate SB is formed primarily of, for example, silicon. Although not depicted in <figref idref="DRAWINGS">FIG. 3</figref>, the multiple photoelectric conversion portions <b>51</b> are disposed in what is a one-dimensional or two-dimensional array when viewed from above. A ground region <b>101</b> is disposed in the semiconductor substrate SB extending across all pixel regions PR in the location furthest from a surface SBa. The ground region <b>101</b> is a region of the semiconductor substrate SB that has not been implanted with impurities. The ground region <b>101</b> contains a P-type impurity.

0040The photoelectric conversion portion <b>51</b> produces a charge pair based on light and accumulates holes, which are signal charges. Each photoelectric conversion portion <b>51</b> is, for example, a photodiode. The photoelectric conversion portion <b>51</b> includes a charge accumulating area <b>107</b>, a surface region <b>108</b>, and an effective sensitivity region (charge collecting area) <b>109</b>. The effective sensitivity region (charge collecting area) is provided as necessary.

0041The charge accumulating area <b>107</b> is disposed below the surface region <b>108</b>. The charge accumulating area <b>107</b> contains a P-type first impurity at a higher density than that of the ground region <b>101</b>. The first impurity is, for example, boron. The charge accumulating area <b>107</b> is formed through, for example, boron ion implantation. The charge accumulating area <b>107</b> accumulates holes.

0042The surface region <b>108</b> contains an N-type impurity at a higher density than the density of the first impurity in the charge accumulating area <b>107</b>. The surface region <b>108</b> contains the N-type impurity at a sixth density. The sixth density is a density that is higher than a fourth density (the density of an N-type impurity in a semiconductor region <b>104</b>), which shall be mentioned later. The surface region <b>108</b> is formed through, for example, arsenic ion implantation. A photodiode becomes a buried photodiode due to the surface region <b>108</b>, and therefore the generation of dark current caused by a dangling bond at the surface SBa of the semiconductor substrate SB can be suppressed.

0043The effective sensitivity region <b>109</b> is disposed below the charge accumulating area <b>107</b>. The effective sensitivity region <b>109</b> contains a P-type impurity at a lower density than that of the charge accumulating area <b>107</b>. While it is possible to form the effective sensitivity region <b>109</b> through boron ion implantation, it is also possible to use a region of the semiconductor substrate SB in which impurities have not been implanted as the effective sensitivity region <b>109</b>. The effective sensitivity region <b>109</b> collects the charge (for example, a positive charge from holes) produced by photoelectric conversion and guides the charge to the charge accumulating area <b>107</b>.

0044The multiple device isolation areas <b>103</b> are disposed between the multiple photoelectric conversion portions <b>51</b> in the semiconductor substrate SB so as to isolate the photoelectric conversion portions <b>51</b> from one another. “Isolation” as used here refers to electrically isolating at least the charge accumulating areas <b>107</b> from each other. It is, however, further preferable for the effective sensitivity regions <b>109</b> to be electrically isolated from each other as well. As opposed to this, the surface regions <b>108</b> and buried regions <b>102</b> need not be isolated. Although not shown here, the multiple device isolation areas <b>103</b> extend between the multiple photoelectric conversion portions <b>51</b> in strip form or grid form so as to isolate the multiple photoelectric conversion portions <b>51</b> from one another.

0045Each device isolation area <b>103</b> is disposed above a channel stop portion CS. The channel stop portion CS is configured so as to include a channel stop region <b>104</b> disposed at the border of a device isolation region and configured of an insulator, and semiconductor regions <b>105</b> and <b>106</b> that function as potential barriers. Each device isolation area <b>103</b> is disposed laterally to the surface region <b>108</b> in the photoelectric conversion portion <b>51</b>. Each device isolation portion <b>103</b> is formed of an insulator such as silicon oxide. The device isolation portion <b>103</b> may have, for example, an STI (Shallow Trench Isolation) structure, or may have a LOCOS (LOCal Oxidation of Silicon) structure. Alternatively, diffusive isolation may be employed.

0046The well portion <b>102</b> configures the photodiode along with the charge accumulating area <b>107</b>. Although the well portion <b>102</b> is illustrated in <figref idref="DRAWINGS">FIG. 3</figref> as being disposed in a location deep within the substrate under the effective sensitivity region, the effective sensitivity region may be omitted and the well portion <b>102</b> provided directly below the charge accumulating area <b>107</b>. The well portion <b>102</b> is disposed above the ground region <b>101</b>. Although not illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the well portion <b>102</b> may be disposed across all pixel regions PR beneath the multiple photoelectric conversion portions <b>51</b> and the multiple device isolation areas <b>103</b>, or in other words, disposed extending across the entirety of the pixel array PA (see <figref idref="DRAWINGS">FIG. 1</figref>).

0047The well portion <b>102</b> contains multiple semiconductor regions at differing depths from the surface SBa of the semiconductor substrate SB. In other words, the well portion <b>102</b> contains a semiconductor region (first semiconductor region) <b>102</b><i>a</i>, a semiconductor region (second semiconductor region) <b>102</b><i>b</i>, a semiconductor region (second semiconductor region) <b>102</b><i>c</i>, and a semiconductor region (third semiconductor region) <b>102</b><i>d. </i>

0048The semiconductor region <b>102</b><i>a </i>is disposed in the shallowest location of the well portion <b>102</b>. The semiconductor region <b>102</b><i>a </i>is disposed below the charge accumulating area <b>107</b>, with the effective sensitivity region <b>109</b> located therebetween. However, the effective sensitivity region <b>109</b> need not be provided. The semiconductor region <b>102</b><i>a </i>contains an N-type second impurity at a first density (see the density profile PF<b>2</b><i>a </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The second impurity uses, for example, arsenic as its primary component. The first density is a density that is higher than the density of the P-type impurity in the ground region <b>101</b>.

0049The semiconductor region <b>102</b><i>b </i>is disposed between the semiconductor region <b>102</b><i>a </i>and the semiconductor region <b>102</b><i>d </i>in the direction that is perpendicular to the surface of the semiconductor substrate SB. The semiconductor region <b>102</b><i>b </i>is disposed below the semiconductor region <b>102</b><i>a</i>. The semiconductor region <b>102</b><i>b </i>contains the N-type second impurity at a second density. The second density is a density that is lower than the first density (see the density profile PF<b>2</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). Note that a P-type region that is completely depleted due to built-in potential and that is of a thickness that does not cause operational problems may be left between the semiconductor region <b>102</b><i>a </i>and the semiconductor region <b>102</b><i>b. </i>

0050The semiconductor region <b>102</b><i>c </i>is disposed between the semiconductor region <b>102</b><i>a </i>and the semiconductor region <b>102</b><i>d </i>in the direction that is perpendicular to the surface of the semiconductor substrate SB. The semiconductor region <b>102</b><i>c </i>is disposed below the semiconductor region <b>102</b><i>b</i>. The semiconductor region <b>102</b><i>c </i>contains the N-type second impurity at the second density. The second density is a density that is lower than the first density (see the density profile PF<b>2</b><i>c </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). Note that a P-type region that is completely depleted due to built-in potential and that is of a thickness that does not cause operational problems may be left between the semiconductor region <b>102</b><i>b </i>and the semiconductor region <b>102</b><i>c. </i>

0051The semiconductor region <b>102</b><i>d </i>is disposed in the deepest location of the well portion <b>102</b>. The semiconductor region <b>102</b><i>d </i>is disposed below the semiconductor region <b>102</b><i>c</i>. The semiconductor region <b>102</b><i>d </i>contains the N-type second impurity at a third density. The third density is a density that is higher than the first density (see the density profile PF<b>2</b><i>d </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). Note that a P-type region that is completely depleted due to built-in potential and that is of a thickness that does not cause operational problems may be left between the semiconductor region <b>102</b><i>c </i>and the semiconductor region <b>102</b><i>d. </i>

0052The multiple channel stop portions CS suppress the formation of channels at the borders of device isolation regions caused by insulators. Furthermore, each channel stop portion CS is disposed below a corresponding device isolation area <b>103</b> in the direction perpendicular to the surface of the semiconductor substrate SB, so as to isolate the multiple photoelectric conversion portions <b>51</b> from one another. Although not shown here, the multiple channel stop portions CS extend between the multiple photoelectric conversion portions <b>51</b> in strip form or grid form so as to isolate the multiple photoelectric conversion portions <b>51</b> from one another.

0053Each channel stop portion CS contains a semiconductor region (fourth semiconductor region) <b>104</b>, as well as a semiconductor region (fifth semiconductor region) <b>105</b> and a semiconductor region (fifth semiconductor region) <b>106</b> disposed between photoelectric conversion portions and functioning as potential barriers for holes.

0054The semiconductor region <b>104</b> covers at least the base surface of the device isolation area <b>103</b>, and furthermore extends to the surface region <b>108</b>. The semiconductor region <b>104</b> is disposed below the device isolation area <b>103</b> so as to cover the base of the device isolation area <b>103</b>. The semiconductor region <b>104</b> is disposed in a position deeper than the surface SBa of the semiconductor substrate SB and extended lateral to the charge accumulating area <b>107</b>. The semiconductor region <b>104</b> contains the N-type second impurity at a fourth density. The second impurity uses, for example, arsenic, which is an N-type impurity, as its primary component. The fourth density is a density that is higher than the second density (see the density profile PF<b>2</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The fourth density may be equal to the first density (see the density profile PF<b>2</b><i>a </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The semiconductor region <b>104</b> is formed by, for example, arsenic ion implantation.

0055The semiconductor region <b>105</b> is disposed below the semiconductor region <b>104</b>. The semiconductor region <b>105</b> is also disposed lateral to the effective sensitivity region <b>109</b>. The semiconductor region <b>105</b> contains the second impurity at a fifth density. The fifth density is a density that is higher than the second density (see the density profile PF<b>2</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The fifth density may be equal to the first density (see the density profile PF<b>2</b><i>a </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The second impurity uses, for example, arsenic, which is an N-type impurity, as its primary component. The semiconductor region <b>105</b> is formed by, for example, arsenic ion implantation.

0056The semiconductor region <b>106</b> is disposed below the semiconductor region <b>105</b>. The semiconductor region <b>106</b> is also disposed lateral to the effective sensitivity region <b>109</b>. The semiconductor region <b>105</b> contains the second impurity at the fifth density. The fifth density is a density that is higher than the second density (see the density profile PF<b>2</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The fifth density may be equal to the first density (see the density profile PF<b>2</b><i>a </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>). The second impurity uses, for example, arsenic, which is an N-type impurity, as its primary component. The semiconductor region <b>105</b> is formed by, for example, arsenic ion implantation.

0057Here, the mass of the second impurity (for example, arsenic) contained in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>in the well portion <b>102</b> is greater than the mass of the P-type impurity (for example, boron). Based on this, the diffusion coefficient of the second impurity is lower than the diffusion coefficient of the P-type impurity. Accordingly, even if the well portion is formed by executing heat treatment following impurity implantation, the impurity density peaks in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>do not easily drop. Therefore, a higher potential barrier (see the potential levels PH<b>2</b><i>a </i>and PH<b>2</b><i>d </i>illustrated in <figref idref="DRAWINGS">FIG. 7C</figref>) can be maintained for holes, which are the signal charge, than in the case where the well portion is formed of multiple semiconductor regions that contain P-type impurities and are located at different depths. The semiconductor region <b>102</b><i>d </i>disposed in the deepest position has the highest impurity density, whereas the semiconductor region <b>102</b><i>a </i>disposed closest to the surface has the next-highest impurity density; the semiconductor regions <b>102</b><i>b </i>and <b>102</b><i>c </i>have the lowest impurity densities. The semiconductor regions <b>102</b><i>b </i>and <b>102</b><i>c </i>may be configured as a single region. Employing such an impurity density relationship makes it possible to maintain the electrical field in the vertical direction and efficiently guide the holes, which make up the signal charge produced by the photoelectric conversion portion, to the charge accumulating area. It is further possible to suppress the expansion of a depleted layer from the charge accumulating area <b>107</b>, thereby making it possible to reduce the driving voltage when reading out signals.

0058As shall be described later, forming the semiconductor regions <b>102</b><i>a </i>and <b>102</b><i>b </i>from arsenic makes it possible to suppress distribution changes in the N well that spreads across the entire pixel, thereby making it possible to further enhance the aforementioned effects. Furthermore, it is difficult for holes to pass through the multiple semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>and reach adjacent photoelectric conversion portions. Therefore, color mixture, which occurs when the distance between adjacent photoelectric conversion portions drops, can be suppressed.

0059Next, a manufacturing method for a photoelectric conversion apparatus according to an embodiment of the present invention shall be described using <figref idref="DRAWINGS">FIGS. 4A to 6B</figref>. <figref idref="DRAWINGS">FIGS. 4A through 6B</figref> are cross-sections illustrating steps of a photoelectric conversion apparatus manufacturing method according to an embodiment of the present invention.

0060In the step illustrated in <figref idref="DRAWINGS">FIG. 4A</figref>, a resist is applied to the semiconductor substrate SB and then patterned through an exposure process, thereby forming a first resist pattern (not shown) that exposes the pixel array PA (see <figref idref="DRAWINGS">FIG. 1</figref>). The semiconductor region <b>102</b><i>d </i>is then formed by implanting the semiconductor substrate SB with the N-type second impurity, using the first resist pattern as a mask. The second impurity uses, for example, arsenic as its primary component. At this time, for example, the dose of the second impurity is 5×10¹³/cm², and the acceleration energy of the implantation is 4000 KeV.

0061The semiconductor region <b>102</b><i>c </i>is then formed by implanting the semiconductor substrate SB with the N-type second impurity, using the first resist pattern as a mask. The second impurity uses, for example, arsenic as its primary component. At this time, for example, the dose of the second impurity is 5×10¹¹/cm², and the acceleration energy of the implantation is 2500 KeV.

0062The semiconductor region <b>102</b><i>b </i>is then formed by implanting the semiconductor substrate SB with the N-type second impurity, using the first resist pattern as a mask. The second impurity uses, for example, arsenic as its primary component. At this time, for example, the dose of the second impurity is 5×10¹¹/cm², and the acceleration energy of the implantation is 1200 KeV.

0063The semiconductor region <b>102</b><i>a </i>is then formed by implanting the semiconductor substrate SB with the N-type second impurity, using the first resist pattern as a mask. The second impurity uses, for example, arsenic as its primary component. At this time, it is preferable for, for example, the dose of the second impurity to be 10¹²/cm², and the acceleration energy of the implantation to be 600 KeV.

0064In the step illustrated in <figref idref="DRAWINGS">FIG. 4B</figref>, an STI device isolation area <b>103</b> is formed by first forming channels in regions in which the multiple photoelectric conversion portions in the semiconductor substrate SB are to be isolated from one another, and then burying an insulator in those channels.

0065In the step illustrated in <figref idref="DRAWINGS">FIG. 4C</figref>, a resist is applied to the semiconductor substrate SB and then patterned through an exposure process, thereby forming a second resist pattern <b>110</b> that exposes the device isolation areas. Semiconductor regions <b>104</b>′ are then formed in the semiconductor substrate SB below the device isolation areas <b>103</b> by implanting the N-type second impurity in the semiconductor substrate SB using the second resist pattern <b>110</b> as a mask. The N-type second impurity in this step is, for example, arsenic, which is an N-type impurity. It is preferable for the acceleration energy of the implantation in the step to be approximately 300 keV to 2 MeV, and further preferable for the acceleration energy to be approximately 500 keV to 900 keV.

0066In the step illustrated in <figref idref="DRAWINGS">FIG. 5A</figref>, semiconductor regions <b>105</b>′ are formed in the semiconductor substrate SB below the semiconductor regions <b>104</b>′ by implanting the semiconductor substrate SB with the N-type second impurity, using the second resist pattern <b>110</b> as a mask. In addition, semiconductor regions <b>106</b>′ are formed in the semiconductor substrate SB below the semiconductor regions <b>105</b>′ by implanting the semiconductor substrate SB with the N-type second impurity, using the second resist pattern <b>110</b> as a mask. The N-type second impurity in this step is, for example, arsenic, which is an N-type impurity. It is preferable for the acceleration energy of the implantation in the step to be approximately 300 keV to 2 MeV, and further preferable for the acceleration energy to be approximately 500 keV to 900 keV.

0067Here, the aforementioned conditions can be used as the conditions for each instance of implantation. Furthermore, in the present embodiment, the semiconductor region <b>104</b>′, the semiconductor region <b>105</b>′, and the semiconductor region <b>106</b>′ can be formed using the same resist pattern. This enables low-cost manufacture without an increase in the number of processing steps. It also makes it possible to suppress variance in the properties arising in the manufacture due to misalignments.

0068In the step illustrated in <figref idref="DRAWINGS">FIG. 5B</figref>, the second resist pattern <b>110</b> is removed.

0069In the step illustrated in <figref idref="DRAWINGS">FIG. 5C</figref>, a resist is applied to the semiconductor substrate SB and then patterned through an exposure process, thereby forming a third resist pattern (not shown) that exposes the regions in which the multiple photoelectric conversion portions are to be disposed. The charge accumulation areas <b>107</b> of the photoelectric conversion portions <b>51</b> are then formed between the multiple device isolation areas <b>103</b> in the semiconductor substrate SB by implanting a P-type first impurity in the semiconductor substrate SB using the third resist pattern as a mask. The P-type first impurity in this step is, for example, boron, which is a P-type impurity. It is preferable for the acceleration energy of the implantation in the step to be approximately 50 to 200 keV.

0070In the step illustrated in <figref idref="DRAWINGS">FIG. 6A</figref>, the surface regions <b>108</b> of the photoelectric conversion portions <b>51</b> are then formed between the multiple device isolation areas <b>103</b> in the semiconductor substrate SB by implanting a P-type impurity in the semiconductor substrate SB using the third resist pattern as a mask. The P-type impurity in this step is, for example, arsenic, which is a P-type impurity. It is preferable for the acceleration energy of the implantation in the step to be approximately 30 to 120 keV.

0071In the step illustrated in <figref idref="DRAWINGS">FIG. 6B</figref>, the semiconductor regions <b>104</b> to <b>106</b> are stabilized through thermal diffusion (heat treatment). During this thermal diffusion, the arsenic contained in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>and the semiconductor regions <b>104</b>′ to <b>106</b>′ has a low diffusion coefficient and thus exhibits little diffusion with respect to the profile immediately following implantation.

0072Next, the effects of the present embodiment shall be described using <figref idref="DRAWINGS">FIGS. 7A to 7C</figref>. <figref idref="DRAWINGS">FIGS. 7A to 7C</figref> are diagrams illustrating the results of a simulation of the effects of thermal diffusion.

0073In <figref idref="DRAWINGS">FIG. 7A</figref>, the solid lines indicate the density profiles PFa to PFd of the arsenic in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d</i>, respectively, following the completion of the step illustrated in <figref idref="DRAWINGS">FIG. 4A</figref> in the present embodiment, which uses arsenic as the second impurity. These conditions shall be called a “working example”.

0074Here, for comparative purposes, a case in which the conductivity types of the constituent elements in the present embodiment are all reversed and the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>are formed through boron ion implantation shall be considered. In this case as well, it is assumed that the density profiles of the boron in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d</i>, respectively, are the same as the density profiles PFa to PFd illustrated in <figref idref="DRAWINGS">FIG. 7A</figref>. These conditions shall be called a “comparative example”.

0075Regarding the conditions of the “comparative example”, the results of a simulation of the effects of thermal diffusion at 900° C. for approximately one hour following boron ion implantation are expressed by density profiles PF<b>1</b><i>a </i>to PF<b>1</b><i>d</i>, indicated by the dotted lines in <figref idref="DRAWINGS">FIG. 7B</figref>. The density profiles PFa to PFd illustrated in <figref idref="DRAWINGS">FIG. 7A</figref> are also shown in <figref idref="DRAWINGS">FIG. 7B</figref> for comparative purposes. As shown in <figref idref="DRAWINGS">FIG. 7B</figref>, when the ion type is boron, the density profiles PF<b>1</b><i>a </i>and PF<b>1</b><i>d </i>of the semiconductor regions <b>102</b><i>a </i>and <b>102</b><i>d</i>, respectively, are broad due to the thermal diffusion. As a result, potential levels PH<b>1</b><i>a </i>and PH<b>1</b><i>d </i>of the semiconductor regions <b>102</b><i>a </i>and <b>102</b><i>d </i>with respect to electrons, which are the carriers of the signal charge in the “comparative example” conditions, are low.

0076However, regarding the conditions of the “working example”, the results of a simulation of the effects of thermal diffusion at 900° C. for approximately 1 hour following arsenic ion implantation are expressed by density profiles PF<b>2</b><i>a </i>to PF<b>2</b><i>d</i>, indicated by the dot-dash lines in <figref idref="DRAWINGS">FIG. 7C</figref>. The density profiles PFa to PFd illustrated in <figref idref="DRAWINGS">FIG. 7A</figref> are also shown in <figref idref="DRAWINGS">FIG. 7C</figref> for comparative purposes. As shown in <figref idref="DRAWINGS">FIG. 7C</figref>, when the ion type is arsenic, the density profiles PF<b>2</b><i>a </i>and PF<b>2</b><i>d </i>of the semiconductor regions <b>102</b><i>a </i>and <b>102</b><i>d</i>, respectively, are kept sharp due to the thermal diffusion. As a result, potential levels PH<b>2</b><i>a </i>and PH<b>2</b><i>d </i>of the semiconductor regions <b>102</b><i>a </i>and <b>102</b><i>d </i>with respect to holes, which are the carriers of the signal charge in the “working example” conditions, are kept high. In other words, <br />PH2a>PH1a,PH2d>PH1d  Equation 1

0077Therefore, according to the “working example” conditions, it is more difficult for the signal charge carrier to pass through the multiple semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>and reach adjacent photoelectric conversion portions than with the “comparative example” conditions. As a result, the “working example” conditions make it possible to suppress color mixture, which occurs when the distance between adjacent photoelectric conversion portions drops, more than the “comparative example” conditions.

0078Furthermore, with the “working example” conditions, the diffusion distance from the semiconductor region <b>102</b><i>a </i>to the effective sensitivity region <b>109</b> in the depth direction is reduced, making it possible to suppress a decrease in the area of the effective sensitivity region <b>109</b> more than with the “comparative example” conditions.

0079Note that the semiconductor region <b>102</b><i>d </i>in the well portion <b>102</b> may contain a third impurity at the third density. The second impurity uses, for example, arsenic as its primary component. Meanwhile, the third impurity uses, for example, phosphorous as its primary component. The mass of the third impurity is lower than the mass of the second impurity. As a result, it is easy to form the semiconductor region <b>102</b><i>d </i>at a deep position in the semiconductor substrate, thereby making it possible to improve the freedom with which the well portion <b>102</b> can be designed.

0080In addition, in this case too, the sharpness of the density profile PF<b>3</b><i>d </i>of phosphorous in the semiconductor region <b>102</b><i>d </i>following thermal diffusion is maintained, as compared to the “comparative example” conditions, as can be seen in <figref idref="DRAWINGS">FIGS. 8A to 8C</figref>. As a result, the potential level PH<b>3</b><i>d </i>of the semiconductor region <b>102</b><i>d </i>with respect to holes, which are the carriers of the signal charge in the “working example” conditions, is kept high. In other words, <br />PH3d>PH1d  Equation 2<br /> Thus, according to the “working example” conditions, it is more difficult for the signal charge carrier to pass through the multiple semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>and reach adjacent photoelectric conversion portions than with the “comparative example” conditions. As a result, the “working example” conditions make it possible to suppress color mixture, which occurs when the distance between adjacent photoelectric conversion portions drops, more than the “comparative example” conditions.

0081<figref idref="DRAWINGS">FIG. 9</figref> is a diagram illustrating the cross-sectional structure of a photoelectric conversion apparatus according to another embodiment of the present invention. Constituent elements that have the same functions as those illustrated in <figref idref="DRAWINGS">FIG. 3</figref> shall be given the same reference numerals, and detailed descriptions thereof shall be omitted.

0082The cross-section shown in <figref idref="DRAWINGS">FIG. 9</figref> illustrates a transfer gate electrode <b>201</b> disposed above the semiconductor substrate surface SBa with an oxide film (not shown) therebetween. A transfer channel is formed below the transfer gate electrode <b>201</b> by a bias applied to the transfer gate electrode <b>201</b>. <b>202</b> is a floating diffusion configured of a P-type semiconductor region. In the present embodiment, the charge accumulating area <b>107</b>, the transfer gate electrode <b>201</b>, and the floating diffusion <b>202</b> configure a P-type transfer transistor.

0083The main difference between the present embodiment and the configuration shown in <figref idref="DRAWINGS">FIG. 3</figref> is as follows: while in <figref idref="DRAWINGS">FIG. 3</figref> the well portion <b>102</b> is disposed in a location deep within the substrate below the effective sensitivity region <b>109</b>, in the present embodiment, the effective sensitivity region <b>109</b> is not provided, and the well portion <b>102</b> is provided near to the charge accumulate in area <b>107</b>.

0084<figref idref="DRAWINGS">FIG. 10</figref> illustrates an impurity density profile in the depth direction following the A-B line shown in <figref idref="DRAWINGS">FIG. 9</figref>. The well portion <b>102</b> contains multiple N-type semiconductor regions of differing depths from the surface SBa of the semiconductor substrate. The semiconductor region <b>102</b><i>d </i>disposed in the deepest position has the highest impurity density, whereas the semiconductor region <b>102</b><i>a </i>disposed closest to the surface has the next-highest impurity density; the semiconductor regions <b>102</b><i>b </i>and <b>102</b><i>c </i>have the lowest impurity densities.

0085The mass of the impurity (for example, arsenic) contained in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>is greater than the mass of the P-type impurity (for example, boron). Accordingly, even if the well portion is formed by executing heat treatment following impurity implantation, the impurity density peak values in the semiconductor regions <b>102</b><i>a </i>to <b>102</b><i>d </i>do not easily drop. According to such a configuration, it is possible to maintain the electrical field in the vertical direction from the location deep within the substrate to the surface and efficiently guide the holes produced by the photoelectric conversion portion <b>51</b> to the charge accumulating area, thereby making it possible to reduce color mixture between pixels.

0086The semiconductor region <b>102</b><i>a</i>, which is closest to the surface, is disposed immediately below the charge accumulating area <b>107</b>. A PN junction is configured by the charge accumulating area <b>107</b> and the semiconductor region <b>102</b><i>a</i>. According to this configuration, the charge accumulating area <b>107</b> and the semiconductor region <b>102</b><i>a </i>are disposed near one another, thereby making it possible to suppress the expansion of a depleted layer from the charge accumulating area <b>107</b>. Increasing the impurity density of the semiconductor region <b>102</b><i>a </i>closest to the surface makes it possible to suppress the expansion of the depleted layer with ease, particularly in the case where the impurity density of the charge accumulating area <b>107</b> has been increased in order to improve the saturation load. Through this, the amplitude of the driving voltage during signal readout can be suppressed even further.

0087<figref idref="DRAWINGS">FIG. 11</figref> is a diagram illustrating the cross-sectional structure of a photoelectric conversion apparatus according to another embodiment of the present invention. Constituent elements that have the same functions as those illustrated in <figref idref="DRAWINGS">FIG. 9</figref> shall be given the same reference numerals, and detailed descriptions thereof shall be omitted.

0088The main difference between the present embodiment and the configuration shown in <figref idref="DRAWINGS">FIG. 9</figref> is that N-type semiconductor regions <b>305</b> and <b>306</b> are disposed below the channel stop region <b>104</b>. The N-type semiconductor regions <b>305</b> and <b>306</b> are disposed so as to surround the photoelectric conversion portion <b>51</b>, and have a higher impurity density than the well portion <b>102</b>. The N-type semiconductor regions <b>305</b> and <b>306</b> function as potential barriers for holes, which are the signal charge. Using such a configuration makes it possible to further reduce color mixture between pixels.

0089In the aforementioned embodiments, the direction in which light enters is not limited. A top-surface incident structure, whereby light enters from the semiconductor substrate surface SBa, can be employed. However, a back-illuminated structure, whereby light enters from the surface opposite to the semiconductor substrate surface SBa, can be employed as well. In a back-illuminated structure, it is necessary to collect the charge in the surface side. As the mobility of holes is lower than that of electrons, it has low diffusion. By applying the present invention to the back-illuminated structure where holes are handled as the signal charge, the lengthwise direction electric field from the deep portion of the substrate toward the surface can be maintained and it is possible to guide the holes to the charge-accumulating region effectively. Therefore, the effect to reduce color mixture between pixels becomes prominent compared with the top-surface incident structure.

0090Next, <figref idref="DRAWINGS">FIG. 12</figref> illustrates an example of an imaging system in which the photoelectric conversion apparatus of the present invention has been applied.

0091As shown in <figref idref="DRAWINGS">FIG. 12</figref>, an imaging system <b>90</b> includes, as its primary components, an optical system, an imaging apparatus <b>86</b>, and a signal processing unit. The optical system includes, as its primary components, a shutter <b>91</b>, a lens <b>92</b>, and an iris <b>93</b>. The imaging apparatus <b>86</b> includes the photoelectric conversion apparatus <b>1</b>. The signal processing unit includes, as its primary components, an imaging signal processing circuit <b>95</b>, an A/D converter <b>96</b>, an image signal processing unit <b>97</b>, a memory unit <b>87</b>, an external I/F unit <b>89</b>, a timing generation unit <b>98</b>, a central control/arithmetic unit <b>99</b>, a recording medium <b>88</b>, and a recording medium control I/F unit <b>94</b>. The signal processing unit does not necessarily need to include the recording medium <b>88</b>.

0092The shutter <b>91</b> is provided in front of the lens <b>92</b> in the optical path, and controls exposures.

0093The lens <b>92</b> refracts incident light, causing an image of a subject to be formed upon an imaging area in the photoelectric conversion apparatus <b>1</b> of the imaging apparatus <b>86</b>.

0094The iris <b>93</b> is provided between the lens <b>92</b> and the photoelectric conversion apparatus <b>1</b> in the optical path, and adjusts the amount of light introduced into the photoelectric conversion apparatus <b>1</b> after passing through the lens <b>92</b>.

0095The photoelectric conversion apparatus <b>1</b> of the imaging apparatus <b>86</b> converts the image of the subject formed upon the imaging area of the photoelectric conversion apparatus <b>1</b> into an image signal. The imaging apparatus <b>86</b> reads out this image signal from the photoelectric conversion apparatus <b>1</b> and outputs the image signal.

0096The imaging signal processing circuit <b>95</b> is connected to the imaging apparatus <b>86</b>, and processes the image signal outputted from the imaging apparatus <b>86</b>.

0097The A/D converter <b>96</b> is connected to the imaging signal processing circuit <b>95</b>, and converts the processed analog image signal outputted from the imaging signal processing circuit <b>95</b> into a digital image signal.

0098The image signal processing unit <b>97</b> is connected to the A/D converter <b>96</b>, and performs various computational processes such as correction on the digital image signal outputted from the A/D converter <b>96</b>, thereby generating image data. This image data is then supplied to the memory unit <b>87</b>, the external I/F unit <b>89</b>, the central control/arithmetic unit <b>99</b>, the recording medium control I/F unit <b>94</b>, and so on.

0099The memory unit <b>87</b> is connected to the image signal processing unit <b>97</b>, and stores the image data outputted from the image signal processing unit <b>97</b>.

0100The external I/F unit <b>89</b> is connected to the image signal processing unit <b>97</b>. This makes it possible to transfer the image data outputted from the image signal processing unit <b>97</b> to an external device (a personal computer or the like) via the external I/F unit <b>89</b>.

0101The timing generation unit <b>98</b> is connected to the imaging apparatus <b>86</b>, the imaging signal processing circuit <b>95</b>, the A/D converter <b>96</b>, and the image signal processing unit <b>97</b>. A timing signal is thus supplied to the imaging apparatus <b>86</b>, the imaging signal processing circuit <b>95</b>, the A/D converter <b>96</b>, and the image signal processing unit <b>97</b>. The imaging apparatus <b>86</b>, the imaging signal processing circuit <b>95</b>, the A/D converter <b>96</b>, and the image signal processing unit <b>97</b> operate in synchronization with the timing signal.

0102The central control/arithmetic unit <b>99</b> is connected to the timing generation unit <b>98</b>, the image signal processing unit <b>97</b>, and the recording medium control I/F unit <b>94</b>, and performs overall control of the timing generation unit <b>98</b>, the image signal processing unit <b>97</b>, and the recording medium control I/F unit <b>94</b>.

0103The recording medium <b>88</b> is connected to the recording medium control I/F unit <b>94</b> in a removable state. As a result, image data outputted from the image signal processing unit <b>97</b> is recorded into the recording medium <b>88</b> via the recording medium control I/F unit <b>94</b>.

0104With the configuration described thus far, if a favorable image signal is obtained by the photoelectric conversion apparatus <b>1</b>, a favorable image (image data) can also be obtained.

0105While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

0106This application claims the benefit of Japanese Patent Application No. 2009-026700, filed Feb. 6, 2009, and No. 2010-011375, filed Jan. 21, 2010, which are hereby incorporated by reference herein in their entirety.