Image pickup apparatus and image pickup system having plural semiconductor regions of a same conductivity type, with one of the semiconductor regions having a higher impurity concentration than and providing a potential to another of the semiconductor regions

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image pickup apparatus and a system utilizing the same, and more particularly to an image pickup apparatus and a system such as a digital camera, a video camera, a copying apparatus, and a facsimile apparatus.

2. Background of the Invention

A solid-state image pickup apparatus formed by a one- or two-dimensional array of photoelectric conversion elements such as photodiodes is widely employed in a digital camera, a video camera, a copying apparatus, a facsimile apparatus and the like. The solid-state image pickup apparatus includes a CCD image pickup device and an amplifying solid-state image pickup apparatus represented by a CMOS sensor which is formed integrally with peripheral circuits by a CMOS process.

Such solid-state image pickup apparatus shows a trend toward a larger number of pixels, with a decrease in the area of a photodiode, as a result of a reduction in the area of a pixel. It is therefore required to handle a signal charge of a smaller amount, and it is therefore required to reduce a dark current constituting a noise component, and to increase an effective area of the photodiode. For such purpose, EP 1017106A1 discloses in FIG. 4 (corresponding to Japanese Patent Application Laid-open No. 2000-232216) a configuration in which floating diffusion regions formed for every pixels are connected by a conductor, and in which the signal reading is executed by an amplification by a common amplifying MOS transistor, thereby reducing a number of transistors per unit pixel and maintaining the area of the photodiode larger.

Also when the solid-state image pickup apparatus becomes larger in the area, it becomes necessary, as disclosed in Japanese Patent Application Laid-open No. 2001-332714 (FIGS. 7 and 10) or Japanese Patent Application Laid-open No. 2001-230400 (FIGS. 1 and 16, corresponding to US 2001-1012133A) to form a well contact in order to obtain a firm substrate potential for the photodiode and the transistor and to suppress a shading phenomenon.

Also a fine structuring of the MOS transistors is essential in the image pickup device or in the peripheral circuits, there is widely employed a transistor having so-called LDD (lightly doped drain) structure.

In the aforementioned image pickup apparatus, in case of forming a well contact between the photodiodes, a element isolation region is formed for a device isolation between the well contact and the photodiode. Then a conductive layer for example of polysilicon is formed thereon, and a side wall may be formed in such conductive layer, in relation to the preparation of a transistor of an LDD structure.

The present invention has found a drawback of an increased dark current of the photodiode, depending on the arrangement of the side wall.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the aforementioned drawback.

The present invention provides an image pickup apparatus including a photoelectric conversion element which has a first semiconductor region of a first conductive type, and a second semiconductor region of a second conductive type constituting a junction with the first semiconductor region, a third semiconductor region of a first conductive type, provided in the first semiconductor region for fixing a potential of the first semiconductor region at a predetermined potential, a element isolation region provided between the third semiconductor region and the second semiconductor region, a conductive layer provided on the element isolation region, and a fourth semiconductor region of the first conductive type provided under the element isolation region:

wherein the conductive layer includes a side wall at a lateral face thereof, and a width c of the element isolation region, a width b of the side wall and a distance a between an end of the element isolation region at the side of the third semiconductor region and an end of the conductive layer at the side of the third semiconductor region satisfy a relation c>a≧b.

The present invention also provides an image pickup apparatus including a photoelectric conversion element which has a first semiconductor region of a first conductive type, and a second semiconductor region of a second conductive type constituting a junction with the first semiconductor region, a third semiconductor region of a first conductive type, provided in the first semiconductor region for fixing a potential of the first semiconductor region at a predetermined potential, a element isolation region provided between the third semiconductor region and the second semiconductor region, a conductive layer provided on the element isolation region, and a fourth semiconductor region of the first conductive type provided under the element isolation region:

wherein the conductive layer includes a side wall at a lateral face thereof, and the side wall is provided on the element isolation region in such a manner that an external end of the side wall does not exceed an end of the element isolation region.

An image pickup system of the present invention utilizes the aforementioned image pickup apparatus of the invention.

Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1</figref> is a cross-sectional view of an embodiment of a photoelectric conversion apparatus and of a first example of a solid-state image pickup apparatus of the present invention;

<figref idrefs="DRAWINGS">FIG. 2</figref> is a cross-sectional view of comparative examples of a photoelectric conversion apparatus and a solid-state image pickup apparatus of the present invention;

<figref idrefs="DRAWINGS">FIG. 3</figref> is a plan view of an embodiment of a solid-state image pickup apparatus of the present invention;

<figref idrefs="DRAWINGS">FIG. 4</figref> is a plan view of a first example of a solid-state image pickup apparatus of the present invention;

<figref idrefs="DRAWINGS">FIG. 5</figref> is an equivalent circuit diagram of a pixel unit surrounded by a broken line in <figref idrefs="DRAWINGS">FIG. 4</figref>;

<figref idrefs="DRAWINGS">FIG. 6</figref> is a plan view of comparative examples of a photoelectric conversion apparatus and a solid-state image pickup apparatus of the present invention;

<figref idrefs="DRAWINGS">FIG. 7</figref> is a configurational view employing, as a solid-state image pickup apparatus of the present invention, a solid-state image pickup apparatus utilizing a photoelectric conversion apparatus of the embodiments or a solid-state image pickup apparatus of Example 1; and

<figref idrefs="DRAWINGS">FIG. 8</figref> is a plan view of a solid-state image pickup apparatus of the present invention.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

<figref idrefs="DRAWINGS">FIG. 1</figref> is a cross-sectional view showing an embodiment of a photoelectric conversion apparatus of the present invention. <figref idrefs="DRAWINGS">FIG. 2</figref> is a cross-sectional view showing a comparative example relating to the present invention.

In <figref idrefs="DRAWINGS">FIG. 1</figref>, there are shown a semiconductor substrate <b>301</b> for example of N type; a P-type well (first semiconductor region of first conductive type) <b>302</b>; and N-type semiconductor regions (second semiconductor regions of second conductive type) <b>101</b><i>a</i>, <b>101</b><i>b </i>capable of accumulating a signal charge and forming junctions with the well <b>302</b> to constitute photodiodes. A well contact <b>110</b> defines a potential of the P-type well <b>302</b> through a P⁺⁺-semiconductor region <b>306</b> (third semiconductor region of a first conductive type). The semiconductor region <b>306</b> has an impurity concentration higher than that of the P-type well. Element isolation regions <b>303</b><i>b</i>, <b>303</b><i>a </i>are formed for example by a LOCOS (local oxidation of silicon) film. Under the element isolation regions <b>303</b><i>b</i>, <b>303</b><i>a</i>, there are respectively provided P⁺-semiconductor regions (fourth semiconductor region of first conductive type) constituting channel stop regions. A conductive layer <b>304</b> provided on the element isolation region <b>303</b><i>b </i>is formed for example with polysilicon. A so-called side wall <b>308</b> for example of a silicon oxide film is formed on a lateral face of the conductive layer. Terms “upper” and “lower” mean, with respect to a principal plane, bearing devices, of the semiconductor substrate, a deeper direction of the substrate as “lower” and an opposite direction as “upper”.

The contact is represented as a well contact, but it becomes a substrate contact in case N-type semiconductor regions <b>101</b><i>a</i>, <b>101</b><i>b </i>are provided directly on the wafer.

Referring to <figref idrefs="DRAWINGS">FIG. 2</figref>, a P-type well <b>1102</b> is provided on an n-type substrate <b>1101</b>, and N-type semiconductor regions <b>1001</b>, <b>1002</b> constituting photodiodes with the well <b>1002</b> are provided therein. Also a semiconductor region (P⁺⁺ region) <b>1003</b> for a well contact of a high concentration is formed so as to be positioned between element isolation regions <b>1103</b> and <b>1104</b>. Under the element isolation regions, there are respectively provided P⁺ type semiconductor regions <b>1105</b>, <b>1106</b> constituting channel stop regions. Also on both sides of a polysilicon wiring <b>1005</b> on the element isolation region <b>1103</b>, side walls <b>1107</b>, <b>1108</b> are provided.

As will be apparent from a comparison of <figref idrefs="DRAWINGS">FIG. 2</figref> showing a comparative example and <figref idrefs="DRAWINGS">FIG. 1</figref> showing an embodiment of the present invention, the semiconductor region <b>1003</b> of the well contact and the channel stop region <b>1105</b> are mutually separated in <figref idrefs="DRAWINGS">FIG. 2</figref>, while, in <figref idrefs="DRAWINGS">FIG. 1</figref>, the semiconductor region <b>306</b> of the well contact is in connection or in contact with the channel stop region <b>307</b><i>b</i>. A term “connection” or “contact” means an absence, between the semiconductor region <b>306</b> and the channel stop region <b>307</b><i>b</i>, of a region of a lower potential, for a charge (electron in this case), than in the peripheral area. Stated differently, it means an absence of a region of a lower concentration of a P-type impurity than in the peripheral area, namely an N-type semiconductor region. In the foregoing there has been explained a relation between a semiconductor region of a well contact and a channel stop region, but such relation is not limited to a well contact and a similar relation applies a region of a same conductive type as in the peripheral well region and having a higher impurity concentration.

On the other hand, in the configuration shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, a P-type well layer is present in a path from the high-concentration P⁺⁺ region <b>1003</b> through the channel stop region <b>1105</b> to the N-type semiconductor region <b>1001</b>. Therefore, as indicated by a potential distribution in a portion X-X′ in <figref idrefs="DRAWINGS">FIG. 2</figref>, electrons constituting the minority carriers are present at a higher concentration in this portion, than in other regions. A part of such electrons may be fetched in the photodiode of a low potential, thereby resulting in an increased dark current.

In the configuration shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, in contrast, a P⁺ region of a high concentration is maintained from the high-concentration P⁺⁺ region <b>306</b> through the channel stop region <b>307</b><i>b </i>to the N-type charge accumulation region <b>101</b><i>b</i>. Therefore, as indicated by a potential distribution in a portion X-X′ in <figref idrefs="DRAWINGS">FIG. 1</figref>, electrons constituting the minority carriers can be maintained at a low concentration, thereby allowing to reduce the dark current.

In order to avoid a potential pocket as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, namely a region of a lower potential for electrons than in the peripheral area, there is preferred a following configuration. As shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, a distance a between an end of the element isolation region <b>303</b><i>b </i>at the side of the P⁺⁺ region <b>306</b> and an end of the conductive layer <b>304</b> at the side of the P⁺⁺ region <b>306</b> is made same as or larger than a width b of the side wall <b>308</b>. This is based on a fact that the potential pocket is generated because, in the processing forming the semiconductor region <b>1003</b> in the well shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, an ion implantation into the P⁺⁺ region has not been executed in the portion of the potential pocket by the presence of the previously formed side wall. Also the distance a is required to be smaller than a device isolating width c, in order to form the conductive layer <b>304</b> thereon. Based on the foregoing, a, b and c are required to meet a relation c&gt;a≧b. Such structure can be also represented as a structure in which the side wall is present on the element isolation region and an external end of the side wall does not exceed an end of the element isolation region.

On the other hand, in the configuration shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, the distance a is smaller than the device isolation width c and is formed on the element isolation region, but is smaller than the width b of the side wall, thereby resulting in a formation or a potential pocket, thus increasing the dark current.

The present embodiment is particularly effective in an image pickup apparatus in which plural pixels are arranged one- or two-dimensionally, because the presence of a well contact commonly used for plural pixels leads to pixels showing an increased dark current and those not showing such increase in periodical manner (every other row in case of the well contact common for two pixels, and in every four rows in case of the well contact common for four pixels), thereby significantly deteriorating the image quality. The aforementioned condition c&gt;a≧b allows to provide an image pickup apparatus of a high S/N ratio.

In <figref idrefs="DRAWINGS">FIG. 1</figref> there has been explained a configuration in which the conductive layer <b>304</b> is provided on the element isolation region <b>303</b><i>b</i>, but the present invention is applicable also to a case where a conductive layer <b>304</b> is provided also on the element isolation region <b>303</b><i>a </i>to realize a configuration satisfying a condition c&gt;a≧b, namely that the side wall is provided on the element isolation region and the external end of the side wall is so provided as not to exceed the end of the element isolation region.

As shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, semiconductor regions <b>101</b><i>a</i>, <b>101</b><i>b </i>constituting pixel photodiodes are arranged two-dimensionally in such a manner that two pixels constitute a group (<b>101</b><i>a </i>and <b>101</b><i>b</i>, <b>101</b><i>a</i>′ and <b>101</b><i>b</i>′ respectively constituting groups), and a well contact is provided for every two pixels (for every group) and between pixels (within the group). In such configuration, in case of a structure as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, amounts of minority carriers Ib flowing from the well contacts into the photodiodes <b>101</b><i>b</i>, <b>101</b><i>b</i>′ of second and fourth rows becomes larger than those of minority carriers Ia flowing from the well contacts into the photodiodes <b>101</b><i>a</i>, <b>101</b><i>a</i>′ of first and third rows. Such difference in the diffusion of the minority carriers leads to a difference in the mounts of the minority carriers Ia and the minority carriers Ib, thereby resulting in an unevenness in the dark current between the odd rows and the even rows. Such difference causes a stripe-shaped noise in every other row, thereby deteriorating the image quality. This phenomenon becomes particularly conspicuous in case of a charge accumulation for plural seconds. The configuration of the present invention allows to prevent formation of a potential pocket, thereby reducing the difference in the dark current.

<figref idrefs="DRAWINGS">FIG. 3</figref> shows a configuration in which two pixels constitute a group, but three or more pixels may form a group. In such case, the well contact may be provided in plural units within a group, according to a number of pixels constituting a group.

The present embodiment of the invention is advantageously applicable to an image pickup apparatus in which signal charges from plural photoelectric conversion elements are amplified and read, through FD regions independently formed for respective photoelectric conversion elements, by a common amplifying MOS transistor.

As an example, let us consider a configuration in which an amplifying MOS transistor is used in common for two pixels and a well contact is not used, as described in EP1017106. In such case, a long time is required for stabilizing the substrate potential in order to increase the drive rate at the readout operation, so that a high-speed readout is difficult to achieve.

Also a well contact, in case formed for each pixel, results in a corresponding decrease of the photodiode area, thereby reducing the effect of using the pixels in common.

It is therefore possible to form a well contact for plural pixels, and to adopt the configuration of the present embodiment in order to solve the drawback of a difference in the dark currents between the pixel rows (rows of photodiodes).

It is also possible, as shown in <figref idrefs="DRAWINGS">FIG. 8</figref>, to form a first group by pixels <b>101</b><i>a</i>, <b>101</b><i>b </i>having a common amplifying MOS transistor, and a second group by pixels <b>101</b><i>a</i>′, <b>101</b><i>b</i>′ having a common amplifying MOS transistor. A well contact is provided between the pixels of the first group and the adjacent pixels of the second group. Thus, it may be provided in a first semiconductor region (well region), between the second semiconductor region in the first group and the second semiconductor region in the second group, adjacent to the second semiconductor region in the first group. Particularly in a configuration in which an amplifying MOS transistor is used in common by plural pixels as shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, it is preferably formed between the pixels <b>101</b><i>b </i>and <b>101</b><i>a</i>′ of the adjacent groups, in consideration of ease of layout. <figref idrefs="DRAWINGS">FIG. 4</figref> shows an example in which the amplifying MOS transistor are used in common for two pixels which form a group, but it is also possible to use the amplifying MOS transistor in common for three or more pixels and to form a group by such three or more pixels. In such case, the well contact may be provided not only between the groups but also within a group.

As explained in the foregoing, the present invention is to reduce or eliminate a difference in the dark currents between adjacent photoelectric conversion elements, and is applicable to an image pickup apparatus having a well contact or a substrate contact between two photoelectric conversion elements, and more specifically to a line sensor in which photoelectric conversion elements are one-dimensionally arranged, or to an area sensor in which photoelectric conversion elements are two-dimensionally arranged.

Examples of the present invention will be explained in the following.

EXAMPLE 1

<figref idrefs="DRAWINGS">FIG. 4</figref> is a plan view of a first example of the present invention. In <figref idrefs="DRAWINGS">FIG. 4</figref>, there are shown a photodiode (semiconductor layer) PD, an active region ACT, a polysilicon layer POL, a contact hole CNT, a first metal layer AL<b>1</b> such as of aluminum, and a through hole TH.

In <figref idrefs="DRAWINGS">FIG. 4</figref>, there are shown N-semiconductor layers <b>101</b><i>a</i>, <b>101</b><i>b</i>, <b>101</b><i>a</i>′ constituting carrier accumulation layers of photodiode for photoelectric conversion; gate electrodes <b>102</b><i>a</i>, <b>102</b><i>b </i>of transfer MOS transistors for reading signal charges from photodiodes (N-semiconductor layers) <b>101</b><i>a</i>, <b>101</b><i>b</i>; drain regions <b>103</b><i>a</i>, <b>103</b><i>b </i>(constituting floating diffusion regions (FD)) of the transfer MOS transistors; a gate electrode <b>104</b> of a reset transistor for resetting the photodiode (N-semiconductor layer) and the FD region, and a gate electrode <b>106</b> of an amplifying MOS transistor constituting a source follower amplifier for converting the read charge into a voltage. The gate electrode of the amplifying MOS transistor and the FD regions <b>103</b><i>a</i>, <b>103</b><i>b </i>are connected by a wiring <b>105</b>. A gate electrode <b>107</b> of a row selecting MOS transistor selectively outputs, to a signal line <b>108</b>, an output of the amplifying MOS transistor constituting a source follower amplifier. A well contact <b>109</b> provided in the pixel region is fixed at a constant potential, for example a ground potential, through a power supply wiring <b>110</b> (connected to a fixed voltage source (including a case of grounding)). In <figref idrefs="DRAWINGS">FIG. 4</figref>, an area surrounded by a chain line indicates a pixel unit constituted of two photodiodes, two transfer MOS transistors, two FD regions, an amplifying MOS transistor, a reset MOS transistor and a selecting MOS transistor. The two photodiodes constitute a group, and m groups are formed in case the photodiodes are provided in a number 2 m (m being a natural number equal to or larger than 1) in the row direction. In case a group is formed by four photodiodes, there are formed m/2 groups in case the photodiodes are provided in a number 2 m (m being a natural number equal to or larger than 2) in the row direction. A pixel unit is constituted by providing a transfer MOS transistor for each photodiode, and providing a reset MOS transistor and a selecting MOS transistor for each group of the photodiodes. One pixel unit is provided with plural photodiodes and includes plural pixels.

<figref idrefs="DRAWINGS">FIG. 5</figref> is an equivalent circuit diagram of the pixel unit surrounded by a broken line in <figref idrefs="DRAWINGS">FIG. 4</figref>. In <figref idrefs="DRAWINGS">FIG. 5</figref>, <b>101</b><i>a </i>and <b>101</b><i>b </i>do not indicate the semiconductor regions but photodiodes themselves, and <b>102</b><i>a</i>, <b>102</b><i>b</i>, <b>104</b>, <b>106</b> and <b>107</b> do not indicate the gate electrodes but respectively indicate a transfer MOS transistor, a reset MOS transistor, an amplifying MOS transistor and a selecting MOS transistor themselves. Photodiodes <b>101</b><i>a</i>, <b>101</b><i>b </i>are connected to an FD region <b>103</b>, respectively through transfer MOS transistors <b>102</b><i>a</i>, <b>102</b><i>b</i>. A backgate potential of all the transistors and anode electrodes of the photodiodes are fixed to a constant potential, such as a ground potential, through the well contact <b>109</b>. Also a drain of the reset transistor <b>104</b> and a drain of the source follower amplifier are fixed to the power supply voltage through a via hole.

<figref idrefs="DRAWINGS">FIG. 1</figref> corresponds to a cross section at A-A′ in <figref idrefs="DRAWINGS">FIG. 4</figref>. Portions similar to those in the cross-sectional configuration of the first embodiment will be omitted from the following explanation. In <figref idrefs="DRAWINGS">FIG. 1</figref>, the conductive layer is constituted of a gate electrode of the transfer transistor <b>102</b><i>b</i>, but it may also be constituted of a gate electrode <b>107</b> of the selecting MOS transistor, a gate electrode <b>104</b> of the resetting MOS transistor or a gate electrode of the amplifying MOS transistor.

A side wall <b>308</b> is formed before an ion implantation for forming a high-concentration diffusion area (N⁺⁺ or P⁺⁺ region) constituting the source-drain of the MOS transistor. A well contact <b>108</b> fixed the potential of the P-type well <b>302</b> through a P⁺⁺ diffusion region <b>306</b>.

As already explained in the embodiments, and as indicated by a potential distribution in a portion X-X′ in <figref idrefs="DRAWINGS">FIG. 2</figref>, electrons constituting the minority carriers are present at a higher concentration than in other regions. A part of such electrons may be fetched in the photodiode of a low potential, thereby resulting in an increased dark current.

In contrast in the present example, as shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, the semiconductor region <b>306</b> of the well contact and the channel stop region <b>307</b><i>b </i>are connected, and a P⁺ region of a high concentration is formed from the high-concentration P⁺⁺ region <b>306</b> through the channel stop region <b>307</b><i>b </i>to the N-type charge accumulation region <b>101</b><i>b</i>. Therefore, the electrons constituting the minority carriers are maintained at a low concentration, thereby allowing to reduce the dark current.

In order to avoid a potential pocket as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, a distance a between an end of the element isolation region <b>303</b><i>b </i>at the side of the P⁺⁺ region <b>306</b> and an end of the polysilicon conductive layer <b>304</b> at the side of the P⁺⁺ region <b>306</b> is made same as or larger than a width b of the side wall <b>308</b>. Also the distance a is made smaller than a device isolating width c. Such structure can be also a structure in which the side wall is present on the element isolation region and an external end of the side wall does not exceed an end of the element isolation region.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a plan view of a solid-state image pickup apparatus, corresponding to the Comparative Example shown in <figref idrefs="DRAWINGS">FIG. 2</figref>. <figref idrefs="DRAWINGS">FIG. 2</figref> corresponds to a cross section along a line A-A′ in <figref idrefs="DRAWINGS">FIG. 6</figref>. Referring to <figref idrefs="DRAWINGS">FIG. 6</figref>, a well contact region <b>1003</b> is provided between two photodiodes <b>1001</b> and <b>1002</b>. Also a polysilicon wiring <b>1004</b> is provided between the photodiodes <b>1001</b> and <b>1003</b>.

A cross-sectional configuration is same as that shown in <figref idrefs="DRAWINGS">FIG. 2</figref>.

Also, wide wall layers <b>1107</b>, <b>1108</b> are formed on both sides of the polysilicon wiring <b>1004</b>. Such side wall layers are formed in a bi-product manner at the formation of MOS transistors in the image pickup apparatus.

A pixel in the present example includes a photodiode, a transfer MOS transistor, an amplifying MOS transistor, a reset MOS transistor, and a selecting MOS transistor, and the amplifying MOS transistor is used in common for plural photodiodes and plural transfer MOS transistors. In the present invention, each transistor is not limited to a MOS transistor, and there can also be employed VMIS (threshold voltage modulation image sensor), BCAST (buried charge accumulator and sensing transistor array) or LBCAST (lateral buried charge accumulator and sensing transistor array). In particular, BCAST or LBCAST can be realized without a substantial change, by replacing a JFET transistor with an amplifying MOS transistor. Also a sensor of a type, in which a signal charge accumulated in a photoelectric conversion portion is guided to a control electrode of a transistor provided in the pixel and an amplified signal is outputted from a main electrode, may be employed in the pixel of the present embodiment. There can also be utilized an SIT image sensor utilizing an SIT as the amplifying transistor (A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics”, IEEE trans., Vol. ED-33, pp. 735-742, June 1986), BASIS utilizing a bipolar transistor (N. Tanaka et al., “A 310K pixel bipolar imager (BASIS)”, IEEE Trans. Electron Devices, vol. 35, pp. 646-652, May 1990), or AMI utilizing JFET with depleted control electrode (Nakamura et al., “Amplified solid-state image element AMI (Amplified MOS Intelligent Imager)”, Bulletin of Television Society, 41, 11, pp. 1075-1082, November 1987). Also the arrangement of the photoelectric conversion elements may assume a honeycomb structure.

The present example shows a configuration in which the amplifying MOS transistor is used in common for plural photodiodes, and the selecting MOS transistor and the reset MOS transistor are also used in common for plural pixels. However the present invention is likewise applicable to a case where each pixel is provided with an amplifying MOS transistor, a selecting MOS transistor and a reset MOS transistor. Also the present invention is applicable, if necessary, to a configuration which is not provided with a selecting MOS transistor and in which a pixel is selected by controlling a potential of an FD region for example by a reset transistor. The wiring layer may be utilized in a gate electrode <b>102</b><i>a </i>of a transfer MOS transistor <b>102</b><i>b</i>, a gate electrode <b>107</b> of a selecting MOS transistor, a gate electrode <b>104</b> of a reset MOS transistor or a gate electrode <b>106</b> of an amplifying MOS transistor.

EXAMPLE 2

<figref idrefs="DRAWINGS">FIG. 7</figref> shows a configuration of a solid-state image pickup system of the present invention, employing a solid-state image pickup apparatus of the present invention. The image pickup system is constituted of a barrier <b>2001</b> serving for lens protection and as a main switch; a lens <b>2002</b> for focusing an optical image of an object on a solid-state image pickup device <b>2004</b>; a diaphragm <b>2003</b> for varying a light amount passing through the lens <b>2002</b>; a solid-state image pickup device <b>2004</b>.for fetching the object, focused by the lens <b>2002</b>, as an image signal (corresponding to an image pickup apparatus explained in the foregoing embodiments); an image pickup signal processing circuit <b>2005</b> for executing various corrections and a clamping on the image signal outputted from the solid-state image pickup device <b>2004</b>; an A/D converter <b>2006</b> for executing an analog/digital conversion on the image signal outputted from the solid-state image pickup device <b>2004</b>; a signal processing unit <b>2007</b> for executing various corrections and a data compression on the image data outputted from the A/D converter <b>2006</b>; and a timing generator <b>2008</b> for outputting various timing signals to the solid-state image pickup device <b>2005</b>, the image pickup signal processing circuit <b>2005</b>, the A/D converter <b>2006</b> and the signal processing unit <b>2007</b>. The circuits <b>2005</b>-<b>2008</b> may be formed on the same chip of the solid-state image pickup device <b>2004</b>. The solid-state image pickup system further includes a whole-control/arithmetic operation unit <b>2009</b> for executing various calculations and controlling the entire still video camera; a memory unit <b>2010</b> for temporarily storing image data; a recording medium control interface <b>2011</b> for executing a recording or a readout into or from the recording medium; a detachable recording medium <b>2012</b> such as a semiconductor memory for data recording or readout; and an external interface (I/F) <b>2013</b> for communication with an external computer or the like.

In the following there will be explained operations of the system shown in <figref idrefs="DRAWINGS">FIG. 7</figref>. When the barrier <b>2001</b> is opened, a main power supply is turned on, then a power supply for the control system is turned on and a power supply for the image pickup circuits such as the A/D converter <b>2006</b> is turned on. Then, in order to control an exposure amount, the whole-control/arithmetic operation unit <b>2009</b> fully opens the diaphragm <b>2003</b>, and a signal outputted from the solid-state image pickup device <b>2004</b> is passed through the image pickup signal processing circuit <b>2005</b> and outputted to the A/D converter <b>2006</b>. The A/D converter <b>2006</b> executes an A/D conversion on the signal for supply to the signal processing unit <b>2007</b>. Based on such data, the signal processing unit <b>2007</b> calculates an exposure amount by the whole-control/arithmetic operation unit <b>2009</b>.

A luminance is judged from the result of such light metering, and the whole-control/arithmetic operation unit <b>2009</b> controls the diaphragm based on such result. Then, based on the signal outputted from the solid-state image pickup device <b>2004</b>, the whole-control/arithmetic operation unit <b>2009</b> extracts a high-frequency component and calculates a distance to the object. Thereafter it drives the lens <b>2002</b> and judges whether it is in an in-focus state, and, if not in focus, it again drives the lens <b>2002</b> and executes a distance calculation.

Then a main exposure is initiated after an in-focus state is confirmed. When the exposure is completed, an image signal outputted from the solid-state image pickup device <b>2004</b> is subjected to a correction in the image pickup signal processing circuit <b>2005</b>, then to an A/D conversion by the A/D converter <b>2006</b>, then passed by the signal processing unit <b>2007</b> and accumulated by the whole-control/arithmetic operation unit <b>2009</b> in the memory unit <b>2010</b>. Then the data accumulated in the memory unit <b>2010</b> are passed, under the control of the whole-control/arithmetic operation unit <b>2009</b>, by the recording medium control I/F <b>2011</b> and recorded in the detachable memory medium <b>2012</b> such as a semiconductor memory. The data may also be supplied through the external I/F <b>1013</b> directly to a computer or the like for image processing.

The present invention is applicable to a solid-state image pickup apparatus, and a solid-state image pickup system utilizing the same, such as a digital camera, a video camera, a copying apparatus or a facsimile apparatus.

This application claims priority from Japanese Patent Application No. 2004-254360 filed Sep. 1, 2004, which is hereby incorporated by reference herein.