Solid-state image sensing device and camera system using the same

Solid-state imaging device and camera system using the solid-state imaging device

This application is a divisional application of the application date of June 27, 2003, the application number is 031484755.1, the title of the invention is the solid-state imaging device and the camera system using the solid-state imaging device.

FIELD OF THE INVENTION The present invention relates to a solid-state imaging device and a camera system using the solid-state imaging device.

Background technique

In recent years, the demand for solid-state imaging devices as imaging devices for image input centered on digital still cameras and video camera encoders has rapidly increased.

CCD (Charge Coupled Device) and MOS solid-state imaging devices are being used as these solid-state imaging devices. Compared with the latter, the former has high sensitivity and low noise, so it is becoming popular as a high-quality imaging device. However, the opposite is that it has high power consumption and high driving voltage, and because it does not use a general semiconductor manufacturing process, it is costly. , It is difficult to integrate the weaknesses of peripheral circuits such as drive circuits.

Due to the above reasons, an enlarged MOS type solid-state imaging device has also been developed so far. The amplifier type solid-state imaging device is a device that introduces the signal charge stored in the photodiode to the control electrode of the amplifying transistor provided in the pixel, amplifies and outputs an output corresponding to the amount of signal charge from the main electrode of the amplifying transistor. In particular, as an amplifier-type solid-state imaging device, efforts are being invested in the development of MOS sensors that use MOS transistors as amplifier transistors.

We anticipate that MOS-type solid-state imaging devices that can overcome the above-mentioned weaknesses of CCDs will be suitable for applications in portable devices that are expected to expand in the future.

Fig. 13 is a circuit diagram showing a typical example of a pixel of a CMOS sensor as a solid-state imaging device.

In FIG. 13, 30 is a unit pixel, 1 is a photodiode for storing signal charges generated by incident light, 6 is an amplifying MOS transistor that outputs an amplified output signal corresponding to the amount of signal charge, and 3 is a photodiode that receives signal charges. The floating diffusion (hereinafter referred to as FD) region connected to the gate of the amplifying MOS transistor 6, 2 is a transfer MOS transistor used to transfer the signal charge stored in the photodiode 1 to the FD region 3, and 4 is used to make the FD Area 3 resets the reset MOS transistor, 5 is a select MOS transistor for selecting output pixels, 9a is a control line for applying a pulse to the gate of the transfer MOS transistor 2 to control the charge transfer operation, and 9b is A control line for applying a pulse to the gate of the reset MOS transistor 4 to control the reset operation, 9c is a control line for applying a pulse to the gate of the selection MOS transistor 5 to control the selection operation, 10a is a power supply wiring that is connected to the drain of the amplifying MOS transistor 6 and the drain of the reset MOS transistor 4 and supplies a power supply potential to them. 10b is the output line for outputting the amplified signal of the selected pixel, 8 is used as a current source, amplifying the MOS transistor 6 and the constant current MOS transistor forming the source follower, and 10c is the constant current operation of the MOS transistor 8 The potential of is supplied to the wiring of the gate of the MOS transistor 8. The above-mentioned pixels 30 are arranged in a two-dimensional matrix to form a pixel region of a two-dimensional solid-state imaging device. However, in this matrix configuration, the output line 10b becomes a common line for the pixels of each column, and the control lines 9a, 9b, and 9c are respectively As a common line for the pixels of each row, only the pixels of the row selected by the control line 9c output signals to the output line 10b.

14 is a diagram showing another pixel circuit of the conventional solid-state imaging device. In FIG. 14, 1 is a photodiode, 2 is a transfer MOS transistor for transferring charge of the photodiode, 3 is a floating diffusion region for temporarily storing transfer charges, and 4 is a reset MOS transistor for resetting the floating diffusion region and the photodiode , 5 is a selection MOS transistor used to select any row in the array, 6 is a source follower MOS transistor that converts the charge in the floating diffusion region into a voltage amplified by a source follower amplifier, 7 is in one column The readout line 8 for common readout of pixel voltage signals is a constant current source for passing a constant current through the readout line 7.

Now we briefly explain the work situation. The photodiode 1 converts incident light into electric charges, and the transfer MOS transistor 2 stores the electric charges in the floating diffusion region 3. Since the reset MOS transistor 4 and the transfer MOS transistor 2 are turned on in advance to reset the floating diffusion region 3 and the photodiode 1 to a certain potential, the potential of the floating diffusion region 3 changes in accordance with the charge generated by incident light. The potential of the floating diffusion region 3 is amplified by the source follower MOS transistor 6 and output to the read line 7. The pixel is selected by turning on the selection MOS transistor 5. In the output circuit not shown in the figure, the optical signal is detected by calculating the difference between the reset potential of the floating diffusion region 3 and the potential after the optical signal is stored.

Fig. 15 is a schematic cross-sectional view of the solid-state imaging device of Fig. 13. In addition, FIG. 15 is a schematic cross-sectional view of a cross section including a photodiode, a transfer MOS transistor, and an FD region. In FIG. 15, 11 is an N-type semiconductor substrate, 12 is a P-type well, 15 is an N-type semiconductor region formed in the P-type well 12, and the P-type well 12 and the N-type semiconductor region 15 form a photodiode. The N-type semiconductor region 15 stores signal charges generated by incident light. 18 is an FD region composed of an N-type semiconductor region formed in the P-type well 12, 14 is the gate of the transfer MOS transistor 2 shown in FIG. 13, and the FD region 18 is also the drain region of the transfer MOS transistor. In addition, the source region of the transfer MOS transistor is the N-type semiconductor region 15. 20 is a wiring connected to the FD region 18, and is connected to the gate of the amplifying MOS transistor not shown in the figure. 17 is an insulating film for element isolation called a LOCOS oxide film, and 29 is a P+ type channel barrier layer having a higher impurity concentration than the P-type well 12 formed under the insulating film 17 for element isolation.

Fig. 16 is a schematic cross-sectional view of the solid-state imaging device shown in Fig. 14. This cross-sectional view 16 is a diagram showing parts of the photodiode 1 and the transfer MOS transistor 2 of FIG. 14. 11 is the n-type silicon substrate, 12 is the P-type well, 13a is the gate oxide film of the MOS transistor, 13b is the thin oxide film on the light receiving part, 14 is the gate of the transmission MOS transistor, 15 is the N of the photodiode 1 Type cathode, 16 is to have a surface P-type region with a structure embedded in the photodiode, 17 is a LOCOS oxide film for element separation, and 18 is an N-type high-type region that forms a floating diffusion region and also becomes the drain region of the transfer MOS transistor 2. Concentration area, 19 is a silicon oxide film that insulates the gate and the first metal layer, 20 is a contact plug, 21 is the first metal layer, 22 is an interlayer insulating film that insulates the first metal layer and the second metal layer, 23 is a second metal layer, 24 is an interlayer insulating film that insulates the second metal layer from the third metal layer, 25 is a third metal layer, and 26 is a passivation film. In the color photoelectric conversion device, a color filter layer not shown in the figure and a microlens for further improving the sensitivity are further formed on the upper layer of the passivation film 26. The light incident from the surface enters the photodiode through the opening of the third layer without metal. Light is absorbed in the N-type cathode 15 or P-type well 12 of the photodiode, and electron/hole pairs are generated. The electrons are stored in the N-type cathode area.

In addition, U.S. Patent No. 6,403,998 discloses a solid-state imaging device in which a p-type buried layer of a predetermined depth is formed from an n-type substrate, and a photoelectric conversion portion is formed on the n-type substrate on the upper side.

Moreover, in US Patent 6,504,193, it is disclosed that one end of the photodiode is formed extending up to the lower part of the readout gate, and a solid body penetrating the barrier layer region is formed in a self-matching manner to the gate at the lower part of the signal detection portion corresponding to the drain region. Camera device.

However, in the case of the existing structures of FIGS. 15 and 16, a part of the signal charge generated under the photodiode is not absorbed by the photodiode, but is absorbed by the FD region 18 and the source and drain regions of the transistor in the pixel. absorb. As a result, the sensitivity is reduced.

In addition, although various improvements have been made to the CMOS-type solid-state imaging device, there is still a problem of low sensitivity in a device with a particularly small pixel size. The present invention provides a CMOS solid-state imaging device capable of obtaining high sensitivity even with fine pixels based on a new structure.

Next, we explain the reason for the low sensitivity in the conventional structure of FIG. 16. Figure 16 shows that electrons generated by light 27 incident on the opening are smoothly stored in the N-type cathode area and work as effective signal charges. However, for example, electrons generated at positions slightly separated from the photodiode such as light 28 are not in the N-type cathode. The cathode region is captured by the N+ type floating diffusion region 18 with a lower potential. In addition, even directly under the photodiode, due to repeated diffusion and trapping of electrons, with a certain probability, the electrons are absorbed by the low-potential region other than the photodiode and do not contribute to the photoelectric conversion signal. If the N-type cathode 15 is formed deeper than the silicon surface, it is easy to collect electrons generated by the photodiode. However, because the N-type cathode region is formed by implanting ions into the P-type well region 12, the impurity concentration cannot be too high. low. The N-type cathode 15 is restricted by the depletion operation, and cannot be formed at a relatively deep position to form a high-concentration structure, which is a problem of the existing structure.

In this way, since there is a limit to the volume of the N-type cathode that becomes the photodiode, the ability to collect electrons generated by incident light is insufficient, and the sensitivity is low.

In addition, even in the existing structure disclosed in U.S. Patent No. 6,403,998, because a potential barrier is provided below the signal readout gate, it is still impossible to prevent electrons generated by incident light at deep positions from floating and spreading. Area 18 absorbs and reduces sensitivity.

In addition, even in the existing structure disclosed in U.S. Patent No. 6,504,193, because the penetrating barrier layer region is only formed at the lower part of the signal detection part, it is impossible to prevent a part of the electrons generated by incident light from being transferred to other parts of the pixel. The source and drain absorption of the transistor and the absorption to adjacent pixels are also the subject of reducing sensitivity.

Summary of the invention

The object of the present invention is to provide a solid-state imaging device with high sensitivity even with tiny pixels. Another object of the present invention is to provide a camera system with low power consumption and low driving voltage and low cost.

In order to solve the above-mentioned problems, the first solid-state imaging device of the present invention is provided with a plurality of arrays consisting of a first conductivity type semiconductor region and a second conductivity type semiconductor region that is opposite to the conductivity type of the first conductivity type semiconductor region. A photodiode, a first transistor having a first conductivity type drain region formed in the second conductivity type semiconductor region, and transmitting signal charges generated in the photodiode to the drain region, and a first transistor having a first conductivity type drain region formed in the second conductivity type semiconductor region. In a solid-state imaging device in which pixels of a second transistor of a first conductivity type source/drain region are formed in a conductivity type semiconductor region, the lower part of the drain region of the first transistor and the second transistor of the second transistor A barrier of the second conductivity type is provided below the source region and/or the drain region.

In addition, the second solid-state imaging device of the present invention is provided with a photodiode composed of a first conductivity type semiconductor region and a second conductivity type semiconductor region of a conductivity type opposite to the above-mentioned first conductivity type, and a photodiode having the above-mentioned In a solid-state imaging device composed of pixels of transistors of the first conductivity type source and drain regions formed in the first conductivity type semiconductor region, a barrier of the second conductivity type is provided below the gate of the transistor.

In addition, the third solid-state imaging device of the present invention has a first conductivity type substrate, a second conductivity type layer, and a first conductivity type layer, and a photodiode is formed by the second conductivity type layer and the first conductivity type layer. In the solid-state imaging device of, a potential barrier composed of a second conductivity type region is formed around the region where the photodiode is formed.

In addition, the fourth solid-state imaging device of the present invention is characterized in that the second conductivity type region forming the barrier is arranged in multiple layers in the depth direction of the first conductivity type layer forming the photodiode.

In addition, the fifth solid-state imaging device of the present invention is characterized in that the uppermost layer of the multilayers forming the barrier controls the charge transfer path from the photodiode to the transfer transistor.

In addition, the sixth solid-state imaging device of the present invention is characterized in that in the first conductive layer at least in the depth near the opposite conductivity type buried layer, the impurity concentration is reduced due to the surrounding opposite conductivity layer.

In addition, the seventh solid-state imaging device of the present invention is characterized in that the first conductive layer has a region in the vicinity of the semiconductor surface with a higher impurity concentration than other portions.

In addition, the eighth solid-state imaging device of the present invention is characterized in that the first conductive layer is completely depleted when charges are transferred.

In addition, the manufacturing method of the first solid-state imaging device of the present invention is characterized in that after the first conductivity type layer is formed by epitaxial growth on the opposite conductivity type buried layer, the opposite conductivity type layer is formed by ion implantation.

In addition, the second method of manufacturing a solid-state imaging device of the present invention is characterized in that the opposite conductivity type buried layer is ion implanted in the first conductivity type semiconductor substrate, and then the opposite conductivity type layer is formed by ion implantation.

Furthermore, the ninth solid-state imaging device of the present invention is characterized in that the separation area between adjacent pixels is formed by STI (Shallow Trench Isolation).

Furthermore, the tenth solid-state imaging device of the present invention is characterized in that the contact surface between the oxide film formed by STI separating the pixels and the silicon is completely covered by the semiconductor layer of the first conductivity type.

Furthermore, the eleventh solid-state imaging device of the present invention is characterized in that the separation area between adjacent pixels is formed by deep trench isolation.

Furthermore, the twelfth solid-state imaging device of the present invention is characterized in that the contact surface between the oxide film and silicon formed by the deep trench separation between adjacent pixels is completely covered by the first conductivity type semiconductor layer.

The function of the first solid-state imaging device of the present invention is that by arranging the potential barrier under the FD region and the source and drain of each transistor, the signal charge generated under the barrier is not affected by the FD region and the barrier provided The source and drain regions of each transistor absorb, so the sensitivity is improved.

The function of the second solid-state imaging device of the present invention is that the barrier provided under the gate of the N-type transistor forming the pixel also serves to prevent short-circuit between the source and drain, and even in the N-type semiconductor region. N-type transistors can also work.

The function of the third solid-state imaging device of the present invention is to generate a barrier to electrons by surrounding the N-type layer of the photodiode with a buried layer of opposite conductivity type and a layer of the same conductivity type as the buried layer to generate a barrier to electrons and form impurities at the same time A photodiode with a low concentration and a large volume can increase the collecting power of collecting light signal electrons.

The function of the fourth solid-state imaging device of the present invention is that the N-type layer of the photodiode is deep, that is, in a structure with sensitivity on the longer wavelength side, an effective barrier can be formed by stacking a plurality of P-type layers. .

The function of the fifth solid-state imaging device of the present invention is to realize a structure capable of reliably transmitting a signal from a photodiode through a transmission transistor.

The function of the sixth solid-state imaging device of the present invention is that when a reverse bias voltage is applied to the photodiode when storing charges, the depletion layer effectively extends to the side of the N-type layer, and it is easy to achieve complete depletion. Since the well layer and the buried layer are at substantially the same position in the plane direction, a high separation effect can be obtained with fewer photomasking steps.

The function of the seventh solid-state imaging device of the present invention is to make the electron potential on the surface of the semiconductor lower than that of other parts, so that the electrons are concentrated near the surface when the charges are stored, and transfer residues are unlikely to occur when the charges are transferred.

The function of the eighth solid-state imaging device of the present invention is to determine the concentration depth for depletion based on the reverse bias voltage applied to the photodiode surrounded by the opposite conductivity type layer, and to form a complete transmission type photodiode without reset noise .

The function of the first method of manufacturing a solid-state imaging device of the present invention is to be able to manufacture a solid-state imaging device corresponding to various spectral characteristics by changing the thickness of the epitaxial growth layer.

The effect of the second method of manufacturing a solid-state imaging device of the present invention is that when a significantly high spectral sensitivity is not required on the long-wavelength side, ion implantation can be used to form uniform embedding in the depth direction with good reproducibility. Floor.

The function of the ninth solid-state imaging device of the present invention is to provide an imaging element with STI capable of suppressing charge leakage between adjacent screens even in fine pixels, low crosstalk, and high sensitivity.

The function of the tenth solid-state imaging device of the present invention is that in STI, a depletion layer is not formed at the interface of silicon oxide film, and an imaging element with less noise in the dark can be formed.

The effect of the eleventh solid-state imaging device of the present invention is to provide an imaging element that further improves the separation between pixels in fine pixels, has low crosstalk, and has high sensitivity.

The function of the twelfth solid-state imaging device of the present invention is to form an imaging element with little noise in the dark by not forming a depletion layer at the interface of silicon oxide film during deep trench separation.

Description of the drawings

Fig. 1 is a schematic cross-sectional view of a solid-state imaging device according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a solid-state imaging device according to a second embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a solid-state imaging device according to a third embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a solid-state imaging device according to a fourth embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a solid-state imaging device according to a fifth embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view of a solid-state imaging device according to a sixth embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 8 is a plan view of a pixel of a solid-state imaging device according to the present invention.

Fig. 9 is a schematic cross-sectional view of a solid-state imaging device according to an eighth embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view of a solid-state imaging device according to a ninth embodiment of the present invention.

Fig. 11 is a part of a circuit diagram of a solid-state imaging device according to the present invention.

Fig. 12 is a block diagram of a camera system using the solid-state imaging device according to the present invention.

Fig. 13 is a circuit diagram showing a typical example of a pixel of a CMOS sensor as a solid-state imaging device.

Fig. 14 is a diagram showing a pixel circuit of a conventional solid-state imaging device.

Fig. 15 is a schematic cross-sectional view of the solid-state imaging device shown in Fig. 13.

Fig. 16 is a schematic cross-sectional view of the solid-state imaging device shown in Fig. 14.

detailed description

(First Embodiment) Fig. 1 is a schematic cross-sectional view of a solid-state imaging device according to a first embodiment of the present invention.

In FIG. 1, 101 is a semiconductor substrate of the first conductivity type (here, exemplified as N-type), 102 is a P-type well that is a second conductivity type semiconductor region, and 103 is a P-type well formed in the P-type well 102. In the N-type semiconductor region of the 1-conductivity semiconductor region, the P-type well 102 and the N-type semiconductor region 103 form a photodiode, and the N-type semiconductor region 103 stores signal charges generated by incident light. 111 is the first conductivity type drain region of the transfer transistor that transfers the signal charge generated in the photodiode as the first transistor, and is the FD region of the N-type semiconductor region formed in the P-type well 102. 109 is the gate of the transfer transistor, and the N-type semiconductor regions 103 and 111 are also the source and drain regions of the transfer transistor, respectively. 113 is a wiring connected to the N-type semiconductor region 111 and connected to the gate 130 of the amplifying transistor as the second transistor. In addition, the amplifying transistor has a configuration in which a gate 130 is formed between the source region 131 and the drain region 132. 133 is a vertical signal line connected to the source electrode 131. In addition, 132 is also the drain of the amplifying transistor and also the source region of the selection transistor of another second transistor. 134 is the drain of the selection transistor, and a gate 135 is formed between the source and the drain. 136 is a drain line connected to the drain 134 of the selection transistor. 107 is an insulating film formed of a thick oxide film for separating elements, 106 is a P+ type channel barrier layer with a higher impurity concentration than the P-type well 102 formed under the insulating film 107 for separating elements, 105 is A potential barrier formed in a P-type semiconductor region of the same conductivity type as the P-type well 102.

In this specification, the transfer transistor is referred to as the first transistor, and transistors other than the transfer transistor formed in the pixel are referred to as the second transistor.

In addition, in order to transfer the signal charge stored in the N-type semiconductor region 103 to the FD region 111 during the transfer operation, the N-type semiconductor region 103 is set to be depleted immediately after the transfer. N-type impurity concentration.

In addition, in the solid-state imaging device of this embodiment, one pixel is composed of a photodiode, a transfer transistor, an amplifying transistor, and a selection transistor, but the configuration of one pixel is not limited to this embodiment. For example, one pixel may be composed of a photodiode, a transfer transistor, and an amplifier transistor. Alternatively, one pixel may be composed of a photodiode, a transfer transistor, an amplifying transistor, a selection transistor, and a reset transistor.

The barrier 105 of the present invention is characterized by being provided under the drain region of the first transistor and under the source and/or drain region of the second transistor. When forming a plurality of second transistors, at least one source and/or drain region is provided.

In addition, the impurity concentration of the barrier 105 is P+ type which is higher than the impurity concentration of the P-type well 102. In addition, the channel barrier layer 106 and the barrier 105 are both the same P+ type semiconductor region, but of course their impurity concentrations can also be different. The barrier 105 is set by ion implantation, for example, by implanting boron and gallium into the P-type well 102. of.

As shown in FIG. 1, the barrier 105 of the present invention is formed under the FD region 111, the source/drain regions 131, 132, and 134 of the amplifying transistor and the selection transistor.

As in the present invention, because the potential barrier 105 is provided under the FD region and the source and drain of each transistor, the signal charge generated under the barrier 105 is not absorbed into the FD region 111 and each of the barriers. The source and drain regions of the transistor improve the sensitivity.

Therefore, it is more suitable because the barrier 105 is provided directly under the source and drain regions of more transistors, so that the signal charge is more difficult to be absorbed by regions other than the photodiode.

In addition, the barrier 105 may be provided under the element isolation region 107. By disposing the potential barrier 105 under the element isolation region 107, a structure in which the signal charge is more difficult to be absorbed by the photodiode or transistor in the adjacent pixel is formed, and it is possible to prevent the signal charge from being mixed between the adjacent pixels.

(Second Embodiment) Fig. 2 is a schematic cross-sectional view of a solid-state imaging device according to a second embodiment of the present invention.

2 is a schematic cross-sectional view of a solid-state imaging device having a photodiode, a transfer transistor, and a reset transistor for resetting the FD electrode 211, and a reset transistor for resetting the FD electrode is provided as a second transistor.

In FIG. 2, 223 is the gate of the reset transistor that resets the FD electrode 211, and 224 is the drain region of the reset transistor that resets the FD electrode 211 connected to the power supply line 226.

The difference between this embodiment and the first embodiment is that the barrier 205 is also provided under the gate of the second transistor in this embodiment. Therefore, since the potential barrier 205 reduces the signal charge absorbed by the N-type semiconductor region other than the photodiode, the sensitivity is improved.

In addition, in this embodiment, the reset transistor is given as an example of the second transistor. However, the second transistor may be the same as the first embodiment. The second transistor may also be an amplification or selection and reset transistor. Alternatively, a plurality of second transistors may be formed.

For example, the barrier 205 of the present invention may be provided in a solid-state imaging device in which one pixel is composed of a photodiode, a transfer transistor, a reset transistor, an amplifying transistor, and a selection transistor.

In addition, when the potential barrier 205 is provided under the gate, source, and drain regions of all transistors formed in the pixel, it is more difficult for signal charges to be absorbed by regions other than the photodiode, so sensitivity is improved.

In addition, a solid-state imaging device is formed in which the barrier 205 is provided under the element isolation region 207, and the barrier 205 of a region deeper than the source and drain regions of the transistor is provided around the photodiode.

Since the barrier 205 is provided around the photodiode as described above, it is more difficult for the signal charge formed on the photodiode to be absorbed by the source or drain region of the adjacent transistor, thereby improving the sensitivity.

In addition, one or more opening portions may be provided in the barrier 205 provided to surround the periphery of the photodiode.

When a barrier 205 is provided around the photodiode without an opening and the signal charge overflows from the photodiode, the signal charge overflowing from the barrier 205 is difficult to be absorbed by the surrounding N-shaped semiconductor region, which easily causes blurring. Therefore, it is better to provide an opening portion where the barrier 205 is not provided on at least a part of the periphery of the photodiode to absorb the signal charge overflowing from the photodiode, thereby suppressing the blur phenomenon.

(Third Embodiment) Fig. 3 is a schematic cross-sectional view of a solid-state imaging device according to a third embodiment of the present invention.

3 is a schematic cross-sectional view of a solid-state imaging device having a photodiode, a transfer transistor, and a reset transistor that resets the FD electrode 311.

In FIG. 3, 303 is the first conductivity type semiconductor region in the N-type well or the N-type semiconductor region on the upper portion of the N-type semiconductor substrate 301, and 302 is the second conductivity region constituting the N-type semiconductor region 303 and the photodiode. The P-type semiconductor region, 312 of the type semiconductor region is a first conductivity type signal charge storage region for collecting signal charges generated in the photodiode, and is a region having a higher impurity concentration than the N-type semiconductor region 303.

The difference between FIG. 3 and FIG. 2 is that in FIG. 2, a transistor with opposite conductivity types of N-type source and drain regions is formed in the P-type well 202, and the barrier 205 is of the same conductivity type as the P-type well 202. Contrary to this, in this embodiment, transistors having N-type source and drain regions of the same conductivity type are formed in the N-type semiconductor region 303 as the first conductivity type semiconductor region, and the conductivity type of the N-type semiconductor region is further opposite to that of the N-type semiconductor region.ofP-type barrier 305.

In addition, in the present embodiment, as the transistors that constitute the pixel together with the photodiode, there are a transfer transistor that transfers signal charges generated in the photodiode and a reset transistor that resets the FD electrode, but the transistor is not limited to this. For example, the transistor in the pixel may be any one or a combination of transfer transistors, reset transistors, amplifying transistors, or selection transistors.

In addition, in this embodiment, the barrier 305 provided under the gate of the N-type transistor forming the pixel serves to prevent short-circuit between the source and the drain, and even in the N-type semiconductor region 303. Transistors can also work.

In addition, the barrier 305 provided under the gate may be a barrier having a size corresponding to the gate region, or may be a barrier formed under the gate.

Therefore, in this embodiment, the barrier under the gate 309 of the transfer transistor is provided under a part of the gate 309, and the barrier corresponding to the size of the gate 323 is provided under the gate 323 of the reset transistor.

In addition, similarly, the barrier provided under the source and drain regions described in this specification may be provided under a part of the source and drain regions.

In addition, in the pixel structure shown in FIG. 3, since a deep N-type region of the photodiode is formed in the direction in which light travels, the quantum efficiency of the signal charge is higher than that of the first embodiment.

In this embodiment, because the N-type transistor in the pixel is formed in the N-type semiconductor region, its threshold potential drops to a value lower than that of the conventional N-type transistor, so the input of the amplifier transistor can be enlarged. Output range.

In addition, the threshold potential of the transistor in the present embodiment can be made higher than the conventional one by making the variation due to the back gate effect small.

In addition, the barrier 305 may be provided under the element isolation region 307. By providing the barrier 305 under the element isolation region 307, a structure is formed in which the signal charge is difficult to be absorbed by the photodiode or transistor in the adjacent pixel, and it is possible to prevent the signal charge from being mixed between the adjacent pixels.

(Fourth Embodiment) Fig. 4 is a schematic cross-sectional view of a solid-state imaging device according to a fourth embodiment of the present invention.

The difference between this embodiment and FIG. 3 is that in this embodiment, the barrier 405 is not limited to only under the gate of the transistor, but can also be provided under the source and/or drain regions of the transistor existing in the pixel. .

Because the potential barrier 405 is provided not only under the gate, but also under the source and/or drain regions, the signal charges formed under the barrier 405 are difficult to be used by the source and/or the transistor of the transistor. The structure of the drain region absorbs, so the sensitivity can be further improved.

In addition, in this embodiment, as the transistors in the pixel, there are a transfer transistor that transfers the signal charge generated in the photodiode and a reset transistor that resets the FD electrode, but the transistor is not limited to this. For example, the transistor in the pixel may be any one or a combination of transfer transistors, reset transistors, amplifying transistors, or selection transistors.

In addition, the barrier 405 may be provided under the element isolation region 407. Since the potential barrier 405 is provided under the element isolation region 407, the signal charge is difficult to be absorbed by the photodiode or transistor in the adjacent pixel. Therefore, it is possible to prevent the signal charge from being mixed between the adjacent pixels.

Since the potential barrier 405 is provided around the photodiode as described above, the signal charge formed in the photodiode is difficult to be absorbed by the source and/or drain regions of the adjacent transistors, so it can be improved compared to the case where there is no barrier. Sensitivity. In addition, one or more opening portions where no barrier is provided may be provided in the barrier 405 provided to surround the periphery of the photodiode.

When the potential barrier 405 is provided on the entire surface of the photodiode without the opening and the signal charge overflows from the photodiode, the overflow signal charge is difficult to be absorbed by the surrounding N-type semiconductor region due to the potential barrier 405, and it is easy to cause blurring. phenomenon. Therefore, absorption in the N-type semiconductor region around the photodiode easily causes blurring. Here, by providing an opening portion where the barrier 405 is not provided on at least a part of the periphery of the photodiode, the signal charge overflowing from the photodiode is absorbed, and the blur phenomenon can be suppressed.

In addition, as another form of suppressing the blur phenomenon, there is a so-called vertical overflow drain in which the impurity concentration of the P-type semiconductor region 402 is lower than the impurity concentration of the barrier 405, and the signal charge from the photodiode escapes from the N-type semiconductor substrate 401.Polar structure. Pole structure. Since the above-mentioned opening part need not be provided in this structure, the sensitivity can be improved compared with the case where the opening part is not provided.

In addition, in this embodiment, the signal charge storage region 412 may not be provided. In addition, it may also be a so-called buried photodiode in which a P-type semiconductor region is formed on the semiconductor interface portion of the signal charge storage region 412 in an N-type semiconductor region that stores signal charges.

As described above, as the pixel structure in the first to fourth embodiments, the polarities of the N-type and P-type may be completely reversed.

(Fifth Embodiment) Fig. 5 is a schematic cross-sectional view of a solid-state imaging device according to a fifth embodiment of the present invention.

A cross-sectional view explaining the fifth embodiment is shown in FIG. 5. Fig. 5 is the same as Fig. 16 of the conventional example, and shows the photodiode part, the transfer MOS transistor part, and the floating diffusion part in the pixel. 501 is an N-type silicon substrate, 502 is a buried P-type high-concentration layer, 503 is an N-type epitaxial growth layer that becomes a cathode of the photodiode, 504a, 504b are P-type separation layers, and 505a, 505b are P-type well layers. In addition, 506a is a channel barrier P-type layer under the field oxide film. 507 is a field oxide film, 508 is a gate oxide film of a MOS transistor, 509 is a gate polysilicon of a transfer MOS transistor, and 510 is a surface P-type layer for making the photodiode a buried type. Also 511 is the N-type drain diffusion region of the transfer MOS transistor, which temporarily stores the transferred charge and functions as a floating diffusion region. Also, 512 is the first interlayer insulating film, 513 is the contact plug, 514 is the first wiring layer, 515 is the second insulating film, 516 is the second wiring layer, and 517 is the third interlayer insulation Film 518 is a third wiring layer, and 519 is a passivation film. In this embodiment, three wiring layers are formed. However, in order to ensure optical characteristics according to the specification of the sensor, making the wiring layer one or two layers is not inconsistent with the gist of the present invention. In addition, by forming a color filter layer on the passivation film when used as a color imaging device, and further forming a microlens on the upper part of the color filter, the light sensitivity can be improved, which can be performed in the same manner as in the conventional imaging device. The P-type separation layers 504a, 504b, and the P-type well layers 505a, 505b, together with the embedded P-type high-concentration layer, surround the N-type epitaxial growth region 503 that becomes the cathode of the photodiode, so that one of the photodiodes adjacent to the pixel Electrical separation between time. Among the electron-hole pairs generated by the incident light 520 and 521 incident on the pixel, the electrons are reliably stored as signal charges in the photodiode due to the potential barriers generated by the various P-type layers surrounding the N-type epitaxial growth layer. The P-type well layer 505a also controls the transfer path when the electrons stored in the N-type epitaxial growth layer 503 are transferred to the floating diffusion region through the channel of the transfer MOS, which is located substantially directly below the transfer MOS transistor. By appropriately designing the concentration, depth, and lateral position of the P-type well layer, when a readout voltage is applied to the MOS gate 509, it is possible to work to completely deplete the N-type epitaxial growth layer 503. The P-type well layer electrically connected to the P-type separation layer 504a functions as a well of the charge transfer MOS transistor, and the threshold voltage of the MOS transistor is also controlled. In addition, the P-type well layer 505a is also arranged on The bottom of other transistors in the pixel functions as a well for these MOS transistors. The depth of the P-type high-concentration buried layer 502 is designed to be a depth that can obtain the spectral characteristics required by the sensor. In addition to forming a potential barrier, it is better to make the peak impurity concentration above IE15 (/cm3). In order to reduce the resistance, it is best to form it with a high concentration. Because high-energy and high-dose ion implantation increases manufacturing costs, the upper limit of concentration is actually determined. In addition, the P-type separation layers 504a and 504b determine the lateral position in consideration of the opening area of the photodiode and the position where the incident light reaches. The impurity concentration is preferably IE15 (/cm3) or more that can form a barrier. In addition, when the thickness of the N-type epitaxial growth layer is thicker than that of the present embodiment, by further adding a second P-type separation layer, a structure connected to the P-type layer in the depth direction can be formed. Next, we describe the manufacturing method used to fabricate the structure of this embodiment. The method of forming the P-type high-concentration buried layer 502 is roughly as shown in the following two methods. In the first method, after ion implantation of boron into the surface of the n-type silicon substrate 501, the n-type silicon layer 503 is epitaxially grown. The impurity concentration of the n-type silicon substrate 501 is suitable in the range of IE13 to IE15 (/cm3). In addition, the P-type buried layer 502 may be in the range of IE15 to IE20 (/cm3). The impurity concentration of the N-type epitaxial growth region 503 may be in the range of IE14 to IE16 (/cm3). The thickness of the N-type epitaxial growth region 503 is set according to the required spectral sensitivity. If it is a normal visible light imaging device, it is suitable to be about 2 μm to 6 μm. In the second method, boron is implanted from the surface of an n-type silicon substrate or an n-type silicon substrate epitaxially grown on an n-type silicon substrate with an impurity concentration of IE14 to IE16 (/cm3) with an acceleration energy of 1MeV to 5MeV to form P-type high-concentration buried layer 502. The surface side of the P-type high-concentration buried layer 502 becomes the N-type epitaxial growth layer 503 in FIG. 5. Next, by forming wiring patterns and ion implantation, P-type separation layers 504a and 504b are formed, and then P-type well layers 505a and 505b are formed. The impurity concentration of the P-type separation layers 504a and 504b can offset the N-type impurity concentration of the N-type silicon of the substrate, and the net P-type IE15 to IE18 (/cm3) can be obtained. When a higher impurity concentration than the N-type epitaxial growth layer is obtained through effective design, and a reverse bias is applied to the PN junction of the photodiode, the P-type layer will not be depleted and can effectively serve as a barrier working. As in this embodiment, when the thickness of the epitaxial growth layer When the thickness is about 4 μm, the P-type separation layers 504a and 504b are suitable as the stroke of ion implantation of 1.5 to 3.0 μm. In this embodiment, boron is used as the ion species, and a dose of 6E11 (cm-2) is implanted with an energy of 1200 KeV. According to this condition, the stroke of boron is 1.9μm, enabling P-type high-density embedding and electrical connection. P-type well layers 505a and 505b are suitable as the stroke of ion implantation of 0.5 to 1.5 μm. In this embodiment, boron is used as the ion species, and a dose of 1E12 (cm-2) is implanted with an energy of 500 KeV. According to this condition, the stroke of boron is 1.0 μm, and it can be electrically connected to the P-type separation layers 504a and 504b. In addition, when the thickness of the epitaxial growth layer changes, the production conditions of the P-type separation layer and the P-type well layer change. In order to electrically connect the P-type well layer and the P-type high-concentration buried layer, the thickness of the epitaxial growth layer is 6 μm or more, and the P-type well layer is suitably composed of two layers. In addition, the P-type separation layer is not required when the thickness of the epitaxial growth layer is 2 μm or less. The thickness of the epitaxial growth layer determines the spectral sensitivity of the long-wavelength side of the imaging element, but because the thickness of the epitaxial growth layer is 4 μm in the normal visible light region, it is sufficient, so the structure of this embodiment is suitable for imaging in the visible light region. element. Next, after forming the channel barrier layers 506a and 506b by ion implantation, the field oxide film 507 is formed by the usual LOCOS separation method or the LOCOS method or the like. After the polysilicon electrode 509 is formed, a P-type surface layer 510 and an N-type high-concentration layer 511 are formed on the surface of the photodiode by ion implantation. Since the manufacturing method after the contact opening process is the same as that of the existing imaging element, it is omitted. According to this embodiment, photocarriers that cannot be partially captured in existing photodiodes can also be captured, and the sensitivity is improved. In addition, in this embodiment, the conductivity type of the epitaxial growth layer is N-type, but the present invention can also be applied when making it a P-type and inverting all other conductivity types to form a hole-storing type pixel. This is self-evident. 5μm is suitable. In this embodiment, boron is used as the ion species, and a dose of 1E12 (cm-2) is implanted with an energy of 500 KeV. According to this condition, the stroke of boron is 1.0 μm, and it can be electrically connected to the P-type separation layers 504a and 504b. In addition, when the thickness of the epitaxial growth layer changes, the production conditions of the P-type separation layer and the P-type well layer change. In order to electrically connect the P-type well layer and the P-type high-concentration buried layer, the thickness of the epitaxial growth layer is 6 μm or more, and the P-type well layer is suitably composed of two layers. In addition, the P-type separation layer is not required when the thickness of the epitaxial growth layer is 2 μm or less. The thickness of the epitaxial growth layer determines the spectral sensitivity of the long-wavelength side of the imaging element, but because the thickness of the epitaxial growth layer is 4 μm in the normal visible light region, it is sufficient, so the structure of this embodiment is suitable for imaging in the visible light region. element. Next, after forming the channel barrier layers 506a and 506b by ion implantation, the field oxide film 507 is formed by the usual LOCOS separation method or the LOCOS method or the like. After the polysilicon electrode 509 is formed, a P-type surface layer 510 and an N-type high-concentration layer 511 are formed on the surface of the photodiode by ion implantation. Since the manufacturing method after the contact opening process is the same as that of the existing imaging element, it is omitted. According to this embodiment, photocarriers that cannot be partially captured in existing photodiodes can also be captured, and the sensitivity is improved. In addition, in this embodiment, the conductivity type of the epitaxial growth layer is N-type, but the present invention can also be applied when making it a P-type and inverting all other conductivity types to form a hole-storing type pixel. This is self-evident. 5μm is suitable. In this embodiment, boron is used as the ion species, and a dose of 1E12 (cm-2) is implanted with an energy of 500 KeV. According to this condition, the stroke of boron is 1.0 μm, and it can be electrically connected to the P-type separation layers 504a and 504b. In addition, when the thickness of the epitaxial growth layer changes, the production conditions of the P-type separation layer and the P-type well layer change. In order to electrically connect the P-type well layer and the P-type high-concentration buried layer, the thickness of the epitaxial growth layer is 6 μm or more, and the P-type well layer is suitably composed of two layers. In addition, the P-type separation layer is not required when the thickness of the epitaxial growth layer is 2 μm or less. The thickness of the epitaxial growth layer determines the spectral sensitivity of the long-wavelength side of the imaging element, but because the thickness of the epitaxial growth layer is 4 μm in the normal visible light region, it is sufficient, so the structure of this embodiment is suitable for imaging in the visible light region. element. Next, after forming the channel barrier layers 506a and 506b by ion implantation, the field oxide film 507 is formed by the usual LOCOS separation method or the LOCOS method or the like. After the polysilicon electrode 509 is formed, a P-type surface layer 510 and an N-type high-concentration layer 511 are formed on the surface of the photodiode by ion implantation. Since the manufacturing method after the contact opening process is the same as that of the existing imaging element, it is omitted. According to this embodiment, photocarriers that cannot be partially captured in existing photodiodes can also be captured, and the sensitivity is improved. In addition, in this embodiment, the conductivity type of the epitaxial growth layer is N-type, but the present invention can also be applied when making it a P-type and inverting all other conductivity types to form a hole-storing type pixel. This is self-evident. 0 μm, which can be electrically connected to the P-type separation layers 504a and 504b. In addition, when the thickness of the epitaxial growth layer changes, the production conditions of the P-type separation layer and the P-type well layer change. In order to electrically connect the P-type well layer and the P-type high-concentration buried layer, the thickness of the epitaxial growth layer is 6 μm or more, and the P-type well layer is suitably composed of two layers. In addition, the P-type separation layer is not required when the thickness of the epitaxial growth layer is 2 μm or less. The thickness of the epitaxial growth layer determines the spectral sensitivity of the long-wavelength side of the imaging element, but because the thickness of the epitaxial growth layer is 4 μm in the normal visible light region, it is sufficient, so the structure of this embodiment is suitable for imaging in the visible light region. element. Next, after forming the channel barrier layers 506a and 506b by ion implantation, the field oxide film 507 is formed by the usual LOCOS separation method or the LOCOS method or the like. After the polysilicon electrode 509 is formed, a P-type surface layer 510 and an N-type high-concentration layer 511 are formed on the surface of the photodiode by ion implantation. Since the manufacturing method after the contact opening process is the same as that of the existing imaging element, it is omitted. According to this embodiment, photocarriers that cannot be partially captured in existing photodiodes can also be captured, and the sensitivity is improved. In addition, in this embodiment, the conductivity type of the epitaxial growth layer is N-type, but the present invention can also be applied when making it a P-type and inverting all other conductivity types to form a hole-storing type pixel. This is self-evident. 0 μm, which can be electrically connected to the P-type separation layers 504a and 504b. In addition, when the thickness of the epitaxial growth layer changes, the production conditions of the P-type separation layer and the P-type well layer change. In order to electrically connect the P-type well layer and the P-type high-concentration buried layer, the thickness of the epitaxial growth layer is 6 μm or more, and the P-type well layer is suitably composed of two layers. In addition, the P-type separation layer is not required when the thickness of the epitaxial growth layer is 2 μm or less. The thickness of the epitaxial growth layer determines the spectral sensitivity of the long-wavelength side of the imaging element, but because the thickness of the epitaxial growth layer is 4 μm in the normal visible light region, it is sufficient, so the structure of this embodiment is suitable for imaging in the visible light region. element. Next, after forming the channel barrier layers 506a and 506b by ion implantation, the field oxide film 507 is formed by the usual LOCOS separation method or the LOCOS method or the like. After the polysilicon electrode 509 is formed, a P-type surface layer 510 and an N-type high-concentration layer 511 are formed on the surface of the photodiode by ion implantation. Since the manufacturing method after the contact opening process is the same as that of the existing imaging element, it is omitted. According to this embodiment, photocarriers that cannot be partially captured in existing photodiodes can also be captured, and the sensitivity is improved. In addition, in this embodiment, the conductivity type of the epitaxial growth layer is N-type, but the present invention can also be applied when making it a P-type and inverting all other conductivity types to form a hole-storing type pixel. This is self-evident.

Fig. 8 is an example of a plan view. In order to surround the photodiode 801, the P-type well layer and the separation layer 802 are arranged in the region of the dotted line. At one end of the photodiode 801, a gate line 803 of a transfer transistor for transferring charge is arranged. Also 804 is a floating diffusion area for temporarily storing and transferring charges. In the plan view, MOS transistors for amplification, MOS transistors for reset, or MOS transistors for row selection are not shown, but in order to realize the present invention, no new restrictions are imposed on the arrangement of these elements. The main point of this plane is to surround the photodiode with a well layer and a separation layer to separate adjacent pixels.

Fig. 11 is a schematic diagram of a circuit configuration when a plurality of pixel circuits of the present invention are arranged two-dimensionally. In one pixel 1101, there are a photodiode 1102, a transfer MOS transistor 1103, an amplifying MOS transistor 1104, a reset MOS transistor 1105, and a selection MOS transistor 1106. The gates of the select MOS transistors in the same row are connected with the select line 1107, the gates of the reset MOS transistors are connected with the reset line 1108, and the gates of the transfer MOS transistors are connected with the transfer line 1109, and the vertical scanning circuit 1110 is used for scanning. select. The current source 1112 is connected to the output line 1111 in the same column, and the potential of the output line can be read by the operation of the source tracker. Separately, the optical signal readout line 1115 is used to store the optical signal on the output line in the charge storage portion 1118 through the selected optical signal transfer MOS transistor 1113, and the noise signal readout line 1116 is used to transfer the MOS transistor 1114 through the selected noise signal. The noise signal is stored in the charge storage part 1118. The horizontal scanning circuit sequentially scans and reads out the signals stored in the charge storage portion 1118, and outputs the difference between the optical signal and the noise signal through a differential amplifier circuit not shown in the figure.

Fig. 12 is a diagram showing an example of a circuit block diagram when the solid-state imaging device according to the present invention is applied to a camera. In front of the photographic lens 1202 is a shutter 1201, which controls exposure. When necessary, the light quantity is controlled by the aperture 1203, and the image is formed on the solid-state imaging element 1204. The signal output from the solid-state imaging element 1204 is processed by the signal processing circuit 1205, and converted from an analog signal to a digital signal by an A/D converter. The output digital signal is further subjected to calculation processing in the signal processing section 1207. The processed digital signal is stored in the memory 1210 and sent to the external device through the external I/F 1213. The solid-state imaging device 1204, the imaging signal processing circuit 1205, the A/D converter 1206, and the signal processing section 1207 are controlled by the timing generation section 1208, and the entire system is controlled by the overall control/calculation section 1209. In order to record an image on the recording medium 1212, a digital signal is recorded and output by the recording medium control I/F section 1211 controlled by the overall control and calculation section.

According to the present invention, in addition to greatly improving the sensitivity of the CMOS solid-state imaging device, it is also possible to construct a photodiode with a larger N-type layer volume than the conventional one, so that the saturation current of the imaging element can be increased. In addition, since the impurity concentration of the junction portion of the N-type epitaxial growth layer 503 connected to the surface P-type layer 510 of the buried photodiode is lower than the conventional one, the occurrence rate of pixel defects can be reduced, thereby comparing with the conventional example It can also improve quality.

(Sixth Embodiment) Fig. 6 is a schematic cross-sectional view of a solid-state imaging device according to a sixth embodiment of the present invention.

A cross-sectional view explaining the sixth embodiment is shown in FIG. 6. Since the wiring part except for the gate is the same as in the fifth embodiment, it is not shown in the figure.

The difference from the fifth embodiment is that another N-type layer 612 is added near the surface of the N-type epitaxial growth layer 603 in the structure of the photodiode. The N-type layer 612 has a structure that is under the P-type surface layer 610, and a part of it enters under the gate 609. It is suitable that the impurity concentration of the N-type layer 612 is higher than that of the N-type epitaxial growth layer by about IE15 to IE17. In this way, since the N-type layer 612 becomes a place with a low electric potential for electrons, electrons are collected in the N-type layer 612 during charge storage. Therefore, it is a structure suitable for completely transferring electrons when the MOS transistor transfers electric charges. Since the number of electrons remaining in the photodiode does not fluctuate by completely transferring charges, it is possible to construct an image pickup element with little random noise. The N-type layer 612 is formed by forming a wiring pattern and ion implantation in the process before forming the polysilicon gate 609. Alternatively, after the polysilicon gate 609 is formed, an oblique ion implantation method can be used to drill under the polysilicon gate 609. The other parts of the cross-sectional view of FIG. 6 are the same as in the fifth embodiment. The gist of the present invention is that the P-type separation layers 604a and 604b and the P-type well layers 605a and 605b can be formed by the same method as in the fifth embodiment. Since the other parts are also the same, their description is omitted.

The effect of this embodiment is that by providing a portion with a higher impurity concentration than other portions on the surface side of the cathode portion of the photodiode, it is easy to transfer the stored electrons by the transfer MOS transistor. According to this structure, it is possible to realize a device that is easy to completely transfer the charge of the photodiode and has little random noise. In addition, the present embodiment can effectively operate as an imaging system based on the planar structure, circuit structure, and block structure shown in FIGS. 8, 11, and 12.

(Seventh Embodiment) Fig. 7 is a schematic cross-sectional view of a solid-state imaging device according to a seventh embodiment of the present invention.

A cross-sectional view explaining the seventh embodiment is shown in FIG. 7.

In this embodiment, the P-type separation layers 704a and 704b have a structure in which the P-type well layers 705a and 705b and the P-type high-concentration buried layer 702 are not in contact with each other in terms of impurity concentration. Even with this structure, these P-type regions can be used if they form a sufficient barrier for the N-type region (N-type epitaxial growth layer 703) of the photodiode. The potential barrier can be determined by the amount of charge to be stored in the photodiode. In addition, in the fifth embodiment, the thickness of the N-type epitaxial growth layer is 2 μm to 6 μm, but since a barrier is formed in the P-type layer, the number of separation layers can be increased to a plurality in the depth direction. Since the other parts of the cross-sectional view of FIG. 7 are the same as those of the fifth embodiment, their description is omitted.

In this embodiment, it is shown that if the separation layer is not in contact with the P-type well layer and the P-type buried layer, and a sufficient barrier is formed, the present invention can be applied. It means that it is better to design the required number and concentration of separation layers according to the instructions of this embodiment and corresponding to the thickness of the N-type epitaxial growth layer.

(Eighth Embodiment) Fig. 9 is a schematic cross-sectional view of a solid-state imaging device according to an eighth embodiment of the present invention.

A cross-sectional view explaining the eighth embodiment is shown in FIG. 9.

In this embodiment, the case where STI (Shallow Trench Isolation) is used as the element separation method is shown. The P-type separation layers 904a and 904b represent structures that do not contact the P-type well layers 905a and 905b and the P-type high-concentration buried layer 902 at all in terms of impurity concentration. This structure is the same as that of the seventh embodiment. In FIG. 9, there are P-type regions 906 a and 906 b below the STI oxide film 907 so as not to deplete the interface between the STI oxide film 907 and silicon. This P-type region is particularly important in order not to deplete the side surface of the STI oxide film. The P-type well layers 905a and 905b are formed to the same depth as in the seventh embodiment, to prevent electric charges from penetrating into adjacent pixels, and to control the transmission path of the transmission MOS transistor and also control the threshold of the transmission MOS transistor. In addition, the P-type well layer 905b directly under the STI oxide film 907 forms a barrier directly under the element separation, and also functions as a channel barrier layer under the STI oxide film 907. The P-type separation layers 904a and 904b, as in the other embodiments, form barriers between the P-type well layers 905a and 905b and the P-type high-concentration buried region 902.

Since the other structures are the same as those of the sixth embodiment to the seventh embodiment, their description is omitted.

In this embodiment, STI is used for element separation, which has the following effect: the separation between adjacent photodiodes is improved. Because the surface is flat, the shape of the barrier layer is stabilized by micro processing. Since the P-type separation layer and the P-type well layer can be formed by ion implantation after forming the STI, the P-type separation layer and the P-type well layer can form a fine pattern that does not widen due to thermal diffusion during oxidation.

This embodiment using STI is suitable for manufacturing fine pixel image pickup elements.

(Ninth Embodiment) Fig. 10 is a schematic cross-sectional view of a solid-state imaging device according to a ninth embodiment of the present invention.

A cross-sectional view explaining the ninth embodiment is shown in FIG. 10.

In this embodiment, a case where the deep trench isolation method is used as the element separation method is shown. In this embodiment, the P-type separation layer 1004 and the P-type well layer 1005 have a structure that does not contact the P-type high-concentration buried layer 1002 at all in terms of impurity concentration. This structure is the same as the seventh and eighth embodiments. The trench isolation oxide film 1007 has a depth of 3 μm in silicon, and the P-type regions 1006a and 1006b cover the interface in order not to deplete the interface between the trench isolation oxide film 1007 and silicon. The P-type regions 1006a and 1006b prevent dark current from forming barriers in the trench separation oxide film 1007 and the P-type high-concentration buried region 1002 at the same time.

Since the other structures are the same as those of the sixth embodiment to the eighth embodiment, their description is omitted.

In this embodiment, the deep trench separation method is used to separate the elements, which has the following effect: Compared with STI, the separation between adjacent photodiodes is further improved. Because the width of the separation area is small and it can be separated up to deep areas, it is a structure suitable for fine pixels.

As described above, according to the present invention, a high-sensitivity solid-state imaging device can be realized as a structure in which a potential barrier is provided in the pixel to make it difficult for signal charges to be absorbed by parts other than the photodiode.

Furthermore, according to the present invention, since a photodiode with a larger volume of the N-type layer can be constructed as compared with the prior art, the saturation current of the image pickup element can also be increased. In addition, since the impurity concentration of the junction part of the N-type epitaxial growth layer connected to the surface P-type layer of the buried photodiode is lower than usual, the occurrence rate of pixel defects can be reduced, and it can be compared with conventional examples. Improve quality.

Furthermore, by providing a part with a higher impurity concentration than other parts on the surface side of the cathode part of the photodiode, it is easy to completely transfer the charge of the photodiode, and a solid-state imaging device with less random noise can be realized.