US3786195A

Variable delay line signal processor for sound reproduction

Abstract

An electrical delay line which has variable delay controlled by a signal input thereto is connected in a sound signal channel for signals such as human speech, to compress or expand the sound signal waveform depending on whether the time delay in the line is increased or decreased. By periodically sweeping the delay line from minimum to maximum time delay or vice-versa, repeated segments of a continuous sound signal waveform are processed so that an output audio signal can be obtained having the original frequency components of the signal and occupying a time duration which is equal to or smaller or larger than the original sound sequence with the successive segments of the signal processed by the variable delay line assembled with regard both to the significant parameters of human speech or other coding and the electrical conditions imposed by the system to produce a composite audio signal which is an intelligible replica of the original and substantially free of annoying aberrations introduced by the delay line processor. Variable delay using analog or digital signal storage is also provided.

US3786195A, drawing sheet 1
Sheet 1 of 35

Term

Term ended

Expired 15 January 1991, 35.7 years ago.

  1. Priority and filed
  2. Granted
  3. Expired
  4. Today

64 claims: 12 independent, 52 dependent

  1. 1
    I claim:1. A processor for electric signals representing coded audible signals such as speech or the like comprising: means for deriving said electric signals as analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals;variable delay line means having an input and an output, said input coupled to said means for deriving said electric signals for propagating representations of said electric signals to said output with controllable time delay;means for controlling said delay line means for periodic linear variation of said time delay between predetermined delay values;and means coupled to said output of said delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said time delay for producing output signals reproducible as an audible representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible signals.
  2. 2
    A processor for electric signals representing coded audible signals such as speech or the like comprising:means for deriving said electric signals as analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals;variable delay line means having an input and an output, said input coupled to said means for deriving said electric signals for propagating representations of said electric signals to said output with controllable time delay;means for controlling said delay line means for periodic linear variation of said time delay between predetermined delay values;and means coupled to said output of said delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said time delay for producing output signals reproducible as an audible representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible signals;and in which said means for controlling said delay line means provides periods of linearly changing unidirectional delay variation alternating with reset intervals wherein said delay line is returned to an initial predetermined delay value and including means for blanking output signals from said output of said delay line means to substantially zero amplitude during said reset intervals.
  3. 11
    A processor for electric signals representing coded audible signals such as speech or the like comprising:means for deriving said electric signals as analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals;variable delay line means having an input and an output, said input coupled to said means for deriving said electric signals for propagating representations of said electric signals to said output with controllable time delay;means for controlling said delay line means for periodic linear variation of said time delay between predetermined delay values;and means coupled to said output of said delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said time delay for producing output signals reproducible as an audible representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible signals;and in which said means for controlling said delay line means provides periods of linearly changing unidirectional delay variation alternating with reset intervals wherein said delay line is returned to an initial predetermined delay value and further including: second delay line means coupled to said means for deriving said electric signals;and means for interrupting signals from the output of said variable delay line means and substituting signals from the output of said second delay line means during said reset intervals to produce said output signals reproducible as said audible representation.
  4. 13
    A processor for electric signals representing coded audible signals such as speech or the like, said electric signals being analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals comprising:first and second variable delay line means coupled to a source of said electric signals for propagating said electric signals therein with controllable time delay;means for controlling said first and second delay line means for periodic linear variation of said time delay between predetermined delay values, said means for controlling said first and second delay line means providing periods of linearly changing unidirectional delay variation alternating with reset intervals wherein said delay lines are returned to an initial predetermined delay value, said reset intervals for each said delay line means occurring within the period of the unidirectional delay variation of the other said delay line means;and means coupled to the outputs of said first and second delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said delay for producing an audible representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible signals.
  5. 18
    A processor for electric signals representing coded audible signals such as speech or the like, said electric signals being analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals comprising:first and second variable delay line means coupled to a source of said electric signals for propagating said electric signals therein with controllable time delay;input high pass filter means having adjustable low frequency cutoff interposed between said source and the input of said variable delay line means;means for controlling said first and second delay line means for periodic linear variation of said time delay between predetermined delay values, said means for controlling said first and second delay line means providing periods of linearly changing unidirectional delay variation alternating with reset intervals wherein said delay lines are returned to an initial predetermined delay value, said reset intervals for each said delay line means occurring within the period of the unidirectional delay variation of the other said delay line means;means for adjusting the effective rate of said periodic linear variation to adjust the factor by which frequencies propagated through said delay line are altered;means coupling said cutoff adjusting means and said effective rate adjusting means for related variation to eliminate low frequency components which would otherwise produce frequency components in said delay line means below an audio low fre quency limit related to said factor and the period of said variation;and, means coupled to the outputs of said first and second delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said delay for producing an audible representation of said electric signals having frequency components altered by substantially said given factor to approximate the frequency components of said audible signals.
  6. 23
    A processor for recordings representing coded audible signals such as speech or the like comprising:playback means operable to reproduce said record- ing at a rate faster by a given factor than the recording rate thereby producing electric signals which are the time compressed analog of said audible signals with frequency components increased by said factor;variable delay line means coupled to said playback means for propagating said electric signals therein with controllable time delay;means for controlling said delay line means for periodic linear increase of said time delay between predetermined delay values;and, means coupled to the output of said delay line means and responsive subtantially only to signals propagating through said delay line means which have been subject to said increase of said time delay for producing an audible representation of said electrical signals having frequency components reduced substantially by said factor to approximate the frequency components of said audible signals. 3,786,195
  7. 33
    A processor for recordings representing coded audible signals such as speech or the like comprising:playback means operable to reproduce said recording at a rate faster by a given factor than the recording rate thereby producing electric signals which are the time compressed analog of said audible signals with frequency components increased by said factor;first and second variable delay line means coupled to said playback means for propagating said electric signals therein with controllable time delay;means for controlling said first and second delay line means for periodic linear variation of said time delay between predetermined delay values, said means for controlling said first and second delay line means providing periods of linearly changing unidirectional delay variation alternating with reset intervals wherein said delay lines are returned to an initial predetermined delay value, said reset intervals for each said delay line means occurring within the period of the unidirectional delay variation of the other said delay line means;and means coupled to the outputs of said first and second delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to unidirectional variation of said delay for producing an audible representation of said electric signals having frequency components reduced by substantially said factor to approximate the frequency components of said audible signals.
  8. 43
    A processor for recordings representing coded audible signals such as speech or the like comprising:playback means operable to reproduce said recording at a rate slower by a given factor than the recording rate thereby producing electric signals which are the time expanded analog of said audible signals with frequency components decreased by said factor;variable delay line means coupled to said playback means for propagating said electric signals therein with controllable time delay;means for controlling said delay line means for periodic linear decrease of said time delay between predetermined delay values;and means coupled to the output of said delay line means and responsive substantially only to signals propagating through said delay line means which have been subject to said decrease of said time delay for producing an audible representation of said electrical signals having frequency components increased substantially by said factor to approximate the frequency components of said audible signals.
  9. 54
    55. The method of processing random speech signals 20 to convey information intelligibly to a human listener at a rate different than the normal speaking equivalent for said information and without objectionable alteration of the frequency components of said equivalent as reproduced for the listener comprising the steps of:25 developing a full speech signal train of said information with the elapsed time for said signal train altered into a time interval differing by a predetermined factor from that of the normal speaking equivalent for said signal train thereby changing by 30 said factor the frequency of the spectral components in said signal train relative to said equivalent;processing said signal train by a linear periodic”time delay function to alter a regular succession of predetermined length segments of said signal train into 35 segments approximating a continuous signal with the frequency components in said continuous signal altered by said factor relative to said components in said signal train to approximate the components of said normal speaking equivalent;and 40 reproducing said continuous signal as an intelligible representation of said information content with the elapsed time altered by said factor but with the frequency components unchanged relative to said equivalent. 45
  10. 57
    58. A processor for electric signals representing coded audible signals such as speech or the like, said ” electric signals being analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals comprising:65 two similar delay lines coupled to a source of said electric signals for propagating said electric signals between the input and output terminals thereof ,195 with controllable frequency transformation;means for controlling said delay lines alternately for periodic propagation of said electric signals to produce predetermined frequency transformation of signals emerging at the outputs of said delay lines;and means coupled to said outputs of both said delay line means and responsive substantially only to signals propagating through said delay lines which have been subject to said predetermined frequency transformation for producing an audible representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible signals.
  11. 60
    61. The method of processing random speech signals to convey information intelligibly to a human listener at a rate different than the normal speaking equivalent for said information and without objectionable alteration of the frequency components of said equivalent as reproduced for the listener comprising the steps of:developing a full speech signal train of said information with the elapsed time for said signal train altered into a time interval differing by a predetermined factor from that of the normal speaking equivalent for said signal train thereby changing by said factor the frequency of the spectral components in said signal train relative to said equivalent;propagating said signal train through a storage channel within which it is subject to a periodic frequency transformation function to alter a regular succession of predetermined length input segments of said signal train into output segments approximating a continuous signal with the frequency components in said continuous signal altered by the inverse of said factor relative to said components in said signal train to approximate the components of said normal speaking equivalent;and reproducing said continuous signal as an intelligible audible representation of the information content of said signal train but with the frequency components unchanged relative to said equivalent.
  12. 64
    65. In a processor for electric signals such as those representing the coded audible sounds of speech or the like, said electric signals being analog representations of said audible sounds with the frequency components of said electric signals related by a given factor to the frequency components of said audible sounds, the improvement comprising:controllable delay means having an input and an output, said input coupled to a source of said electric signals for passing signals from said source into said delay means, and said delay means passing signals therein to said output with controllable time delay;means for controlling said delay means with repetitive variation of said controllable time delay between predetermined delay values the period of said variation being greater than the period of the lowest frequency component of said electric signals at said output of said delay means thereby progressively delaying signals during each period of said repetitive variation as they pass through said delay where c is said factor, /(t) is the time delay function representing said variation of said controllable time delay t in is the input time of a given signal element to said delay mearis and t oui is the output time for said given signal element;and means coupled to said output of said delay means and responsive substantially only to signals at said output having said predetermined frequency transformation for producing a composite output signal representation of said electric signals having frequency components altered by substantially said factor to approximate the frequency components of said audible sounds. * * * * * UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3,786,195 Page 1 of 5 DATED January 15, 1974 INVENTOR(S) : Murray M. Schiffman It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: [73] Assignees: Cambridge Research and Development Group, Westport, Conn.;Sanford D. Greenberg, Washington, D. C.;D. T. Liquidating Partnership, New York, N.Y. should read as follows: --[73] Assignees: Cambridge Research and Development Group, Westport, Conn.;Sanford D. Greenberg, Washington D.C.;D. T. Liquidating Partnership, New York, N. Y.;and Murray M. Schiffman, Newton, Mass. — UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. DATED INVENTOR(S) 3,786,195 January 15, 1974 Murray M. Schiffman Page 2 of 5 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: c-l Column 7, line 55, d=2 (c-l/c+1) should read -- d=2 c+1 — Column 8, line 1, tdt should read — t dt —;Column 8, line 3, T£ n 2 should read — T 2 in — Column 8, line 9, d/2 should read — d —;2 Column 8, line 11, c-l/c+1 should read — c-l — c+2 Column 8, line 22, ”(=(l/e)t in =(l/4)t in should read 1 _ 1 e ^in “ 4 t in^ Column 8, line 24, (=( 1-e /e)t= - 3 /4) should read 1-e 3 , - (=±^t = -Jt) Column 8, line 35, Hence, c*Ti n =(dT in + dT out / 2 ) (l-e/e)T in = d/2 [T in +(T in/e )] d = 2 (1-e/l+e) should read tt 1 + dTont — Hence , c τ · = in _____ in l~e T in = d (T in +Tin ) θ 2 Ί e d = 2— 1+e UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3,786,195 p , . DATED January 15, 1974 INVENTOR(S) : Murray M. Schiffman It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. : 3,786,195 Page 4 of 5 DATED : January 15, 1974 INVENTOR(S) : Murray M. Schiffman It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: Column 19, line 57, d=2(1-e/l+e) = (N'/t) [ (1/f-t) ” (l/f o )] should read „ 1-e Ν' 1 1 . — d-2 1+e _ t Column 19, line 63,t N = Ν' /2[( l/f N ) + (l/f o ) ] should read t N = Ν' (1 + 1) — 2 f o - 2p Column 20, line 13, (2p/p-l) should read — p=i Column 20, line 22, after pulse delete derived;and insert — shift — Column 20, line 23, after quency correct the spelling of derieved to — derived — Column 21, line 18, 1/f should read — | Column 25, line 49, after segment delete into c-1 Column 32, line 35, d-2c-l/c+l,c should read —d-2 c+1 ' c Column 32, line 49, 2(c-l/c+l)t where t should read c-1 — 2 where t — UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. DATED INVENTOR(S) 3,786,195 January 15, 1974 Murray M. Schiffman Page 5 of 5 It is certified that error appears in the above-identified patent and that said Letters patent are hereby corrected as shown below: Column 34, line 65, N(p-l/p) p-1 1 should read — N ~~ ( 7 P r t [i/f t - d/f o ] = 2 1 C-1 . f ) “ 2 c+1 t (c-l/c+1)t Signed and Sealed this thirtieth JDay of August 1977 (SEAL] Attest: RUTH C. MASON Attesting Officer C. MARSHALL DANN Commissioner of Patents and Trademarks