Data transmission

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002This invention relates to data transmission.

00032. Description of the Prior Art

0004Direct Stream Digital (DSD) is a high-resolution single-bit audio coding system used for the so-called Super Audio CD consumer disc format. DSD was developed with a view to producing audio signals comparable to those reproduced from the best analogue formats. DSD signals can produce a frequency response from DC to 100 kHz and have a dynamic range of greater than 120 dB across the audio band.

0005DSD makes use of 1-bit digital audio and requires a high frequency audio sample clock at 64 Fs=2.8224 MHz (the sample clock of standard PCM systems (Fs) is 44.1 kHz). This high frequency sample clock is transmitted along with the data to facilitate accurate signal reconstruction at the receiving end. Furthermore each channel of 64 Fs DSD audio requires a transmission bandwidth of 2.8224 Mbit/s.

0006Several known audio networking systems make use of Ethernet to transmit high bandwidth audio-data between a network of audio processing devices. For example the “Magic” system proprietary to Gibson makes use of the Ethernet Media Access Control MAC layer (i.e. physical layer and data link layer) to transmit audio data at a fixed audio sampling frequency of 48 kHz using one Ethernet frame per sample period. The CobraNet audio networking system proprietary to Peak Audio also uses the Ethernet MAC layer to transmit uncompressed digital audio data between networked devices. The CobraNet system uses a 48 kHz sampling rate and allows for transmission of 20-bit and 24-bit audio data. However, none of these known systems provides an interconnection suitable for linking DSD audio devices. This is because Ethernet frame timing is completely unsuitable for transmitting a 2.8224 MHz DSD sample clock.

0007Copending application Ser. Nos. 10/620,671 and 10/803,621 relate to techniques for carrying such bitstreams over the physical layer of an Ethernet-type interface. The systems described in these two copending applications aim to provide circuit-switched interconnections between large-scale multi-track production equipment for DSD audio such as multi-channel ADC/DACs, DSD mixers and multi-channel DSD recorders.

0008So, in the systems of the two copending applications techniques are provided which are based on the direct use of the Ethernet physical layer interface. This can be shown to provide effective and low-latency circuit-switched links at audio data rates of the order of 64 Fs, such systems also being useful for the transmission of other streamed digital signals such as PCM audio signals. Auxiliary data channels can also be handled by the same means. However, as this is achieved by deliberately avoiding the use of higher levels of the Ethernet protocol, there is no convenient way of providing packet-switched auxiliary data routing within such a system.

SUMMARY OF THE INVENTION

0009This invention provides a data communication system for communicating one or more payload streamed data signals and an auxiliary data signal, the auxiliary data signal being organised as one or more data packets according to a data packet protocol, each packet having a respective packet destination address, the system comprising: <ul id="ul8S-d0e22100001" list-style="none"><li id="ul8S-d0e22100002-li00002"><ul id="ul8S-d0e22100002" list-style="none"><li id="ul8S-d0e22100002-p00010" num="00010"> (i) at least two data handling nodes, a transmitting one of said data handling nodes being arranged to transmit data to a receiving one of said data handling nodes across a data connection link; </li><li id="ul8S-d0e22100002-p00011" num="00011"> (ii) a transmission data formatter associated with said transmitting node for formatting said data packets of said auxiliary data signal into a streamed data signal format and for multiplexing said payload streamed data signals and said formatted auxiliary data signal into a bitstream for transmission; </li><li id="ul8S-d0e22100002-p00012" num="00012"> (iii) a received data reformatter associated with said receiving node for demultiplexing said input streamed data signals and said formatted auxiliary data signal and for reformatting said auxiliary data signal into packets according to said data packet protocol. </li></ul></li></ul>

0013This invention also provides a data router arranged to receive a data stream containing data packets, having associated destination indicators, via two or more input/output channels and to direct each packet to one or more input/output channels in dependence on said respective destination indicator, in which each input/output channel has an associated maximum data rate, said router comprising: <ul id="ul8S-d0e22100003" list-style="none"><li id="ul8S-d0e22100004-li00004"><ul id="ul8S-d0e22100004" list-style="none"><li id="ul8S-d0e22100002-p00014" num="00014"> an Ethernet router; and a routing interface associated with each input/output channel; said routing interface and said Ethernet router being operable to communicate at a data rate higher than said maximum data rate associated with at least some of said individual input/output channels; </li><li id="ul8S-d0e22100002-p00015" num="00015"> said routing interface being arranged to supply data packets received via said data stream associated with that input/output channel to said Ethernet router in said form of Ethernet data packets; </li><li id="ul8S-d0e22100002-p00016" num="00016"> said routing interface being arranged to receive data packets to be output via said corresponding input/output channel from said Ethernet router and to provide said data packets as a data stream for output by that channel at a data rate no greater than said channel's maximum data rate; and </li><li id="ul8S-d0e22100002-p00017" num="00017"> said routing interface and said Ethernet router co-operating to selectively inhibit said transfer of data packets from said Ethernet router to said routing interface in order to avoid exceeding that channel's maximum data rate. </li></ul></li></ul>

0018Further respective aspects and features of the invention are defined in the appended claims.

0019The invention addresses the above problems by embedding packetised auxiliary data into the streamed payload signal, and then on reception demultiplexing the packets into a format suitable for routing using a standard (e.g. Ethernet) router.

BRIEF DESCRIPTION OF THE DRAWINGS

0020The above and other objects, features and advantages of the invention will be apparent from the following detailed description of the illustrative embodiments which is to be read in connection with the accompanying drawings, in which:

0021<figref idref="DRAWINGS">FIG. 1</figref> shows the standard seven-layer Open Systems Interconnection (OSI) model for network protocol architectures and sub-layers of the Ethernet physical layer;

0022<figref idref="DRAWINGS">FIG. 2</figref> illustrates a known system for signal transfer in DSD systems;

0023<figref idref="DRAWINGS">FIG. 3</figref> schematically illustrates a DSD interconnection according to an embodiment of the present invention;

0024<figref idref="DRAWINGS">FIG. 4</figref> illustrates a star-configuration interconnection that can be formed between several individual items of DSD equipment;

0025<figref idref="DRAWINGS">FIG. 5</figref> schematically illustrates an audio data transmission system according to an embodiment of the present invention;

0026<figref idref="DRAWINGS">FIG. 6</figref> schematically illustrates how the 64 F_saudio sample clock signal is transmitted in parallel with the DSD audio data along different signal pairs of the category 5 cable;

0027<figref idref="DRAWINGS">FIG. 7</figref> schematically illustrates reception of the high frequency audio sample clock in parallel with reception of the DSD audio data signal;

0028<figref idref="DRAWINGS">FIG. 8</figref> schematically illustrates the signal path of the 64 Fs DSD sample clock signal;

0029<figref idref="DRAWINGS">FIG. 9</figref> depicts an embodiment of the invention in which the synchronisation of the physical layer device is adjusted such that it is an exact multiple of the audio sample clock frequency;

0030<figref idref="DRAWINGS">FIG. 10</figref> schematically illustrates a point-to-point audio device link in which one device acts as a clock master whilst the other device acts as a clock slave;

0031<figref idref="DRAWINGS">FIG. 11</figref> is a flow chart which illustrates the sequence of events followed to establish a synchronised link between the master device and the slave device of <figref idref="DRAWINGS">FIG. 8</figref>;

0032<figref idref="DRAWINGS">FIG. 12</figref> schematically illustrates an apparatus in which multiple parallel links are used between two pieces of audio equipment in order to achieve a higher channel count than that achievable via a single point-to-point link;

0033<figref idref="DRAWINGS">FIG. 13</figref> is a flow chart illustrating how the local clock signals F_s(A) and F_s(B) are employed to ensure that the outputs of two receivers are kept synchronous;

0034<figref idref="DRAWINGS">FIG. 14</figref> schematically illustrates how audio data buffering is performed in the transmitter;

0035<figref idref="DRAWINGS">FIG. 15</figref> schematically illustrates how audio data buffering is performed at the receiver;

0036<figref idref="DRAWINGS">FIG. 16</figref> schematically illustrates the data structure corresponding to a standard Ethernet frame;

0037<figref idref="DRAWINGS">FIG. 17</figref> shows the structure of an audio data frame according to an embodiment of the present invention;

0038<figref idref="DRAWINGS">FIG. 18A</figref> shows the audio data frame format arranged as 384*4-byte data words;

0039<figref idref="DRAWINGS">FIG. 18B</figref> schematically illustrates a 24 DSD channel frame format in which each frame comprises 368 data words including 352 DSD samples for 24 channels plus 88 bytes of auxiliary data;

0040<figref idref="DRAWINGS">FIG. 19</figref> shows the control data format arranged as 26*4-byte data words;

0041<figref idref="DRAWINGS">FIG. 20</figref> schematically illustrates the structure of each of the three 16-bit frame format field sections corresponding to the frame format of <figref idref="DRAWINGS">FIG. 18B</figref>;

0042<figref idref="DRAWINGS">FIG. 21</figref> schematically illustrates the three 4-nibble sections of the frame format ID containing a set of data entries to be processed at the receiver;

0043<figref idref="DRAWINGS">FIG. 22</figref> schematically illustrates the format of the 32-bit data block corresponding to the 24 DSD channel frame format of <figref idref="DRAWINGS">FIG. 18B</figref>;

0044<figref idref="DRAWINGS">FIG. 23A</figref> schematically illustrates how six parity bits P<b>0</b> to P<b>5</b> are generated from 24 audio data bits and the two auxiliary data bits;

0045<figref idref="DRAWINGS">FIG. 23B</figref> schematically illustrates how a syndrome is calculated by performing XNOR operations on the received data elements;

0046<figref idref="DRAWINGS">FIG. 24</figref> is a table showing a the composition of a stream of nibbles from the interleaver for the 24 DSD channel frame format of <figref idref="DRAWINGS">FIG. 18B</figref>;

0047<figref idref="DRAWINGS">FIG. 25</figref> schematically illustrates the protocol layers of the MAC-DSD protocol for the particular example embodiment using the 24 DSD channel frame format;

0048<figref idref="DRAWINGS">FIG. 26A</figref> schematically illustrates the AES3 sub-frame format;

0049<figref idref="DRAWINGS">FIG. 26B</figref> schematically illustrates the sub-frame format for PCM transmission according to the present technique;

0050<figref idref="DRAWINGS">FIGS. 27A</figref> to D schematically illustrate how three different indications S, Z and V are <ul id="ul2S-d0e28500001" list-style="none"><li id="ul2S-d0e28500002-li00002"><ul id="ul2S-d0e28500002" list-style="none"><li id="ul2S-d0e28500002-p00051" num="00051"> multiplexed using the M-bit of <figref idref="DRAWINGS">FIG. 26B</figref>; </li></ul></li></ul>

0052<figref idref="DRAWINGS">FIGS. 28A</figref> to E schematically illustrates circumstances in which the S-bit takes precedence over the Z-bit in the M-bit of the sub-frame format according to <figref idref="DRAWINGS">FIG. 26B</figref>;

0053<figref idref="DRAWINGS">FIG. 29</figref> is a table 10 defining a frame type value index for a each of a number of different frame formats including frame types having different numbers of PCM samples per frame;

0054<figref idref="DRAWINGS">FIG. 30</figref> is a table specifying the information derivable from the flag bits of the frame format of <figref idref="DRAWINGS">FIG. 18B</figref>;

0055<figref idref="DRAWINGS">FIG. 31</figref> specifies how values for the two flag bits associated with the base clock are interpreted;

0056<figref idref="DRAWINGS">FIG. 32</figref> schematically illustrates how a multiplexed clock signal is formed in dependence upon a 64 Fs signal and a word clock signal;

0057<figref idref="DRAWINGS">FIG. 33</figref> schematically illustrates five consecutive DSD samples and their timing relationship with the local 64 Fs clock and the word clock;

0058<figref idref="DRAWINGS">FIG. 34</figref> schematically illustrates a MAC DSD transmitter adapted for transmission of both PCM and DSD data;

0059<figref idref="DRAWINGS">FIG. 35</figref> schematically illustrates a MAC DSD receiver adapted for reception of both PCM and DSD data;

0060<figref idref="DRAWINGS">FIG. 36</figref> schematically illustrates a system in which two sample-synchronous links are operated in parallel and in which the Fs/n sync is used to synchronise the parallel links;

0061<figref idref="DRAWINGS">FIG. 37</figref> schematically illustrates a measured difference in propagation delay between the two parallel links of <figref idref="DRAWINGS">FIG. 27</figref>;

0062<figref idref="DRAWINGS">FIG. 38</figref> is a schematic diagram showing auxiliary data routing by a MAC-DSD router;

0063<figref idref="DRAWINGS">FIG. 39</figref> is a schematic diagram showing a protocol by which auxiliary data is carried;

0064<figref idref="DRAWINGS">FIG. 40</figref> schematically illustrates a data structure of an auxiliary data frame;

0065<figref idref="DRAWINGS">FIGS. 41 and 42</figref> schematically illustrate the operation of an auxiliary data router in a data receive mode and a data send mode respectively;

0066<figref idref="DRAWINGS">FIGS. 43 and 44</figref> schematically illustrates a data scrambler and a complementary descrambler respectively;

0067<figref idref="DRAWINGS">FIG. 45</figref> schematically illustrates the generation of a carrier sense/receive data valid signal; and

0068<figref idref="DRAWINGS">FIG. 46</figref> is a schematic state diagram illustrating the use of an RMII lock function.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0069As described above, some known audio networking systems use the data link layer of Ethernet for transmission of uncompressed digital audio data at standard sampling frequencies of around 48 kHz. By way of contrast, embodiments of the present invention use the physical layer of Fast Ethernet to provide a point to point connection for transmission of high frequency (2.8224 MHz) digital audio data. The advantages of using the physical layer of Fast Ethernet for audio data transmission are that it offers a large bandwidth, has proven electromagnetic compatibility and has error detection functionality (cyclic redundancy checks) already in place. Use of the physical layer makes the logic easy to design and implement. There is no need to be concerned with hardware addressing and implementation of windowing protocols as would likely be required if the audio data were encoded using higher layer (e.g. MAC layer) technology. Furthermore at the physical layer level, Ethernet data transmission is robust and spectrum controlled so that electromagnetic emissions are low.

0070In order to explain the principles by which the present embodiments operate, the layered structure of network protocol architectures and the lower layers of the Ethernet architecture will be described in detail below.

0071<figref idref="DRAWINGS">FIG. 1</figref> shows the standard seven-layer Open Systems Interconnection (OSI) model for network protocol architectures. The model comprises an application layer <b>270</b>, a presentation layer <b>260</b>, a session layer <b>250</b>, a transport layer <b>240</b>, a network layer <b>230</b>, a data link layer <b>220</b>, and a physical layer <b>210</b>.

0072The application layer <b>270</b> provides a user interface, usually in the form of an application program, to a range of distributed information services on the network. The services provided by this layer include file transfer, access and management, as well as general document and message interchange services such as electronic mail.

0073The presentation layer <b>260</b> is concerned with the representation of data during transfer between two communicating application processes. It selects an appropriate transfer syntax to be used during a transaction, so that the structure of the messages being exchanged between two application entities is maintained. The presentation layer <b>260</b> also manages data encryption and data compression.

0074The session layer <b>250</b> establishes sessions between communicating applications on communicating network nodes. It may optionally provide interaction management during two-way alternate i.e. half-duplex (rather than two-way simultaneous i.e. full-duplex) data exchange. Further optional features provided by this layer are synchronisation for lengthy network transactions and exception reporting.

0075The transport layer <b>240</b> acts as an interface between the higher application-oriented layers (session <b>250</b>, presentation <b>260</b> and application <b>270</b> layers) and the underlying network-dependent protocol layers <b>210</b>, <b>220</b>, <b>230</b>. The transport layer provides the session layer with a defined set of message transfer facilities. It offers a number of classes of services appropriate to different types of network, ranging from class 0 which provides basic connection establishment to class 4 which provides full error control and flow control.

0076The lowest three layers (network <b>230</b>, data link <b>220</b> and physical layers <b>210</b>) of the OSI model are all network dependent. The network layer <b>230</b> is responsible for establishing and clearing a connection between two transport layer protocol entities and it supports network routing and addressing. The data link layer <b>220</b> provides the network layer with a reliable information transfer facility and is responsible for such functions as error detection and message retransmission. Typically both a connectionless and a connection-oriented service is provided. The connectionless service simply discards received frames in which an error is detected whereas a connection-oriented service aims to provide an error-free information transfer facility. Finally, the physical layer <b>210</b> provides the data link layer <b>220</b> with a means of transmitting a serial bit stream between two pieces of equipment. It converts the data into the stream of electric or analogue pulses that will actually cross the transmission medium and it oversees the transmission of data.

0077Ethernet is a local area network (LAN) technology, which uses a simple or branching bus-like connection line. The transmission medium in an Ethernet network is formed from one or more continuous lines of cable linked by hubs. Network devices are connected to the cable and they compete for network access using a Carrier Sensing Multiple Access with Collision Detection (CSMA/CD) protocol. According to the CSMA/CD protocol, all client devices monitor the transmission medium and wait until the transmission line is available before transmitting any messages. If two network nodes try to transmit messages at the same time, a collision occurs. The client devices then stop, wait for a random time interval and attempt to transmit again.

0078Standard Ethernet systems known as 10BASE-T systems provide transmission speeds up to 10 Mega bits per second (Mbps) whereas so-called “Fast Ethernet” (or 100BASE-T) systems provide transmission speeds of up to 100 Mbps. Further higher performance systems are available such as so-called “Gigabit Ethernet”. Fast Ethernet uses the same wiring systems, Media Access Control (MAC) method and frame methods as 10BASE-T Ethernet. The embodiments may use any of these systems.

0079Ethernet systems may use twisted pair cabling or an optical fibre connection. Twisted pair is standard copper wire that is typically used to connect computers to a telephone link. To reduce cross-talk or electromagnetic induction between pairs of wires, two or more insulated wires are twisted around each other. The twisting reduces the effective radiating area of the cable because electromagnetic effects of alternate twists tend to cancel at distances greater than the twist pitch. Each connection on twisted pair requires two wires. If the twisted pair is enclosed by a shield that functions as a ground it is known as shielded twisted pair (STP). Standard twisted pair cabling is known as unshielded twisted pair (UTP).

0080In Fast Ethernet systems the segment length for twisted pair cable segments is set to a maximum of 100 m to ensure that signal round-trip timing specifications are met. The problem with Fast Ethernet is how to achieve a data transfer rate of 100 Mbit/s over unshielded twisted-pair cable (UTP). In practice there are two standards that can be used to achieve this, one of which (100BASE-4T) uses voice-grade category 3 cable and another (100BASE-X) which uses either high-quality category 5 UTP cable, shielded twisted-pair cable (100BASE-TX) or optical fibre (100BASE-FX). In the 100BASE-X system each type of transmission medium requires a different Physical Medium Dependent (PMD) sublayer. Category 5 UTP comprises 4 signal pairs, two pairs of which are typically utilised for Ethernet i.e. one signal pair for clock transmit and receive and one signal pair for data transmit and receive. This leaves two unused signal pairs.

0081The sub-layers of the Ethernet physical layer and data link layer are shown alongside the seven layer OSI model.

0082The data link layer <b>220</b> comprises the Media Access Control (MAC) layer <b>224</b> and the Logical Link Control (LLC) layer <b>222</b>. The physical layer comprises a reconciliation sub-layer <b>219</b>, a Media Independent Interface (MII) <b>218</b>, a physical coding sub-layer <b>216</b>, a physical medium attachment sub-layer <b>214</b>, a physical medium dependent sub-layer <b>212</b> and a Medium Dependent Interface (MDI) <b>211</b>.

0083The MAC sub-layer <b>224</b> performs the two main functions of data encapsulation and media access management. The data encapsulation functionality includes data framing, handling of source and destination addresses and detection of physical medium transmission errors. The medium access management functionality includes medium allocation (collision avoidance) and contention resolution (collision handling).

0084The MAC sub-layer <b>224</b> can operate either in half-duplex mode or in full duplex mode. In half-duplex mode, network nodes contend for use of the physical medium using multiple access (CSMA/CD) algorithms. The full duplex mode allows for simultaneous transmission and reception without interference. For the full duplex mode to be used three conditions must first be satisfied. Firstly, the physical medium must be capable of supporting simultaneous transmission and reception without interference. Secondly there must be exactly two nodes on the local area network so that the physical medium is treated as a full duplex point-to-point link between the nodes. The use of CSMA/CD algorithms is unnecessary in this full duplex case because there is no contention for use of a shared medium. The third condition is that both network nodes must be configured to use full duplex operation.

0085The Logical Link Control (LLC) layer <b>222</b> performs error-checking functions on data frames and manages links between communicating network nodes.

0086The Reconciliation <b>219</b> sublayer maps the signal set provided at the Media Independent Interface <b>218</b> to the Physical Coding Sublayer <b>216</b>.

0087The Physical Coding Sub-layer (PCS) <b>216</b> provides a uniform interface to the Reconciliation sub-layer for all 100BASE-TX physical layer entity (PHY) implementations. The PCS <b>216</b> provides all services required by the MII including: encoding of MII 4-bit “data nibbles” to 5-bit code groups (and also decoding from 5-bit to data nibbles); generation of carrier sense and collision detect indications; serialisation of code-groups for transmission on the underlying PMA sub-layer <b>214</b> (and de-serialisation of code groups on reception from the PMA <b>214</b>); and mapping of transmit, receive, carrier sense and collision detection between the MII <b>218</b> and the underlying PMA <b>214</b>.

0088The Physical Medium Attachment (PMA) sub-layer <b>214</b> provides a medium-independent means for the PCS to support the use of a range of physical media. The 100BASE-TX PMA performs the functions of: mapping of transmit and receive code-bits between the underlying Physical Medium Dependent (PMD) sub-layer <b>212</b> and the PCS <b>216</b>; and generating a control signal indicating the availability of the PMD <b>212</b> to a PCS <b>216</b>. The PMA sub-layer <b>214</b> may optionally: generate indications of carrier errors from the underlying PMD sub-layer <b>212</b>; sense receive channel failures; and transmit far-end fault indications.

0089The PMD sub-layer <b>212</b> is effectively a set of signalling standards that define 125 Mbit/s full duplex signalling systems, which accommodate multi-mode optical fibre (F), shielded twisted pair (STP) and unshielded twisted pair (UTP) wiring.

0090The purpose of the Media Independent Interface (MII) <b>218</b> is to provide a simple interconnection between the MAC sub-layers <b>222</b>, <b>224</b> and the physical layer entities (PHYs) for data transfer at 10 Mbit/s and 100 Mbit/s. The functionality is identical at both data rates, as are the signal timing relationships. The only difference between 10 Mbit/s and 100 Mbit/s operation is the nominal clock frequency. The MII <b>218</b> is used to provide media independence for various forms of unshielded twisted-pair wiring, shielded twisted-pair wiring, fibre optic cabling and potentially other media, so that identical MACs may be used with any of these media. The MII <b>218</b> maximises media independence by cleanly separating the Data Link Layer <b>220</b> and the Physical Layer <b>210</b> of the OSI seven-layer reference model. The data and delimiters of the MII <b>218</b> are synchronous to clock references and the MII uses Low Voltage Transistor-Transistor Logic (LVTTL) signal levels compatible with common integrated circuit processes. The MII <b>218</b> provides independent 4-bit wide data-transmit and data-receive paths and full duplex operation. Each direction of data transfer is serviced with 7 signals: a 4-bit data bundle, a 1-bit delimiter signal, a 1-bit error signal and a 1-bit clock signal.

0091<figref idref="DRAWINGS">FIG. 2</figref> illustrates a known system for signal transfer in Direct Stream Digital systems. The apparatus <b>300</b> comprises an analogue-to-digital/digital-to-analogue (ADC/DAC) converter <b>310</b> connected to a DSD multi-channel recorder <b>320</b>. The connection comprises two separate cables: a first cable <b>315</b> is an optical fibre carrying 8 channels (about 22.6 Mbit/s) of DSD audio data and a second cable <b>325</b> carries the high frequency sample clock. It is standard studio practice to use separate cables for the audio data and the sample clock.

0092<figref idref="DRAWINGS">FIG. 3</figref> schematically illustrates a DSD interconnection according to an embodiment of the present invention. In this arrangement <b>400</b>, a single cable <b>405</b> is used to connect a multi-channel ACD/DAC <b>410</b> to a DSD multi-channel recorder <b>420</b>. The cable <b>405</b> is a category 5 unshielded twisted pair cable. This cable has four signal pairs, two pairs of which are used to transmit and receive audio data, encoded using Ethernet physical layer technology and the remaining two pairs of which are used to convey a DSD sample clock in both directions across the link (see Table 1 below). The clock signal and the audio data signal are conditioned to decrease the likelihood of interference between the two signals degrading the quality of the clock signal. The clock signal is used to synchronise a phase locked loop (PLL) in the receiving device, which in turn may be used as a sample clock for ADCs and DACs. Any jitter on the sample clock is undesirable since it will manifest itself as distortion on the reproduced analogue audio output. The audio signal is intrinsically digital and consequently more robust to degradation than the clock signal. A packet data transmission system such as Ethernet is capable of carrying the DSD audio data. In this particular embodiment, the physical layer of Fast Ethernet (100BASE-TX) is used to provide a channel bit-rate of 100 Mbit/s which accommodates audio data from 32 DSD channels on a single link. In an alternative embodiment the 100 Mbit/s link is used to support 24 DSD channels on a single link.

0093Ethernet is an asynchronous data link and is thus inherently unsuitable for transmission of the high-integrity, 64 F_saudio clock signal. For this reason the audio sample clock is transmitted on separate signal pairs of the category 5 UTP cable.

0094The single cable connection in <figref idref="DRAWINGS">FIG. 3</figref> is fundamentally a point to point link directly connecting the two audio devices. It uses a special “crossover” category 5 cable that is wired to reverse the input/output connections. In this case a custom made crossover cable is required because conventional crossover cables such as those used for office networking do not reverse the two spare signal pair connections used in this embodiment for transmission of the audio sample clock.

0095In alternative embodiments of the invention, such as that illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, more complex interconnections can be formed between several individual items of DSD equipment. The apparatus illustrated in <figref idref="DRAWINGS">FIG. 4</figref> comprises a star-configuration DSD router <b>430</b>, a multi-channel ADC/DAC <b>440</b>, a DSD mixer <b>450</b> and a DSD multi-channel recorder <b>460</b>. Three point-to-point links <b>445</b>, <b>455</b> and <b>465</b> are connected together via the central DSD router <b>430</b>. Unlike the connection of <figref idref="DRAWINGS">FIG. 3</figref>, standard category 5 cable can be used for each of the three connections in this star configuration. This is because the port connections on the router are internally reversed such that signal outputs of one device connect to signal inputs of another device.

0096The router <b>430</b> comprises a number of signal transceivers, each transceiver comprising a data clock transmitter (described below with reference to <figref idref="DRAWINGS">FIG. 6</figref>) and a data and clock receiver (described below with reference to <figref idref="DRAWINGS">FIG. 7</figref>). Switching and routing functions are carried out by a crosspoint switch (not shown) acting on the recovered clock and streamed audio data. In other words, signals are not transferred across the router in packetised form.

0097The cable <b>405</b> linking the transmitter device to the receiver device in <figref idref="DRAWINGS">FIG. 3</figref> is terminated with 8-terminal RJ45 plugs and both transmitter and receiver devices are fitted with RJ45 sockets. The table below specifies the setting of the RJ45 socket terminal connections for the audio devices of <figref idref="DRAWINGS">FIG. 3</figref> and for the star-configuration router devices of <figref idref="DRAWINGS">FIG. 4</figref>. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="49PT" align="center" /><colspec colname="2" colwidth="70PT" align="left" /><colspec colname="3" colwidth="98PT" align="left" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 1</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>Pin</entry><entry>Function</entry><entry>Function</entry></row><row><entry>number</entry><entry>(audio device)</entry><entry>(star-configuration router)</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>1</entry><entry>Data transmit +</entry><entry>Data receive +</entry></row><row><entry>2</entry><entry>Data transmit −</entry><entry>Data receive −</entry></row><row><entry>3</entry><entry>Data receive −</entry><entry>Data transmit −</entry></row><row><entry>4</entry><entry>Clock transmit +</entry><entry>Clock receive +</entry></row><row><entry>5</entry><entry>Clock transmit −</entry><entry>Clock receive −</entry></row><row><entry>6</entry><entry>Data receive +</entry><entry>Data transmit +</entry></row><row><entry>7</entry><entry>Clock receive −</entry><entry>Clock transmit −</entry></row><row><entry>8</entry><entry>Clock receive +</entry><entry>Clock transmit +</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0098<figref idref="DRAWINGS">FIG. 5</figref> schematically illustrates an audio data transmission system according to an embodiment of the present invention. The apparatus <b>500</b> comprises a first audio processing device <b>510</b> and a second audio processing device <b>520</b> linked by a category 5 unshielded twisted pair cable <b>515</b>. Each audio processing device comprises a Field Programmable Gate Array (FPGA) <b>512</b>, a physical layer interface (PHY) <b>514</b>, a transformer <b>516</b> and an RJ45 8-pin connector <b>518</b>. The FPGA <b>512</b> provides a Multichannel Audio Connection for DSD (MAC-DSD).

00991-bit 64 Fs direct stream digital data is supplied from the audio device to the FPGA <b>512</b>. During a transmission operation the FPGA <b>512</b> performs audio data buffering and framing operations whereas during data reception the FPGA extracts data from the framed structure and converts it back to a DSD stream. The FPGA performs transmission and reception concurrently, implementing a full-duplex audio connection. The format of the data frames will be described in detail below with reference to <figref idref="DRAWINGS">FIGS. 15 and 16</figref>. The PHY device <b>514</b> performs physical layer coding of the framed audio data, implements spectrum control processing and has line drivers that amplify the current and hence the power of the signal to increase its robustness during transmission. The PHY device <b>514</b> effectively implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) and Physical Medium Dependent (PMD) sub-layers of the physical layer <b>210</b>. In this embodiment the PHY device <b>514</b> is an Intel™ LXT972a component and it operates in full duplex mode with no auto-negotiation and with data scrambling on. The transformer <b>516</b> outputs the data for transmission on the category 5 cable <b>515</b>. On reception the transformer <b>516</b> receives the signal prior to physical layer processing. The interface between the FPGA <b>512</b> and the PHY device <b>514</b> is a Media Independent Interface (MII). Thus the FPGA replaces the network address handling Media Access Controller (MAC) of the conventional Ethernet system. Multiple sample rates are supported and the system is able to accommodate potential developments towards higher DSD sample rates. Any change to the audio sample rate affects the way audio data streams are packed into data frames and this functionality is determined by circuitry in the FGPA <b>512</b>. Provided that the physical layer link has sufficient bandwidth changes in the audio sample rate have no effect on the PHY device <b>514</b>.

0100<figref idref="DRAWINGS">FIG. 6</figref> schematically illustrates how the 64 F_saudio sample clock signal is transmitted in parallel with the DSD audio data along different signal pairs of the category 5 cable. As in <figref idref="DRAWINGS">FIG. 5</figref>, the FPGA <b>512</b>, the PHY device <b>514</b> and the transformer <b>516</b> perform the audio data signal processing prior to its transmission on two signal pairs of the Category 5 UTP cable <b>515</b>. The 64 F_saudio sample clock is supplied as input both to the FPGA, which performs framing and buffering, and to a low pass filter <b>552</b>. The low-pass filter serves to reduce electro-magnetic emissions during transmission of the clock signal. The output of the low-pass filter <b>552</b> is supplied as input to a differential line driver <b>554</b> and is subsequently fed through a 10BASE-T type Ethernet transformer <b>556</b>. The clock signal is fed via the RJ45 connector <b>518</b> onto a signal pair on the category 5 UTP cable <b>515</b> where it is transmitted in parallel with the audio data. Transmission of the audio sample clock signal is important since it enables the FPGA of the receiving device to resynchronise the received audio data and thus to reconstitute the DSD bitstreams. The category 5 UTP cable used in this embodiment of the invention has a characteristic impedance of 100 Ohms. Alternative embodiments may use screened twisted pair cable which gives enhanced electromagnetic compatibility (EMC) performance. Further alternative cable types that may be used include category 5e cable (for data rates of up to 250 Mbit/s), category 6 cable (suitable for Gigabit Ethernet or category 7 cable which allows even higher data transmission rates.

0101The FPGA is only one solution to achieve the functionality required at the transmitter and receiver. Software-controlled general purpose microprocessors may of course be used, in which case the software could be provided by a storage medium (e.g. a read-only memory, flash memory, magnetic disk or optical disk) or a transmission medium (e.g. a network or the internet).

0102<figref idref="DRAWINGS">FIG. 7</figref> schematically illustrates reception of the high frequency audio sample clock in parallel with reception of the DSD audio data signal. The parallel signals are received from the cable <b>515</b> at the RJ45 connector <b>522</b> of the receiving device. The DSD audio signal is received by a transformer <b>524</b> and is then supplied to a physical layer interface <b>526</b> followed by an FPGA <b>528</b> which unframes the data and produces a DSD bit stream. The DSD audio stream is output from the FGPA according to a 64 Fs clock signal <b>529</b> derived from the local phase locked loop of the receiving device.

0103The received audio clock signal is supplied to a transformer <b>562</b> on arrival at the receiving device. The output of the transformer is supplied to a high pass filter <b>563</b> and then to a low pass filter <b>564</b>, which is of the same type as the low pass filter <b>552</b> in the transmitting device. The low pass filter <b>564</b> in the receiver serves to remove any high frequency interference in the received signal, derived either from the audio data signal, which it travelled adjacent to along the cable <b>515</b>, or from external sources. The output from the low-pass filter is supplied to a comparator <b>568</b> where it is converted to a logic signal. The logic signal from the comparator is used to drive a local phase locked loop (PLL) circuit. A phase locked loop (PLL) is an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. In this case the received high frequency clock signal is the reference signal. The PLL circuit generates a local audio reference clock which is used for reproduction of the DSD audio data.

0104<figref idref="DRAWINGS">FIG. 8</figref> schematically illustrates the signal path of the 64 Fs DSD sample clock signal. As explained above, the DSD sample clock is transmitted in both directions via dedicated differential signal pairs in the category 5 UTP interconnection cable <b>515</b>. The sequence of processing operations performed on the high frequency (64 F_s) clock signal will now be described with reference to <figref idref="DRAWINGS">FIG. 8</figref>. Special analogue conditioning of the sample clock signal is performed to facilitate its transmission on a signal pair of the UTP cable adjacent to the asynchronous data signal. The analogue conditioning reduces the severity of electromagnetic interference effects from the asynchronous data signal (or from external sources) which compromise the integrity of the high frequency sample clock signal. As schematically illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, the sample clock processing that occurs in the clock master system involves the low pass filter <b>552</b>, the differential line driver <b>554</b> and the transformer <b>556</b>. The sample clock processing chain in the clock slave system involves the transformer <b>562</b>, a high pass filter <b>563</b> and the comparator <b>568</b>.

0105The input to the low pass filter <b>552</b> of the clock master is a 2.8224 MHz (64 Fs) logic signal <b>551</b>. The frequency tolerance of this signal is in accordance with the Grade 2 specification defined by the standards document AES11-1997. Accordingly the sample clock has a long-term frequency stability of +/−10 parts per million (ppm), with an external synchronisation range of +/−50 ppm. The duty cycle of the sample clock in the range 40-60% and a Low Voltage Transistor-Transistor Logic (LVTTL) logic signal is used.

0106The 64 Fs logic clock signal <b>569</b> output by the comparator <b>568</b> of the clock slave system is also a logic signal of frequency 2.8224 MHz (64 Fs). This clock output signal <b>569</b> is not used to synchronise any digital audio components directly because the link <b>515</b> characteristics may well have introduced substantial jitter and asymmetry to the clock signal. Rather, the clock output signal is used exclusively to synchronise an edge-triggered phase locked loop (PLL) in the receiver system. The clock output signal <b>569</b> is carefully routed within the receiver to ensure that any noise and jitter on the signal does not couple into other high-quality clock signals. The PLL circuit (not shown) of the clock slave system is used to generate high quality audio clock signals for distribution throughout the receiving system.

0107The low pass filters <b>552</b>, <b>564</b> in both the transmitting (clock master) system and receiving (clock slave) system are second-order low-pass Butterworth filters, each having a cut-off frequency fc=2.9 MHz.

0108The transmitter low-pass filter <b>552</b> attenuates high-frequency components of the clock signal that may otherwise cause interference with the adjacent audio data signals in the cable or cause excessive RF emissions from the cable. The receiver low-pass filter <b>564</b> on the other hand, removes high-frequency interference from the clock signal induced by either the adjacent high-frequency data signals or by external sources.

0109The differential line driver <b>554</b> located in the transmitter generates a symmetrical output signal of differential peak-peak voltage 1.5V-2.5V into 100 Ohms (the impedance of the category 5 UTP link).

0110The transformers <b>556</b>, <b>562</b> in both transmitter and receiver are 10Base-T Ethernet transformers having a 1:1 turns ratio and line-side common mode chokes.

0111The high-pass filter <b>563</b> in the receiver is a first-order high pass filter having a cut-off frequency fc=500 Hz. This filter removes low-frequency interference from mains supply sources, and blocks DC offset. This filter is implemented with a simple resistance-capacitance (R-C) combination.

0112The comparator <b>568</b> in the receiver converts the filtered analogue clock signal from the low pass filter <b>564</b> into a logic signal. In order to avoid or reduce noise-induced multiple edges a 2% hysteresis is used.

0113<figref idref="DRAWINGS">FIG. 9</figref> shows an embodiment of the invention in which the synchronisation of the physical layer device is adjusted so it is an exact multiple (9*64 F_s) of the audio sample clock frequency 64 F_s. The Ethernet standard specifies a 25 MHz symbol rate for data transmission. It is conceivable that transmission of the 2.8224 MHz sample clock along the same category 5 UTP as a asynchronous 25 Mhz audio data signal could result in undesirable degradation of the audio clock. Synchronising the audio data transmission with the sample clock may help to reduce the degradation of the high-quality audio clock signal. The apparatus shown in <figref idref="DRAWINGS">FIG. 9</figref> comprises a multiplier <b>572</b> which takes a 64 F_sclock signal as input and up-converts it in frequency by a factor of 9 using a phase locked loop. The output from the ×9 multiplier <b>572</b> is input to the PHY device of the transmitter so that a 576 F_s(25.4016 MHz) audio data signal is generated. Accordingly, this embodiment uses a 25.4016 MHz symbol rate for audio data transmission rather than the standard 25 MHz Ethernet symbol rate. As a consequence of the increased symbol rate the channel bit rate increases from 100 Mbit/s to 101.6064 Mbit/s.

0114Therefore, this embodiment of the invention can potentially reduce degradation of the audio clock signal but this is at the expense of removing compatibility with the 25 MHz symbol rate of standard Ethernet systems.

0115<figref idref="DRAWINGS">FIG. 10</figref> schematically illustrates a point-to-point audio link in which one device acts as a clock master <b>600</b>M whilst the other device acts as a clock slave <b>600</b>S. Each of the audio processing devices comprises a clock source PLL <b>602</b>M/<b>602</b>S, a clock receiver (Rx) <b>604</b>M/<b>604</b>S, a lock detect module <b>606</b>M/<b>606</b>S, a clock transmitter (Tx) <b>608</b>M/<b>608</b>S, an audio input/output (I/O) system <b>610</b>M/<b>610</b>S and a switch <b>612</b>M/<b>612</b>S. The suffix M denotes a component associated with the master device <b>600</b>M whereas the suffix S indicates a component associated with the slave device <b>600</b>S. DSD audio data passes along a UTP cable (not shown) which links the audio I/O system <b>610</b>M of the master with that of the slave <b>610</b>S.

0116The category 5 UTP cable provides independent connections such that under normal operating conditions clock signals are transferred in both directions between two audio devices. However in an active link one of the devices must be designated clock master <b>600</b>M and the other device is thus designated the clock slave <b>600</b>S. The clock master transmitter <b>608</b>M sends an audio clock signal <b>605</b>M to the clock receiver <b>604</b>S of the clock slave. The master clock signal <b>605</b>M is used by the phase locked loop <b>602</b>S of the slave to produce a synchronisation signal that is supplied to the slave audio I/O system <b>610</b>S. The audio clock signal <b>605</b>S that is sent from the slave transmitter <b>608</b>S to the clock receiver of the master <b>604</b>M is not supplied to the phase locked loop <b>602</b>M of the master because the switch <b>612</b>M of the master is left in an open state. However the slave clock signal <b>605</b>S is compared with the local master clock by the lock detect module <b>606</b>M of the master device to detect synchronisation of the remote slave system.

0117<figref idref="DRAWINGS">FIG. 11</figref> is a flow chart which illustrates the sequence of events followed to establish a synchronised link between the master device and the slave device of <figref idref="DRAWINGS">FIG. 10</figref>.

0118At stage <b>620</b> the transceiver of device B <b>600</b>S is set to slave mode and the clock transmitter <b>608</b>S is temporarily disabled (until the link is established and a lock state has been achieved). This acts as a safeguard against two slave devices attempting to synchronise each other with unpredictable consequences.

0119At stage <b>630</b> the UTP cable is used to physically connect the master device <b>600</b>M to the slave device <b>600</b>S thereby establishing the link. On connection of the cable both the master device <b>600</b>M and the slave device <b>600</b>S detect that the link is currently valid. The master device begins transmitting the clock signal <b>605</b>M but the slave device's clock transmitter <b>608</b> is temporarily disabled.

0120At stage <b>640</b> the slave device's clock receiver <b>604</b>S detects the incoming master clock signal <b>605</b>M and feeds this to the local slave phase locked loop circuit <b>602</b>S which locks to the incoming master clock signal.

0121At stage <b>650</b> the slave device <b>600</b>S detects the lock condition by comparing its local system clock with the incoming master clock signal <b>605</b>M via the lock detect module <b>606</b>S. Closing the switch <b>612</b>S completes the circuit between the slave PLL <b>602</b>S the slave clock receiver <b>604</b>S and the slave lock detect module <b>606</b>S and thus enables lock detection. Once the slave lock detect module <b>606</b>S signals that lock with the master clock has been established, the slave clock transmitter <b>608</b>S is switched from the disabled state to an enabled state and the slave device <b>600</b>S audio buffers (located in the audio I/O system <b>610</b>S) are reset.

0122At stage <b>660</b> the master device clock receiver <b>604</b>M receives the echoed clock signal from the recently enabled slave clock transmitter <b>608</b>S and checks the phase of this echoed signal to verify that the slave device has synchronised correctly with the master clock signal <b>605</b>M. If synchronisation has not been correctly established then audio transmission is not enabled.

0123At stage <b>670</b>, having established that the slave device is correctly synchronised the master device resets its audio buffers (located in the audio I/O system <b>610</b>M) and enables audio data transmission, whereupon framed DSD audio data is sent along the UTP cable linking master and slave devices.

0124The flow chart of <figref idref="DRAWINGS">FIG. 11</figref> describes the standard process of establishing synchronisation between the master device and the slave device. However, it may be the case that an attempt is made to establish a link between two audio devices, both of which have been set to slave mode. In this event, the clock transmitters of both devices are disabled at the point where the devices detect a valid data link and an indication is made to the operator that the link is not synchronised. The link conditions are indicated to the user via LED status indicators (not shown) located adjacent to the RJ45 cable connection ports. Table 2 below gives an LED status for each of a number of possible link conditions. In particular a red or yellow LED “on” status corresponds to a clock synchronisation failure of the type that would be encountered during an attempt to link two slave mode audio devices. <tables id="TABLE-US-00002" num="2"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="56PT" align="left" /><colspec colname="2" colwidth="161PT" align="left" /><thead><row><entry namest="1" nameend="2" align="center">TABLE 2</entry></row><row><entry /></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row><row><entry>LED status</entry><entry>Condition</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>No LED on</entry><entry>No Ethernet PHY connection detected</entry></row><row><entry>Red (or yellow)</entry><entry>Ethernet PHY connection detected, but clock</entry></row><row><entry>LED on</entry><entry>synchronisation failed/not present/not locked.</entry></row><row><entry /><entry>Audio transfer inhibited</entry></row><row><entry>Green LED on</entry><entry>Ethernet PHY connection detected, slave device</entry></row><row><entry /><entry>has locked to master device clock, and link is active</entry></row><row><entry>Both LEDs on</entry><entry>(illegal indication)</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0125<figref idref="DRAWINGS">FIG. 12</figref> schematically illustrates an apparatus in which multiple parallel links are used between two pieces of audio equipment. Use of multiple links means a higher channel count is achieved than that achievable via a single point-to-point link. In this case two links are used to provide a total of 64 channels. A transmitter device <b>700</b>A comprises a first transmitter <b>702</b>, a second transmitter <b>704</b> and a clock generator <b>706</b>. A receiver device <b>700</b>B comprises a first receiver <b>712</b>, a second receiver <b>714</b> and a clock generator <b>716</b>. A first category 5 UTP cable <b>721</b> carries audio data channels <b>1</b> to <b>32</b> (or <b>1</b> to <b>24</b>) and links the first transmitter <b>702</b> to the first receiver <b>712</b>. A second category 5 UTP cable <b>723</b> carries audio data channels <b>33</b> to <b>64</b> (or <b>25</b> to <b>48</b>) and links the second transmitter <b>704</b> to the second receiver <b>714</b>.

0126When operating the apparatus of <figref idref="DRAWINGS">FIG. 12</figref>, it is necessary to ensure that the DSD audio data streams output by the first receiver <b>712</b> are sample-synchronised with the DSD audio data streams output by the second receiver <b>714</b> i.e. the samples from channels <b>1</b> to <b>32</b> (or <b>1</b> to <b>24</b>) are synchronised with the samples from channels <b>33</b> to <b>64</b> (or <b>25</b> to <b>48</b>). The transmit and receive latencies of the PHY devices in the transmitters <b>702</b>, <b>704</b> and in the receivers <b>712</b>, <b>714</b> mean that it is possible that the output of receivers <b>712</b>, <b>714</b> could slip out of synchronisation by more than one DSD audio sample period (3.543×10⁻⁷seconds). Manufacturer specifications for commonly used PHY devices indicate that combined transmit and receive latencies of the PHY devices could vary by up to 6×10⁻⁸seconds so that slippage of one DSD sample between receivers is conceivable. Any differences in the lengths of cables <b>721</b> and <b>723</b> will also affect synchronisation.

0127As shown in <figref idref="DRAWINGS">FIG. 12</figref>, the first and second transmitters <b>702</b>, <b>704</b> of the transmitting audio system <b>700</b>A use a common synchronisation reference clock signal F_s(A) running at F_s=44.1 kHz. Similarly the first and second receivers <b>712</b>, <b>714</b> of the receiving audio system <b>700</b>B use a common synchronisation reference clock F_s(B) running at F_s=44.1 kHz. These two 44.1 kHz synchronisation clock signals F_s(A) and F_s(B) have identical frequencies both having been derived from a 64 Fs master clock signal, but their phases, being arbitrary, are unlikely to match. The arbitrary phases are due to F_s(A) and F_s(B) having been derived from the common 64 Fs clock via independent clock dividers. The flow chart of <figref idref="DRAWINGS">FIG. 13</figref> illustrates how the signals F_s(A) and F_s(B) are employed to ensure that the outputs of receivers <b>712</b> and <b>714</b> (which have derived their audio data from separate link cables <b>721</b> and <b>723</b> respectively) are kept synchronous.

0128At stage <b>730</b> of the flow chart of <figref idref="DRAWINGS">FIG. 13</figref>, a communication link between the transmitting system <b>700</b>A and the receiving system <b>700</b>B is established. Each of the two transmitters <b>702</b>, <b>704</b> awaits receipt of a clock edge from the local 44.1 kHz clock signal F_s(A) and then transmits the first audio frame. The data frame is packed such that the first DSD sample is input synchronously with the clock edge. The flow chart of <figref idref="DRAWINGS">FIG. 13</figref> relates to an embodiment in which there are 32 channels of DSD audio. As shall be described in detail below with reference to <figref idref="DRAWINGS">FIG. 18A</figref>, for the 32-channel system each frame comprises 384 data words and words <b>13</b> to <b>382</b> each contain a 1-bit DSD sample value for each of 32 channels (370 sample values per channel are contained in each frame). The first transmitter transmits the first audio frame corresponding to channels <b>1</b> to <b>32</b> whilst the second transmitter transmits the first audio frame corresponding to channels <b>33</b> to <b>64</b>. Since in this embodiment each frame contains 370 samples and there are 64 samples per Fs period, a coincident frame start (1^stDSD sample value output) and Fs-period start (Fs(A) clock edge) will occur every 370×64 samples. However, 370 and 64 have a common factor of 2 so a frame-start and Fs period-start occur together every (370*64)/2 samples i.e. every 32 frames. Accordingly, the 1^stDSD sample value of the frame will be output synchronously with the local F_s(A) clock edge for frames <b>1</b>, <b>33</b>, <b>65</b>, <b>97</b> . . . and so on. These particular frames have a specific bit flag in a “frame type” field (see <figref idref="DRAWINGS">FIG. 16</figref>) of the data frame set to one.

0129At stage <b>732</b> of the flow chart both the first receiver <b>712</b> and the second receiver <b>714</b> capture a phase count value Φ_j(j=1 or 2 corresponding to first and second receivers respectively) marking the point in time at which the first DSD sample value in the first received frame is ready for output. Note that at system start-up the receiver audio outputs are muted and transmitter audio outputs are only enabled once synchronisation of the 64 Fs sample clocks has been verified by the master device. The time at which the receiver is ready to output the first DSD sample value will depend on the time taken for the slave device to achieve phase lock with the 64 Fs clock signal of the master device. It will also depend on the setting of the threshold level of a FIFO buffer of the particular transmitter. Each receiver derives the phase count value Φ_jfrom a counter in the receiver which is clocked by the 64 F_slocal clock signal and reset by the 44.1 kHz signal F_s(B).

0130At stage <b>734</b>, a system controller (not shown) compares the phase count values, Φ₁and Φ₂, for each of the receivers and determines if they are identical. If Φ₁=Φ₂then the receivers are synchronised to within the same DSD sample period which is the desired condition. In this event the process proceeds to stage <b>738</b> where the audio outputs are unmuted. If however, Φ₁≠Φ₂at stage <b>734</b> then the process proceeds to stage <b>736</b> where the system controller adjusts the buffer read positions of the receivers in an attempt to achieve synchronisation. The receiver that synchronised with the 64 Fs master clock earliest (and hence received DSD audio data first) has its buffer read position adjusted to match the buffer read position of the latest synchronised receiver (which started to receive DSD data later). This buffer read position adjustment is equivalent to modification of the phase count values Φ_jsuch that they are both equal to the higher of the two compared phase counts. Only when synchronisation has been achieved i.e. when the phase count values of the receivers are identical will the audio outputs be enabled.

0131The phase count values of the receivers are cross-checked for every flagged frame (first frame and every following 32^ndframe) to ensure that synchronisation of the receivers is maintained. Frames are transmitted every 131.25 μs so that flagged frames occur approximately every 4.2 ms (32×131.25 μs). Any receiver synchronisation problem should be detectable and correctable within this 4.2 ms period. Stages <b>742</b>, <b>744</b>, <b>746</b>, of <figref idref="DRAWINGS">FIG. 13</figref> show the check that is performed by the system controller for every flagged frame. At stage <b>742</b> the controller checks the modified phase count value for the current flagged frame and compares it with the final (possibly modified) recorded phase count value for the previous flagged data frame i.e. frame X-<b>32</b>. If the phase count values match then the system continues with audio data transmission at stage <b>746</b>. If however the phase count values for the two flagged frames do not match, this indicates that the two receivers are not outputting the same audio sample value simultaneously and the process proceeds to stage <b>744</b> where the system controller initiates resetting of the data links in an attempt to restore proper synchronisation. When the data links are reset the receiver logic is put in a reset condition so that the process of stages <b>732</b> to <b>738</b> of <figref idref="DRAWINGS">FIG. 11</figref> is carried out. In alternative embodiments the data links are reset by adjustment of the buffer read positions, but in this case a buffer overrun/underrun would trigger a total reset of the link. Sample synchronisation slippage could occur, for example, due to a cable glitch.

0132For the alternative 24 DSD channel embodiment, as shall be described in detail below with reference to <figref idref="DRAWINGS">FIG. 18B</figref>, each frame comprises 368 data words and words <b>15</b> to <b>366</b> contain 352 DSD samples for 24 channels plus 88 bytes of auxiliary data. Each 32-bit sample comprises 1-bit from each of the 24 DSD channels, 2 bits of auxiliary data and 6 check-bits. Bit <b>0</b> of each sample corresponds to the first logical audio channel whereas bit <b>23</b> corresponds to the 24^thlogical audio channel. In this case the first transmitter transmits the first audio frame corresponding to channels <b>1</b> to <b>24</b> whilst the second transmitter transmits the first audio frame corresponding to channels <b>25</b> to <b>48</b>. Since in this embodiment each frame contains 352 samples and there are 64 samples per Fs period, a coincident frame start (1^stDSD sample value output) and Fs-period start (Fs(A) clock edge) will occur every 352×64 samples. However, 352 and 64 have a common factor of 32 so a frame-start and F_speriod-start occur together every (352*64)/32 samples i.e. every alternate frame. Accordingly, in the 24 DSD channel embodiment the 1^stDSD sample value of the frame will be output synchronously with the local F_s(A) clock edge for frames <b>1</b>, <b>3</b>, <b>5</b>, <b>7</b>, <b>9</b> . . . and so on. It follows that every alternate frame will be a flagged frame and the phase count values of the receivers will be cross-checked every alternate frame.

0133<figref idref="DRAWINGS">FIG. 14</figref> schematically illustrates how audio data buffering is performed in the transmitter. The buffering apparatus <b>800</b> comprises a First In First Out (FIFO) buffer <b>810</b> in series connection with a frame assembler <b>820</b>. In operation, 32 channels of Direct Stream Digital 1-bit sample data are continuously fed into the FIFO buffer at a rate of 64 Fs which corresponds to 90.3168 Mbit/s. When the occupation level of the FIFO buffer reaches a predetermined threshold level <b>815</b> a signal is generated by the system controller to initiate transmission of a new audio data frame. In response to this signal, the frame assembler assembles the frame preamble and headers, during which time incoming DSD samples continue to be buffered. As soon as the audio data payload assembly begins, the frame assembler starts to extract data from the FIFO. The rate at which data is extracted from the FIFO corresponds to the Ethernet transmission rate of 100 Mbit/s (or 101.6064 Mbit/s for embodiments in which the symbol rate is locked to 9*64 F_s). Since the FIFO is filling at a rate of 90.3168 Mbit/s and emptying at a rate of 100 Mbit/s the net buffer occupation level will steadily decrease during this period. The predetermined threshold level <b>815</b> is set in dependence upon the data input rate, the data output rate and the frame size (370 1-bit samples for 32 channels) so that the buffer occupation level will be almost, but not quite, zero at the end of each frame transmission i.e. data from the next frame for transmission is present in the buffer. The fact that the transmitter buffer <b>810</b> is not completely empty by the time the frame transmission ends breaks the rules of the MAC. Once the frame transmission is complete the FIFO occupation level will increase rapidly until the threshold level is reached whereupon the frame transmission cycle will repeat.

0134For a transmission system with an input data rate of 90.3168 Mbit/s, an output rate of 101.6064 Mbit/s and a (370 1-bit sample) (32 channel) frame capacity it can be shown that the minimum buffer size is 42 DSD samples and the corresponding minimum threshold level is 30 DSD samples. The audio latency introduce by this minimum size buffer is 14.9 μs (=42/64 Fs).

0135<figref idref="DRAWINGS">FIG. 15</figref> schematically illustrates how audio data buffering is performed at the receiver. The receiver buffering apparatus comprises a frame receiver <b>860</b> in series connection with a FIFO buffer <b>870</b>. Audio data arrives (via the category 5 UTP cable) in framed format at the frame receiver <b>860</b> at a rate of 100 Mbit/s (or 101.6064 Mbit/s for the 9*64 F_ssymbol rate). The frame receiver strips off the preamble and headers of each data frame and optionally performs a cyclic redundancy check (CRC) to verify the integrity of the received data. Unframed audio data is passed directly from the frame receiver <b>860</b> to the FIFO buffer <b>870</b>. Audio data extraction from the FIFO starts immediately since there is no threshold level set in the buffer at the receiver. This ensures that near-zero receiver latency is achieved. The audio data frames contain a cyclic redundancy check word (CRC). The CRC algorithm, check word location and scope are as defined in IEEEE802.3-2000 section 3.2.8. This 32-bit check word will generally detect any error within the frame. In known Ethernet systems a CRC is performed on each frame both at the transmitter and at the receiver. At the receiver complete frames are output only once the result of the CRC on that frame is determined. This results in substantial latency before the data is output at the receiver in known systems. According to the present technique, although the CRC check is still performed at the receiver, data is output from the buffer before the result of the CRC check is obtained. Error control is performed by decoding parity bits at a stage subsequent to data output at the receiver FIFO. In particular, error control is performed when data is extracted from the 32-bit data blocks prior to output as a 32 DSD channel audio stream. Unlike standard Ethernet systems, the MAC-DSD protocol according to the present technique does not support frame re-transmissions in case of an error, as this would require buffering of at least two 125 microsecond audio frames, increasing system latency to an unacceptable degree. Although the primary purpose of the IEEE802.3 CRC is to detect frame errors and thereby generate a retransmission request, the CRC is included for sake of compatibility. It will be appreciated that support for CRC-initiated MAC-DSD frame retransmission may be provided for applications requiring greater robustness at the expense of latency. Audio data is extracted from the FIFO at a continuous rate of 90.3168 Mbit/s and because the data output rate is less than the data input rate, the FIFO gradually fills up as the frame is received. Once a complete frame has been received there will be an inter-frame latency time before reception of audio data from the next frame and the FIFO buffer will continue to empty (although not completely) during this idle period.

0136In the event that the receiver buffer fills completely or empties completely an error signal will be sent to the system controller. In this event the system controller will mute the audio outputs because a completely full or empty buffer indicates that one of the following situations has arisen: data link has failed; transmitter has failed; or DSD master clocks have not been properly synchronised between transmitter and receiver.

0137<figref idref="DRAWINGS">FIG. 16</figref> schematically illustrates the data structure of a standard Ethernet frame. The frame structure is defined in the IEEE 802.3 standard. As shown in <figref idref="DRAWINGS">FIG. 16</figref> the Ethernet frame comprises a preamble, a start frame delimiter, a destination address field, a source address field, a data length field, a data payload and a checksum.

0138The preamble is 7 bytes long, each byte containing the bit pattern 10101010 and this is followed by a single-byte start frame delimiter S containing the bit pattern 10101011. The preamble and start frame delimiter are used for hardware timing purposes. The destination address field is 6 bytes long and specifies the physical address of the network adapter that is to receive the frame. The source address field is 6 bytes long and contains the physical address of the network adapter that is sending the frame. The data length field is 2 bytes long and specifies the size of the data payload. The data payload is a variable length field which is a minimum of 46 bytes and a maximum of 1500 bytes long. The checksum field is 4 bytes long and contains a checksum value for the frame that is used to perform a cyclic redundancy check (CRC). The CRC is a common means of verifying data transmissions. The sending network node calculates a CRC value for the frame according to a predetermined algorithm and encodes it in the frame. The receiving network node then recalculates the CRC and checks the CRC field to see if the values calculated by the transmitter and the receiver match. If the values do not match this indicates that data has been lost or corrupted during transmission. This Ethernet frame will be passed to the Physical layer components where it will be converted to a bit stream and sent across the transmission medium. Note that slight variations of this Ethernet frame format exist.

0139<figref idref="DRAWINGS">FIG. 17</figref> shows the structure of an audio data frame according to an embodiment of the present invention. The audio data frame has a total size of 1536 bytes comprising: an 8 byte preamble (following which the physical layer will accept up to 1528 bytes of arbitrary data); a 6-byte field reserved for the destination MAC address (default value 0xffffff); a 6 byte field reserved for the source MAC address (default value 0x000000); a 2-byte data length field which specifies the number of bytes (always 1510 bytes) following this field but excluding the CRC; a 28-byte field reserved for networking headers; a 12-bit reserved field (as yet unallocated); a 4-bit frame type field which is used for example for synchronisation purposes; an audio data payload of 1480 bytes which holds 370 samples of 32 channel DSD audio; and a 4-byte CRC field containing a checksum. The CRC checksum procedure used in embodiments of the invention will be described below. The audio data frame structure illustrated in <figref idref="DRAWINGS">FIG. 17</figref> is of a form that allows for compatibility with Internet Protocol (IP) networks. Accordingly the audio data frame may be treated as a User Datagram Protocol (UDP)/IP datagram for transmission over wider IP networks. UDP is a connectionless (best try) transport layer protocol. In this particular embodiment only the physical layer is used. The MAC layer is not used so the MAC address fields are not actually required by the system. These fields are simply reserved and filled with default values to allow (potential later) compatibility with Local Area Networks (LAN) or UDP/IP.

0140The audio frame CRC validity check will now be described in more detail. All frames use a 4-byte CRC check word, to verify the validity of the frame. The CRC algorithm, check word location and scope are similar to those defined in the standards document IEEE802.3-2000 section 3.2.8.

0141According to the IEEE802.3 standard, the payload of a frame should not be passed on from the data link layer until the frame validity has been verified with the CRC. However, in the context of embodiments of the invention, this implies that the receiver would have to buffer an entire frame before starting to output the DSD audio bitstreams. Direct implementation of this standard would be undesirable, as it would increase the audio latency by 115 μs, from around 25 μs to 140 μs.

0142The CRC is primarily used to check the validity of a data link between audio devices at system start-up. Link failures after start-up, such as a cable disconnection are indicated by a receiver error assertion from the PHY device, following which the audio output is muted. Since the link is a simple point-to-point connection, with deterministic, synchronised frame transmission and no collisions, other modes of failure are unlikely.

0143Accordingly, a relatively simple CRC check is implemented in embodiments of the invention. The receiver audio outputs are muted on start-up, until the first received frame has been received in full and verified by its CRC. If the CRC check fails, the audio outputs remain muted, and an error condition indicated to the local system controller. Following the verification of the first frame, the CRC is only be checked retrospectively. This allows audio data to be streamed out with near-zero receiver latency. The CRC is used only to alert a host processor that a CRC error has occurred.

0144If an invalid audio data frame is encountered, it is theoretically possible for up to 131 μs of invalid audio data to pass, before the output is muted in response to the retrospective CRC test. However, in practice, a random external perturbation that corrupts PHY line symbols will cause invalid symbols, resulting in rapid assertion of a receiver error condition, which may be detected to mute the audio outputs.

0145If use of a CRC check on every frame is considered necessary then each frame is buffered and verified using the CRC before outputting the DSD audio data. This is not a preferred option because it adds approximately 115 μs extra latency and substantially increases the receiver buffer hardware size.

0146The 1536-byte audio data frames illustrated in <figref idref="DRAWINGS">FIG. 17</figref> each have a transmit duration of 120.9 μs (at a symbol rate of 101.6064 Mbit/s). According to a particular embodiment of the invention, frames are transmitted at intervals of 131.1 μs. A minimum inter-frame time of 96 bit periods is provided which leaves 8.25 μs of “link-time” between transmission of audio frames. This link-time is used to convey auxiliary frames containing control data. The maximum total size of a control data frame in this embodiment is 104 bytes.

0147The structure of a control data frame is identical to that of the audio data frame shown in <figref idref="DRAWINGS">FIG. 15</figref>, with the exception of the length of the data payload which is 1480 bytes for the audio data frame but only 48 bytes for the control data frame. A control data frame is transmitted every 131 μs which provides a control data bandwidth of 2.9 Mbit/s. The control data itself may comprise channel usage information, router control data and clock source control data. The control data will be transmitted from storage in a FIFO buffer at the transmitter and gathered in a FIFO buffer at the receiver before being routed to a system controller of the receiver.

0148<figref idref="DRAWINGS">FIG. 18A</figref> shows the audio data frame format for the 32 DSD channel embodiment which is arranged as 384*4-byte data words. Similarly, <figref idref="DRAWINGS">FIG. 19</figref> shows the control data format for the 32 channel DSD embodiment arranged as 26*4-byte data words. In both <figref idref="DRAWINGS">FIG. 18A</figref> and <figref idref="DRAWINGS">FIG. 19</figref>, bit zero (B<b>0</b>) is transmitted first and bit <b>31</b> (B<b>31</b>) is transmitted last. These audio data frames and control data frames are passed to and received from the Media Independent Interface (MII) connection <b>218</b> that provides a link to the Ethernet physical layer devices. The MII comprises a 4-bit wide transmit data bus and a 4-bit wide receive data bus each of which is clocked from the PHY at the link rate of 25 MHz (or 25.4016 MHz). The MII also has a transmit-enable signal input to initiate data transmission and a receive data valid signal output as well as other error and signal status indicators.

0149Referring now to the audio data frame structure illustrated in <figref idref="DRAWINGS">FIG. 18A</figref> it can be seen that the payload of the audio data frame contains 370 samples of 32-channel 64 Fs DSD audio. These channels are multiplexed per-bit. Each 32-bit word represents one 64 Fs DSD sample for 32 audio channels. Word <b>13</b> is the first DSD sample in the frame, and word <b>382</b> is the last. Bit <b>0</b> of an audio data word is always the single-bit sample data for channel <b>1</b> (the first channel in the system) whereas Bit <b>31</b> of an audio data word is always the single-bit sample data for channel <b>32</b> (the last channel in the system). Table 3 below indicates how successive samples for each channel are stored in the data words of the audio frame. For example: bit <b>0</b> of word <b>13</b> is the channel <b>1</b> sample data, for the first DSD sample in the frame; bit <b>6</b> of word <b>14</b> is the channel <b>7</b> sample data, for the second DSD sample in the frame; and bit <b>31</b> of word <b>382</b> is the channel <b>32</b> sample data, for the last DSD sample in the frame. <tables id="TABLE-US-00003" num="3"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="21PT" align="left" /><colspec colname="2" colwidth="63PT" align="left" /><colspec colname="3" colwidth="63PT" align="left" /><colspec colname="4" colwidth="14PT" align="left" /><colspec colname="5" colwidth="56PT" align="left" /><colspec colname="6" colwidth="56PT" align="left" /><thead><row><entry namest="1" nameend="6" align="center">TABLE 3</entry></row><row><entry /></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row><row><entry>Word</entry><entry>Bit 31</entry><entry>Bit 30</entry><entry>. . .</entry><entry>Bit 1</entry><entry>Bit 0</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry> 13</entry><entry>Ch. 32, sample 1</entry><entry>Ch. 31, sample 1</entry><entry>. . .</entry><entry>Ch. 2, sample 1</entry><entry>Ch. 1, sample 1</entry></row><row><entry> 14</entry><entry>Ch. 32, sample 2</entry><entry>Ch. 31, sample 2</entry><entry>. . .</entry><entry>Ch. 2, sample 2</entry><entry>Ch. 1, sample 2</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>. . .</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>. . .</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>. . .</entry><entry>.</entry><entry>.</entry></row><row><entry>382</entry><entry>Ch. 32, sample 370</entry><entry>Ch. 31, sample 370</entry><entry>. . .</entry><entry>Ch. 2, sample 370</entry><entry>Ch. 1, sample 370</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0150Although Table 3 above represents the frame format in 32-bits words, these are supplied to and from MII four bits (a nibble) at a time rather than a word (4-bytes) at a time. The sequence of nibbles supplied to the MII for the single 24 DSD channel frame of <figref idref="DRAWINGS">FIG. 18B</figref> is as shown in Table 4 below. The start of the 14^thdata 4-byte word (word <b>13</b>) corresponds to the start of the 105^th4-bit nibble (nibble <b>104</b>). The column headings TXD and RXD in the table below refer to the MII transmit and receive data buses respectively, which transfer nibbles of data synchronously with a 25 MHz (or 25.4016 MHz) clock.

0151Nibble <b>0</b> is the first nibble in the frame, and contains part of the preamble pattern (0×5). Nibble <b>104</b> is the first nibble of the audio data field (first nibble of word <b>13</b>), and nibble <b>3063</b> is the last nibble of the audio data field (last nibble of word <b>382</b>). <tables id="TABLE-US-00004" num="4"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="28PT" align="center" /><colspec colname="2" colwidth="70PT" align="left" /><colspec colname="3" colwidth="70PT" align="left" /><colspec colname="4" colwidth="77PT" align="left" /><colspec colname="5" colwidth="70PT" align="left" /><thead><row><entry namest="1" nameend="5" align="center">TABLE 4A</entry></row><row><entry /></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row><row><entry>nibble</entry><entry>TXD(3)/RXD(3)</entry><entry>TXD(2)/RXD(2)</entry><entry>TXD(1)/RXD(1)</entry><entry>TXD(0)/RXD(0)</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>  0</entry><entry>0</entry><entry>1</entry><entry>0</entry><entry>1</entry></row><row><entry>  1</entry><entry>0</entry><entry>1</entry><entry>0</entry><entry>1</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry> 104</entry><entry>channel 4 sample 1</entry><entry>channel 3 sample 1</entry><entry>Channel 2 sample 1</entry><entry>channel 1 sample 1</entry></row><row><entry> 105</entry><entry>channel 8 sample 1</entry><entry>channel 7 sample 1</entry><entry>Channel 6 sample 1</entry><entry>channel 5 sample 1</entry></row><row><entry> 106</entry><entry>channel 12 sample 1</entry><entry>channel 11 sample 1</entry><entry>Channel 10 sample 1</entry><entry>channel 9 sample 1</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry> 111</entry><entry>channel 32 sample 1</entry><entry>channel 31 sample 1</entry><entry>Channel 30 sample 1</entry><entry>channel 29 sample 1</entry></row><row><entry> 112</entry><entry>channel 4 sample 2</entry><entry>channel 3 sample 2</entry><entry>Channel 2 sample 2</entry><entry>channel 1 sample 2</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>3062</entry><entry>channel 28 sample 370</entry><entry>channel 27 sample 370</entry><entry>Channel 26 sample 370</entry><entry>channel 25 sample 370</entry></row><row><entry>3063</entry><entry>channel 32 sample 370</entry><entry>channel 31 sample 370</entry><entry>Channel 30 sample 370</entry><entry>channel 29 sample 370</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0152<figref idref="DRAWINGS">FIG. 18B</figref> schematically illustrates the audio data frame format for the 24 DSD channel embodiment. In this case the frame comprises 368*4-byte data words. The payload of the audio data frame comprises 352 DSD samples, each sample comprising 1-bit from each of the 24 channels. Data words <b>15</b> to <b>366</b> contain the audio data payload. Words <b>2</b> to <b>4</b> are reserved for source and destination MAC addresses. Bits <b>0</b> to <b>15</b> of word <b>5</b> specifies the total number of bytes in the frame from the beginning of the length field onwards but excluding the CRC field, which in this case is 1446 bytes. Bits <b>16</b> to <b>31</b> of word <b>5</b>, words <b>6</b> to <b>12</b> and bits <b>0</b> to <b>15</b> of word <b>13</b> are data fields reserved for UDP and IP parameters. These data fields facilitate optional use of UDP/IP. When UDP/IP operation is not required the transmitter fills these fields with zeros. The receiver may ignore all these UDP/IP header fields, with the exception of the first four bits (bits <b>16</b> to <b>19</b> of word <b>5</b> in this case) which indicate the IP Version. The data entry in the IP version field is checked and an action is taken in correspondence with the determined value as specified in Table 5 below: <tables id="TABLE-US-00005" num="5"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="63PT" align="left" /><colspec colname="2" colwidth="154PT" align="left" /><thead><row><entry namest="1" nameend="2" align="center">TABLE 5</entry></row><row><entry /></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row><row><entry>IP Header Value</entry><entry>Consequent Action</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>0x0</entry><entry>Process frame as normal (i.e. transmitter did not</entry></row><row><entry /><entry>fill IP fields)</entry></row><row><entry>0x4</entry><entry>Process frame as normal (i.e. transmitter filled frame</entry></row><row><entry /><entry>header fields according to IP version 4)</entry></row><row><entry>any other</entry><entry>Discard the frame</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0153The IP Version check is performed to ensure backwards compatibility of the current IP version 4 from future IP versions (i.e. IP version 6). Future IP versions may have different header lengths, and consequently the Frame Format ID fields may be located at a different position in the frame. The safeguard of checking the IP version field means that such a frame would be discarded by the receiver (due to having a value other than 0×0 or 0×4) which avoids the possibility of the frame being incorrectly interpreted due to the Frame Format ID fields not being in the expected location at words <b>13</b> and <b>14</b>.

0154Bits <b>16</b> to <b>31</b> of word <b>13</b> and bits <b>0</b> to <b>31</b> word <b>14</b> in <figref idref="DRAWINGS">FIG. 18B</figref> are fields for specifying the MAC-DSD frame format. This 48-bit frame format field is logically divided into three distinct 16-bit (4-nibble) sections, each of which contains an identical set of frame format data on transmission. The same set of frame format data is repeated three times within a given frame to ensure that the frame format identifier is robust to transmission errors i.e. multiple copies of the data are sent to serve as an error protection mechanism. This data-repeat error protection mechanism has the advantage that it gives the required error correction capability given that 48 bits are available to convey 16 bits of information yet it is simple to implement. An alternative embodiment might use an error correction code such as a convolutional code to transmit the frame format ID payload.

0155Each of the three 16-bit frame format field sections are structured as illustrated in <figref idref="DRAWINGS">FIG. 20</figref>. The first nibble (bits <b>0</b>-<b>3</b>) of each 16-bit section specifies the Protocol Minor Version (OxO-Oxf). The protocol minor Version field is used to indicate minor updates to the protocol specification. A more recent Minor Version should be fully backwards-compatible with a previous Minor Version associated with the same Major Version so that for example a Version 1.7 protocol must incorporate all the functionality of Version 1.6 protocol, and a Version 1.7 transceiver must be able to communicate fully with a Version 1.6 transceiver. The second nibble (bits <b>4</b>-<b>7</b>) of each 16-bit section specifies the Protocol Major Version (OxO-Oxf). This field is used to indicate major updates to the protocol specification. Backwards-compatibility with previous Major Versions of the protocol is desirable but not mandatory. The third nibble (bits <b>8</b>-<b>11</b>) of each 16-bit section specifies the Frame Type (OxO-Oxi). This field can be used to indicate different frame types used by a given version of the protocol. Within a given Major Version level, the definitions of frame types should be consistent. The basic type of audio frame is always Type 0. The table below specifies the information derivable from the Frame type number specified by bits <b>8</b> to <b>11</b> according to the described embodiment. <tables id="TABLE-US-00006" num="6"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="42PT" align="left" /><colspec colname="2" colwidth="35PT" align="left" /><colspec colname="3" colwidth="140PT" align="left" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 6</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>Frame Type</entry><entry /><entry /></row><row><entry>Number</entry><entry>Name</entry><entry>Description</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>0x0</entry><entry>DSD</entry><entry>352 DSD (2.8224 MHz) samples, 24-channel,</entry></row><row><entry /><entry>audio</entry><entry>plus 88 bytes aux data, (32, 26) Hamming</entry></row><row><entry /><entry>frame</entry><entry>linear block code error correction,</entry></row><row><entry /><entry /><entry>256-nibble interleaving</entry></row><row><entry>other</entry><entry>(invalid)</entry><entry>Invalid - reject frame</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0156The fourth nibble (bits <b>12</b>-<b>15</b>) of each 16-bit section contains one or more flags used for example to flag frames for synchronisation purposes as described above with reference to the flow chart of <figref idref="DRAWINGS">FIG. 13</figref>. The definition of the flag bits is dependent upon the Major Version protocol level. The table below specifies the information derivable from the frame flag bits <b>12</b>-<b>15</b> according to the described embodiment. In particular bit <b>0</b> of the flags field is the 44.1 kHzsync flag. If flag <b>0</b> has a value 1 this indicates that the first DSD sample in frame was received at transmitter simultaneously with 44.1 kHz sync clock positive edge whereas if bit <b>0</b> of the flags field has value 0, this indicates that the first DSD sample in frame was not received at transmitter simultaneously with 44.1 kHz sync clock positive edge. <tables id="TABLE-US-00007" num="7"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="28PT" align="left" /><colspec colname="2" colwidth="35PT" align="left" /><colspec colname="3" colwidth="154PT" align="left" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 7</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>Flag bit</entry><entry>Name</entry><entry>Description</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>0</entry><entry>44.1 kHz</entry><entry>1: First DSD sample in frame was received at</entry></row><row><entry /><entry>sync flag</entry><entry>transmitter simultaneously with 44.1 kHz sync clock</entry></row><row><entry /><entry /><entry>positive edge</entry></row><row><entry /><entry /><entry>0: First DSD sample in frame was not received at</entry></row><row><entry /><entry /><entry>transmitter simultaneously with 44.1 kHz sync clock</entry></row><row><entry /><entry /><entry>positive edge</entry></row><row><entry>others</entry><entry>(not used)</entry><entry>Set to 0 by transmitter, ignored by receiver</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0157<figref idref="DRAWINGS">FIG. 21</figref> schematically illustrates the three 4-nibble sections of the frame format ID containing a set of data entries to be processed at the receiver. Section <b>0</b> comprises nibble <b>0</b> (n<b>0</b>) to nibble <b>3</b> (n<b>4</b>), section <b>1</b> comprises nibble <b>4</b> (n<b>4</b>) to nibble <b>7</b> (n<b>7</b>) and section <b>2</b> comprises nibble <b>8</b> (n<b>8</b>) to nibble <b>11</b> (n<b>11</b>). The manner in which the repetition of data sections is used at the receiver to reject data transmission errors will now be explained in the context of <figref idref="DRAWINGS">FIG. 21</figref>. According to the present technique it is known that on transmission, each of the three sections should contain an identical data set such that data entries in corresponding nibble positions of each of the three sections match. On particular it is expected that: n<b>0</b>=n<b>4</b>=n<b>8</b>; n<b>1</b>=n<b>5</b>=n<b>9</b>; n<b>2</b>=n<b>6</b>=n<b>10</b>; and n<b>3</b>=n<b>7</b>=n<b>11</b>. At the receiver triplets of corresponding nibbles are compared for equality, and a majority decision is taken as to the correct data value. Consider the example incoming receiver data set shown in <figref idref="DRAWINGS">FIG. 21</figref>. For the first triplet of nibbles it can be seen that n<b>0</b>=1101b, n<b>4</b>=1101b, n<b>8</b>=1101b i.e. the corresponding nibble values are identical so the value is assumed to be correct and the first nibble of the Frame Format, which specifies the protocol minor version, is set to the value 1101b. Similarly, for the second triplet of nibbles n<b>1</b>=n<b>5</b>=n<b>9</b>=1110b so the value is assumed to be correct and the second nibble of the Frame Format, which specifies the protocol major version, is set to 1110b. However, for the third triplet of nibbles there is a discrepancy between the data values since n<b>2</b>=n<b>10</b>=0110b but n<b>6</b>=1011b. In this case n<b>6</b> is rejected as being erroneous on the basis of a majority decision so that the receiver and outputs the third nibble of the Frame Format, which corresponds to the frame type, as 0110b. For the fourth and final triplet of nibbles it can be seen from <figref idref="DRAWINGS">FIG. 21</figref> that none of the corresponding nibbles match n<b>3</b>=0010b, n<b>7</b>=0111b, n<b>11</b>=1100b. In this case a majority decision is impossible so the frame format cannot be determined and consequently the frame is rejected.

0158An alternative embodiment uses a modified Frame Format error detection/correction strategy. This alternative strategy also involves using the data repetition and majority decision approach but the strategy is augmented by using the 100Base-TX PHY ‘MII receive error’ (rx_er) signal to flag nibbles that are known to be in error. For example consider receiving the following values for the fourth triplet of nibbles with associated error flags as indicated: n<b>3</b>=1000b (rx_er=true), n<b>7</b>=0100b (rx_er=false), n<b>11</b>=1000b (rx_er=true). In this case, although the majority decision determines that 1000b is the correct value, the rx_er signal indicates that n<b>3</b> and n<b>11</b> are definitely incorrect. Thus according to this alternative strategy the data vale n<b>7</b> is selected in preference to n<b>7</b> and n<b>11</b> to give a Frame Format Flags value of 0100b.

0159Returning now to the frame data fields of <figref idref="DRAWINGS">FIG. 18B</figref>, the last word (word <b>367</b>) of the 24 DSD channel data frame is a field containing cyclic redundancy check (CRC) data.

0160Table 4B below identifies the sequence of nibbles supplied to the MII for the single 24 DSD channel frame of <figref idref="DRAWINGS">FIG. 18B</figref>. This sequence is transmitted via the nibble-wide MII interface <b>218</b>, starting with the least significant nibble. Nibbles <b>0</b> to <b>8</b> (32 bits) correspond to word <b>0</b> of <figref idref="DRAWINGS">FIG. 18B</figref>, nibbles <b>8</b> to <b>15</b> correspond to word <b>1</b> of <figref idref="DRAWINGS">FIG. 18B</figref>, nibbles <b>16</b> to <b>23</b> correspond to word <b>2</b> of <figref idref="DRAWINGS">FIG. 18B</figref> and so on until the last nibble which corresponds to bits <b>28</b> to <b>31</b> of word <b>366</b>. There are a total of 2936 nibbles (367 words) corresponding to the 1446 byte frame of <figref idref="DRAWINGS">FIG. 18B</figref> since the last word is not transmitted as a nibbles. As mentioned above with reference to <figref idref="DRAWINGS">FIG. 1</figref> the MII <b>218</b> interface provides independent 4-bit wide data-transmit and data-receive paths and full duplex operation. More particularly, the MII <b>218</b> comprises: a four-bit wide transmit data bus, clocked from the physical layer interface (PHY) <b>514</b>, <b>526</b> at the link rate (25 MHz or 25.4016 MHz); a transmit enable signal input; four-bit (nibble) wide receive data bus, clocked from the PHY at the link rate (25 MHz or 25.4016 MHz); a receive data valid signal output; and error and signal status indicators. A full description of the MII interface, can be found in IEEE802.3-2000 Section 22, but note that the clock rate according to the present technique may be 25.4016 MHz rather than the IEEE standardised 25.0000 MHz. <tables id="TABLE-US-00008" num="8"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="35PT" align="left" /><colspec colname="2" colwidth="42PT" align="left" /><colspec colname="3" colwidth="35PT" align="left" /><colspec colname="4" colwidth="35PT" align="left" /><colspec colname="5" colwidth="35PT" align="left" /><colspec colname="6" colwidth="35PT" align="left" /><thead><row><entry namest="1" nameend="6" align="center">TABLE 4B</entry></row><row><entry /></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row><row><entry /><entry>Word (from</entry><entry>MII</entry><entry>MII</entry><entry>MII</entry><entry>MII</entry></row><row><entry>Nibble</entry><entry><figref idref="DRAWINGS">FIG. 18B</figref>)</entry><entry>TXD(3)</entry><entry>TXD(2)</entry><entry>TXD(1)</entry><entry>TXD(0)</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>  0</entry><entry> 0</entry><entry>Bit 3</entry><entry>Bit 2</entry><entry>Bit 1</entry><entry>Bit 0</entry></row><row><entry>  1</entry><entry> 0</entry><entry>Bit 7</entry><entry>Bit 6</entry><entry>Bit 5</entry><entry>Bit 4</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>  7</entry><entry> 0</entry><entry>Bit 31</entry><entry>Bit 30</entry><entry>Bit 29</entry><entry>Bit 28</entry></row><row><entry>  8</entry><entry> 1</entry><entry>Bit 3</entry><entry>Bit 2</entry><entry>Bit 1</entry><entry>Bit 0</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry><entry>.</entry></row><row><entry>2934</entry><entry>366</entry><entry>Bit 27</entry><entry>Bit 26</entry><entry>Bit 25</entry><entry>Bit 24</entry></row><row><entry>2935</entry><entry>366</entry><entry>Bit 31</entry><entry>Bit 30</entry><entry>Bit 29</entry><entry>Bit 28</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0161The nibble is the fundamental unit of data carried on the physical layer. Each 4-bit nibble is mapped to a 5-bit symbol by the PHY <b>514</b>, <b>526</b>, for transmission on the signal line <b>515</b>. All frames for transmission must begin with an eight-byte preamble pattern, following which the physical layer will accept up to 1528 bytes of arbitrary data, supplied 4 bits at a time. Received frames are supplied 4 bits at a time by the receive bus, including the preamble.

0162The 24 DSD channel frame format of <figref idref="DRAWINGS">FIG. 18B</figref> includes a frame payload of 352 DSD samples, each of which consists of a 32-bit data block. <figref idref="DRAWINGS">FIG. 22</figref> schematically illustrates the format of the 32-bit data block. Each data block corresponds to a single DSD sample period of approximately 354 ns. The data block comprises a 24-bit audio data vector each bit of which belongs to a respective one of the 24 audio channels, 2 bits of auxiliary data and 6 check (or parity) bits. As shown in <figref idref="DRAWINGS">FIG. 22</figref> bit numbers <b>0</b> to <b>14</b> contain bits <b>1</b> to <b>15</b> of the audio data vector, bit numbers <b>15</b>, <b>23</b>, <b>27</b>, <b>29</b>, <b>30</b> and <b>31</b> contain the six parity bits, bit numbers <b>26</b> and <b>28</b> contain the two bits of auxiliary data and the remaining nine bits of the audio vector are contained sequentially in bit numbers <b>16</b> to <b>22</b>, <b>24</b> and <b>25</b> of the data block.

0163The six parity bits of the 32-bit data block provide error control capability. The 24-bits of audio data plus the two auxiliary bits (totalling 26 bits) are encoded using a type of linear block code known as a Hamming code. In this case a (31, 26) Hamming code is used, which means that 5 (=31−26) parity bits are generated by the code for each group of 26 data bits. The final bit of the 32-bit block is a global parity bit so there are a total of 6 parity bits and 26 data bits. The (31, 26) Hamming code is capable to detecting 2 errors per data block but is only capable of correcting one error per data block.

0164<figref idref="DRAWINGS">FIG. 23A</figref> schematically illustrates how the six parity bits P<b>0</b> to P<b>5</b> are generated from the 24 audio data bits (numbered <b>1</b>-<b>24</b>) and the two auxiliary data bits A<b>0</b>, A<b>1</b>. Parity bits P<b>0</b> to P<b>5</b> are generated by performing a logical XNOR operation on a predetermined sequence of 15 data elements. For example P<b>0</b> is generated by performing an XNOR operation on audio vector bits <b>1</b> through <b>15</b> whereas P<b>1</b> is generated by performing an XNOR operation on audio vector bits <b>1</b> to <b>8</b> and <b>16</b> to <b>22</b>. Global parity bit P<b>5</b> is obtained by performing the XNOR operation on all 26 data elements. The error detection process at the receiver involves determining whether the parity checks are satisfied in the received data sequence. This is done using a value known as the syndrome. <figref idref="DRAWINGS">FIG. 23B</figref> indicates how the syndrome s is generated by XNOR operations on various combinations of the received data block elements. The syndrome is obtained by comparing the received parity bits and the parity bits recalculated from the received information. Table 8 below indicates how the value of the syndrome is used to detect and correct errors in the received data block. Essentially, if all 6 bits of the syndrome have value 1 (s=111111) then the received data sequence is assumed to be correct. If the sixth bit of the syndrome is zero then there is assumed to be a single error in the received data block, which is correctable by inverting the appropriate bit. The appropriate bit is identified from the value of the syndrome itself e.g. if s=011011 in binary notation, which corresponds to the decimal number 27 then it is determined that bit number 27 (of bits <b>0</b> to <b>31</b>) should be inverted to correct the data block. If the sixth bit of the syndrome is 1 but the other five bits are not all 1 e.g. s=111011 then this indicates that there are two or more errors in the block and the multiple errors are uncorrectable. <tables id="TABLE-US-00009" num="9"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="21PT" align="left" /><colspec colname="2" colwidth="49PT" align="left" /><colspec colname="3" colwidth="147PT" align="left" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 8</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>s₅</entry><entry>s₄s₃s₂s₁s₀</entry><entry>Block status</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>1</entry><entry>11111</entry><entry>No errors in block</entry></row><row><entry>0</entry><entry>other</entry><entry>One error in block, identified by s₄s₃s₂s₁s₀-</entry></row><row><entry /><entry /><entry>correct error by inverting bit</entry></row><row><entry>1</entry><entry>other</entry><entry>More than one error in block - not correctable</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0165The 32-bit data blocks (see <figref idref="DRAWINGS">FIG. 22</figref>) are interleaved in groups of 32, to facilitate correction of groups of errors. The interleaving process involves permuting the data in a predetermined way. This is required because the (31, 26) Hamming code used for each 32-bit data block is only capable of correcting a single bit error in a given block. Since the fundamental unit of data on the physical layer the four-bit data nibble, a single instantaneous corruption on the physical layer will cause a symbol error (recall that a symbol is a 5-bit quantity), resulting in four consecutive bit errors. To facilitate correction of such 4-bit burst errors the erroneous bits must be distributed amongst four different 32-bit data blocks. Consider a stream of 352 32-bit data blocks B<b>0</b>, B<b>1</b>, B<b>2</b>, . . . B<b>351</b> emerging from the parity generator for transmission. Recall that the 24 DSD channel frame of <figref idref="DRAWINGS">FIG. 18B</figref> comprises an audio data payload of 352 32-bit data blocks. The resulting stream of nibbles from the interleaver is comprised as shown in <figref idref="DRAWINGS">FIG. 24</figref>. In this Figure the bits of the audio payload are labelled such that B<b>2</b>[0] refers to bit <b>0</b> of block <b>2</b>, for example. Thus it can be seen that nibble zero comprises bit <b>0</b> of blocks <b>0</b>, <b>1</b>, <b>2</b> and <b>3</b> respectively; nibble <b>1</b> comprises bit <b>0</b> of blocks <b>4</b>, <b>5</b>, <b>6</b> and <b>7</b> respectively and so on. Accordingly, nibbles <b>0</b> to <b>7</b> collectively comprise bit <b>0</b> of each of the thirty-two 32-bit data blocks, nibbles <b>8</b> to <b>15</b> collectively comprise bit <b>1</b> of each of the thirty-two 32-bit data blocks and nibbles <b>2802</b> to <b>2815</b> comprise bit <b>31</b> of each of the thirty-two 32-bit data blocks. The 32-block interleaving system used by MAC-DSD facilitates the correction of up to eight symbol errors (i.e. 32 bits can be corrected overall) in a group of 32 interleaved data blocks (256 nibbles or symbols).

0166In summary, the version of the MAC-DSD protocol used for transmission of 24 DSD channels as described above with reference to <figref idref="DRAWINGS">FIGS. 18B and 20</figref> to <b>23</b> has key features including: 24-channel, full-duplex transfer of 2.8224 MHz DSD audio; 100Base-TX physical layer; audio latency of less than 50 microseconds; Hamming linear block code error correction, with 256-nibble interleaving, to correct up to 8 nibble errors per 256-nibble block group; 64 fs DSD clock transfer in both directions; and frame flag indication for transfer of the 44.1 kHz sync signal.

0167<figref idref="DRAWINGS">FIG. 25</figref> schematically illustrates the protocol layers of the MAC-DSD protocol for the particular example embodiment using the 24 DSD channel frame format. On the transmitter side <b>1000</b> the protocol layers comprise a parity generating and formatting layer <b>1010</b> that receives the incoming 24 channel DSD audio stream and an auxiliary data stream of up to 5.6 Mbit/s. This layer <b>1010</b> generates six parity bits for each 24 audio bit and 2 auxiliary bit sample and formats the resulting 32-bit data block. The 32-bit data blocks output by the parity generating and formatting layer <b>1010</b> are supplied to an interleaving layer <b>1020</b> that interleaves the data blocks in groups of 32 and outputs the interleaved data across the MII <b>218</b> in 4-bit nibbles as specified in <figref idref="DRAWINGS">FIG. 24</figref>. The nibbles of data from the interleaver are supplied to the FIFO buffer <b>810</b> of the transmitter at a continuous data rate of 90.3168 Mbit/s. The nibbles continue to fill the FIFO buffer <b>810</b> until the predetermined threshold buffer occupation level is reached (as described with reference to <figref idref="DRAWINGS">FIG. 14</figref>) whereupon assembly of a data frame begins. During data frame assembly data nibbles are read out of the FIFO buffer <b>810</b> and passed to a frame assembly layer <b>1040</b>. The frame assembly process involves use of a header data generation module <b>1050</b> that generates frame header information and a CRC generation module <b>1060</b> that generates data for the CRC field, which is word <b>367</b> of the frame format of <figref idref="DRAWINGS">FIG. 18B</figref>. The frames are assembled such that they contain a 1408 byte payload of 352 DSD samples contained in 352 32-bit data blocks. Data from the frame assembly layer <b>1040</b> is output as MII frames (which comprise nibbles) at a rate of 101.6064 Mbit/sec and supplied to the transmitter physical layer <b>1070</b> which prepares the data for transmission across the physical medium. The transmitter physical layer <b>1070</b> forms a 5-bit symbol from each 4-bit nibble and the symbols are transmitted to the receiver across a twisted-pair cable. On the receiver side <b>1100</b> a receiver physical layer <b>1110</b> receives the 5-bit symbols and processes them to form MII frames comprising 4-bit nibbles. The MII frames are supplied to a frame disassembling layer <b>1120</b> at a rate of 101.6064 Mbit/sec, which performs the CRC checks and strips off the header data for subsequent processing. The frame payload is output by the frame disassembling layer <b>1120</b> as MII nibbles which are fed to the FIFO buffer <b>870</b> (as described above with reference to <figref idref="DRAWINGS">FIG. 15</figref>) which has a low latency with regard to data output. Data is output from the FIFO buffer <b>870</b> in the form of MII nibbles and passed to a deinterleaving layer <b>1160</b>. The de-interleaver de-interleaves the data in groups of 32 data blocks to reconstruct individual 32-bit data blocks of the format illustrated in <figref idref="DRAWINGS">FIG. 22</figref>. The 32-bit data blocks are then passed to a parity decoding and data extraction layer <b>1170</b> whereupon the parity data is used to perform error control and the recovered payload data is extracted. The output of this layer is a 24 channel DSD audio stream and an auxiliary data stream of up to 5.6 Mbit·s Note that in <figref idref="DRAWINGS">FIG. 25</figref>, although the FIFO buffers <b>810</b>, <b>870</b> do not perform any data translation and therefore are not technically protocol layers, they are included in the schematic illustration of the protocol layer structure for completeness.

0168Note that in the case of the 352 sample payload of the 24 DSD channel frame format of <figref idref="DRAWINGS">FIG. 18B</figref>, the transmission buffer size and predetermined buffer occupancy threshold differs from the buffer size and occupancy threshold specified in the description of <figref idref="DRAWINGS">FIG. 14</figref> above for the 370 sample payload of the 32 DSD channel Frame Format of <figref idref="DRAWINGS">FIG. 18A</figref>. In particular, for the 24 DSD channel frame format the minimum buffer size is 36 data blocks (rather than 42 data blocks) and the corresponding minimum occupancy threshold value is 30 data blocks (as before). The audio latency introduced by this buffering is equivalent to 36 DSD samples (rather than 42 samples) or 14.9 microseconds (rather than 12.2 microseconds).

0169The above described system in which the physical layer of a link such as an Ethernet link is used to provide a data communication system for transmission of DSD data may also be used to transmitted other types of clocked digital data. In particular the system may be adapted to accommodate transmission of Pulse Code Modulated (PCM) digital data. The physical layer connection according to the present technique offers high bandwidth for communication of PCM data.

0170PCM data is clocked at a much lower frequency (e.g. 44.1 kHz-96 kHz) than the 64 Fs clocking frequency of DSD data. Accordingly, in order to support PCM transmission as well as DSD transmission a further lower frequency clock signal, which shall be referred to as the word clock signal, is communicated between networked devices along the twisted pair cable. The word clock is used for reproduction of PCM data at the receiver. The frame format for 24 DSD channels as illustrated in <figref idref="DRAWINGS">FIG. 18B</figref> allows for transmission of 352 bits of data per frame for each of 24 audio channels. Essentially, 352 24 bit DSD samples (one bit per channel) are transmitted in a single frame. Data blocks are transferred over the link at an aggregate rate of 64 Fs, that is, 2.8224 MHz (=64*44.1 KHz) for 44.1 kHz based audio and 3.072 MHz for 48 kHz based audio. In order to transfer PCM data in the desired frequency range of (44.1 kHz-12.5%) to (96 kHz+12.5%) at the required data rates it is necessary to accommodate between 4 and 13 24-bit samples per frame. Accordingly, a number of alternative data formats are defined so that at the transmitter it is decided how many samples should be sent in the next frame and a look-up-table is consulted to select the appropriate one of the alternative data formats. Known PCM transmission formats such as I2S and AES3-1992 and package PCM sample data in serial sub-frames. AES3 is an Audio Engineering Society standard for the serial transmission format for linearly represented digital audio data over conventional shielded twisted-pair conductors, of up to at least 100 m in length, without equalisation. <figref idref="DRAWINGS">FIG. 26A</figref> schematically illustrates the AES3 sub-frame format. Each AES3 frame is uniquely composed of two sub-frames and typically the rate of frame transmission corresponds exactly to the source sampling frequency. The first sub-frame starts with the pre-amble X but the preamble changes to Z once every 192 frames. This defines the block structure used to organise the channel status information. The second sub-frame always starts with preamble Y. As illustrated in <figref idref="DRAWINGS">FIG. 26A</figref> each AES sub-frame is 32-bits long in which: bits <b>0</b> to <b>3</b> contain a preamble; bits <b>4</b> (least significant bit) to <b>27</b> (most significant bit) contain a 24-bit audio sample word; bit <b>28</b> is a “V” field which carries a validity bit associated with the audio sample word; bit <b>29</b> is a “U” field which contains one bit of a user data channel associated with the audio data channel transmitted in the same subframe; bit <b>30</b> is a “C” field or channel status field which carries one bit of channel status information associated with audio data transmitted in the same subframe; and bit <b>31</b> is a “P” field which carries a parity bit such that time slots <b>4</b> to <b>31</b> inclusive will carry and even number of ones and an even number of zeros i.e. even parity. The V bit is logic 0 if the audio sample word is suitable for conversion to an analogue audio signal and is logic 1 otherwise. The C bit is one-bit of channel status information specifying for example the length of audio sample words, number of audio channels, sampling frequency etc. Channel status information is organised in 192-bit blocks sub-divided into 24 bytes. The first bit of each block is carried in the frame having preamble Z.

0171<figref idref="DRAWINGS">FIG. 26B</figref> schematically illustrates the sub-frame format for PCM transmission according to the present technique. This 27-bit sub-frame structure includes the U bit and C bit fields of the known AES3 sub-frame format to facilitate transparent transfer of AES3 format data across the physical layer link. As illustrated in <figref idref="DRAWINGS">FIG. 26B</figref>, bits <b>0</b> to <b>23</b> contain data, bit <b>24</b> contains the U bit, bit <b>25</b> contains the C bit and bit <b>26</b> contains an M bit. The U and C bits are taken directly from incoming AES3 data streams or from the user data and channel status buffer memory in the transmitter. The M-bit is a multiplexed bit specific to the present technique and may be used to contain any of the three following indications at certain points in the bitstream: an S bit which is a flag that identifies an external Fs/n (n integer) synchronised data sample and is repeated across all data channels every n periods of Fs; the Z bit that signals the start of the AES3 U/C data block which repeats on each channel every 192 samples; and the V bit which is the sub-sampled AES3 V-bit status. The S and Z indications are each used to identify particular samples within the audio data stream. Since the S and Z indications are by their nature periodic it should in principle be sufficient to simply specify their phase with respect to the sample clock. However, in practice the S and Z indications should be repeated moderately frequently to enable the link to lock rapidly on start-up and to detect any link failures in a timely manner. The M-bit marks an S indication with two consecutive logical 1's in the bitstream as shown in <figref idref="DRAWINGS">FIG. 27B</figref> whereas a Z indication is marked by a single logical ‘1’ as shown in <figref idref="DRAWINGS">FIG. 27A</figref>. In order to indicate the sync sample (S-bit) by two consecutive logical ‘1’s in the M bit data stream a counter is provided at the transmitter to pre-empt the occurrence of the sync signal. The V-bit status is indicated for each channel in the bit immediately following the S indication. This implies that V is indicated less frequently than per-sample, but is indicated per-channel at intervals of the S sync (i.e. typically Fs/2048, or about 46 ms at 44.1 kHz), and also assumes that V-bit status does not change rapidly, which is a reasonable assumption for the vast majority of audio applications. <figref idref="DRAWINGS">FIG. 27C</figref> shows a V-bit indication which is a logical 1 (true), thereby signalling that channel samples are valid resulting in three consecutive logical 1's in the bit stream (two 1's for the S-bit and 1 for the V-bit). <figref idref="DRAWINGS">FIG. 27D</figref> shows a V-bit indication of 0 (false) immediately following the two logical 1's of the S-bit. This signals that the channel samples are invalid. Since the M-bit is used to indicate a number of alternative events it is likely that event indications will either coincide or be close enough in succession to interfere. For this reason priority is always given to S indications over Z indications. As a consequence of this Z indications will occasionally be missed so it is appropriate to maintain counts of the U/C block phases in the receiver in order to set the Z-bits in outgoing AES3 streams in these circumstances. <figref idref="DRAWINGS">FIGS. 28A</figref> to <b>28</b>E give examples of relative occurrences of S indications and Z indications and indicate whether or not the relative positioning requires that the Z indication be disabled. In <figref idref="DRAWINGS">FIG. 28A</figref> the Z indication coincides with the second bit of the S indication so Z is disabled and only S is indicated. In <figref idref="DRAWINGS">FIG. 28B</figref> the Z indication immediately precedes the S indication in the received M-bit sequence, in which case Z is disabled because S is imminent. Otherwise the three consecutive logical 1's would be indistinguishable from the S and V indication of <figref idref="DRAWINGS">FIG. 27C</figref>. In <figref idref="DRAWINGS">FIG. 28C</figref> the Z indication precedes the S indication but is separated from it by a single bit period. Since Z and S are sufficiently separated so that they do not interfere so both the Z indication and the S indication are enabled here. In <figref idref="DRAWINGS">FIG. 28D</figref> the Z indication immediately follows the S indication and could lead to ambiguity so the Z indication is disabled. In <figref idref="DRAWINGS">FIG. 28D</figref>, the Z indication follows the S indication with a single bit-period separation. As for <figref idref="DRAWINGS">FIG. 28C</figref>, Z and S are sufficiently separated so that they do not interfere so both the Z indication and the S indication are enabled here.

0172For the purposes of transferring PCM data between devices on the physical layer the frame format is basically the same as the format described above in relation to <figref idref="DRAWINGS">FIG. 18B</figref>. In particular, each frame is 1472 bytes long and the data payload consists of 352 32-bit data blocks. Each 32-bit block comprises 24 audio data bits and two auxiliary data bits, which together form <b>26</b> independent bit-stream segments of 352 bits per frame. In PCM mode, each of the 24 audio bitstreams is divided into a number of sample subframes which are separated by padding. The number of subframes varies from 4 to 13 in dependence upon the particular PCM sample frequency. This enables support for samples rates from 44.1 kHz−12.5% to 96 kHz+12.5%. Each sample sub-frame contains data from a single PCM sample.

0173For each possible number of sample subframes per bitstream segment, a specific arrangement of sample subframes and padding bits is defined. All padding bits should have the value 0. This determinism enables the receiver to correctly extract the sample subframes from the bitstream segment. These arrangements are shown in Table 9A. Table 9B gives a specific example of the subframe arrangement for the case of 9 sample subframes per frame. <tables id="TABLE-US-00010" num="10"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="84PT" align="center" /><colspec colname="2" colwidth="56PT" align="center" /><colspec colname="3" colwidth="77PT" align="center" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 9A</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry /><entry>Final padding</entry></row><row><entry /><entry /><entry>bits at end of</entry></row><row><entry>Number of sample</entry><entry>Padding bits after</entry><entry>bitstream</entry></row><row><entry>subframes</entry><entry>each subframes</entry><entry>segment</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry> 9</entry><entry>12 </entry><entry>1</entry></row><row><entry>10</entry><entry>8</entry><entry>2</entry></row><row><entry>11</entry><entry>5</entry><entry>0</entry></row><row><entry>12</entry><entry>2</entry><entry>4</entry></row><row><entry>13</entry><entry>0</entry><entry>1</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0174<tables id="TABLE-US-00011" num="11"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="OFFSET" colwidth="35PT" align="left" /><colspec colname="1" colwidth="105PT" align="left" /><colspec colname="2" colwidth="77PT" align="center" /><thead><row><entry /><entry namest="OFFSET" nameend="2" align="center">TABLE 9B</entry></row><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row><row><entry /><entry>Element</entry><entry>Bits</entry></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>sample subframe 1 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 2 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 3 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 4 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 5 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 6 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 7 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 8 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>sample subframe 9 of 9, bit 0 first</entry><entry>27</entry></row><row><entry /><entry>padding</entry><entry>12</entry></row><row><entry /><entry>final padding</entry><entry> 1</entry></row><row><entry /><entry>Total</entry><entry>352 </entry></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0175Accordingly, the data block audio bit usage for the frame format of <figref idref="DRAWINGS">FIG. 18B</figref> in PCM mode differs from the audio bit usage in DSD mode. A further difference in the frame format in PCM mode relative to DSD mode relates to the Frame Format ID values contained in the three identical frame ID sections in words <b>13</b> and <b>14</b> of <figref idref="DRAWINGS">FIG. 18B</figref>. The frame format ID fields of each section were outlined above with reference to <figref idref="DRAWINGS">FIG. 20</figref>. In summary, each frame format ID section comprises a flags field, a frame type field, a protocol major version field and a protocol minor version field. To accommodate PCM mode, the frame type field values are extended relative to those defined in Table 6 above. As specified in the table of <figref idref="DRAWINGS">FIG. 29</figref>, 10 new frame type values have been defined corresponding to the 10 different possibilities <ul id="ul6S-d0e72400001" list-style="none"><li id="ul6S-d0e72400002-li00002"><ul id="ul6S-d0e72400002" list-style="none"><li id="ul6S-d0e72400002-p00176" num="00176"> (integers in the range 4 to 13) for the number of sample subframes per frame. Two separate formats for the frame flags field of the frame format ID (see words <b>13</b> and <b>14</b> of <figref idref="DRAWINGS">FIG. 18B</figref> and <figref idref="DRAWINGS">FIG. 20</figref>) have been defined: one format for DSD frames and another format for PCM frames. The table of <figref idref="DRAWINGS">FIG. 30</figref> shows the flags field format for a DSD frame. In this case flag bit <b>0</b> indicates whether or not the first DSD sample in the frame was received simultaneously with the 44.1 kHz sync clock positive edge whereas flag bit <b>1</b> indicates whether or not the first DSD sample in the frame was received simultaneously with the Fs/n sync clock positive edge. The tables of <figref idref="DRAWINGS">FIG. 31</figref> show the flags field format for a PCM frame. In this case flag bits <b>0</b>:<b>1</b> specify the frequency of the audio base clock whereas flag bits <b>3</b>:<b>2</b> specify the base clock sample rate multiplier. The sample rate can be specified to be 1, 2, 4 or 8 times the base clock frequency Fs. </li></ul></li></ul>

0177The PMC frame format described above relate to an example embodiment in which 24 audio channels are accommodated. An alternative embodiment may involve accommodating 48 audio channels in IFs PCM mode (sample rate 44.1 kHz or 48 kHz+12.5%). In this case two audio channels are multiplexed onto each bitstream. The multiplexing may be implemented per sub-frame or per bit. The clock and synchronisation functions of the PCM mode will now be considered in detail. As mentioned above, for transmission of PCM data across the network a word clock is required in addition to the 64 Fs MAC-DSD cable clock. Rather than sending two separate clock signals across the twisted pair cable, the 64 Fs clock and the word clock are multiplexed. The multiplexing process involves modulating the word clock signal onto the 64 Fs clock signal by shifting at least one edge of the 64 Fs clock pulse i.e. by generating a “clock pulse width deviation”. The clock pulse width deviation acts as a phase indicator signal for the word clock, which is embedded in the 64 Fs clock. The clock pulse width deviation is formed by identifying certain transitions in the 64 Fs clock signal which are determined to be coincident with the word clock transitions at the transmitter. Since in this embodiment the positive-going transitions of the 64 Fs clock are used for timing synchronisation, the phase of the word clock is encoded by shifting the positions of negative-going 64 Fs clock transitions. In particular, where a word clock and 64 Fs clock transitions positive-going transition coincide, the preceding negative-going transition of the 64 Fs clock is shifted to produce a multiplexed clock signal. <figref idref="DRAWINGS">FIG. 32</figref> schematically illustrates how the multiplexed clock signal is formed in dependence upon the 64 Fs signal and the word clock signal. In <figref idref="DRAWINGS">FIG. 32</figref> the uppermost signal <b>3210</b> is the unmodified 64 fs clock signal used to synchronise the PLL in the receiver, the middle signal <b>3220</b> is the word clock signal used to synchronise PCM data framing in the receiver and the lowermost signal <b>3230</b> is the multiplexed clock signal in which the negative-going transitions have been shifted. The multiplexed clock signal <b>3230</b> is the clock signal that is transferred over the MAC-DSD link. In <figref idref="DRAWINGS">FIG. 32</figref> time is increasing to the right along the horizontal axis. It can be seen that the positive going edge <b>3212</b> of the 64 Fs clock signal coincides with the positive-going edge <b>3222</b> of the word clock signal. Accordingly, the preceding negative-going edge <b>3214</b> of the 64 fs clock signal has been shifted back in time by time t_clkmodthereby reducing the width of that clock pulse (see edge <b>3234</b> of in the multiplexed clock signal <b>3230</b>) whilst the subsequent negative-going transition <b>3216</b> of the 64 fs clock edge has been shifted forwards in time by a corresponding time increment t_clkmod(see edge <b>3236</b> of the multiplexed clock signal <b>3230</b>) thereby increasing the width of the pulse. The negative transition <b>3236</b> after the word clock edge <b>3222</b> is delayed by the same amount that the preceding negative edge <b>3234</b> is advanced. The delay of the subsequent negative-going transition <b>3236</b> is performed by way of compensation to avoid DC content in the signal. DC content in the signal is likely to cause periodic “baseline shift” at the word clock frequency, when the signal is transmitted in an AC-coupled system. Performing this compensation on the clock cycle following the coincidence of the word clock and 64 Fs clock also reduces the Fs/n clock frequency content in the 64 fs signal. This is important, since it is desirable to reduce low-frequency jitter in the received 64 fs clock, which is typically used to feed a PLL circuit to generate an ADC/DAC audio sample clock. The edge offset time (t_clkmod) shown in <figref idref="DRAWINGS">FIG. 32</figref> is exaggerated for ease of illustration. The true time shift will typically be very small, for example, one 2048 fs period (11.07 ns, at Fs=44.1 kHz). Note that the shift or “pulse width deviation” introduced to the clock mux signal shown in <figref idref="DRAWINGS">FIG. 32</figref> does not occur every word clock cycle. Rather the clock pulse width deviation only occurs once every n clk_fs cycles, where n is an integer value controlled by a register. Effectively, introduction of the clock pulse width deviation every n word clock cycles amounts to multiplexing a clock signal of frequency Fs/n with the 64 fs clock. Since the frequency of the sample clock (word clock) is known, all that needs to be communicated by the transmitter is phase information which enables the receiver to reconstitute the word clock signal with a six-bit counter. The counter is reset by the Fs/n signal and incremented by the 64 fs clock. Note that the signal forms of <figref idref="DRAWINGS">FIG. 32</figref> apply to both the transmitter (which generates the multiplexed clock) and receiver (which generates the Fs clock) ends of the connection.

0178<figref idref="DRAWINGS">FIG. 34</figref> schematically illustrates a MAC DSD transmitter <b>3400</b> (the counterpart of the FPGA <b>512</b> in <figref idref="DRAWINGS">FIG. 6</figref>) adapted for transmission of both PCM and DSD data. The MAC DSD transmitter module comprises: a 64 Fs clock generator <b>3410</b>; an Fs sync generator (word clock generator) <b>3420</b>; a clock multiplexer module <b>3430</b>, a counter <b>3440</b>; an S-bit generator <b>3450</b>; an encoding and block construction module <b>3460</b>; an interleaver <b>3470</b>; a FIFO buffer <b>3490</b> and a frame assembler <b>3492</b>.

0179The clock multiplexer <b>3430</b> generates the pulse width deviated clock signal (illustrated in <figref idref="DRAWINGS">FIG. 32</figref>) by shifting certain negative-going edges of the 64 Fs clock signal in dependence upon output from the word clock sync generator <b>3420</b>. The pulse width deviated clock signal is transmitted across the twisted pair cable to the receiver. The counter <b>3440</b>, keeps track of the 64 fs clock signal in order to pre-empt the occurrence of the Fs sync signal. It is necessary to pre-empt the Fs sync signal to facilitate generation of the S-bit in the audio data stream, which is performed by the S-bit generator module <b>3450</b>. Note that the PCM samples are individually labelled with sync markers via the M-bit encoding (see 27-bit PCM audio sample structure of <figref idref="DRAWINGS">FIG. 27</figref>) whereas DSD mode frames rely on a frame flag bit being set in the transmitter and the marker bit of the first sample of the flagged frame being set on entry to the receiver FIFO. The output of the S-bit generation module <b>3450</b> is supplied to the encoding and block construction module where parity bits are generated and padding bits are inserted for PCM mode frames only to construct the 32-bit data blocks of the frame payload (see <figref idref="DRAWINGS">FIG. 18B</figref>). Data blocks from the encoding and block construction module <b>3460</b> are supplied to the interleaver <b>3470</b> which outputs 4-bit nibbles of interleaved data to the FIFO buffer <b>3490</b>. The transmitter FIFO <b>3490</b> bridges the audio clock and link clock (PHY <b>514</b> in <figref idref="DRAWINGS">FIG. 6</figref>) domains of the transmitter. The transmitter FIFO buffer <b>3490</b> is 25 bits wide. Of the 25 bits, 24 bits are associated with 24 respective channels of concurrent DSD or PCM audio samples, the 25th bit being reserved as a synchronisation marker. The 25^thbit indicates whether the corresponding DSD or PCM audio sample occurred simultaneously with an Fs/n clock edge in the transmitter. This is illustrated in <figref idref="DRAWINGS">FIG. 33</figref> which shows five consecutive DSD samples (n−2), (n−2), n, (n+1), (n+2) and their timing relationship with the local 64 Fs clock and the word clock. It can be seen that sample n corresponds in time to the coincidence of the positive going edge of the word clock and 64 Fs clock. Accordingly the positive-going edge of the marker bit coincides with the beginning of DSD sample n. Data is read out from the transmitter FIFO <b>3490</b> in dependence upon the occupancy threshold (as described above with reference to <figref idref="DRAWINGS">FIG. 14</figref>) and supplied to the frame assembler <b>3492</b>. Data from the frame assembler <b>3492</b> is supplied to the PHY of the transmitter. The transmitter start-up procedure differs slightly for PCM mode and DSD mode operations. In PCM mode on start-up, the transmitter starts transmitting as soon as possible. Marked samples are explicitly indicated via the PCM sample subframe ‘M-bit’ encoding. However in DSD mode marked samples are not explicitly indicated but are derived from flag bit <b>1</b> of the frame flags as specified in the table of <figref idref="DRAWINGS">FIG. 30</figref>. Accordingly, on start-up in DSD mode, the transmitter holds-off transmitting the first frame until one of the marked samples (i.e. sample synchronous with Fs/n clock) is available in the FIFO. While the transmitter is in this hold-off state, samples are read-out of the PHY clock side of the FIFO and dropped. When a marked sample becomes available (as indicated by flag bit <b>1</b>), the interleaving, encoding and frame formatting mechanisms are enabled, such that the first sample in the first frame is the marked sample. From this point, frame transmission is governed by the buffer status (to initiate frame assembly) and frame format rules.

0180<figref idref="DRAWINGS">FIG. 35</figref> schematically illustrates a MAC DSD receiver <b>3500</b> (the counterpart of the FPGA <b>526</b> in <figref idref="DRAWINGS">FIG. 7</figref>) adapted for reception of both PCM and DSD data. The MAC-DSD receiver <b>3500</b> comprises: an Fs/n sync detection module <b>3510</b>; an Fs clock generation module <b>3520</b>; a monostable counter <b>3530</b>; a frame receiving and decoding module <b>3540</b>; a FIFO buffer <b>3550</b>; a deinterleaver <b>3560</b>; and a decode/block deconstruction module <b>3570</b>. The Fs/n sync detection module receives the pulse width deviated clock signal from the twisted pair cable and determines the relative phases of the 64 fs clock and the word clock on the basis of this signal. The Fs/n phase information is supplied as input to the word clock generation module <b>3520</b>, which outputs the word clock (Fs) signal.

0181The incoming cable clock signal is passed directly to the local phase locked loop of the receiver system in order to synchronise the system. It is not possible to use the extracted Fs clock derived from the word clock generation module <b>3520</b> for this purpose. This is because the word clock generation module <b>3520</b> requires sequential logic that is clocked form the local PLL so that the extracted signal is always synchronous wit the local PLL. This means that the output of the word clock generation module <b>3520</b> is unsuitable as a synchronisation source for the PLL.

0182Note that the Fs clock signal in the receiver is of the same phase as the Fs clock signal in the transmitter as a result of the Fs/n sync. The Fs/n phase information is also supplied to the monostable counter. The monostable counter is triggered by reception of each Fs/n indication to count 64 fs clock periods. The FIFO output is disabled on detection of the first marked sample in the FIFO <b>3550</b>, whereupon the FIFO begins to fill with data. After a number of 64 fs cycles equal to the predetermined link latency, the FIFO <b>3550</b> outputs are enabled. The predetermined link latency incorporates the delay incurred in the transmitter due to data encoding and frame assembly plus the delay incurred at the receiver due to the decoding process. The predetermined latency of the data link is programmed to be an exact multiple of 64 fs clock periods measured with respect to the Fs/n sync signal transmitted on the cable clock.

0183MII frames (comprising nibbles) from the PHY <b>526</b> of the receiver (see <figref idref="DRAWINGS">FIG. 7</figref>) are supplied as input to the frame reception and decoding module, where header data is removed, and error checks are performed. The decoded data is supplied as input to the FIFO <b>3550</b> in the form of MII nibbles. The FIFO outputs 4-bit data nibbles, which are supplied to the deinterleaver <b>3560</b> for deinterleaving. The deinterleaved data is then fed to the decode/block deconstruction module <b>3570</b> where the audio data payload data is extracted and output as an audio data stream.

0184<figref idref="DRAWINGS">FIG. 36</figref> schematically illustrates a system in which two sample-synchronous links are operated in parallel and in which the Fs/n sync signal is used to synchronise the parallel links. The system comprises a transmitting device <b>3600</b> which is connected by a first cables <b>3603</b> and a second cable <b>3605</b> to a receiving device. The transmitting device <b>3600</b> has a first MAC-DSD transmitter <b>3610</b> which is connected to a first MAC-DSD receiver <b>3710</b> in the receiving device <b>3700</b> via the first cable <b>3603</b>. The transmitting device <b>3600</b> also has a second MAC-DSD transmitter <b>3620</b> which is connected to a second MAC-DSD receiver <b>3720</b> in the receiving device <b>3700</b> via the second cable <b>3603</b>. The two MAC-DSD transmitters <b>3620</b>, <b>3620</b> are driven by an internal clock source <b>3630</b> that supplies them with both a 64 Fs clock and a word clock. In the receiving device <b>3700</b> only the first MAC-DSD receiver <b>3710</b> acts as a clock source thereby serving as a master clock. This receiver <b>3710</b> derives the word clock signal and the 64 Fs clock signal from the multiplexed clock signal received via the first cable <b>3603</b>. Note that if a separate word clock source were used then neither of the MAC-DSD receivers <b>3710</b>, <b>3720</b> would serve as a master clock source. The 64 Fs and word clocks extracted from the link cable <b>3603</b> are supplied to a PLL <b>3730</b> that outputs a word clock signal and a 64 Fs clock signal to both the first MAC-DSD receiver <b>3710</b> and the second MAC-DSD receiver <b>3720</b>. The second MAC-DSD receiver <b>3720</b>, which is not serving as the master clock source, should re-clock the multiplexed clock signal received via the second cable <b>3605</b> in order to detect the Fs/n indicator (i.e. the clock pulse width deviation). The propagation delay on the link via the first cable <b>3603</b>, is likely to be different from the propagation delay on the link via the second cable <b>3605</b>. The difference in propagation delay between the first link <b>3603</b> and the second link <b>3605</b> is determined by comparing the position of the received 64 fs clock edges with the locally-regenerated 64 fs clock (from PLL <b>3730</b>), and by comparing the position of the received Fs/n indicator with the locally-regenerated Fs word clock, (also from PLL <b>3730</b>). <figref idref="DRAWINGS">FIG. 37</figref> schematically illustrates a measured difference in propagation delay between the two links. It can be seen from <figref idref="DRAWINGS">FIG. 37</figref> that the positive-going clock edge <b>3812</b> immediately following the shifted negative-going clock edge (pulse width deviated pulse) in the clock multiplexed signal <b>3810</b> is shifted relative to the corresponding positive-going clock edge of the locally regenerated 64 Fs clock signal <b>3822</b> and relative to the positive edge <b>3832</b> of the locally regenerated word clock signal <b>3830</b> by an amount t_offset. In particular, the received cable clock Fs/n indicator occurs later in time than the local Fs clock edge. Given that the local Fs clock edge is derived to be synchronous with the received cable clock Fs/n indicator on the clock master MAC-DSD link, this indicates that the cable propagation delay for the second link <b>3605</b> is longer than the cable propagation delay for the clock master link <b>3603</b>. The relative difference in propagation delay between the clock master link <b>3603</b> and the other link <b>3605</b> is t_offset. The time t_offsetis defined to be negative in the case that the non-master link <b>3605</b> is delayed relative to the clock master link <b>3603</b> as shown above, and positive in the case that the non-master link <b>3605</b> is advanced relative to the clock master link.

0185Once t_offsetis determined at the receiver, the following algorithm must be followed to adapt the latency monostable counter <b>3530</b> of the receiver to ensure synchronous operation with the clock master link. If t_offsetis positive (i.e. non-master link <b>3605</b> is advanced in time relative to clock master <b>3603</b> link) then when the Fs/n indicator is detected via link <b>3605</b> the latency monostable counter in MAC_DSD receiver <b>3720</b> is not started until the next word clock edge. However, if t_offsetis negative (i.e. non-master link <b>3605</b> is delayed relative to master link <b>3603</b> as in <figref idref="DRAWINGS">FIG. 37</figref>) t_offsetis rounded down to an integer number of 64 fs periods and one is subtracted from this value to derive a value for the timeout for the non-master latency monostable counter. The latency monostable counter in MAC-DSD <b>3720</b> (non-master) is started at the first 64 Fs clock edge following the timeout. This will result in the non-master latency monostable counter timing out synchronously with the monostable counter in the clock master receiver.

0186If the predetermined link latency period expires before a marked sample is detected in the FIFO <b>3550</b> this is an indication that either there is a fault in the system or that the predetermined link latency has been set at too small a value for the link conditions. Accordingly, if the latency period expires before the marked sample is detected an interrupt signal is raised and error indicator bits are set. Table 10 below specifies for each of seven audio data formats an example link latency in 64 Fs periods and in microseconds. <tables id="TABLE-US-00012" num="12"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="14PT" align="left" /><colspec colname="1" colwidth="63PT" align="left" /><colspec colname="2" colwidth="70PT" align="left" /><colspec colname="3" colwidth="70PT" align="center" /><thead><row><entry /><entry namest="OFFSET" nameend="3" align="center">TABLE 10</entry></row><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>Audio format</entry><entry>Latency (64fs periods)</entry><entry>Latency (μs)</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="14PT" align="left" /><colspec colname="1" colwidth="63PT" align="left" /><colspec colname="2" colwidth="70PT" align="left" /><colspec colname="3" colwidth="70PT" align="char" char="." /><tbody valign="top"><row><entry /><entry>DSD</entry><entry>127</entry><entry>44.9</entry></row><row><entry /><entry> 44.1 kHz PCM</entry><entry>192 (3 samples)</entry><entry>68</entry></row><row><entry /><entry>  48 kHz PCM</entry><entry>192 (3 samples)</entry><entry>62.5</entry></row><row><entry /><entry> 88.2 kHz PCM</entry><entry>160 (5 samples)</entry><entry>56.6</entry></row><row><entry /><entry>  96 kHz PCM</entry><entry>160 (5 samples)</entry><entry>52.1</entry></row><row><entry /><entry>176.4 kHz PCM</entry><entry>144 (9 samples)</entry><entry>51.0</entry></row><row><entry /><entry>  192 kHz PCM</entry><entry>144 (9 samples)</entry><entry>46.9</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0187<figref idref="DRAWINGS">FIG. 38</figref> is a schematic diagram showing auxiliary data routing by a MAC-DSD router <b>4030</b>.

0188The router comprises a number of MAC-DSD transceivers <b>4000</b>, each of which is arranged as described above to transmit auxiliary data and audio data via an Ethernet physical layer device, and, on receiving such a bit stream, to separate out the audio data and auxiliary data streams. It should be noted that audio data routing and handling is not shown in <figref idref="DRAWINGS">FIG. 38</figref>.

0189In order to transmit auxiliary data over this system, the auxiliary data is formatted into Ethernet-like packets and the packets are then multiplexed into the two auxiliary data channels in the MAC-DSD protocol.

0190Non-limiting examples of the types of auxiliary data that might be carried are remote control data for recording and playback functions; general remote control data for audio and video devices; timecode; media content metadata; and auxiliary media, such as streamed compressed video images to accompany an audio feed for audio-visual production.

0191When a bit stream is received by one of the transceivers <b>4000</b>, the auxiliary data bit stream is separated out and supplied to an auxiliary data bit stream-RMII interface <b>4010</b>. RMII stands for Reduced Media Independent Interface, and is established as a standard arrangement within Ethernet systems, but it will be appreciated that other interfaces such as MII (media independent interface), SMII (serial media independent interface) and SS-SMII (source-synchronous serial media independent interface), which are all widely supported and used in multi-channel Ethernet PHY interfaces, could be used. The functionality of all of these is broadly equivalent; they just offer different trade-offs in pin-count reduction versus logic complexity.

0192As described above, the auxiliary data is carried as periodic single bits, or small groups of bits, interspersed amongst the audio data bits.

0193The RMII interface <b>4010</b> converts the auxiliary data bit stream from the two channels within the MAC-DSD protocol back into data packets which are set up so as to mimic Ethernet protocol data packets. The data packets have a packet address specifying another one of the MAC-DSD transceivers (or, in the case of a “broadcast” message, all of them).

0194The pseudo-Ethernet packets are supplied to a conventional Ethernet switch circuit <b>4020</b> which effects the routing on the basis of the packet addresses. In accordance with that routing, the packets are passed back to the auxiliary bit stream-RMII interface <b>4010</b> to be formatted back into an auxiliary data channel format for carriage by the appropriate MAC-DSD channel. From the interface <b>4010</b> the auxiliary data is passed to the appropriate one(s) of the transceivers <b>4000</b>.

0195<figref idref="DRAWINGS">FIG. 39</figref> is a schematic diagram showing a protocol by which the auxiliary data is carried.

0196At the bottom of <figref idref="DRAWINGS">FIG. 39</figref> there is shown the Ethernet physical interface layer (PHY). This layer is common between the protocol shown in <figref idref="DRAWINGS">FIG. 39</figref> and a standard Ethernet protocol. Physical layer data frames are prefixed only by a preamble.

0197On top of the physical layer there is imposed the MAC-DSD frame format made up of 1448-byte frames as described above. Over this, the payload encoding provides twenty-six 64 Fs channels (bit streams) with forward error correction and interleaving. It will be clear that the choice of the number of such channels is merely an implementation detail.

0198Again, as described above, the payload can include an audio bit stream, for example in DSD or PCM format and an auxiliary data bit stream. In the case of the auxiliary data, 512-byte frames are demarcated in the continuous 128 Fs bit stream forming the two auxiliary data channels. Within those 512-byte frames, there is defined an Ethernet data frame format. (512 bytes is just an example frame length used in a first implementation. Other implementations can use different frame lengths, at least up to 1536 bytes, which is the maximum frame length for conventional Ethernet transmission).

0199So, the system carries frames which, when separated out from the rest of the physical bit stream, appear to be Ethernet auxiliary data frames. However, they are not carried by a conventional Ethernet protocol, but instead are carried by being inserted into the 128 Fs bit stream forming the two auxiliary data channels. So, the pseudo-Ethernet frames are transmitted as successive auxiliary data bits interspersed within an audio data bit stream. They would not be directly recognisable as Ethernet frames by a conventional Ethernet data handling device.

0200<figref idref="DRAWINGS">FIG. 40</figref> schematically illustrates a data structure of an auxiliary data frame. The structure comprises a fixed header <b>4040</b>, a destination address <b>4050</b>, a length field <b>4060</b>, a payload <b>4070</b> and an error detecting code <b>4080</b>. The total length of the frame in this embodiment is a maximum of 128 words, which equates to 512 8-bit bytes.

0201<figref idref="DRAWINGS">FIG. 41</figref> schematically illustrates the operation of the interface <b>4010</b> and the switch <b>4020</b> of <figref idref="DRAWINGS">FIG. 38</figref> in a data receiving mode.

0202The 128 Fs auxiliary data bit stream, comprising the two logical channels of auxiliary data separated out by the MAC-DSD transceiver <b>4000</b>, is supplied to a frame identifier <b>4100</b>. Frames are identified in the auxiliary data stream by a synchronisation flag comprising 01111111110 (a zero, nine ones, a zero). The frame is then transmitted serially. To ensure the uniqueness of the synchronisation flag, a zero is inserted (on transmission) after any eight consecutive ones of the frame data—so the occurrence of nine consecutive ones can only indicate a synchronisation flag. The extra zero is inserted irrespective of the bit following the run eight ones. At the end of the frame, another synchronisation flag is transmitted. During intervals when a frame is not being transmitted, the bit stream comprises contiguous synchronisation flags.

0203Therefore, at the frame identifier <b>4100</b>, incoming data is examined to detect the presence of nine consecutive ones, thereby indicating a frame synchronisation flag.

0204The data is then passed to a descrambler <b>4110</b>. To put the descrambler into context, the reason for scrambling the data in the first place will now be described.

0205Certain data payloads which feature frequent long strings of ones could cause the system to insert large numbers of additional zeros, with a correspondingly large increase in the amount of data to be sent. This in turn could cause a very non-deterministic reduction in the effective bandwidth of the system. This may be mitigated by scrambling the data with a convolutional encoder before the bit stuffing (insertion of extra zeroes) is carried out. In this case, the expansion from the insertion of extra zeroes will be reduced to a factor of approximately 1/(2⁸) (1 bit in 256, or 0.39%).

0206The scrambling encoder is schematically illustrated in <figref idref="DRAWINGS">FIG. 43</figref> and the corresponding decoder in <figref idref="DRAWINGS">FIG. 44</figref>.

0207The encoder contains a 9-bit shift register and XOR gates, so that with an input V and an output W it implements: <br /><i>W=V*W</i>⁻⁵<i>*W</i>⁻⁹

0208The descrambling circuit of <figref idref="DRAWINGS">FIG. 44</figref> again comprises a nine bit-shift register and XOR gates, so that with an input Y and an output Z it implements: <br /><i>Z=Y*Y</i>⁻⁵<i>*Y</i>⁻⁹

0209Note that neither the scrambler nor the descrambler imposes a delay upon the signal. Thus a cascade of the scrambler and descrambler imposes no algorithmic delay.

0210Therefore, at the descrambler <b>4110</b> (returning to <figref idref="DRAWINGS">FIG. 41</figref>) any additional zeroes (i.e. a zero after a run of eight ones) are first removed and then the data is descrambled using the descrambler of <figref idref="DRAWINGS">FIG. 44</figref>.

0211The resulting descrambled data is then passed to a dual port random access memory (DPRAM) <b>4120</b>. This contains two storage areas, each large enough to hold at least a single data packet. Data is written into one storage area while it is being read out of the other, and then vice versa. When substantially all of a packet has been loaded into one side of the DPRAM, and assuming that the channel protocol allows it at that instant (see below), the packet of data is read out by an RMII interface <b>4130</b>. The data is passed from the RMII interface <b>4130</b> to the Ethernet switch circuit <b>4020</b>. The way in which this is achieved will be described below.

0212Referring to <figref idref="DRAWINGS">FIG. 42</figref>, when a data packet is received by the RMII interface from the Ethernet switch chip <b>4020</b>, it is stored in a further DPRAM <b>4200</b>. As a packet of data is assembled in the DPRAM <b>4200</b>, it is passed to a scrambler (as <figref idref="DRAWINGS">FIG. 43</figref>) which includes a bit stuffer to add a zero after a run of eight ones in the scrambled data stream, and from there to a frame marker <b>4220</b> which inserts the frame synchronisation code 01111111110. The resulting bitstream is then transmitted within the auxiliary data channels of a MAC-DSD link.

0213The Ethernet switch chip <b>4020</b> and the RMII interface <b>4130</b> both operate under the control of an RMII interface synchronisation signal, for example a clock source <b>4140</b> running at 50 MHz. In other embodiments, however, the implementation may be simplified by running the RMII interface and the Ethernet switch chip at a non-standard rate such as a clock rate synchronous with the audio master clock. In such arrangements the clock source <b>4140</b> would be replaced by a clock generator receiving as an input the 64 Fs clock signal (or a signal related to it) shown in, for example, FIGS. <b>6</b> to <b>10</b> above.

0214The transmission protocol used between the RMII interface <b>4130</b> and the Ethernet switch circuit <b>4020</b> is the so called 100 Base-T half duplex system. This is a 100 Mbit/s arrangement in which only one of the parties to the communication can transmit at any one time. So, although the transmission can be bi-directional (to or from the Ethernet switch circuit <b>4020</b>), the data transfer can occur in only one of the two directions at any one instant. The reason that the 100 Base-T half duplex system is used will now been explained.

0215The incoming data rate from the MAC-DSD transceiver (as received by the frame identifier <b>4100</b>) is 128 Fs, or about 5.6 Mbit/s. This is therefore the maximum speed at which data packets need to be transmitted from the RMII interface <b>4130</b> to the Ethernet switch chip <b>4020</b>. It is also the maximum speed at which data can be sent from the Ethernet switch chip to the RMII interface for retransmission via a MAC-DSD transceiver <b>4000</b>. But in a system having several nodes connected via a single router, it is quite possible that multiple packets could be routed to a single output MAC-DSD channel at a certain time. This could in principle mean that the Ethernet switch chip might attempt to send data to a single RMII interface at a data rate greater than 5.6 Mbit/s.

0216The Ethernet switch chip <b>4020</b> is a standard Ethernet device. This is considered desirable because such devices are cheap and they contain logic for avoiding various types of transmission or reception faults. However, a 100 Base-T Ethernet switch chip does not contain logic for dealing with an output channel limited to a streamed data rate of 5.6 Mbit/s.

0217So, to avoid this problem happening, it is important that the RMII interface can regulate the flow of data which it receives from the Ethernet switch chip <b>4020</b>. This is carried out using the half duplex arrangement.

0218In basic terms, an RMII interface can assert a signal referred to as “RMII CRS_DV”, or the carrier sense signal, to indicate that it is going to send data to the Ethernet switch circuit <b>4020</b>. Assertion of this signal by one party allows the other communicating party to complete the transmission of a current frame but not to start transmission of a next frame. This arrangement is modified in the present embodiment so that the RMII CRS_DV signal can be asserted in one of two ways. Referring to <figref idref="DRAWINGS">FIG. 46</figref>, an OR gate combines two signals which can be asserted by the RMII device. One is a frame generator CRS_DV, which is a conventional carrier sense signal which is asserted only when a frame is to be transmitted, and the other is a signal referred to as RMII_lock.

0219RMII_lock is used as a “false” carrier sense signal to prevent the Ethernet switch chip transmitting any data to the RMII device. It is used at times when the RMII device or further downstream devices are not ready to receive any more data. The way in which RMII lock is asserted will be described with reference to <figref idref="DRAWINGS">FIG. 46</figref>.

0220<figref idref="DRAWINGS">FIG. 46</figref> is a state diagram illustrating states entered by the RMII device <b>4130</b>.

0221Starting from an idle state <b>4300</b>, if more than 450 bytes have been received from a MAC-DSD transceiver for onward transmission to the Ethernet switch chip, then RMII_lock is asserted (a state <b>4310</b>). This in turn asserts RMII CRS_DV. If the Ethernet switch chip is transmitting data back to the RMII device at that point, it is allowed to finish its current frame but not to start transmitting a new frame. However, because the Ethernet switch chip is running at 100 Mbit/s, higher than the data rate of all (or at least some in other embodiments) of the MAC-DSD transceivers, asserting RMII_lock when the input data reaches 450 bytes still allows time for the Ethernet switch chip to finish sending an entire frame back to the RMII device.

0222Then, when the input memory reaches an occupancy greater than 486 bytes, the RMII device transmits the data to the Ethernet switch chip (a state <b>4320</b>). The threshold of 486 bytes is chosen with reference to a comparison of the two data rates of 5.6 Mbit/s and 100 Mbit/s, so that by the time that the frame has been almost fully transmitted to the Ethernet switch chip, the remainder of that frame should have arrived in the DPRAM. The RMII interface then returns to the idle state.

0223As soon as the input memory is less than 450 bytes full or the output memory is less than 486 bytes full, and the device is in the idle state, then RMII_lock is de-asserted (state <b>4330</b>).

0224On the receiving side, if data is received from the Ethernet switch chip (state <b>4340</b>) and the reception has been completed, RMII_lock is asserted (state <b>4350</b>) and the device returns to the idle state. As mentioned above, RMII_lock is not de-asserted until the memory starts to empty of the data which has been received from the switch circuit.

0225The invention may be embodied in software, programmable hardware (e.g. FPGA, ASIC), hardware or a combination of these. In the case of a software component, the invention also includes a providing (e.g. storage, transmission) medium by which such software is provided.

0226Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.