Digital transmission of audio signals

The present invention relates to data communication.

Direct Stream Digital (hereinafter referred to as DSD) is a high-resolution 1-bit audio coding method used for consumer disc formats called Super Audio CDs. The DSD signal can achieve a frequency response from DC to 100kHz and have a dynamic range of 120dB or more over the audio band.

DSD uses 1-bit digital audio and is 64F_sRequires a high frequency audio sampling clock of 2.8224MHz (standard pulse code modulation schemes require a sampling clock (F)._s) Is 44.1kHz). This high frequency sampling clock is transmitted to the receiving side along with the data so that an accurate signal on the receiving side can be facilitated. Furthermore, 64F_sEach channel of DSD audio requires a transmission bandwidth of 2.8224MHz.

Several audio network systems are known that utilize Ethernet® to transmit wideband audio data between networked audio processors. For example, Gibson's "Magic" system utilizes Ethernet's Media Access Control (MAC) layer (ie, physical layer and link layer) at 1 per sample period. It uses Ethernet frames to transmit audio data at a fixed audio sampling frequency of 48kHz. Peak Audio (Peak) Audio)'s CobraNet (trademark) audio network system also uses the Ethernet MAC layer to transmit uncompressed digital audio data between network devices. The Cobranet system uses a sampling rate of 48kHz and enables the transmission of 20-bit and 24-bit audio data. However, no system suitable for interconnecting DSD audio equipment is known. This is because the Ethernet frame timing is completely unsuitable for DSD's 2.8224MHz sampling clock.

At the same time, pending US patent applications Nos. 10 / 620,671 and 10 / 803,621 disclose techniques for transmitting such bitstreams through the physical layer of Ethernet-type interfaces. These two patent documents are circuit-switched between large-scale multi-track playback equipment for DSD audio such as multi-channel A / D and D / A converters, DSD mixers, and multi-channel DSD recorders. The purpose is to realize interconnections).

Therefore, the techniques presented in these two patent documents are based on the direct use of Ethernet physical layer interfaces. Such a method is 64F_sIt is possible to provide an efficient and low delay circuit switching link at an audio data rate of an order of magnitude, and this method is also useful for the transmission of other digital signal streams, such as PCM audio signals. Auxiliary data channels can be handled in a similar manner. However, this effect is achieved by deliberately avoiding the use of higher levels of the Ethernet protocol, making it difficult for such schemes to provide auxiliary data routing by packet switching. ..

<p> The present invention is a data communication system that communicates one or more streamed payload data signals with auxiliary data signals configured as one or more data packets, each based on a data packet protocol, each having a packet destination address. There are at least two data processing nodes, including (1) a receiving node and a transmitting node that sends data to the receiving node over a data communication link, and (2) related to the transmitting node, of auxiliary data signals. Related to the transmit data formatter, which formats the data packet into the format of the streamed data signal and multiplexes the streamed payload data signal and the formatted auxiliary data signal into a bit stream for transmission, and (3) the receiving node. Provided is a data communication system including a received data reformatter that separates the input streaming data signal and the formatted auxiliary data signal and reformates the auxiliary data signal into a packet based on the data packet protocol.</p><p> The present invention also receives a data stream containing data packets associated with destination instruction information via two or more input / output channels, each associated with the highest data rate, and in each destination instruction information. Based on, a data router that sends each packet to one or more input / output channels, with an Ethernet router and a routing interface associated with each input / output channel, the routing interface and the Ethernet router being individual inputs. Communicating at a data rate higher than the highest data rate associated with at least some of the output channels, the routing interface receives data packets received through the data stream associated with that input / output channel as Ethernet data packets. The routing interface receives data packets that are output from the Ethernet router through the corresponding I / O channel and goes through the I / O channel at a data rate that is not higher than the channel's highest data rate. Outputting data packets, the routing interface and the Ethernet router work together to provide a data router that selectively blocks the transfer of data packets from the Ethernet router to the routing interface so that the maximum data rate of the channel is not exceeded. ..</p><p> Various other aspects and features of the invention are described in the appended claims.</p><p> The present invention solves the above problems by embedding packetized auxiliary data in a streamed payload signal and using a standard (eg Ethernet) router on the receiving side to separate the packets into a format suitable for routing. Solve.</p>

As mentioned above, some well-known audio network systems use the Ethernet data link layer to transmit uncompressed digital audio data with a standard sampling frequency of about 48 kHz. On the other hand, in the present invention, high frequency (2.8224MHz) digital audio data is transmitted using the physical layer of high-speed Ethernet that provides a point-to-point connection. The advantage of using the high-speed Ethernet physical layer for audio data transmission is that the physical layer has a large bandwidth, electromagnetic compatibility is guaranteed, and it already has an error detection function (Cyclic Redundancy Check). .. By using the physical layer, a logic circuit can be easily designed and realized. If the audio data is encoded by the technology of the higher layer (for example, MAC layer), the hardware that handles and realizes the windowing protocol is required, and it is necessary to consider such hardware in the present invention. Absent. In addition, Ethernet data transmission at the physical layer level is robust and has a controlled spectrum, resulting in less electromagnetic radiation.

In order to clarify the principle in which the embodiments of the present invention operate, first, the layer structure of the network protocol architecture and the lower layers of the Ethernet architecture will be described in detail.

Figure 1 shows a standard 7-tier Open Systems Interconnection (OSI) reference model for network protocol architectures. This OSI reference model includes an application layer 270, a presentation layer 260, a session layer 250, a transport layer 240, a network layer 230, a data link layer 220, and a physical layer 210.

The application layer 270, in the form of an application program, provides a user interface to a predetermined range of information services distributed over the network. Services provided by this layer include file transfer, file access, file management, and the exchange of general-purpose documents or messages such as e-mail.

Presentation layer 260 relates to the representation of data when transferring data between two communication application processes. For example, presentation layer 260 chooses the appropriate transfer syntax to use during a transaction so that the structure of the messages exchanged between the two application entities is maintained. The presentation layer 260 also manages data encryption and compression.

Session layer 250 establishes a session between communication applications on a communication network node. The session layer 250 can also provide an interaction management function during bidirectional alternating, i.e., half-duplex (bidirectional simultaneous, i.e. not full-duplex) data exchange. In addition, the presentation layer 250 can also provide features such as very long network transaction synchronization and exception reporting.

The transport layer 240 acts as an interface between the upper application-oriented layers (session layer 250, presentation layer 260, application layer 270) and the lower network-dependent protocol layers 210, 220, and 230. The transport layer 240 provides the session layer 250 with a defined set of message forwarding functions. Transport layer 240 is suitable for each of the various types of networks, ranging from class 0, which provides basic connection establishment, to class 4, which provides complete error and flow control. Provide a class of service.

All three layers below the OSI reference model (network layer 230, data link layer 220, and physical layer 210) are network-dependent layers. Network layer 230 has the ability to establish and release connections between two transport layer protocol entities, and supports network routing and addressing. The data link layer 220 provides a highly reliable information transfer function, and also provides functions such as error detection and message retransmission. In many cases, both connectionless and connectionless services are provided. The connectionless service simply deletes the received frame in which an error is detected, while the connectionless service aims to provide an error-free information transfer function. The physical layer 210 provides the data link layer 220 with a means of transmitting a serial bitstream between the two devices. That is, the physical layer 210 converts the data into a stream of electrical pulses, ie analog pulses, that are actually transmitted through the transmission medium, and monitors the transmission of the data.

Ethernet is a type of local area network (LAN) technology that uses simple or branched bus-type connection lines. The transmission medium in an Ethernet network is formed from one or more continuous lines of cables connected by a hub. Network devices are connected to this cable and compete for network access using the Carrier Sensing Multiple Access with Collision Detection (CSMA / CD) protocol. In the CSMA / CD protocol, all client devices monitor the transmission medium, wait for the transmission line to become available, and then begin sending messages. Conflicts occur when two network nodes try to send a message at the same time. In this case, the client device stops transmission, waits for a randomly determined time, and tries to transmit again.

The standard Ethernet method, known as 10BASE-T, delivers transfer rates up to 10 megabits per second (Mbps), while the "fast Ethernet (or 100BASE-T)" method delivers transfer rates up to 100 Mbps. To. Higher performance methods such as so-called "Gigabit Ethernet" can also be used. High-speed Ethernet uses the same wiring system, media access control (hereinafter referred to as MAC) method and framing method as 10BASE-T Ethernet. In the present invention, any kind of network technology among these may be used.

The Ethernet method may use a twisted pair cable connection or an optical fiber connection. Twisted pair cable is a standard copper wire commonly used to connect a computer to a telephone line. In twisted pair cable, two or more insulated wires are twisted together to reduce crosstalk or electromagnetic induction between the pairs of wires. By twisting the wires in this way, the effective radiation region of the cable becomes smaller. This is because the electromagnetic effect of the alternating stranded wires is canceled at a distance greater than the stranded wire pitch. Each twisted pair connection requires two wires. When a twisted pair is shielded by a shield that functions as a ground, this twisted pair is called a shielded twisted pair (hereinafter referred to as STP). A standard twisted pair is called an unshielded twisted pair (hereinafter referred to as UTP).

In the high-speed Ethernet system, the segment length of the twisted pair cable segment is set to a maximum of 100 m to ensure that the signal round-trip timing specifications are satisfied. In high-speed Ethernet, the problem is how to achieve a data transfer rate of 100 Mbps using unshielded twisted pair (UTP). In reality, there are two standards to achieve this transfer rate. One (100BASE-4T) uses a voice-grade category 3 cable, and the other (100BASE-X) uses a high quality category 5 UTP cable, shielded twisted pair cable (100BASE-TX) and fiber optics. Use one of (100BASE-FX). In the 100BASE-X system, each type of transmission medium depends on a different physical medium (Physical Medium). Dependent: Hereafter referred to as PMD. ) Requires a secondary layer. Category 5 UTP consists of four pairs of signal lines, two of which are typically used for Ethernet, for example one signal pair for clock transmission and reception and the other signal pair for data transmission and reception. Will be done. In this case, two pairs of unused signal lines remain.

Figure 1 shows the Ethernet physical layer and data link layer sublayers next to the 7-tier OSI reference model.

The data link layer 220 includes a media access control (hereinafter referred to as MAC) layer 224 and a logical link control (hereinafter referred to as LLC) layer 222. The physical layer 210 includes a reconciliation sublayer 219, a medium dependent interface (hereinafter referred to as MII) 218, a physical coding sublayer 216, a physical medium connection sublayer 214, and a physical medium dependent sublayer. It has a layer (Medium Dependent Interface: hereinafter referred to as MDI) 211.

MAC sublayer 224 has two main functions: data encapsulation and medium access control. The data encapsulation function includes functions such as data framing, processing of source and destination addresses, and detection of physical medium transmission errors. The media access management function includes media allocation (collision avoidance) and conflict resolution (collision processing) functions.

The MAC sublayer 224 can operate in either half-duplex mode or full-duplex mode. In half-duplex mode, network nodes use a multiple access (CSMA / CD) algorithm to compete for the use of physical media. In full-duplex mode, transmission and reception can be performed at the same time without interference. When using full-duplex mode, three conditions must be met. First, the physical medium needs to support transmission and reception at the same time without interference. Second, there must be exactly two nodes on the local area network so that the physical medium can be considered a full-duplex point-to-point link between the nodes. In the case of this full duplex, there is no conflict regarding the use of shared media, so there is no need to use the CSMA / CD algorithm. The third condition is that both nodes must be configured to operate in full-duplex mode.

Logical link control (LLC) layer 222 performs error checking on data frames and manages links between communication network nodes. The Reconciliation sublayer 219 maps the signal set provided in the media independent interface 218 to the physical coding sublayer 216.

The Physical Coding Sub-layer (hereinafter referred to as PCS) 216 provides the arbitration sub-layer 219 with the same interface for executing all 100BASE-TX physical layer entities (PHYs). The PCS216 provides all the services required by the MII218, which are encoded from the MII's 4-bit "data nibbles" into 5-bit code groups (and 5-bit codes to data nibbles). Serialization of code groups (and from PMA sublayer 214) for decoding to), generation of carrier sensing and collision detection instruction information, transmission to lower PMA (Physical Medium Attachment: PMA) sublayer 214 Code group deserialization for reception), transmission between MII218 and lower PMA sublayer 214, reception, carrier sensing and collision detection mapping, etc.

Physical Medium Attachment (PMA) sublayer 214 provides the PCS216 with a medium-independent function to support the use of a range of physical media. The 100BASE-TX PMA sublayer 214 has functions such as mapping transmission and reception code bits between the lower Physical Medium Dependent (PMD) sublayer 212 and PCS216, and generating control signals to inform PCS216 of the availability of PMD212. Fulfill. In addition to these, the PMA sublayer 214 generates a signal indicating a carrier error from the lower PMD sublayer 212, detects a receive channel fault, and transmits far-end fault indications to the far end. You may.

The PMD sublayer 212 is effectively a set of signaling standards that define a 125 Mbps full-duplex signaling scheme, which includes multimode optical fiber (F), shielded twisted pair (STP), and unshielded twisted pair ( UTP) wiring is included.

The purpose of the Medium Independent Interface (MII) 218 is to provide a simple interconnect for 10 Mbps and 100 Mbps data transfer between the LLC sublayer 222 and MAC sublayer 224 and the physical layer entity (PHY). .. This function is the same for both data transfer rates, as is the signal timing relationship. The only difference between 10Mbps and 100Mbps operation is the difference in nominal clock frequency. The MII218 is used to achieve independence from a variety of media including unshielded twisted pair wiring, shielded twisted pair wiring, fiber optic cabling and other possible media, thereby any of these media. In this case, the same MAC can be used. The MII218 maximizes media independence by completely separating the data link layer 220 and the physical layer 210 of the 7-layer OSI reference model. The MII218 data and delimiters are synchronized to the clock reference, and the MII218 is a low voltage transistor-transistor logic circuit (Low) compatible with common integrated circuit processes. Voltage Transistor-Transistor Logic: Hereafter, it is called LVTTL. ) Signal level is used. The MII218 provides an independent 4-bit wide data transmit and receive path and full-duplex operation. A 7-bit signal consisting of a 4-bit data bundle, a 1-bit delimiter signal, a 1-bit error signal, and a 1-bit clock signal is supported for each direction of data transfer.

Figure 2 shows a well-known system for Direct Stream Digital (DSD) signal transmission. The system 300 includes an analog / digital converter and a digital / analog converter (A / D and D / A converter) 310, and a DSD multi-channel recorder 320 connected to the A / D and D / A converter 310. To be equipped. This connection is made by two independent cables. The first cable 315 is an optical fiber that transmits eight channels (about 22.6 Mbps) of DSD audio data, and the second cable 325 transmits a high frequency sampling clock. It is customary in standard studios to use separate cables for audio data and sampling clocks.

An example of DSD interconnection based on the present invention is shown in FIG. In this configuration 400, a single cable 405 is used to connect the multi-channel A / D and D / A converter 410 to the DSD multi-channel recorder 420. Cable 405 is a Category 5 unshielded twisted pair cable. The cable 405 has four pairs of signal lines, two of which are used to transmit and receive audio data encoded using Ethernet physical layer technology, and the remaining two pairs are links. It is used to transmit the DSD sampling clock in both directions via (see Table 1 below). The clock signal and audio data are specified to reduce the possibility that interference between the two signals will degrade the quality of the clock signal. The clock signal is the receiver's phase locked loop. loop: Hereinafter referred to as PLL. ), And can also be used as a sampling clock for A / D converters and D / A converters. When jitter occurs in the sampling clock, any jitter in the sampling clock is undesirable because the jitter manifests itself as distortion in the playback analog audio output signal. Audio signals are inherently digital signals and are therefore more robust to degradation than clock signals. Packet data transmission systems such as Ethernet can transmit DSD audio data. In this particular embodiment, the physical layer of Fast Ethernet (100BASE-TX) is used to achieve a channel bit rate of 100 Mbps that allows 32 DSD channels to be transmitted over a single link. As another embodiment, 24 DSD channels may be transmitted over a single link using a 100 Mbps link.

Ethernet is an asynchronous data link and therefore 64F_sIt is essentially unsuitable for transmitting audio clock signals with high integrity. Therefore, the audio sampling clock is transmitted as an independent signal pair for a category 5 UTP cable.

The single cable connection shown in Figure 3 is basically a point-to-point link that connects two audio devices directly. This connection uses a special "crossover" Category 5 cable that is wired to reverse the I / O connection. For example, the conventional crossover cable used for an office network or the like does not reverse the two pairs of signal line connections used for transmitting the audio sampling clock in the embodiment of the present invention, so a custom-made crossover cable is used here. is necessary. For example, in another embodiment of the invention shown in FIG. 4, more complex interconnections can be made between a plurality of individual devices in a DSD facility. The system shown in FIG. 4 includes a star-configured DSD router 430, a multi-channel A / D and D / A converter 440, a DSD mixer 450, and a DSD multi-channel recorder 460. Three point-to-point links 445, 455, and 465 are connected to the central DSD router 430. Unlike the embodiment shown in FIG. 3, this star configuration allows standard Category 5 cable to be used for each of the three connections. This is because the port connection is reversed inside the DSD router 430 so that the signal output of one device is connected to the signal input of another device.

The DSD router 430 includes a plurality of signal transmitters / receivers, each of which includes a data clock transmitter (described later with reference to FIG. 6) and a data and clock receiver (described later with reference to FIG. 7). To be equipped. Switching and routing functions are performed by a crosspoint switch (not shown) that operates on the playback clock and streamed audio data. In other words, the signal does not pass through the router in packetized form.

In the embodiment shown in FIG. 3, the cable 405 connecting the transmitter and the receiver is terminated by an 8-terminal RJ45 plug, and both the transmitter and the receiver are provided with an RJ45 socket. Table 1 shows the RJ45 socket terminal settings for the audio equipment shown in FIG. 3 and the star configuration router equipment shown in FIG.

<tables num="1"><img file="JP4625670B2_D0001.tif" /></tables>

FIG. 5 is a block diagram showing a configuration of an audio data transmission system based on the present invention. System 500 comprises a first audio processor 510 and a second audio processor 520 connected via Category 5 unshielded twisted pair cable 515. Each audio processing device 510 or 520 has a Field Programmable Gate Array (hereinafter referred to as FPGA) 512, a physical layer interface (PHY) element 514, a transformer 516, and an 8-pin RJ45 connector 518. Be prepared. FPGA512 provides a multichannel audio connection for DSD (Multichannel Audio Connection for DSD: hereinafter referred to as MAC-DSD).

1 bit 64F_sDirect stream digital data is supplied from the audio device to the FPGA 512. In the transmission operation, the FPGA 512 buffers and frames the audio data, and in the reception operation, it extracts data from the framed structure and returns the extracted data to the DSD stream. FPGA512 executes transmission and reception at the same time, and realizes a full-duplex audio connection. The format of the frame will be described in detail later with reference to FIGS. 15 and 16. The PHY element 514 performs physical layer coding of the framed audio data, executes spectrum control processing, and has a line driver, which amplifies the current, thereby amplifying the power of the signal. Improves robustness during transmission. The PHY element 514 actually implements the physical coding sublayer (PCS) 216, the physical medium connection (PMA) sublayer 214, and the physical medium dependent (PMD) sublayer 212 of the physical layer 210. In this embodiment, the PHY element 514 is Intel: Trademark) LXT972a element, which does not have auto-negotiation function and operates in full dual mode with data scrambling function. The transformer 516 outputs data to be transmitted via Category 5 cable 515. Upon reception, the transformer 516 receives the signal, which is then processed at the physical layer. The interface between the FPGA 512 and the PHY element 514 is a media independent interface (MII). This causes the FPGA 512 to replace the network address that handles medium access control (MAC) in traditional Ethernet systems. Ethernet systems support multiple sampling rates and can accommodate higher DSD sampling rates that may be developed in the future. When the audio sampling rate changes, how the audio data stream is packed into data frames also needs to be changed, and this change is determined by the circuitry within the FGPA512. If the physical layer link has sufficient bandwidth, changing the audio sample rate will not affect the PHY element 514.

Figure 6 shows 64F_sIt is a figure explaining the method of transmitting an audio sampling clock signal in parallel with DSD audio data through a different signal line pair of a category 5 cable. Similar to the embodiment shown in FIG. 5, the audio data signal is processed by the FPGA 512, the PHY element 514 and the transformer 516 and then transmitted via the two pairs of signal lines of the category 5 UTP cable 515. 64F_sThe audio sampling clock is supplied as an input to both the FPGA 512 and the low-pass filter 552, which frames and buffers the data. The low-pass filter 552 serves to reduce electromagnetic radiation during clock signal transmission. The output of the low-pass filter 552 is supplied to the differential line driver 554 as an input and then to the 10BASE-T type Ethernet transformer 556. The clock signal is supplied via the RJ45 connector 518 to a pair of signal lines of the category 5 UTP cable 515 and transmitted in parallel with the audio data. Transmission of the audio sampling clock signal is important because the receiver FPGA 512 synchronizes the received audio data with the audio sampling clock signal, i.e. reconstructs the DSD bitstream. The characteristic impedance of the category 5 UTP cable used in this embodiment of the present invention is 100Ω. In other embodiments, electromagnetic compatibility (electromagnetic) A screen twisted pair cable with high compatibility (EMC) performance may be used. In yet another embodiment, other types including Category 5e cable (for data transfer speeds up to 250 Mbps), Category 6 cable (suitable for Gigabit Ethernet) or Category 7 cable that allows higher data transfer speeds, etc. Cable may be used.

FPGAs are just one example of a solution to achieve the functionality required in transmitters and receivers. Of course, a software-controlled general-purpose microprocessor may be used. In this case, the software can be provided by a storage medium (eg, read-only memory, flash memory, magnetic disk, optical disk, etc.) or a transmission medium (eg, network, Internet, etc.).

FIG. 7 is a diagram illustrating an operation of receiving a high frequency audio sampling clock in parallel with a DSD audio data signal. The parallel signal is supplied to the receiver's RJ45 connector 522 via cable 515. The DSD audio data signal is fed to the physical layer interface element 526 via the transformer 524 and then to the FPGA 528, which unframes the data to generate a DSD bitstream. FPGA528 is 64F supplied from the receiver's local phase-locked loop._sOutputs a DSD audio stream based on the clock signal.

The received audio clock signal is first supplied to the transformer 562 at the receiver. The output signal of the transformer 562 is supplied to the high-pass filter 563 and then to the low-pass filter 564. The low-pass filter 564 is the same type of filter as the low-pass filter 552 in the transmitter. The receiver's lowpass filter 564 removes any high frequency interference in the received signal. Such high frequency interference is derived from an audio signal or an external noise source transmitted in parallel on the cable 515. The output signal of the low-pass filter 564 is supplied to the comparator 568 and converted into a logic signal. The logic signal from the comparator 568 is used to drive a local phase-locked loop (PLL) circuit. A phase-locked loop (PLL) is an electrical circuit that controls an oscillator to maintain a constant phase angle with respect to a reference signal. In this case, the received high frequency clock signal becomes the reference signal. The PLL circuit generates a local audio reference clock used to reproduce DSD audio data.

Figure 8 shows 64F_sIt is a figure which shows the signal path of a DSD sampling clock signal. As mentioned above, the DSD sampling clock is transmitted in both directions by a dedicated differential signal pair within the Category 5 UTP interconnect cable 515. Below, using Fig. 8, the high frequency (64F)_sA series of processing performed on the clock signal of) will be described. The sampling clock signal is subjected to special analog conditioning to facilitate transmission in parallel with the asynchronous data signal via the signal pair of the UTP cable. This analog tuning reduces the effects of electromagnetic interference from asynchronous data signals (or external noise sources) that degrade the quality of high frequency sampling clock signals. As shown in FIG. 8, the sampling clock processing circuit of the clock master device includes a low-pass filter 552, a differential line driver 554, and a transformer 556. On the other hand, the sampling clock processing circuit of the clock slave device includes a transformer 562, a high-pass filter 563, and a comparator 568.

2.8224MHz (64F) for the low-pass filter 552 of the clock master device_s) Logic signal 551 is input. The frequency tolerance of this signal is based on the Grade 2 standard of the 1997 AES11 specification. Therefore, the long-term frequency stability of the sampling clock is +/- 10 / million (ppm) and the external synchronization range is +/- 50ppm. The duty cycle of the sampling clock is 40 to 60%, and a logic signal of a low voltage transistor-trangistor logic (hereinafter referred to as LVTTL) is used.

64F output from the comparator 568 of the clock slave device_sLogical clock signal 569 is also 2.8224MHz (64F)_s) Is a logical signal. This clock output signal is not used directly to synchronize the digital audio signal, as the characteristics of the link 515 can introduce substantial jitter or asymmetry into the clock signal. The clock output signal is used exclusively to synchronize the receiver's edge-triggered phase-locked loop (PLL). The clock output signal 569 needs to be carefully routed within the receiver so as not to superimpose noise or jitter on other high quality clock signals. The PLL circuit of the clock slave device (not shown) is used to generate the high quality audio clock signal used throughout the receiver.

The low-pass filters 552 and 564 provided on both the transmitting side (clock master) device and the receiving side (clock slave) device are secondary Butterworth slow-pass filters having a cutoff frequency of 2.9 MHz, respectively.

The low-pass filter 552 of the transmitter attenuates the high frequency components of the clock signal. Such high frequency components may interfere with audio data transmitted simultaneously in the cable or cause excessive RF emission from the cable. On the other hand, the low-pass filter 564 of the receiver has a role of removing from the clock signal the high-frequency interference induced in the clock signal by the high-frequency data signal or the external noise source transmitted at the same time.

The differential line driver 554 installed in the transmitter produces a symmetric output signal with a differential peak-to-peak voltage of 1.5-2.5V at an impedance of 100Ω (Category 5 UTP link impedance).

The transformers 556,562 provided in both the transmitter and the receiver are 10Base-T Ethernet transformers having a common mode choke coil on the line side and a turns ratio of 1: 1.

The high-pass filter 563 of the receiver has a cutoff frequency of f._c= 500Hz first-order high-pass filter. This high-pass filter 563 removes low-frequency interference from the mains and prevents DC offsets from occurring. This high-pass filter 563 is realized by a simple resistance-capacitive (RC) coupling.

The receiver comparator 568 converts the analog clock signal filtered by the low-pass filter 564 into a logic signal. Hysteresis of 2% is used to eliminate or reduce noise-induced multiple edges.

In Figure 9, the synchronization frequency of the physical layer device is the audio sampling clock frequency 64F._sInteger multiple of (9 * 64F_s) Is shown as an embodiment of the present invention. The Ethernet standard stipulates that a symbol rate of 25 MHz should be used for data transmission.

Transmission of a 2.8224MHz sampling clock using the same category 5 UTP cable as a 25MHz audio data signal can result in unfavorable degradation of the audio clock. By synchronizing the transmission of audio data with the sampling clock, deterioration of the high quality audio clock signal can be suppressed. The device shown in Fig. 9 uses a phase-locked loop to input 64F._sIt is equipped with a multiplier 572 that upconverts the clock signal to 9 times the frequency. × 9 The output from the multiplier 572 is supplied to the PHY element 514 of the transmitter, and is 576F._sAn audio data signal of (25.4016MHz) is generated. That is, in this embodiment, audio data is transmitted at a symbol rate of 25.4016MHz instead of the standard 25MHz Ethernet symbol rate. As a result of increasing the symbol rate, the channel bit rate will increase from 100 Mbps to 101.6064 Mbps.

Therefore, the embodiments of the present invention can potentially suppress the degradation of the audio clock signal, but lose compatibility with the standard Ethernet 25 MHz symbol rate.

FIG. 10 shows the configuration of a point-to-point audio link in which one device functions as a clock master 600M and the other device functions as a clock slave 600S. Each audio processing device has a clock source, PLL602M, 602S, and a clock receiver (R)._x) 604M, 604S, lock detection modules 606M, 606S, and clock transmitter (T)_x) 608M, 608S, audio input / output (I / O) devices 610M, 610S, and switches 612M, 612S. Subscript M indicates a component related to the master device 600M, and subscript S indicates a component related to the slave device 600S. The DSD audio data is transmitted via a UTP cable (not shown) that connects the audio I / O device 610M of the master device 600M to the audio I / O device 610S of the slave device 600S.

Category 5 UTP cables provide an independent connection so that under normal operating conditions, the clock signal is transmitted bidirectionally between the two audio devices. However, in the active link, it is necessary to specify one device as the clock master 600M and the other device as the clock slave 600S. The clock transmitter 608M of the clock master 600M transmits an audio clock signal 605M to the clock receiver 604S of the clock slave 600S. The slave phase-locked loop 602S uses the audio clock signal 605M from this master to generate a synchronization signal and supplies it to the slave audio I / O device 610S. The audio clock signal 605S transmitted from the slave clock transmitter 608S to the master clock receiver 604M is not supplied to the master phase-locked loop 602M because the master switch 612M is open. The slave clock signal 605S is compared with the local master clock in the master lock detection module 606M, and is used to detect synchronization in the remote slave device 600S.

FIG. 11 is a flowchart illustrating an operation sequence performed to establish a synchronous link between the master device and the slave device shown in FIG.

In step 620, the transmitter / receiver of the slave device 600S, which is the device B, is set to slave mode, and the clock transmitter 608S is temporarily disabled (until the link is established and locked). This operation is done to prevent the two devices from becoming slaves and trying to synchronize with each other with unpredictable results.

In step 630, the UTP cable is used to physically connect the master device 600M to the slave device 600S and establish a link. With this cable connection, the master device 600M and the slave device 600S detect that the link is currently enabled. At this time, the master device 600M starts transmitting the clock signal 605M, but the clock transmitter 608S of the slave device 600S is temporarily disabled.

In step 640, the clock receiver 604S of the slave device 600S detects the input master clock signal 605M and supplies it to the slave local phase-locked loop circuit 602S, and the phase-locked loop circuit 602S sends the input master clock signal 605M. Locked.

In step 650, the slave device 600S detects the lock state by comparing the local system clock with the input master clock signal 605M by the lock detection module 606S. Closing the switch 612S closes the circuit between the slave PLL602S, slave clock receiver 604S and slave lock detection module 606S and enables lock detection. Once the signal from the slave lock detection module 606S indicates that the lock has been established by the master clock signal 605M, the slave clock transmitter 608S is switched from the disable state to the enable state and the audio buffer of the slave device 600S ( It is installed in the audio I / O device 610S.) Is reset.

In step 660, the clock receiver 604M of the master device 600M receives the echoed clock signal from the previously enabled slave transmitter 608S, examines the phase of this returned signal, and slaves. Make sure that the device 600S is properly synchronized with the master clock signal 605M. Here, if synchronization is not established correctly, audio data transmission will not be enabled.

If the slave device 600S is properly synchronized, in step 670, the master device 600M resets the audio buffer (provided in the audio I / O device 610M) and enables the transmission of audio data. The DSD audio data framed by the above is transmitted via the UTP cable that connects the master device 600M and the slave device 600S.

The flowchart shown in FIG. 11 shows a standard process for establishing synchronization between the master device 600M and the slave device 600S. In some cases, an attempt is made to establish a link between two audio devices, both of which are set to slave mode. In this case, when the device detects a valid data link, the clock transmitters of both devices are disabled and the operator is informed that the links are out of sync. The user is informed of the link status by the LED status display (not shown) provided adjacent to the connection port of the RJ45 cable. Table 2 below shows the LED states that correspond to the multiple possible link states. In particular, the red or yellow LED "on" corresponds to a clock synchronization error that can occur when trying to link two slave mode audio devices.

<tables num="2"><img file="JP4625670B2_D0002.tif" /></tables>

FIG. 12 shows a system in which multiple parallel links are used between two devices in an audio facility. By using a plurality of links, it is possible to support a larger number of channels as compared with a single point-to-point link. In this example, two links are used to provide a total of 64 channels. The transmitting audio device 700A includes a first transmitter 702, a second transmitter 704, and a clock generator 706. The receiving side audio device 700B includes a first receiver 712, a second receiver 714, and a clock generator 716. The first category 5 UTP cable 721 connects the first transmitter 702 and the second receiver 712 and provides audio data channels 1-32 (or 1-24). The second category 5 UTP cable 723 connects the second transmitter 704 to the second receiver 714 and provides audio data channels 33-64 (or 25-48).

When operating the system shown in FIG. 12, the DSD audio data stream output from the first receiver 712 must be synchronized between the samples to the DSD audio data stream output from the second receiver 714, ie. It is necessary to synchronize the samples of channels 1-32 (or 1-24) with the samples of channels 33-64 (or 25-48). Due to the latency of the PHY device in transmitters 702 and 704 and the PHY device in receivers 712 and 714, the output of receivers 712 and 714 has multiple DSD audio sample periods (3.543 x 10).^-7Seconds) Sync may be out of sync. According to the manufacturer's specifications commonly used for PHY devices, the combination of transmission and reception latency for PHY devices is up to 6x10.^-8It indicates that it changes to seconds, and therefore it is possible that there will be a deviation of 1 DSD sample between receivers. Differences in the length of cables 721 and 723 also affect synchronization.

As shown in FIG. 12, the first and second transmitters 702 and 704 of the transmitting audio device 700A are F._s= 44.1kHz common reference clock signal F_s(A) is used. Similarly, the first and second receivers 712 and 714 of the receiving audio device 700B are F._s= 44.1kHz common reference clock signal F_s(B) is used. These two 44.1kHz synchronous clock signals F_s(A), F_s(B) is 64F_sIt has the same frequency derived from the master clock signal of, but the phase is arbitrary, and it is unlikely that the two phases are matched. Clock signal F_s(A), F_s(B) is 64F, which is common to each independent clock driver._sThis phase difference occurs because it is derived from the clock. FIG. 13 shows the clock signal F._s(A), F_s(B) is a flowchart explaining how to maintain the synchronization of the output signals of the receivers 712 and 714 (these are obtained from the audio data from the independent link cables 721 and 723, respectively). ..

In step 730 of FIG. 13, the link between the transmitting side audio device 700A and the receiving side audio device 700B is established. The two transmitters 702 and 704 each have a local 44.1kHz clock signal F._sWaiting for the clock edge of (A), the first audio frame is transmitted. The data frame is packed so that the first DSD sample is input synchronously with the clock edge. The flowchart of FIG. 13 corresponds to an embodiment having a 32DSD audio channel. In a 32-channel system, each frame consists of 384 data words, with words 13-382 containing the respective 1-bit DSD sample values for the 32 channels, as described in detail later with reference to FIG. 18A. (370 sample values are included in each frame for each channel). The first transmitter 702 transmits the first audio frame corresponding to channels 1 to 32, while the second transmitter 704 transmits the first audio frame corresponding to channels 33 to 64. In this example, each frame contains 370 samples, 1F_sSince there are 64 samples in the period, the start of the frame (output of the first DSD sample value) and F_sStart of period (F_s(A) Clock edge) matches every 370 x 64 samples. Here, 370 and 64 have a common factor of 2, so the start of the frame and F_sThe start of the period coincides every (370 × 64) / 2 samples, that is, every 32 frames. Therefore, for frames 1, 33, 65, 97 ..., the first DSD sample value in the frame is the local F._s(A) Output synchronized with the edge of the clock. For these special frames, a specific bit flag in the data frame's Frame Type field (see Figure 16) is set to 1.

In step 732 of the flowchart, the first receiver 712 and the second receiver 714 have a phase count value of Φ._j(j captures 1 for the first receiver 712, 2 for the second receiver 714) and marks the time to output the first DSD sample value in the first received frame. To do. When the system starts up, the audio output on the receiving side is muted, and it depends on the master device at 64F._sOnce the sampling clock synchronization is confirmed, only the transmitting audio output is enabled. The time when the receiving side is ready to output the first DSD sample value is 64F when the slave device is the master device._sIt depends on the time it takes to phase lock the clock signal. This time also depends on the setting of the threshold level of the FIFO buffer of a specific transmitter. Each receiver is on the local 64F_sOperates by clock signal, 44.1kHz signal F_sFrom the counter reset by (B), the phase count value Φ_jIs derived.

In step 734, the system controller (not shown) has a phase count value Φ for each receiver.₁, Φ₂Are compared to determine if they are the same. Here, Φ₁= Φ₂In the case of, the receivers are synchronized within the same DSD sample period, which is a desirable condition. In this case, the process proceeds to step 738 and the audio output is unmuted. On the other hand, in step 734, Φ₁ Φ₂If, the process proceeds to step 736, where the system controller adjusts the receiver's buffer read position to achieve synchronization. 64F earliest_sThe receiver synchronized with the master clock (and therefore the receiver that first received the DSD audio data) is the buffer of the receiver that last synchronized its buffer read position (the receiver that last started receiving DSD data). Adjust to match the reading position. The adjustment of this buffer read position is performed by two phase count values Φ._jThis is equivalent to adjusting both phase count values to the larger phase count value. Audio output is enabled only when synchronization is achieved, that is, when the phase counts of each receiver are equal.

The phase counts of the receivers are checked against each other for each flagged frame (first frame and every 32 frames from the first frame) to see if synchronization between receivers is maintained. .. Frames are transmitted every 131.25 μs, so flagged frames are transmitted about every 4.2 ms (131.25 μs × 32). All receiver synchronization issues can be detected and fixed within this 4.2ms. Steps 742, 744, and 746 shown in FIG. 13 show the confirmation process performed by the system controller for each flagged frame. In step 742, the system controller checks for a modified phase count value for the current frame being flagged, and this phase count value and the flagged frame, i.e. the X-32nd. Compare the last stored (possibly modified) phase count value for the frame. If these phase count values are the same, the system controller continues transmitting audio data in step 746. On the other hand, if the phase counts for the two flagged frames are different, this means that the two receivers are not outputting the same audio sample value at the same time, and the process proceeds to step 744, where the system controller Initiates a datalink reset to restore proper synchronization. When the data link is reset, the receiver logic is reset so that steps 732-738 shown in FIG. 11 can be performed. As another embodiment, the data link may be reset by adjusting the buffer read position. However, in this case, buffer overrun / underrun may trigger a reset of the entire link. The out-of-sync is caused, for example, by a cable glitch.

In another embodiment using 24 DSD channels, which will be described in detail later with reference to FIG. 18B, each frame consists of 368 data words, where words 15-366 are 352 DSD samples of 24 channels and 88 bytes. Contains ancillary data. Each 32-bit sample contains 1 bit from each of the 24DSD channels, 2 bits of auxiliary data, and 6 bits of check bits. Bit 0 of each sample corresponds to the first logical audio channel and bit 23 corresponds to the 24th logical audio channel. In this case, the first transmitter 702 transmits the first audio frame corresponding to channels 1 to 24, and the second transmitter 704 transmits the first audio frame corresponding to channels 25 to 48. .. In this example, each frame contains 352 samples, 1F_sSince 64 samples are sent for each period, the start of the frame (output of the first DSD sample value) and F_sStart of period (F_s(A) Clock edge) matches every 352 x 64 samples. Here, 352 and 64 have a common factor of 32, so the start of the frame and F_sThe start of the period coincides every (352 × 64) / 32 samples, that is, every other frame. Therefore, in the 24DSD channel example, for frames 1, 3, 5, 7, 9 ..., the first DSD sample value of the frame is the local F._s(A) Output synchronized with the edge of the clock. Therefore, a flag is set every other frame, and the phase count value of the receiver is mutually confirmed every other frame.

FIG. 14 is a diagram showing how audio data is buffered in the transmitter. The transmitter buffering device 800 includes a First In First Out (FIFO) buffer 810 and a frame assembler 820 connected in series with the FIFO buffer 810. During operation, 32 channels of DSD 1-bit sample data are stored in the FIFO buffer 810 at 64F._sSupplied at the bit rate of 64F_sIs equivalent to 90.3168 Mbps. When the occupation level of the FIFO buffer 810 reaches a predetermined threshold level 815, the system controller generates a signal to start transmitting a new audio frame. In response to this signal, the frame assembler 820 assembles the frame preamble and header, during which the input DSD sample continues to be buffered. When the assembly of the audio data payload is started, the frame assembler 820 starts reading the data from the FIFO buffer 810. The data read speed from the FIFO buffer 810 is 100 Mbps (or symbol rate 9 * 64F), which is the transfer speed of Ethernet._sIn the example of locking to 101.6064 Mbps). Since data is supplied to the FIFO buffer 810 at a speed of 90.3168 Mbps and data is read at a speed of 100 Mbps, the net buffer occupation level gradually decreases. The predetermined threshold level 815 is based on the data input rate, the data output rate, and the frame size (370 1-bit samples for 32 channels), and the buffer occupancy level is exactly 0 at the end of each frame transmission. Set it to be approximately 0, that is, the data of the next frame to be transmitted exists in the FIFO buffer 810. It is a violation of MAC rules that the FIFO buffer 810 is not completely empty at the end of frame transmission. Once frame transmission is complete, the occupied level of FIFO buffer 810 increases rapidly until threshold level 815 is reached, repeating the frame transmission cycle.

For a 1-bit sample (32 channels) transmission system with an input data rate of 90.3168 Mbps, an output data rate of 101.6064 Mbps, and a frame capacity of 370, the minimum buffer size is 42 DSD samples and the corresponding minimum threshold level is 30 DSD samples. is there. The audio latency caused by this minimum buffer size is 14.9 μs (ie 42 / 64F)._s).

FIG. 15 is a diagram showing how audio data is buffered in the receiver. The receiver buffering device 850 includes a frame receiver 860 and a FIFO buffer 870 connected in series with the frame receiver 860. Audio data is in frame format (via 5UTP cable) at 100Mbps (or 9 * 64F)_sAt the symbol rate, it is supplied to the frame receiver 860 at a data transfer rate of 101.6064 Mbps). The frame receiver 860 separates the preamble and header of each frame, and further provides cyclic redundancy. You may run check: CRC) to verify the integrity of the received data. The frame receiver 860 unframes the framed data and feeds the unframed data directly to the FIFO buffer 870. Since no threshold level is set for the FIFO buffer 870 in the receiver, reading data from the FIFO buffer 870 is started immediately. As a result, the waiting time at the receiver can be made substantially zero. The audio data frame contains a Cyclic Redundancy Check (CRC) word. The CRC algorithm, check word insertion position and range are defined in IEEE 803.3 (2000) Section 3.2.8. This 32-bit inspection word can usually detect all errors in a frame. In well-known Ethernet systems, CRC is performed for each frame on both the transmitter and receiver. On the receiver side, the frame is output only when the result of the CRC inspection related to the frame is determined. As a result, in well-known Ethernet systems, the receiver has a substantial waiting time before data is output. On the other hand, in the present invention, while performing CRC inspection at the receiver, data is output from the buffer before the result of CRC inspection is obtained. Error control is performed by the decoding parity bit in the subsequent stage where the data output from the FIFO buffer 870 of the receiver is supplied. Specifically, error control is performed at the time of extracting data from a 32-bit data block before outputting it as a 32DSD channel audio stream. Unlike standard Ethernet systems, the MAC-DSD protocol based on the present invention does not support reforwarding in the event of an error. This is because retransfer requires buffering at least twice as many audio frames as 125 μs, which makes the system latency unacceptably high. IEEE802. The original purpose of CRC in the three standards is to detect frame errors and thereby generate retransfer requests, but here CRC is included for compatibility. Of course, applications that require higher robustness at the expense of latency may support CRC-initiated MAC-DSD frame reforwarding. Audio data is continuously read from the FIFO buffer 870 at a speed of 90.3168 Mbps, and the data output rate is slower than the data input rate, so the FIFO buffer 870 is gradually filled with data each time a frame is received. Is done. Once a frame is fully received, there is a latency between frames before the audio data for the next frame is supplied, and during this pause, the FIFO buffer 870 keeps approaching the sky (completely zero). Must not be).

If the receiver's FIFO buffer 870 is completely full or completely empty, an error signal is sent to the system controller. A fully full or completely empty buffer means that the data link has failed, the transmitter has failed, or the DSD master clock is properly synchronized between the transmitter and receiver. In this case, the system controller mutes the audio output.

Figure 16 shows the data structure of a standard Ethernet frame. This frame structure is defined in the IEEE 802.3 standard. As shown in FIG. 16, an Ethernet frame is composed of a preamble, a start frame delimiter, a destination address field, a source address field, a data length field, a data payload, and a checksum.

The length of the preamble is 7 bytes, and each byte has a bit pattern 10101010, followed by a 1-byte start frame delimiter S containing the bit pattern 10101011. The preamble and start frame delimiters are used for the purpose of adjusting the timing in the hardware. The length of the destination address field is 6 bytes, and the destination address field specifies the physical address of the network adapter that receives the frame. The source address field is 6 bytes long and contains the physical address of the network adapter sending the frame. The length of the data length field is 2 bytes and the data length field indicates the size of the data payload. The data payload is a variable length field with a minimum length of 46 bytes and a maximum length of 1500 bytes. The checksum field is 4 bytes long and is used when performing a cyclic redundancy check (CRC). CRC is a common means of verifying data transmission. The network node on the transmitting side calculates the CRC value for the frame based on a predetermined algorithm, and encodes this CRC value in the frame. Then, the network node on the receiving side recalculates the CRC value and inspects the CRC field to check whether the value calculated on the transmitting side matches the value calculated on the receiving side. If these values do not match, it indicates that data was lost or an error occurred during transmission. This Ethernet frame is supplied to the circuit of the physical layer, where it is converted into a bit stream and transmitted via a transmission medium. There are several variations of Ethernet frames.

The data structure of the audio data frame based on the present invention is shown in FIG. This audio data frame has a total size of 1536 bytes, with an 8-byte preamble (the physical layer that follows accepts up to 1528 bytes of arbitrary data) and 6 reserved for the destination MAC address. A byte field (default value is 0xffffff), a 6-byte field reserved for the source MAC address (default value is 0x000000), and a 2-byte data length indicating the number of subsequent bytes (always 1510 bytes) excluding CRC. Fields, a 28-byte field reserved for networking headers, a 12-bit spare field (not yet allocated), a 4-bit frametype field used for synchronization purposes, for example, and a 32-channel DSD audio 370. It consists of a 1480-byte audio data payload that holds the sample and a 4-byte CRC field that holds the checksum. The CRC checksum processing in the examples of the present invention will be described later. The data frame structure shown in FIG. 17 is the Internet Protocol (Internet). Protocol: IP) Compatible with networks. Therefore, audio dataframes can be treated as User Datagram Protocol (UDP) / IP datagrams and can be transmitted over a wider IP network. UDP is a connectionless (best try) transport layer protocol. In this particular embodiment, only the physical layer is used. No MAC layer is used here, so the MAC address field is not really required by the system. These fields are reserved and filled with default values for compatibility with Local Area Network (LAN) or UDP / IP (if needed later). There is.

Next, the CRC validity check of the audio data frame will be described in detail. All frames use a 4-byte CRC check word to check the validity of the frame. The CRC algorithm, check word insertion position and range are similar to those defined in IEEE 803.3 (2000) Section 3.2.8.

According to the IEEE802.3 standard, the payload of a frame must not be passed from the data link layer until the CRC confirms the validity of the frame. On the other hand, in the context of the embodiments of the present invention, such processing means that the entire frame must be buffered before starting the output of the DSD audio data stream. Direct compliance with this standard would result in audio latency of approximately 25-140 μs, eg 115 μs, which is not desirable.

CRC is primarily used to validate data links between audio devices at system startup. Post-boot link failures, such as cable disconnections, are indicated by error assertions from the PHY device. Links are simple point-to-point connections, with deterministic, synchronized phrase transfers, and no conflicts, so they are unlikely to fail in other modes.

Therefore, in the examples of the present invention, a relatively simple CRC test is performed. The receiver's audio output is muted from startup until the first frame is fully received and confirmed by its CRC. If the CRC check shows any anomalies, the audio output remains muted and the local system controller is notified of the error condition. After checking the first frame, the CRC is only retrospectively checked. As a result, the receiver can output the audio data stream with a waiting time of substantially zero. The CRC is only used to warn the processor that a CRC error has occurred.

If an invalid audio frame is encountered, theoretically up to 131 μs of invalid audio data may be output before the output is muted in response to a retrospective CRC check. However, in practice, if the symbol becomes invalid due to a random disturbance that destroys the PHY line symbol, the error state of the receiver can be determined early, and this error state can be detected to mute the audio output.

If it is considered necessary to perform CRC inspection on all frames, buffer each frame and verify the validity using CRC before outputting DSD audio data. This approach is not a desirable option, as this process results in an additional latency of about 115 μs and requires a substantial increase in the receiver's hardware buffer size.

Each 1536 byte audio data frame shown in FIG. 17 has a transfer period of 120.9 μs (at a symbol rate of 101.6064 Mbps). In certain embodiments of the invention, frames are transferred at 131.1 μs intervals. There is also a minimum inter-frame time corresponding to the 96-bit period, leaving an 8.25 μs link-time between audio frame transfers. This link time can be used to transfer an auxiliary frame containing control data. The maximum total size of control data in this embodiment is 104 bytes.

The structure of the control data frame is similar to that of the audio data frame shown in FIG. 15, except that the data payload, which is 1480 bytes long in the audio data frame, is 48 bytes long in the control data frame. The control data frame is transmitted every 131 μs, which results in a control data bandwidth of 2.9 Mbps. The control data itself may include channel usage information, router control data, clock source control data, and the like. The control data is transmitted from the storage area in the FIFO buffer of the transmitter, stored in the FIFO buffer of the receiver, and then sent to the system controller of the receiver.

FIG. 18A shows the format of an audio data frame in an example of a 32DSD channel configured as a 384 * 4 byte data word. On the other hand, FIG. 19 shows the format of the control data frame in the example of the 32DSD channel configured as a 26 * 4 byte data word. In both FIGS. 18A and 19, bit zero (B0) is transmitted first and bit 31 (B31) is transmitted last. These audio and control data frames are passed to and received from the connection of the media independent interface (MII) 218, which provides a link to the Ethernet physical layer device. The MII218 has a 4-bit wide data transmit bus and a 4-bit wide data receive bus, each of which is clocked to a link rate of 25 MHz (or 25.4016 MHz) from the PHY. The MII218 further has a transmit enable signal input to initiate data transmission, a signal output indicating the validity of the received data, and other error and signal status indications.

As shown in the audio data frame structure of Figure 18A, the payload of the audio data frame is 32 channels 64F._sContains 370 samples of DSD audio. These channels are multiplexed bit by bit. Each 32-bit word is one 64F for 32 audio channels_sRepresents a DSD sample. Word 13 is the first DSD sample in the frame and word 382 is the last DSD sample. Bit 0 of the audio data word is always 1 bit sample data of channel 1 (the first channel in the system) and bit 31 of the audio data word is 1 bit sample of channel 32 (the last channel in the system). It is data. Table 3 below shows how consecutive samples of each channel are stored within the data word of the audio frame. For example, bit 0 of word 13 is the sample data of channel 1 for the first DSD sample in the frame, bit 6 of word 14 is the sample data of channel 7 for the second DSD sample in the frame, and the word Bit 31 of 382 is the sample data of channel 32 for the last DSD sample in the frame.

<tables num="3"><img file="JP4625670B2_D0003.tif" /></tables>

This Table 3 shows the 32-bit word frame formats, which are sent and received to MII as 4-bit (nibbles) rather than being sent and received as words (4 bytes) at the same time. The sequence of nibbles supplied to the MII for a single 24DSD channel frame shown in Figure 18B is shown in Table 4. The beginning of the 4-byte word (word 13) of the 14th data corresponds to the beginning of the 105th 4-bit nibble (nibble 104). The column headings TXD and RXD in Table 4 represent the MII transmit data bus and the MII receive data bus, respectively, which send and receive nibbles in synchronization with the 25 MHz (or 25.4016 MHz) clock.

Nibble 0 is the first nibble in the frame and contains part of the preamble pattern (0x5). The nibble 104 is the first nibble in the audio data field (the first nibble in word 13) and the nibble 3063 is the last nibble in the audio data field (the last nibble in word 382).

<tables num="4A"><img file="JP4625670B2_D0004.tif" /></tables>

FIG. 18B shows an audio data frame format in an example of a 24DSD channel. In this embodiment, the frame is composed of 368 * 4 bytes of data words. The payload of the audio data frame consists of 352 DSD samples, each sample containing 1 bit from each of the 24 channels. Data words 15 to 366 include the audio data payload. Words 2-4 are reserved for source and destination MAC addresses. Bits 0 to 15 of word 5 indicate the total number of bytes from the beginning of the data length field excluding the CRC field, which is 1446 bytes here. Bits 16-31 of word 5, words 6-word 12, and bits 0-15 of word 13 are data fields reserved for UDP and IP parameters. These data fields are used for UDP / IP options. If no UDP / IP processing is required, the transmitter fills these fields with zeros. The receiver may ignore all UDP / IP header fields except the first 4 bits indicating the IP version (in this example, bits 16-19 of word 5). The receiver examines the data entry in the IP version field and performs the following actions depending on the value of this data entry, as shown in Table 5 below.

<tables num="5"><img file="JP4625670B2_D0005.tif" /></tables>

IP version checking is done to ensure backward compatibility from future IP versions (ie IP version 6) to current IP version 4. Future IP versions may have different header lengths, so the frame format ID field may be provided at different locations within the frame. The significance of the safeguard to inspect the IP version field is that these frames are discarded by the receiver (because they have a value other than 0x0 or 0x4), which causes the frame format ID field to be expected in word 13 and word 14. The point is that it is possible to prevent the frame from being misinterpreted because it does not exist in the correct position.

Bits 16 to 31 of word 13 and bits 0 to 31 of word 14 shown in FIG. 18B are fields for specifying the MAC-DSD frame format. This 48-bit frame format field is logically divided into three separate 16-bit (4 nibble) sections, each containing the same set of frame format data for transmission. In this way, by repeating the same set of frame format data three times within a predetermined frame, the frame format identifier becomes robust to transmission errors, that is, transmitting multiple copies of the data is an error protection mechanism. Functions as. The error protection mechanism by repeating this data makes it easy to achieve the required error correction capability if 48 bits can be used to convey 16 bits. As another embodiment, the frame format ID payload may be transmitted using an error correction code such as a convolutional code.

Each of the three 16-bit frame format field sections has the structure shown in FIG. The first nibble (bits 0-3) of each 16-bit section specifies the protocol minor version (0x0-0xf). The protocol minor version field is used to indicate minor update information in the protocol specification. Recent minor versions need to be backward compatible with previous minor versions of the same major version, for example the version 1.7 protocol must include all the features of the version 1.6 protocol, version. The 1.7 transmitter / receiver must be able to fully communicate with the version 1.6 transmitter / receiver. The second nibble (bits 4-7) of each 16-bit section specifies the protocol major version (0x0-0xf). This field indicates major update information for the protocol specification. It is desirable to maintain backward compatibility with previous major versions of the same protocol, but this is not a requirement. The third nibble (bits 8-11) of each 16-bit section specifies the frame type (0x0-0xi). This field indicates the different frame types used by a given version of the protocol. Within a given major version level, the frame type definitions must match. The basic type of audio frame is always type 0. Table 6 below shows the information derived from the frame type numbers specified by bits 8-11 in this embodiment.

<tables num="6"><img file="JP4625670B2_D0006.tif" /></tables>

The fourth nibble (bits 12-15) of each 16-bit section contains one or more flags used, for example, as a flag frame for synchronization purposes described with reference to the flowchart of FIG. The definition of the flag bit is based on the major version protocol level. Table 7 shown below shows the information derived from the frame flag bits 12 to 15 in this embodiment. In particular, bit 0 of the flag field is a 44.1kHz synchronization flag. A value of 1 for this flag 0 indicates that the first DSD sample in the frame was received at the rising edge of the 44.1kHz synchronous clock at the transmitter, while the value of bit 0 in the flag field is 0. If, it indicates that the first DSD sample in the frame is not received at the transmitter at the rising edge of the 44.1kHz synchronous clock.

<tables num="7"><img file="JP4625670B2_D0007.tif" /></tables>

FIG. 21 shows three 4-nibble sections of a frame format ID, including a set of data entries processed by the receiver. Section 0 contains nibbles 0 (n0) to nibbles 3 (n3), section 1 contains nibbles 4 (n4) to nibbles 7 (n7), and section 2 contains nibbles 8 (n8) to nibbles 11 (n11). )including. Using the received data section, how the receiver eliminates data transmission errors will be described with reference to FIG. In this technique, it is known that at the time of transmission, each of the three sections contains the same data set and the data entries at the corresponding nibble positions of the three sections match. Specifically, it is expected that n0 = n4 = n8, n1 = n5 = n9, n2 = n6 = n10, n3 = n7 = n11. The receiver compares the corresponding nibbles of a set of three (hereinafter referred to as triplets) to determine whether they are the same, and determines the correct data value by majority vote. Consider the set of data supplied to the receiver, shown in Figure 21. For the triplet of the first nibble, n0 = 1101b, n4 = 1101b, n8 = 1101b, i.e. the corresponding nibble values are the same, so this value is considered correct and is a minor version of the protocol. The value of the first nibble of the frame format that specifies is set to 1101b. Similarly, for the triplet of the second nibble, n1 = n5 = n9 = 1110b, so this value is considered correct and the value of the second nibble in the frame format that identifies the major version of the protocol. Is set to 1110b. On the other hand, for the triplet of the third nibble, n2 = n10 = 0110b, but n6 = 1011b, and there is a discrepancy between the data values. In this case, based on a majority vote, n6 is rejected as incorrect, so the receiver issues a third nibble of the frame format corresponding to the frame type as 0110b. Power. For the triplet of the last fourth nibble, n3 = 0010b, n7 = 0111b, n11 = 1100b, and none of the nibbles match. In this case, a majority vote is not possible and therefore the frame format cannot be determined and the frame is rejected.

In other embodiments, a modified frame format error detection / correction method is used. Techniques in other embodiments include repeating data and using majority voting, but also using the 100Base-TX PHY "MILL Receive Error" (rx_er) signal for flagnibles known to result in errors. As a result, the error detection / correction capability is improved. For example, suppose the triplet value of the fourth nibble is associated with the following error flag: That is, it is assumed that n3 = 1000b (rx_er = true), n7 = 0111b (rx_er = false), and n11 = 1000b (rx_er = true). In this case, 1000b is the correct value in the majority vote, but the rx_er signal clearly indicates that n3 and n11 are incorrect values. Therefore, in this other embodiment, n7 is selected in preference to n3 and n11, and the frame flag format value is set to 0100b.

In the frame data field shown in FIG. 18B, the last word (word 367) of the 24DSD channel data frame is the field containing the cyclic redundancy check (CRC) data.

Table 4B, shown below, shows the sequence of nibbles supplied to the MII for a single 24DSD channel frame in Figure 18B. This sequence is transmitted over the nibble-wide MII interface and starts at the lowest nibble. Nibbles 0-8 (32 bits) correspond to word 0 in Figure 18B, nibbles 8-15 correspond to word 1 in Figure 18B, and nibbles 16-23 correspond to word 2 in Figure 18B. Such a relationship continues as well, with the last nibble corresponding to bits 28-31 of word 366. Here, the last word is not sent as a nibble, so a total of 2936 nibbles (367 words) correspond to the 1446-byte frame in Figure 18B. As described above with reference to FIG. 1, the MII218 is individually provided with a 4-bit width data transmission path and a data reception path, respectively, and supports full-duplex operation. Specifically, the MII218 has a 4-bit wide transmit data bus synchronized with the link rate (25 MHz or 25.4016 MHz) by clocks from the physical layer interface (PHY) elements 514 and 526, and a transmit enable signal input and a clock from the PHY. It includes a 4-bit wide reception data bus synchronized with the link rate (25MHz or 25.4016MHz), received data valid signal output, and error and signal status display. A complete description of the MII interface is given in section 22 of IEEE802.2 (2000), but in the present invention the clock rate is 25.4016MHz instead of the IEEE standardized 25.0000MHz. May be good.

<tables num="4B"><img file="JP4625670B2_D0008.tif" /></tables>

A nibble is a basic unit of data processed in the physical layer. Each 4-bit nibble is mapped to a 5-bit symbol by the PHY elements 514, 526 for transmission over signal line 515. Every frame transmitted must start with an 8-byte preamble pattern, which is followed by the physical layer being able to receive up to 1528 bytes of arbitrary data, which are simultaneously fed 4 bits at a time. The received frame contains a preamble and is supplied 4 bits at a time via the receiving bus.

The 24DSD channel frame format in Figure 18B contains a frame payload of 352 DSD samples, each composed of 32-bit data blocks. The format of the 32-bit data block is shown in Figure 22. Each data block corresponds to a 1DSD sample period of approximately 354ns. The data block consists of a 24-bit audio data vector, each bit corresponding to a 24-audio channel, 2-bit auxiliary data, and 6-bit check (or parity) bits. As shown in FIG. 22, bit numbers 0 to 14 include bits 1 to 15 of the audio data vector, and bit numbers 15, 23, 27, 29, 30, and 31 include 6-bit parity bits. 26 and 28 contain 2 bits of auxiliary data, and the remaining 9 bits of the audio vector are continuously contained in bit numbers 16 to 22, 24 and 25 of the data block.

The 6-bit parity bit of the 32-bit data block provides error control functionality. The 24-bit audio data and the 2-bit auxiliary data (26 bits in total) are encoded using a type of linear block coding known as Hamming coding. In this embodiment, the (31,26) Hamming code is used, i.e., the code for each block of 26 data bits produces 5 (= 31-26) parity bits. The last bit in the 32-bit block is the global parity bit, so there are a total of 6 parity bits and 26 data bits. (31,26) The Hamming code can detect two errors per data block, but only one error can be corrected per data block.

How to generate 6 parity bits P0 to P5 from 24 audio data bits (numbers 1 to 24), 2 auxiliary data bits A0, and A1 will be described with reference to FIG. 23A. Parity bits P0 to P5 are obtained by performing XNOR logical operations on a predetermined sequence of 15 data elements. For example, the parity bit P0 is obtained by performing an XNOR logical operation on the audio vector bits 1 to 15, and P1 is obtained by performing an XNOR logical operation on the audio vectors 1 to 8 and the audio vectors 16 to 22. The global parity bit P5 is obtained by performing XNOR logical operations on all 26 data elements. The error detection process in the receiver includes a process of determining whether or not the result of the parity check is correct in the received data sequence. This determination is made using a value known as a syndrome. It will be described with reference to FIG. 23 how the syndrome is generated by the XNOR logical operation for various blocks of the elements of the received data block. The syndrome is obtained by comparing the received parity bit with the parity bit recalculated from the received information. Table 8 below shows how the syndrome values are used to detect and correct errors in the received data block. Basically, if the value of all 6 bits of the syndrome is 1 (s = 111111), the received data sequence is considered correct. If the sixth bit of the syndrome is 0, then the received data block is considered to have a single error, which can be corrected by inverting the appropriate bits. This appropriate bit can be identified from the value of the syndrome, for example, if s = 011011 in binary representation, this is 27 in decimal, which causes bit number 27 (bits 0-31). It can be seen that the data block can be corrected by inverting it. Also, the syndrome

<tables num="8"><img file="JP4625670B2_D0009.tif" /></tables>

The 32-bit data block (see Figure 22) is interleaved into 32 groups, which allows correction of group errors. The interleaving process includes a process of patterning data by a predetermined method. This process is necessary because the (31,26) Hamming code used for each 32-bit data block can only correct a single bit error within a given block. Since the basic data unit of the physical layer is a 4-bit data nibble, a single simultaneous destruction in the physical layer causes a symbol error (a symbol corresponds to 5 bits), resulting in continuity. Four bit errors occur. In order to be able to correct such a 4-bit burst error, it is necessary to distribute the bit containing the error into four different 32-bit data blocks.

For example, suppose that 352 32-bit data blocks B0, B1, B2 ... B351 are output from the parity generator for transmission. As mentioned above, the 24DSD channel frame shown in Figure 18B contains 352 32-bit data blocks. The stream of nibbles generated by the interleaver is shown in Figure 24. In FIG. 24, the bits of the audio payload show, for example, bit 0 of block 2 as B2 [0]. That is, nibble 0 contains bit 0 of each of blocks 0, 1, 2, and 3, and nibble 1 contains bit 0 of each of blocks 4, 5, 6, and 7. Therefore, nibbles 0-7 collectively contain bit 0 of each of the 32 32-bit data blocks, and nibbles 8-15 collectively contain bit 1 of each of the 32 32-bit data blocks. The nibbles 2802 to 2815 contain bit 31 of each of the 32 32-bit data blocks. The 32-block interleaving method used by MAC-DSD allows correction of up to 8 symbol errors out of 32 interleaved data blocks (256 nibbles or symbols) (ie, 32 bits in total). Can be corrected).

In summary, the version of the MAC-DSD protocol used for the transmission of the 24DSD channel described above with reference to FIGS. 18B, 20 and 23 has the following main features: That is, this protocol can correct 24-channel full-duplex transfer of 2.8224MHz DSD audio, 100Base-TX physical layer, audio latency of 50μs or less, and up to 8 nibble errors per 256 nibble block group. Humming linear block code error correction with 256 nibbles interleaving, bidirectional 64F_sIt has features such as DSD clock transmission and a frame flag indicating transmission of 44.1kHz sync signal.

FIG. 25 shows the protocol layer of the MAC-DSD protocol in a particular embodiment using the 24DSD channel frame format. In the transmitter 1000, the protocol layer includes a parity generation and data format layer 1010, and the parity generation and data format layer 1010 is supplied with an input 24-channel DSD audio stream and an auxiliary data stream of up to 5.6 Mbps. This parity generation and data format layer 1010 generates 6 parity bits for each of the 24 audio bits and 2 auxiliary bit samples, and generates a data block in a 32-bit format. Parity generation and data format 32-bit data blocks output from layer 1010 are supplied to interleaved layer 1020, which interleaves the data blocks into 32 groups, as described with reference to FIG. As a bit nibble, the interleaved data is supplied to the FIFO buffer 810 via the MII218. Data nibbles from the interleaved layer 1020 are 90. It is fed to the transmitter's FIFO buffer 810 at a continuous data rate of 3168 Mbps. The nibbles are continuously fed to the FIFO buffer 810 until a predetermined buffer occupancy threshold level (described above with reference to FIG. 14) is reached, at which the data frame assembly begins. During data frame assembly, the data nibble is read from FIFO buffer 810 and passed to frame assemble layer 1040. The frame assembly process includes a process of generating frame header information using the header data generation module 1050 and a process of generating data for CRC fields using the CRC generation module 1060. The data for the CRC field corresponds to word 367 in the frame format shown in Figure 18B. The frame is constructed so that 352 32-bit data blocks contain 1408 payloads of 352 DSD samples. The data from the frame assemble layer 1040 is output as an MII frame (composed of nibbles) at a rate of 101.6064 Mbps and supplied to the physical layer 1070 of the transmitter. This physical layer 1070 prepares for data transmission via a physical medium. The physical layer 1070 of transmitter 1000 produces 5-bit symbols from each 4-bit nibble, and these symbols are transmitted to receiver 1100 via twisted pair cable. In the receiver 1100, the physical layer 1110 of the receiver 1100 receives the 5-bit symbols and converts these 5-bit symbols into MII frames consisting of 4-bit nibbles. The MII frame is 101. It is supplied to the frame disassembled layer 1120 at a rate of 6064 Mbps, which performs CRC inspection and separates the header data for subsequent processing. The frame disassembler layer 1120 supplies the frame payload as a MII nibble to the FIFO buffer 870, which has a low latency for data output (described with reference to FIG. 15). The data output from the FIFO buffer 870 in the MII nibble format is passed to the deinterleaved layer 1160. The deinterleaved layer 1160 deinterleaves the data in the 32 groups and reproduces the individual 32-bit data blocks as shown in the format in FIG. The 32-bit data block is supplied to the parity decoding and data extraction layer 1170, and the parity decoding and data extraction layer 1170 performs error control using the parity data and extracts the reproduction payload data. A 24-channel DSD audio data stream and an auxiliary data stream of up to 5.2 Mbps are output from the parity decoding and data extraction layer 1170. Note that in FIG. 25, the FIFO buffers 810 and 870 do not convert any data and are therefore technically not a protocol layer, but here, for the sake of clarity, the FIFO is shown graphically in the protocol layer. It contains a buffer. A 2Mbps auxiliary data stream is output. Note that in FIG. 25, the FIFO buffers 810 and 870 do not convert any data and are therefore technically not a protocol layer, but here, for the sake of clarity, the FIFO is shown graphically in the protocol layer. It contains a buffer. A 2Mbps auxiliary data stream is output. Note that in FIG. 25, the FIFO buffers 810 and 870 do not convert any data and are therefore technically not a protocol layer, but here, for the sake of clarity, the FIFO is shown graphically in the protocol layer. It contains a buffer.

For the 352 sample payloads of the 24DSD channel frame shown in FIG. 18B, the transmit buffer size and the given buffer occupancy threshold level are the buffer sizes described in FIG. 14 for the 370 sample payloads of the 32DSD channel frame format shown in FIG. And different from the occupancy threshold. Specifically, for the 24DSD channel frame format, the buffer size corresponds to 36 data blocks (rather than 42 data blocks) and the corresponding minimum occupancy threshold corresponds to 30 data blocks (as in the previous example). The audio latency introduced by this buffering is 36 DSD samples (rather than 42 samples) or 14.9 μs (rather than 12.2 μs).

The above-mentioned system that provides the data communication system with the function of transmitting DSD data by the physical layer of the link such as an Ethernet link can also be used for the transmission of other types of synchronized digital data. For example, the system may be configured to carry Pulse Code Modulated (PCM) digital data. A wide bandwidth PCM data communication is realized by the physical layer connection based on this technology.

PCM data is 64F of DSD data_sIt is synchronized at a frequency well below the clock frequency (eg 44.1-96kHz). Therefore, in order to support PCM transmission in addition to DSD transmission, a clock signal having a lower frequency, for example, a word clock signal, is transmitted and received between network devices via a twisted pair cable. The word clock is used to reproduce the PCM data at the receiver. The frame format for the 24DSD channel shown in Figure 18B allows 352-bit data to be transmitted frame by frame for each of the 24 audio channels. Basically, 352 24-bit DSD samples (1 bit per channel) are transmitted in a single frame. The data block is 64F via the link_sAggregate rate, that is, 2.8224MHz (64 * 44.1kHz) for 44.1kHz audio data and 3.072MHz for 48kHz audio data. In order to transfer PCM data at a frequency in the desired range of (44.1kHz-12.5%) to (96kHz + 12.5%), it is necessary to include 4 to 13 24-bit samples per frame. Therefore, multiple alternative data formats are defined, the transmitter determines how many samples should be sent in the next frame, and the transmitter examines the look-up table for multiple alternative data. Select the appropriate data format from the formats. In I2S and AES3 (1992 edition) and packaged PCM, data is sampled into serial subframes. AES3 is an Audio Engineering Society for serial transmission of linearly represented digital audio data via a conventional shielded twist pair conductor of at least 100 m without equalization by an equalizer. Society) standard. Figure 26A shows the AES3 subframe format. Each AES3 frame consists of two uniquely constructed subframes, and the frame transfer rate usually exactly matches the source sampling frequency. The first subframe starts at preamble X and the preamble is changed to Z every 192 frames. This defines the block structure used to organize the channel state information. The second subframe always starts with preamble Y. As shown in FIG. 26A, the AES3 subframe is composed of 32 bits, of which bits 0 to 3 store the preamble and bits 4 (most significant bit) to 27 (most significant bit) are 24. Bits Stores the audio sample word, where bit 28 is the validity bit associated with the audio sample word. It is a "V" field that is bit), where bit 29 is a "U" bit containing one bit of the user data channel associated with the audio data channel transmitted in the same subframe, and bit 30 is the same subframe. A "C" field containing 1 bit of channel state information related to the audio data transmitted in, that is, a channel state field, in which bits 4 to 31 have an even number of 1's and an even number of 0's. A "P" field that stores the parity bits set to include, that is, even parity. The V-field bit (V-bit) is set to 0 if the audio sample word is suitable for conversion to an analog audio signal, and 1 otherwise. The bit (C bit) of the C field is one bit of the channel state information that specifies, for example, the length of the audio sample word, the number of audio channels, the sampling frequency, and the like. The channel state information is organized as a 192 bit block that is subdivided into 24 bytes. The first bit of each block is stored in a frame with a preamble Z.

A subframe format for PCM transmission based on the present invention is shown in FIG. 26B. This 27-bit subframe structure includes U-bit and C-bit fields in the well-known AES3 subframe format, enabling transparent transmission of AES3 format data over the physical layer link. As shown in FIG. 26B, bits 0 to 23 contain data, bit 24 contains U bits, bit 25 contains C bits, and bit 26 contains M bits. The U and C bits are taken directly from the input AES3 data stream or from the user data and channel information buffer memory in the transmitter. The M bit is a multiplexed bit specific to the technology based on the present invention, and can be used to include one of the following three indications at a certain point in the bitstream. it can. These three instruction information are external F_sShows a data sample synchronized to / n (n is an integer), F_sAn S bit that repeats over all data channels every n periods, the start of the AES3U / C data block, a Z bit that repeats on each channel every 192 samples, and a V that indicates the subsampled AES3V bit state. It's a bit. The instructional information S and Z are used to identify a particular sample in the audio data stream, respectively. Since the S and Z indications are inherently periodic, in theory it is sufficient to simply identify their phase with respect to the sampling clock. However, in practice, the S and Z instruction information needs to be reasonably repeated in order to lock the link quickly at startup and detect the link failure early. In the M-bit data stream, the instruction information S is indicated by two consecutive logical values 1 in the bitstream, as shown in FIG. 27B, and the instruction information Z is indicated by a single logical value, as shown in FIG. 27A. Shown by 1. In an M-bit data stream, a counter is provided in the transmitter to pre-empt the generation of a synchronization signal in order to indicate a synchronization sample (S bit) by two consecutive 1s. The V-bit state is indicated by the bit immediately following the instruction information S for each channel. Therefore, V is less frequently than per sample, and is a period of Ssync per channel (often F)._sIt is shown at intervals of 46ms) at 1kHz. This is based on the assumption that the V-bit state does not change rapidly, which is valid for the majority of audio applications. Figure 27C shows the V-bit indication information with a logical value of 1 (true), which indicates that the channel sample is valid, resulting in three consecutive logical values 1 in the bitstream. (Two ones for the S bit and one for the V bit). FIG. 27D shows the case where the V-bit instruction information immediately after the two logical values 1 corresponding to the S bit is 0 (false). This indicates that the channel sample is invalid. Since the M bit is used to indicate a plurality of other events, event instruction information may occur at the same time or in close proximity to interfere with each other. For this reason, the instruction information S always takes precedence over the instruction information Z. As a result, the instruction Z is sometimes lost, so it is desirable to keep the U / C block phase count at the receiver and set the Z bits in the output AES3 stream to these states. 28A to 28E are specific examples of the relative positional relationship between the instruction information S and the instruction information Z, and show whether or not the instruction information Z should be disabled in these relative positional relationships. There is. In FIG. 28A, the instruction information Z overlaps the second bit of the instruction information S, so Z is disabled and only S is shown. In FIG. 28B, in the received M-bit sequence, the instruction information Z occurs immediately before the instruction information S, and in this case, Z is disabled because S comes immediately after. If Z is not disabled in the specific example of FIG. 27B, three logical values 1 will be continuous and S and V cannot be distinguished. In FIG. 28C, the instruction information Z precedes the instruction information S, but the instruction information Z is separated from the instruction information S by one bit period. In this case, both Z and S are enabled because Z and S do not interfere with each other and are sufficiently distinguishable. In FIG. 28D, the instruction information Z is immediately after the instruction information S. Z is disabled because it has become indistinguishable. In FIG. 28E, the instruction information Z follows the instruction information S one bit away. In this case, as in the case of FIG. 28C, both Z and S are enabled because Z and S do not interfere with each other and can be sufficiently distinguished.

In order to transfer PCM data between devices via the physical layer, the frame format of the PCM data needs to be basically the same as the format described above using FIG. 18B. Specifically, each frame is 1472 bytes long and the data payload consists of 352 32-bit data blocks. Each 32-bit block contains 24 audio data bits and 2 auxiliary data bits, forming 26 independent bitstream segments for each 352-bit frame. In PCM mode, the 24 audio bitstream is split into multiple sample subframes separated by padding. The number of subframes varies from 4 to 13 depending on the individual PCM sampling frequency. This makes it possible to support sampling rates in the range of 44.1kHz-12.5% to 96kHz + 12.5%. Each sample subframe contains data from a single PCM sample.

Unique sample subframes and padding are defined for each possible sample subframe for each bitstream. The value of all padding bits must be 0. With this definition, the receiver can correctly extract sample subframes from the bitstream segment. Table 9A shows these configurations. On the other hand, Table 9B shows a configuration example of subframes in a specific specific example in which nine sample subframes are provided for each frame.

<tables num="9A"><img file="JP4625670B2_D0010.tif" /></tables>

<tables num="9B"><img file="JP4625670B2_D0011.tif" /></tables>

As described above, the use of the data block audio bit in the PCM mode of the frame format shown in FIG. 18B is different from the use of the audio bit in the DSD mode. A further difference between PCM mode and DSD mode in frame format is related to the frame format ID values contained in the three identical frame ID sections in words 13 and 14 shown in Figure 18B. The frame format ID field for each section is as described with reference to FIG. In summary, each frame format ID section comprises a flag field, a frame type field, a protocol major version field, and a protocol minor version field. To accommodate PCM mode, the frame type field values are extended from the frame type field values defined in Table 6 above. As shown in the table in FIG. 29, 10 different frame type field value choices (the number of integers from 4 to 13) corresponding to the number of sample subframes per frame are defined. Two separate formats are defined for the frame type field of the frame format ID (see words 13 and 14 in Figures 18B and 20). Of these, one format is for DSD frames and the other is for PCM frames. The table in Figure 30 shows the flag field format for DSD frames. In this case, flag bit 0 indicates whether the first DSD sample in the frame was received at the same time as the rising edge of the 44.1kHz synchronous clock, and bit 1 indicates whether the first DSD sample in the frame was F._s/ n Indicates whether or not it was received at the same time as the rising edge of the synchronous clock. The table in Figure 31 shows the flag field formats for PCM frames. In this case, flag bit 0: 1 identifies the frequency of the audio base clock, and flag bit 3: 2 is the base clock sampling rate multiplier. The sampling rate is the base clock frequency F_sCan be specified as 1x, 2x, 4x or 8x.

The PCM frame format described above relates to specific examples corresponding to 24 audio channels. As another example, 1F_s48 audio channels may be supported in PCM mode (44.1kHz or 48kHz ± 12.5%). In this case, each bitstream is multiplexed with two audio channels. This multiplexing may be performed for each subframe or bit.

Hereinafter, the clock and synchronization functions of the PCM mode will be described in detail. As mentioned above, in the transmission of PCM data over the network, 64F_sA word clock is required in addition to the MAC-DSD cable clock. These two clocks are not transmitted separately via twisted pair cable, but 64F_sThe clock and word clock are multiplexed. This multiplexing process is on the 64th floor_s64F by word clock signal by shifting at least one edge of the clock pulse, i.e. by generating a "clock pulse width deviation"_sIncludes processing to modulate the clock signal. Clock pulse width deviation is 64F_sIt functions as the phase indicator of the word clock built into the clock. The clock pulse width deviation is 64F, which is determined by the transmitter to match the transition of the word clock._sIt is generated by specifying the transition position of the clock signal. In this example, 64F_sSince the rising transition of the clock is used for the purpose of timing synchronization, the phase of the word clock is 64F._sEncoded by shifting the position of the falling transition of the clock. For details, see Word Clock and 64F_sIf the rising transitions of the clocks match, 64F_sA multiplexed clock signal is generated by shifting the leading fall in the clock. Figure 32 shows 64F_sIt is a figure explaining the process of generating a multiplexed clock signal based on a signal and a word clock signal. In Figure 32, the signal 3210 shown at the top is the unchanged 64F used to synchronize the PLL in the receiver._sThe clock signal, the intermediate signal 3220, is the word clock signal for synchronizing the PCM data frame at the receiver, and the signal 3230 shown at the bottom is multiplexed, with the falling transition shifted. It is a clock signal. The multiplexed clock signal 3230 is a clock signal that is actually transmitted via the MAC-DSD link. In FIG. 32, the horizontal right direction shows the passage of time. As you can see from this Figure 32, 64F_sThe rising edge 3212 of the clock signal coincides with the rising edge 3222 of the word clock signal. Therefore, 64F_sThe leading falling edge 3214 in the clock signal 3210 is the time t_clkmodIt is shifted backwards by a minute (see Edge 3234 of the Multiplexed Clock Signal 3230), which narrows the clock pulse width. On the other hand, 64F_sSubsequent falling edges 3216 in the clock signal 3210 have a corresponding time t_clkmodIt is shifted forward by a minute (see Edge 3236 of Multiplexed Clock Signal 3230), which widens the pulse width. That is, the falling transition 3236 after the word clock edge 3222 is delayed backward by the same amount of time as the preceding falling edge 3234 was advanced forward. The delay of the subsequent falling transition 3236 is provided as compensation to avoid the occurrence of DC components in the signal. The DC component of a signal can cause a periodic "baseline shift" at the word clock frequency when the signal is transmitted in an AC-coupled system. In addition, word clock and 64F_s64F by making such compensation for the clock cycle following clock matching_sF at the signal_s/ n Clock frequency components can be reduced. Reducing such frequency components is supplied to the PLL circuit and is used to generate the D / A and D / A converter audio sampling clocks at receive 64F._sIt is important to reduce low frequency jitter in the signal. Offset time (t) shown in Figure 32_clkmod) Is emphasized to clarify the figure. The actual amount of time shift is very small, for example 2014F_sPeriod (F_sIt is about 11.07ns) at = 44.1kHz. The shift or "pulse width deviation" introduced in the multiplexed clock signal 3230 shown in FIG. 32 does not have to be performed for every word clock cycle. The clock pulse width deviation may be performed every n × clk_fs clock cycle. Where n represents an integer controlled by a register. By introducing the clock pulse width deviation every n-word clock cycle in this way, the frequency F_s/ n clock signal is 64F_sIt is multiplexed into a clock signal. Since the frequency of the sampling clock (word clock) is known, the only information that should be transmitted by the transmitter is phase information, and this phase information allows the receiver to reproduce the word clock signal using a 6-bit counter. .. This counter is F_sReset by n signal, 64F_sIncremented by the clock. The signal formats shown in FIG. 32 are the transmitting side (generates a multiplexed clock signal) and the receiving side (F) in the connection._sGenerate a clock. ) Applies to both terminals.

FIG. 34 shows the configuration of a MAC-DSD transmitter 3400 (equipment equivalent to FPGA 512 shown in FIG. 6) suitable for transmitting both PCM and DSD data. MAC-DSD transmitter 3400 is 64F_sClock generator 3410 and F_sSynchronous signal generator (word clock generator) 3420, clock multiplier 3430, counter 3440, S-bit generator 3450, coding and block construction module 3460, interleaver 3470, FIFO buffer 3490, and frame assembler. Equipped with 3492.

The clock multiplier 3430 is based on the output from the word clock synchronous signal generator 3420, 64F._sA pulse width deviation clock signal (described with reference to FIG. 32) is generated by shifting a predetermined falling edge of the clock signal. The pulse width deviation clock signal is transmitted to the receiver via the twisted pair cable. Counter 3440 is 64F_sTrack the clock signal, F_sPre-empts the generation of synchronization signals. For the generation of S bits in the audio bitstream performed by the S bit generator 3450, F_sThe sync signal needs to be preempted. Note that the PCM sample is individually marked with a synchronization marker by M-bit encoding (see the 27-bit PCM audio sample structure in FIG. 27), while the DSD mode frame has a frame flag set in the transmitter and reception. It relies on the marker bit of the first sample of the flagged frame, which is set at the entrance of the machine's FIFO. The output signal from the S-bit generator 3450 is fed to the coding and block building module 3460, which generates the parity bit, inserts the padding bit only in the PCM mode frame, and frame payload. Build a 32-bit data block (see Figure 18B). The output signal from the coding and block building module 3460 is fed to the interleaver 3470, which feeds a 4-bit nibble of interleaved data to the FIFO buffer 3490. The transmitter FIFO buffer 3490 bridges the transmitter audio clock region and the link clock region (PHY element 514 in FIG. 6). The transmitter FIFO buffer 3490 has a width of 25 bits. Of these 25 bits, 24 bits are related to each of the 24 channels of the coexisting DSD or PCM audio sample, and the 25th bit is reserved as a synchronization marker. The 25th bit is the F of the transmitter whose corresponding DSD or PCM audio sample is_s/ n Indicates whether or not it appears at the same time as the clock edge. This will be described with reference to FIG. 33. Figure 3 shows five consecutive DSD samples (n-2), (n-1), n, (n + 1), (n + 2) and the local 64F of these samples._sThe relationship between the clock and the word clock is shown. As shown in Figure 33, the DSD sample n is a word clock and 64F._sIt coincides in time with both rising edges of the clock. Therefore, the rising edge of the marker bit is aligned with the start of the DSD sample n. Data from the transmitter's FIFO buffer 3490 is read according to the occupancy threshold level (as described above with reference to FIG. 14) and fed to the frame assembler 3492. The data from the frame assembler 3492 is fed to the transmitter PHY. The transmitter performs slightly different startup processing in PCM mode and DSD mode. In PCM mode, the transmitter will start transmitting as soon as possible at startup. Marked samples are explicitly indicated by PCM sample subframe "M-bit" coding. On the other hand, in DSD mode, the marked sample is not explicitly shown and is derived from flag bit 1 of the frame flag, as specified in the table shown in FIG. Therefore, when in DSD mode, the transmitter is one of the samples marked in the FIFO (ie, F)._sHolds the transmission of the first frame until the / n clock-synchronized sample) is readable. While the transmitter is in this hold state, the sample is read and dropped on the PHY clock side of the FIFO. An interleaving, coding and frame formatting mechanism such that when the marked sample becomes readable (indicated by flag bit 1), the marked sample becomes the first sample in the first frame. Is enabled. From this point of view, it can be said that the transmission of frames is governed by the buffer state (the state in which frame assembly can be started) and the rules of the frame format.

FIG. 35 shows the configuration of the MAC-DSD receiver 3500 (FIG. 7) adapted to receive both PCM and DSD data. MAC-DSD receiver 3500 is F_s/ n Synchroscope 3510 and F_sIt includes a clock generator 3520, a monostable counter 3530, a frame receiver and decoder 3540, a FIFO buffer 3550, a deinterleaver 3560, and a decoding / block disassembly module 3570. F_sA pulse width deviation clock signal is supplied to the / n synchroscope 3510 via a twisted pair cable, and F_s/ n Synchroscope 3510 is based on this signal, 64F_sDetermine the relative phase of the clock and word clock. F_s/ n Phase information is supplied to the word clock generator 3520, which is the word clock (F)._s) Output the signal.

The incoming cable clock signal is fed directly into the receiver system's local phase-locked loop to synchronize the receiver system. F derived from word clock generator 3520_sThe clock cannot be used for this purpose. This is because the word clock generator 3520 requires sequential logic to synchronize to the local PLL, and therefore the extracted signal is always synchronized to the local PLL. Therefore, the output signal of the word clock generator 3520 is not suitable as a synchronous source for the PLL.

In addition, F of the receiver_sThe clock signal is F_sAs a result of / n synchronization, transmitter F_sIt has the same phase as the clock signal. F_s/ n Phase information is also supplied to the monostable counter. Monostable counter is each F_sTriggered by reception of / n indication (Fs / n indication), 64F_sCount the clock period. The FIFO output is disabled by the detection of the first sample marked in the FIFO buffer 3550, at which point data fill into the FIFO buffer 3550 begins. 64F equal to the specified link wait time_sAfter the number of cycles has elapsed, the output of FIFO buffer 3550 is enabled. The predetermined link latency is set taking into account the delay that occurs in the transmitter for data coding and frame assembly and the delay that occurs in the receiver for decoding processing. The given latency of the data link is transmitted by the cable clock F_s/ n 64F measured for sync signal_sIt is programmed to be an integral multiple of the clock period.

The MII frame (consisting of nibbles) from the receiver's PHY element 526 (see Figure 7) is fed to the frame receiver and decoder 3540, which separates the header data and performs error checking. .. The decrypted data is supplied to the FIFO buffer 3550 in the form of MII nibbles. The FIFO buffer 3550 supplies the 4-bit data nibble to the deinterleaver 3560, and the deinterleaver 3560 deinterleaves the 3-bit data nibble. The deinterleaved data is supplied to the decryption / block disassembly module 3570, which extracts the audio data payload and outputs the audio data stream.

Figure 36 shows two sample sync links working in parallel, F._sThe configuration of the system in which this parallel link is synchronized using the / n synchronization signal is shown. The system consists of a transmitter 3600 and a receiver 3700 connected to the transmitter 3600 via a first cable 3603 and a second cable 3605. Transmitter 3600 comprises a first MAC-DSD transmitter 3610, which is connected to receiver 3700's first MAC-DSD receiver 3710 via first cable 3603. Has been done. The transmitter 3600 further comprises a second MAC-DSD transmitter 3620, which is the second MAC-DSD receiver 3720 of the receiver 3700 via the second cable 3605. It is connected to the. Two MAC-DSD transmitters 3610, 3620 are driven by the internal clock source 3630, and the internal clock source 3630 is on these MAC-DSD transmitters 3610, 64F._sIt supplies both clocks and word clocks. In receiver 3700, only the first MAC-DSD receiver 3710 operates as a clock source, thereby serving as a master clock. The first MAC-DSD receiver 3710 receives a word clock signal and 64F from the multiplexed clock signal received via the first cable 3603._sDerived the clock signal. When an independent word clock source is used here, neither the first and second MAC-DSD transmitters 3610 and 3620 function as a master clock source. 64F extracted from the signal supplied from the link cable 3603_sThe clock and word clock are supplied to the PLL3730, which supplies the word clock signal and 64F to both the first MAC-DSD receiver 3710 and the second MAC-DSD receiver 3720._sSupply a clock signal. The second MAC-DSD receiver 3720 does not function as a master clock source, F_s/ n It is necessary to reclock the multiplexed clock signal received via the second cable 3605 to detect the indicated information (ie, clock pulse width deviation). The propagation delay on the link over the first cable 3603 is often different from the propagation delay on the link over the second cable 3605. The difference in propagation delay between the link over the first cable 3603 and the link over the second cable 3605 is 64F received._sThe position of the edge of the clock signal is compared with the position of the edge of the locally reproduced clock signal (output from the PLL 3730), and the received F_s/ n The position of the instruction information and the locally played F_sJudgment is made by comparing with the word clock (also output from the PLL 3730). FIG. 37 shows a specific example of the difference in propagation delay measured between two links. In the specific example of FIG. 37, in the multiplexed clock signal 3810, the rising clock edge 3812 immediately after the shifted falling clock edge (pulse width deviated pulse) is 64F locally reproduced._sFor the corresponding rising edge 3822 of the clock signal 3822 and for the rising edge 3832 of the locally reproduced word clock signal 3830, t_offsetIt is shifting by minutes. That is, the received cable clock F_s/ n Instruction information is local F_sIt appears later in time than the clock edge. Local F_sClock Edge Clock Master Received Cable Clock F on MAC-DSD Link_sIf derived to synchronize with the / n directive, this indicates that the cable propagation delay on the second link 3605 is longer than the cable propagation delay on the clock master link 3603. The difference in propagation delay between the clock master link 3603 and the other link 3605 is t_offsetIs. Time t_offsetIs a negative value if the non-clock master link 3605 lags behind the clock master link 3603, as in the specific example above, and conversely, the non-clock master link 3605 is ahead of the clock master link 3603. If so, it will be a positive value.

At the receiver t_offsetWhen is determined, the following algorithm is executed to adapt the receiver latency monostable counter 3530 and ensure synchronization with the clock master link. t_offsetIf is positive (ie, if the non-clock master link 3605 is ahead of the clock master link 3603 in time), then F via link 3605_sWhen the / n instruction information is detected, the latency monostable counter 3530 in the MAC-DSD receiver 3720 is not started until the next word clock edge. On the other hand, t_offsetIf is negative (ie, the non-clock master link 3605 is behind the clock master link 3603 in time), t_offsetIs 64F_sRounded to an integral multiple of the period, subtract 1 from this value to calculate the value indicating the timeout for the non-master wait time monostable counter 3530. The latency monostable counter 3530 in the MAC-DSD receiver 3720 (non-master) is the first 64F following this outage._sIt is started at the clock edge of the clock signal. As a result, the stop period of the non-master waiting time monostable counter 3530 is synchronized with the monostable counter in the clock master receiver.

If a given link wait time elapses before the marked sample is detected in FIFO buffer 3550, this is a system failure or a set link wait time for the link state. Indicates that is too small. Therefore, if a waiting time elapses before the marked sample is detected, an interrupt signal is generated and an error indicating bit is set. Table 10 shows the link latency of 64F for each of the seven audio data formats._sIt is indicated by the period and μs.

<tables num="10"><img file="JP4625670B2_D0012.tif" /></tables>

FIG. 38 is a diagram illustrating the routing of auxiliary data by the MAC-DSD router 4030.

The router 4030 includes a plurality of MAC-DSD transmitters / receivers 4000, and each MAC-DSD transmitter / receiver 4000 transmits auxiliary data and voice data via an Ethernet physical layer device as described above, and such bits. When the stream is received, the audio data and the auxiliary data stream are separated. Note that the routing and processing of voice data is not shown in FIG. 38.

To transmit auxiliary data through this system, the auxiliary data is formatted into Ethernet-like packets, which are multiplexed into two auxiliary data channels by the MAC-DSD protocol. Will be done.

Specific examples of the types of auxiliary data carried include, but are not limited to, remote control data for recording and playback functions, general remote control data for audio and video equipment, and the like. There are time codes, media content metadata, auxiliary media such as streamed compressed video images associated with audio feed for audiovisual playback, and the like.

When one of the transmitters / receivers 4000 receives a bitstream, the transmitter / receiver 4000 separates the auxiliary data bits and feeds them to the auxiliary data bitstream-RMII interface 4010. RMII stands for Reduced Media Independent Interface and is established as a standard configuration in the Ethernet system, but it is also widely supported and is widely used in multi-channel Ethernet physical interfaces. Other interfaces such as media independent interface, SMII (serial media independent interface), SS-SMII (source synchronous serial media independent interface) may be used. The functionality of all these interfaces is roughly equivalent, but with different settings regarding the trade-off between pin count reduction and logic complexity.

As mentioned above, the auxiliary data is carried as a periodic single bit or a small group of bits distributed within the audio data bits.

The RMII interface 4010 converts auxiliary data bits from two channels within the MAC-DSD protocol into data packets, which are configured to mimic Ethernet protocol data packets. The data packet has a packet address that specifies the other one of the MAC-DSD transmitters and receivers (or both MAC-DSD transmitters and receivers in the case of "broadcast communication" messages).

The pseudo Ethernet packet is supplied to the conventional Ethernet switch circuit 4020, and the Ethernet switch circuit 4020 routes based on the packet address. Based on that routing, the packet is returned to the auxiliary bitstream-RMII interface 4010 and reformatted into the auxiliary data channel format for proper transport over the MAC-DSD channel. Auxiliary data is passed from interface 4010 to one or more suitable transmitters and receivers 4000.

FIG. 39 outlines a protocol for transporting auxiliary data.

At the bottom of Figure 39 is the Ethernet Physical Interface (PHY) layer. This layer is a common layer between the protocol shown in Figure 39 and the standard Ethernet protocol. Only the preamble is provided at the beginning of the physical layer data frame.

As described above, it is stipulated that data in the MAC-DSD frame format composed of 1448-byte frames is provided above the physical layer. At this top, payload coding provides 26 64Fs channels (bitstreams), including forward error correction and interleaving. However, this number of channels is arbitrarily selected according to the embodiment.

Further, as mentioned above, the payload can include, for example, an audio bitstream in DSD or PCM format and auxiliary data bits. For auxiliary data, a 512-byte frame is configured as a continuous 128Fs bitstream consisting of two auxiliary data channels. Within this 512-byte frame, the Ethernet data frame format is defined. (512 bytes is only a specific example of the frame length used in the first embodiment. In other embodiments, up to 1536 bytes, which is the highest frame length for conventional Ethernet transmission. If it is a length, different frame lengths can be used).

Therefore, the system carries frames that appear to be Ethernet auxiliary data frames when separated from the rest of the physical bitstream. However, these frames are not carried by the conventional Ethernet protocol, but instead are carried by being inserted into a 128Fs bitstream forming two auxiliary data channels. That is, the pseudo Ethernet frame is transmitted as continuous auxiliary data bits distributed within the audio data bits. Conventional Ethernet data processing devices cannot directly recognize these frames as Ethernet frames.

FIG. 40 shows the data structure of the auxiliary data frame. This data structure includes a fixed header 4040, a destination address 4050, a length field 4060, a payload 4070 and an error detection code 4080. The total length of the frame in this embodiment is a maximum of 128 words, which corresponds to 512 8-bit bytes.

FIG. 41 is a diagram illustrating the operation of the data reception mode of the interface 4010 and the switch 4020 shown in FIG. 38.

The 128Fs auxiliary data bits, which include two logical channels of auxiliary data and are separated in the MAC-DSD transmitter / receiver 4000, are supplied to the frame classifier 4100. Frames are identified in the auxiliary data stream by synchronization flags containing 01111111110 (1 0, 9 1, 1 0). Then, the frame is transmitted serially. To ensure the uniqueness of the synchronization flag, always insert (transmit) 0 immediately after 8 consecutive 1s in the frame data. Therefore, nine consecutive 1s indicate only the synchronization flag. An additional 0 is inserted regardless of what the bits following the 8 1s are. At the end of the frame, another sync flag is transmitted. During periods of no frame transmission, the bitstream contains a continuous synchronization flag.

Therefore, the frame classifier 4100 examines the received data and detects the presence of nine consecutive 1's, thereby detecting the frame synchronization flag.

The data is then passed to the descrambler 4110. Here, the reason for scrambling the data will be described.

In the above method, a large number of 0s are inserted into the data payload having the characteristic that 1s are frequently contiguous, which greatly increases the amount of data to be transmitted. This can significantly reduce the effective bandwidth of the system. Here, such a situation can be avoided by scrambling the data with a convolutional coder before performing bit stuffing (insertion of additional 0s). In this case, the increase in the amount of data due to the insertion of additional zeros is about 1 / (2).⁸) (1 bit for 256 bits, that is, 0.39%).

The scrambling encoder that performs this scrambling process is shown in FIG. 43, and the corresponding decoder is shown in FIG. 44.

The encoder is composed of a 9-bit shift register and an exclusive OR gate, whereby the input V and the output W have the following relationship. W = V * W^-5* W^-9 The descramble circuit shown in FIG. 44 is also composed of a 9-bit shift register and an exclusive OR gate, whereby the input Y and the output Z have the following relationship. Z = Y * Y^-5* Y^-9 Neither the scrambler nor the descrambler delays the signal. Therefore, there is no computational delay due to the cascade of scrambler and descrambler.

That is, the descrambler 4110 (FIG. 41) first removes all additional 0s (ie, the 0s after 8 consecutive 1s), and then the descrambler of FIG. 44 descrambles the data. To do.

The descrambled data obtained in this way is passed to the dual port random access memory (hereinafter referred to as DPRAM) 4120. The DPRAM4120 has two storage areas, each capable of storing at least a single data packet. While the data is being read from one storage area, it is written to the other storage area, and then the reverse processing is performed. Virtually all of the packets are loaded into one storage area of the DPRAM, and then, if the channel protocol allows (see description below), the packets of data are read by the RMII interface 4130. This data is passed from RMII interface 4130 to Ethernet switch circuit 4020. The details of this process will be described later.

As shown in FIG. 42, when the RMII interface 4130 receives a data packet from the Ethernet switch chip 4020, it stores this data packet in an additional DPRAM 4200. When a packet of data is constructed on the DPRAM 4200, it is passed to the scrambler 4210 (Figure 43). The scrambler 4210 includes a bit stuffer that adds 0 after eight consecutive 1s in the scrambled data stream. Further, the packet is passed from the scrambler 4210 to the frame marker adder 4220, where the frame synchronization code 01111111110 is inserted. Then, the bit stream obtained by this is transmitted via the auxiliary data channel of the MAC-DSD link.

Both the Ethernet switch chip 4020 and the RMII interface 4130 operate under the control of the RMII interface synchronization signal from, for example, a clock signal source 4140 operating at 50 MHz. As another embodiment, the configuration is simplified by operating the RMII interface and the Ethernet switch chip 4020 at a non-standard rate such as a clock rate synchronized with the audio master clock. it can. In such a configuration, the clock signal source 4140 may be replaced with, for example, a clock generator to which a 64Fs clock signal (or a signal related thereto) as shown in FIGS. 6 to 10 described above is input.

The transmission protocol used between the RMII interface 4130 and the Ethernet switch circuit 4020 is the so-called 100 Base-T half duplex system. This is a 100 Mbps configuration in which only one partner in the communication can transmit information at any time. Therefore, transmission (to or from Ethernet switch circuit 4020) may be bidirectional, but data transfer may occur in only one of two directions at any given moment. I can't. The reason for using the 100BASE-T half-duplex method will be described below.

The received data rate from the MAC-DSD transmitter / receiver (received by the frame classifier 4100) is 128 Fs or about 5.6 Mbps. Therefore, this is the maximum speed at which data packets should be sent from RMII interface 4130 to Ethernet switch chip 4020. This is also the maximum speed at which data can be transmitted from the Ethernet switch chip 4020 to the RMII interface 4130 during re-transmission via the MAC-DSD transmitter / receiver 4000. In a system with several nodes connected through a single router, multiple packets are often routed to a single egress MAC-DSD channel at a given time. This means that, in principle, the Ethernet switch chip 4020 may attempt to send data to a single RMII interface at data rates faster than 5.6 Mbps.

The Ethernet switch chip 4020 is a standard Ethernet device. Such devices are considered suitable because they are inexpensive and include logic for avoiding various types of transmission or reception errors. However, the 100BASE-T Ethernet switch chip 4020 does not include the logic to handle output channels whose streamed data rate is limited to 5.6 Mbps.

To avoid such problems, the RMII interface must have the ability to regulate the flow of data received from the Ethernet switch chip 4020. This is achieved using a half-duplex configuration.

As a basic matter, the RMII interface can indicate that it is going to send data to the Ethernet switch circuit 4020 using a signal called "RMII CRS_DV" or a carrier wave detection signal. When one party sends this signal, the other party in communication can complete the transmission of the current frame, but cannot start the transmission of the next frame. In this embodiment, this method is modified so that the RMII CRS_DV signal can be generated by one of the two methods described below. As shown in Figure 46, an OR gate combines two signals that can be generated by an RMII instrument. One signal is the frame generation signal CRS_DV, which is a conventional carrier wave detection signal generated only when a frame is about to be transmitted, and the other signal is a signal called RMII_lock.

RMII_lock is used as a "false" carrier detection signal to prevent the Ethernet switch chip 4020 from transmitting any data to the RMII device. RMII_lock is used when the RMII device or even the downstream device is not ready to receive further data. The method of generating RMII_lock will be described with reference to FIG.

FIG. 46 is a state diagram showing the state of the RMII device 4130.

First, in the idle state 4300, when receiving 450 bytes or more of data to be transferred from the MAC-DSD transmitter / receiver to the Ethernet switch chip 4020, RMII_lock is asserted (state 4310). Following this, the RMII device 4130 asserts CRS_DV. At this time, if the Ethernet switch chip 4020 is about to return data to the RMII device 4130, the Ethernet switch chip 4020 can complete the processing related to the current frame, but is allowed to start the transfer of a new frame. Not done. However, the Ethernet switch chip 4020 is operating at 100 Mbps, which is supplied because it is faster than the data rates of all (or at least some in other embodiments) MAC-DCD transmitters and receivers. Even if RMII_lock is asserted when the incoming data reaches 450 bytes, the Ethernet switch chip 4020 can complete the process of returning the entire frame to the RMII device 4130.

Then, when the input memory occupancy exceeds 486 bytes, the RMII device supplies data to the Ethernet switch chip 4020 (state 4320). The 486-byte threshold is based on a comparison of two data rates, 5.6 Mbps and 100 Mbps, and the rest of the frame is fed to DPRAM by the time almost the entire frame is transferred to the Ethernet switch chip 4020. Is the value selected as. Then, the RMII interface returns to the idle state.

RMII_lock is deasserted when the input memory is less than 450 bytes or the output memory is less than 486 bytes and the RMII device 4130 is idle (state 4330).

On the receiving side, data is received from the Ethernet switch chip 4020 (state 4340), and when reception is complete, RMII_lock is asserted (state 4350) and the RMII device 4130 returns to the idle state. As mentioned above, RMII_lock is not deasserted until the memory outputs the data received from the switch circuit.

The present invention may be realized by software, programmable hardware (eg FPGA or ASIC), hardware or a combination thereof. When the present invention is realized as a software component, the scope of the present invention includes a providing medium (for example, a storage medium, a transmission medium, etc.) that provides such software.

Although the present invention has been described in detail with reference to the accompanying drawings, the invention is not limited to the details of the embodiments described above, and those skilled in the art will appreciate the invention as defined in the appended claims. Various modifications and modifications can be made to the above embodiments without departing from the idea and scope.

<figref num="1">It is a diagram showing an Open Systems Interconnection (OSI) reference model with seven layers standard for a network protocol architecture and a sub-layer of the Ethernet physical layer.</figref><figref num="2">It is a figure which shows the structure of the well-known system for signal transmission in a DSD system.</figref><figref num="3">It is a figure which shows the DSD interconnection based on this invention.</figref><figref num="4">It is a figure which shows the star composition interconnection formed between a plurality of devices in a DSD facility.</figref><figref num="5">It is a figure which shows the audio data transmission system based on this invention.</figref><figref num="6">64F in parallel with DSD audio data via different signal pairs on Category 5 cable_sIt is a figure explaining the method of transmitting an audio sampling clock signal.</figref><figref num="7">It is a figure explaining the operation which receives a high frequency audio sampling clock in parallel with a DSD audio data signal.</figref><figref num="8">64F_sIt is a figure which shows the signal path of a sampling clock signal.</figref><figref num="9">The synchronization frequency of the physical layer device is the audio sampling clock frequency 64F_sIt is a figure which shows the Example which adjusts so that it becomes an integral multiple of.</figref><figref num="10">It is a figure which shows the structure of the point-to-point audio link which one device functions as a clock master 600M, and the other device functions as a clock slave 600S.</figref><figref num="11">It is a flowchart explaining the operation sequence performed to establish a synchronization link between a master device and a slave device shown in FIG.</figref><figref num="12">It is a figure which shows the structure of the system which made it possible to correspond to a larger number of channels as compared with a single point-to-point link by using a plurality of parallel links between two devices in an audio equipment.</figref><figref num="13">Clock signal F_s(A), F_sIt is a flowchart explaining how to maintain the synchronization of the output signals of two receivers using (B).</figref><figref num="14">It is a figure which shows how the buffering of audio data is performed in a transmitter.</figref><figref num="15">It is a figure which shows how the buffering of audio data is performed in a receiver.</figref><figref num="16">It is a figure which shows the data structure of the standard Ethernet frame.</figref><figref num="17">It is a figure which shows the data structure of the audio data frame based on this invention.</figref><figref num="18A">It is a figure which shows the format of the audio data frame configured as 384 4-byte data words.</figref><figref num="18B">FIG. 5 shows a 24DSD channel frame format in which each frame contains a 352 word sample for 24 channels and 88 bytes of auxiliary data.</figref><figref num="19">It is a figure which shows the format of the control data which was configured as 26 4-byte data words.</figref><figref num="20">It is a figure which shows three 16-bit frame format fields corresponding to the frame format shown in FIG. 18B.</figref><figref num="21">FIG. 5 shows three 4-nibble sections of a frame format ID, including a set of data entries processed by the receiver.</figref><figref num="22">It is a figure which shows the format of the 32-bit data block corresponding to the 24DSD channel frame format shown in FIG. 18B.</figref><figref num="23">A is a diagram illustrating how to generate 6 parity bits P0 to P5 from 24 audio data bits and 2 auxiliary data bits, and B is an XNOR for the received data element. It is a figure explaining how the syndrome is generated by performing a logical operation.</figref><figref num="24">It is a table which shows the structure of the stream of the nibble output from the interleaver for the 24DSD channel frame format shown in FIG. 18B.</figref><figref num="25">It is a figure which shows the protocol layer of the MAC-DSD protocol in a specific example using a 24DSD channel frame format.</figref><figref num="26">A is a diagram showing an AES3 subframe format, and B is a diagram showing a subframe format for PCM transmission based on the present invention.</figref><figref num="27">It is a figure which shows how to multiplex three different instruction information S, Z, V using the M bit shown in FIG. 26B.</figref><figref num="28">It is a figure explaining the situation that the S bit has priority over the Z bit in the M bit of the subframe format shown in FIG. 26B.</figref><figref num="29">It is a figure which shows 10 different frame type field values corresponding to the number of sample subframes per frame.</figref><figref num="30">It is a table which shows the information derived from the flag field of the frame format shown in FIG. 18B.</figref><figref num="31">It is a table showing how to interpret the values of the two flag bits related to the base clock.</figref><figref num="32">64F_sIt is a figure explaining the process of generating a multiplexed clock signal based on a signal and a word clock signal.</figref><figref num="33">5 consecutive DSD samples and the local 64F of these samples_sIt is a figure which shows the relationship with respect to a clock and a word clock.</figref><figref num="34">It is a figure which shows the structure of the MAC-DSD transmitter adapted to the transmission of both PCM data and DSD data.</figref><figref num="35">It is a figure which shows the structure of the MAC-DSD receiver adapted to receive both PCM data and DSD data.</figref><figref num="36">Two sample sync links work in parallel, F_sIt is a figure which shows the structure of the system which this parallel link is synchronized using the / n synchronization signal.</figref><figref num="37">It is a figure which shows the specific example of the difference of the propagation delay measured between two links shown in FIG. 27.</figref><figref num="38">It is a figure explaining the routing of auxiliary data by a MAC-DSD router.</figref><figref num="39">It is a figure which shows the protocol which transmits auxiliary data.</figref><figref num="40">It is a figure which shows the data structure of the auxiliary data frame graphically.</figref><figref num="41">It is a figure which shows the operation of the auxiliary data router in a data reception mode.</figref><figref num="42">It is a figure which shows the operation of the auxiliary data router in a data transmission mode.</figref><figref num="43">It is a figure which shows the structure of the data scrambler.</figref><figref num="44">It is a figure which shows the structure of the data desk ramper.</figref><figref num="45">It is a figure explaining the generation of the carrier wave detection / reception data confirmation signal.</figref><figref num="46">It is a figure explaining the RMII lock function.</figref>