Subscriber unit for wireless digital subscriber communication system

INTERNATIONAL MOBILE MACHINES CORPORATION

Subscriber unit for a digital radio electric subscriber communications system

Background and Summary of the Invention

The present invention is generally directed to subscriber communication systems, particularly addressing an improved subscriber unit for wireless communication with a base station in a digital radio subscriber communication system.

U.S. Patent Application No. 06 / 893,916, filed August 7, 1986 by David N. Critchlow et al., Describes a typical subscriber unit. A base station used such as a subscriber unit in a digital subscriber communication system is described in U.S. Patent 4,777,633 issued to Thomas E. Fletcher, Wendeline R. Avis, Gregory T. Safee and Karle J. Johnson.

The subscriber unit described in said patent application N-06/893 916 includes means for the transcoding of

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a digital voice input signal for providing digital input symbols; means for finite-impulse-response (FIR) filtering of input digital symbols; means for deducing an intermediate frequency analog input signal from the filtered input symbols; means for combining the intermediate frequency input signal with an RF carrier for radio transmission to the base station; means for demodulating an output signal received at the base station to provide digital output symbols; and means for synthesizing an output digital vocal signal from the output digital symbols. The subscriber unit includes a baseband processor chip and a modem processor chip. They are both TMS32020 digital signal processors. The microprocessors of the baseband processors transcode the incoming digital voice signal, synthesize the outgoing digital symbols and various control functions in the baseband; and the modem processor chip performs FIR filtering of the input digital symbols and demodulation of the output signal received from the base station. The modem processor chip generally acts as the system steering device.

Summary of the invention

The present invention provides a more economical subscriber unit. The subscriber unit of the present invention includes means for transcoding an input digital voice signal to provide input digital symbols;

means for FIR filtering of input digital symbols; means for modulating an intermediate frequency digital signal with the filtered input symbols to provide an intermediate frequency modulated input signal; means for processing the modulated input signal for transmission to the base station; means for demodulating an output signal received from the base station to provide digital output symbols; and means for synthesizing an output digital vocal signal from the output digital symbols; the subscriber unit including an FIR chip for FIR filtering of input digital symbols; a Digital Intermediate Frequency (DIF) chip for digitally synthesizing said digital intermediate frequency signal and for modulating said digital intermediate frequency signal; and a single processor chip for effecting said transcoding of said digital input voice signal, for effecting said demodulation of said output signal from the base station and for performing said output digital symbol synthesis.

The FIR chip performs the FIR filtering function which was performed practically programmatically on the prior art subscriber unit modem processor described above. By removing the time-consuming transmission FIR filtering function from the modem processor and performing the demodulation function with the same processor as the basic band processing function, only one processor chip is required.

The means for digitally synthesizing the digital intermediate frequency signal comprises a direct digital synthesizer (DDS), including means coupled to the processor chip for accumulating phase data provided by the processor chip to indicate a predetermined intermediate frequency; and means for processing the accumulated phase data to generate the digital intermediate frequency signal at the predetermined intermediate frequency. The present invention thus adds new functionality to the subscriber unit, which did not exist in the prior art subscriber unit described above, in that direct digital synthesis allows for extremely flexible tuning of the subscriber unit. In the prior art subscriber unit described above, tuning was limited to a finite set of channels, spaced by 25 KHz increments. Also the frequency difference between transmit and receive was set at 5 MHz. The DIF chip DDS function removes these limitations, thus allowing other types of channel spacing and other transmit / receive deviations, which are allowed with minimal modification, or even without modification to the subscriber unit's material equipment.

Accordingly, the DIF chip provides a fully modulated intermediate frequency (IF) digital signal, which can be digitally synthesized at any of a number of predetermined different IF frequencies, and frequency adjustment with a higher resolution can be provided. on the DIF chip to enable frequency tracking of the output signal received at the base station. These two features allow the subscriber unit radio to contain only one fixed LO frequency reference and eliminate the need for an RF synthesizer. These two features also allow the primary frequency reference on the subscriber unit to be fixed, all tuning adjustments being made by the DIF chip.

A direct digital synthesizer is stable and easy to produce. Phase noise specifications can be met without the need for an expensive and complex PLL RF synthesizer. DDS features provide frequency agility within the IF band and provide easier frequency modifications to operate on other bands.

Another feature of the present invention is that the FIR chip includes means for generating time distribution signals for timing distribution for the transcoding operation and for the digital output vocal signal synthesizing operation by the processor chip.

However, the microprocessor chip demodulates the output signal received from the base station, regardless of the time distribution signals generated by the FIR chip. The processor chip receives said output signal according to the time distribution signals generated by the FIR chip and temporarily stores the output signal received for demodulation, thereby allowing the processor chip to perform said demodulation when not in use. to perform the above transcoding and synthesizing operations.

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The present invention also reduces manufacturing costs by including a combination of a slow memory coupled to the processor chip to store processing codes used by the processor chip, when said codes do not have to be operated with zero wait states and a fast memory coupled to the processor chip to temporarily store codes used by the processor chip when said codes are operated with zero wait states. Fast RAM (with a zero wait state) and fast EPROM memories with the same density as the chip are very expensive. To reduce costs, processor codes can be stored in a slow EPROM (with one or more wait states) and, when null wait states are required, the code can be loaded upward from slow memory to memory. quick and run from there.

Other features of the present invention are described in connection with the description of a preferred embodiment.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings, the figures represent:

Fig. 1 is a block diagram of a preferred embodiment of the subscriber unit according to the present invention;

Fig. 2 is a block diagram of the FIR chip included in the embodiment shown in FIG. 1;

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Fig. 3 is a block diagram of the DIF chip included in the embodiment shown in FIG. 1;

Fig. 4, the processing tasks performed by the processor chip represented in the embodiment of FIG. 1; and

Fig. 5, the processing routines included in the modem processing task shown in FIG. 4

DEFINITION OF ABBREVIATIONS AND ACRONYMS

Following is the definition of acronyms for acronyms used here:

A / D Analog to Digital - Analog to Digital

AGC Automatic Gain Control - Automatic Gain Control

ASIC Application Specific Integrated Circuit - BPSK Application Specific Integrated Circuit Binary Phase Shift Keying - Phase Shift Binary Modulation

CCT Channel Control Task - Channel Control Task

CCU Channel Control Unit - Channel Control Unit

CRC Cyclic Redundancy Check - Cyclic Redundancy Control

DAC Digital to Analog Converter - Digital to Analog Converter

DDS Direct Digital Synthesizer - Direct Digital Synthesizer

DIF Digital Intermediate Frequency

DIP Dual In-Line Package - Two In-Line Package

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ACHE

DPSK

DSP

EPROM

FIR

I / O

LSB

MPT

MSB

Mux

PCM

PLL

PWM

QPSK

RAM

CCR

RELP

RF

ROM

RX

RXCLK

Data Output Ready - Ready Output Data

Differential Phase Shift Keying - Differential Phase Shift Modulation

Digital Signal Processing - Digital Signal Processing

Erasable Read Only Memory - Erasable Programmable Physical Memory

Finite Impulse Response - Finite Impulse Response Input / Output - Input / Output

Least Significant Bit - Least Significant Bit

Modem Processing Task - Modem Processing Task Most Significant Bit - Most Significant Bit Multiplexer - Multiplexer

Pulse Code Modulation - Phase Locked Loop Coded Pulse Modulation - Forced Phase Locked Loop

Pulse Width Modulation - Quadrature Phase Shift Keying - Quadrature Phase Shift Modulation

Random Access Memory - Random Access Memory Radio Control Channel - Radio Control Channel

Residual Excited Linear Predictive - Residual Excited Linear Predictive

Radio Frequency - Radio Frequency

Read Only Memory - Fixed Memory

Receive - Reception

Receive Clock - Receive Clock

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RSOS Receive Start of Slot

SCT Subscriber Control Task - Subscriber Control Task

SLIC Substriber Line Interface Circuit - Subscriber Line Interface Circuit

SPC Signal Processing Control - Signal Processing Control

SPT Signal Processing Task - Signal Processing Task

SPTCTL Signal Processing Task Controller - Signal Processing Task Controller

SSB Switch-hookSampl-e Buffer Switch Buffer Memory

TDM Time Division Multiplexing - Time Division Multiplexing

TX Transmit - Issue

TXCLK Transmit Clock - Broadcast Clock

UART Universal Asynchronous Receiver Transmitter - Universal Arrhythmic Emitter / Receiver

VLSI Very Large Scale Integration - Very Large Scale Integration

XOR Exclusive OR - OR Exclusive

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, a preferred embodiment of the subscriber unit according to the present invention includes a telephone interface circuit (10), a

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SLIC and encoder-decoder (11),_Ua processor chip (12), a fast memory (13), a slow memory (14), an address decoder (15), an FIR chip (16), a DIF chip (17), a DAC (18), an A / D converter (19), a radio (20), a draw current generator circuit (21) and an oscillator (22).

The FIR chip 16 which is an ASIC chip has an interface with the DIF chip 17 along lines 23 and 24 with the processor chip 12 along the bus line 25 and line 26 for A / D converter 19 for line 27 for SLIC circuit and encoder-decoder 11 for line 29 for radio 20 for line 30) and to the ring current generator circuit (21) by line (31).

The telephone interface circuit 10 is interfaced with a telephone 32 which converts sound waves into an input voice signal and converts a freckle voice signal into sound waves.

The SLIC and encoder-decoder circuit (11) is coupled to the telephone interface circuit (10) to convert the input voice signal to an input baseband digital signal, which is provided to the processor chip (12).

In an alternate embodiment (not shown), the processor chip also interfaces directly with a UART to alternatively receive digital input signals directly from a digital signal device 1/0 and output digital signals directly to the UART. same.

The processor chip (.12) includes a model TMS320C25 digital signal processor, which transcodes the signal

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bandwidth input digital according to a RELP algorithm for providing TX digital data input symbols on the processor bus (25). The use of a digital signal processor to perform a RELP algorithm is described in International Patent Application NPCT / US85 / 02168, International Publication No. WO 86/02726, published May 9, 1986.

The FIR chip 16 filters the input digital symbols and provides I, Q data to the DIF chip 17 by the lines 24.

The DIF chip 17 interpolates the filtered input digital symbols and modulates an intermediate frequency digital signal with the interpolated input symbols to provide a modulated input digital signal.

DAC 18 converts the modulated digital input signal to a modulated analog input signal.

The radio 20 outputs the modulated analog input signal to the base station and receives and demodulates an analog output signal from the base station.

Oscillator (22) is a free oscillating oscillator that provides clock signals to the processor chip (12).

U.S. Patent No. 4,777,633 describes the relationship between the subscriber unit and the base station.

The A / D converter 19 converts the demodulated received analog output signal to a digital output signal containing symbols

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digital outputs.

The processor chip 12 synthesizes a baseband digital signal from the output digital symbols.

International Publication No. WO 86/02726 also describes the synthesis of RELP transcoded symbols by a digital signal processor. The processor chip 12 further performs echo suppression as described in U.S. Patent No. 4,697,261 to David TK Wang and Philip J. Wilson.

The SLIC and encoder-decoder circuit (11) converts the basic band digital output signal to the output vocal signal that is provided to the telephone interface circuit to the telephone (32).

FIR chip 16 consolidates circuit functionality into a VLSI device to reduce the cost of subscriber unit production by eliminating many separate, medium-scale integrated parts.

Referring to fig. 2, the FIR chip 16 includes an output fan buffer 33, an internal decoding module 34, an RX sampling buffer 35, command and status registers 36, a external address decoding module (37), a surveillance time distribution module (38), an RX time distribution module (39), a TX time distribution module (40), a FIR TX filter (42), a codec time distributor module (44) and a call current generator control module (45).

FIR chip 16 provides 45 ms frame marker pulse generation, 11.25 ms time band marker pulse generation, 16 KHz symbol clock generation, RX sampling buffer memories, TX symbol buffer memories, 8 KHz codec timing distribution generation, processor interface decoding, timing distribution generation for the call current generator, decoding of external addresses and generation of reset pulses of the surveillance circuit time generator. The FIR chip 16 temporarily stores two 5-bit TX symbols with a frequency of 8 KHz. FIR chip 16 converts and filters TX symbols into I and Q symbols, each of which is 10-bit symbols with a frequency of 160 KHz. The data I and Q are interlaced and constitute an output to the DIF chip 17 at a frequency of 320 KHz. The FIR chip 16 also temporarily stores RX data samples with a frequency of 64 KHz, and four RX data samples are read by the processor chip 12 with a frequency of 16 KHz. Clock signals and time distribution signals are generated by the FIR chip 16 from a received 3.2.MHz parent clock signal. Processor chip 12 is synchronized to these data rates by time slot and symbol interruptions generated by FIR chip 16. The 8 KHz time distribution synchronization pulses of the encoder-decoder and processor are generated by the FIR chip 16 and synchronized with the time of the received RX samples. FIR chip 16 also generates command and time distribution signals for

14controlling the form and timing of the draw current voltage provided by the draw current generator circuit (21).

Surveillance time distributor module (38) provides a reset signal in case the processor chip (12) does not perform the functions properly.

The output fan buffer 33 temporarily stores a 3.2 MHz clock signal received by line DIF chip 17a, an early 3.2 MHz clock signal received by line 23b ) of the DIF chip (17) and a reset signal received on the line (51) of the surveillance time distributor (38). Unless otherwise indicated, all times within the FIR chip 16 are derived from the 3.2 MHz clock signal on line 23a. 0 3.2 MHz clock ahead on line 23b is advancing with respect to the 3.2 MHz clock signal on line 23a of a 21.76 MHz reference signal cycle which is present inside the DIF chip (17). The 3.2 MHz clock signal is derived from the 21.76 MHz reference on the DIF chip 17, with the minimum pulse duration being 276 ns.

Advance 3.2 MHz clock signal from line 23b is provided from buffer 33 through internal line 47 to the FIR TX filter 42 and to the encoder timing module decoder (44). The TX FIR filter 42 is made in part by a pseudo-static ROM which requires its activation input to be deactivated by the 3.2 MHz clock signal advanced on line 47 between successive accesses.

The HW RESET signal on line 51 resets all circuits of the FIR chip 16 and provides a material replacement of the modules of FIG. 1.

Internal clocks are either versions, obtained through buffered (temporary) memories, of the 3.2 MHz mother clock received on line 23a, or divisions of this clock.

internal address decoding module (34) allows the processor chip (12) to access internal functions of the FIR chip (16) for purposes of controlling those functions and determining their status. This internal address decoding module (34) receives processor addresses and processor synchronization pulses over the bus line (25). The internal address decoding module (34) provides output signals on the internal bus line (48).

Bus line output signals 48 from internal address decoding module 34 include an RX sample buffer read enable signal (35), a control write signal and status read signals for control and status registers (36), a write signal for the FIR TX filter (42), time band and clock write signals for the time distribution module RX (39), a write signal for the TX time distributor module (40) and control signals for the FIR TX filter module (42) and for the RX sample buffer (35), and an AM sync pulse signal, which causes the time distribution module RX (39) to reset the time distribution of time bands. At a time, one of the signals respectively of

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Reading or writing is always active on the bus (48) from the internal address decoding module (34).

The RX sample buffer (35) receives four samples at each RX symbol time from the A / D converter (19) through line (27a) at the frequency of 64 KHz; temporarily memorizes up to two data symbols, giving a total of eight samples, then outputting these data samples to processor chip 12 via bus 25. The RX sample buffer (35) is implemented by a two page RAM. The RX sample buffer (35) receives a read enable signal from the internal bus line (48) from the internal address decoding module (34) and a write synchronization pulse signal from the internal line (49) of the RX time distributor module (39).

The control and status registers (36) allow the processor chip (12) to control the internal functions of the FIR chip (16) and allow the processor chip (12) to read the status of the TX FIR filter (42) and the RX sample memory (35), and other internal signals. The control signals are provided by the processor chip 12 via the processor bus 25 and the status indications are derived from various internal modules of the FIR chip 16. Status indications are provided to the processor chip (12) via the bus line (25). Status indications are RX UNDERRUN, RX OVERRUN, TX UNDERRUN TX OVERRUN, START-OF-FRAME, RX START OF SLOT, TX SYMBOL CLOCK,

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RX SYMBOL · CLOCK and TX FIR FILTER OVERFLOW.

The control signals, which are provided by the control registers (36) for the internal circuits via the internal bus line (48), include the following: TX ENABLE, MODULATION LEVEL, RINGER ENABLE, SOFTWARE RESET, TRISTATE and WATCHDOG STROBE.

TX ENABLE signal indicates the start of a time range ΊΧ based on the TX delay set in the time distributor module (40).

The Modulation Light signal is supplied to the time distribution module RX (39) and determines whether the time span duration is 180 or 360 symbols.

The Software Reset signal allows the processor chip (12) to reset internal functions within the FIR chip (16).

The Tristate signal allows the processor chip (12) to disable the outputs of the FIR chip (16).

The Ringer Enable signal allows the processor chip (12) to turn the call current generator circuit (21) on and off. This signal provides a 2 s and 4 s rate for the draw current signal.

Watchdog Strobe signal allows the processor chip (12) to reset the watchdog timing module to prevent a replacement of media.

The processor chip 12 receives an RX clock interrupt signal (RXCLKINT) from the distribution module ί

RX (39) through line (26c) when data has been written to the first four positions of the double-page RAM of RX sample buffer (35). The processor chip 12 then reads RX samples from the first four positions of the two-page RAM through the processor bus 25. Samples are now being written in the next four positions of dual-page RAM, at a frequency of 64 KHz. 0 The 16 KHz event is derived from the 64 KHz event, which keeps the read and write events synchronized. This ensures that read and write operations do not occur at the same time in any memory position and also ensures an appropriate response time from the microprocessor chip portion (12).

A TX symbol buffer in the FIR TX filter (42) receives TX symbols from the processor chip (12) via the processor bus (25) and temporarily stores up to two TX symbols. The processor chip 12 is interrupted at alternate times of TX symbols to write two more symbols in the TX symbol buffer.

The TX symbol buffer in the FIR TX filter (42) receives a write signal through the internal bus line (48) from the internal address decoding module (34).

After each TX clock interrupt signal (TXCLKINT) at 8 KHz on line 26a, processor chip 12 outputs two 5-bit TX symbols. The data is in Gray DPSK code format. TX symbol buffer outputs a symbol at 16 KHz frequency for processing

19. by the FIR TX filter (42). This signal is temporarily memorized doubly due to an asynchronism between the FIR chip 16 and the processor chip 12. The last data value is repeated until new data is written. This way no data can be repeated. The TX symbol buffer is cleared during a reset.

During training, a fixed sequence of symbols is issued to the FIR chip 16 by the processor chip 12. The FIR chip. (16) performs FIR filtering of these symbols and outputs pairs I, Q to chip DIF (17).

radio (20) returns the data loop to the A / D converter (19). Samples are read by the processor chip (12) as in-line mode, the processor FIR RX filter coefficients being performed on the processor chip (12). The only critical training times are generated by the time distribution modules RX and TX (39) and (40).

The time distribution module RX 39 generates all reference clocks and synchronization pulses for processing the RX symbols. The times are adjusted by the processor chip 12 so that processing can be synchronized with the received RX samples through the base station line 27a. The RX time distributor module (39) includes an RX clock fraction time distribution circuit and an RX time band time distribution circuit. The purpose of these two circuits is to synchronize modem reception times within processor chip 12 to RX samples received on base station line 27a, and through A / D converter 19, and also adjust the TX time distribution module (40) and the encoder-decoder time distribution module (44).

Time distributor module RX 39 receives clock pulses at 3.2 MHz and receives the following inputs of control chips from processor chip 12 via processor bus 25: an AM Strobe signal, a RX Slot Clock Write signal and an RX Bit Tracking signal.

Several outputs are generated by the time distribution module RX (39). Write synchronization pulses at 64 KHz are provided on line 49 to control writing to RX sample buffer 35. A 64 kHz A / DSYNC sync pulse signal is provided on line 27b to the A / D converter 19 to synchronize its operation. An 8 kHz sync pulse signal is also provided to the encoder-decoder time distribution module (44) via line (52). An output of a 16 kHz RX clock interrupt signal (RXCLKINT) on line (26c) and an RX time range start interrupt signal (RXSOSINT) on line (26b) is provided to the processor chip ( 12). A time distribution synchronization signal of the pre-RX time range on line 54 is provided to control the TX time distributor module 40.

The time distribution circuit fractionated in the time distribution module RX (39) is adjusted by the chip.

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of processor (12) to generate the RX time range start interrupt signal on line (26b). The processor chip 12 determines the situation of an AM void (sync signal) transmitted by the base station during acquisition. When the processor chip (12) detects the AM Strobe signal, the time slot timing circuit in the time slot module RX (39) is reset by a reset signal from the processor chip (12). This aligns the frame and time mark marks on the AM Strobe signal. The frame mark is a 62.5 micro-second pulse that occurs every 45 ms. The timeline mark is a 62.5 micro-second pulse that repeats all 11.25 ms, or all 22.5 ms when in QPSK mode.

The received RX symbols are demodulated by the processor chip 12 and the times are reset if necessary. To adjust the 16 KHz RX symbol clock, the processor chip forces the fractional time distribution (bit tracking) circuit to shorten or extend the 64 KHz synchronization pulses to fifty 3.2 MHz cycles.

Processor chip 12 monitors the relationship of RX symbols to frame times and makes adjustments to the 16 KHz RX clock accordingly. When the RX clock is set, the time and frame marks also change, as they are derived from the RX clock.

To maintain the number of PCM samples provided to or by the SLIC and the synchronous encoder-decoder circuit (11)

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The time distribution module RX (39) controls the time distribution module of the encoder-decoder (44).

TX time distributor module 40 includes a TX delay circuit and a TX control time distribution circuit. These circuits generate a TX clock interrupt signal (TXCLKINT) which is provided to the processor chip 12 via line 26a. The TX timing distributor module (40) is synchronized with the RX timing distributor module (39) by the timing band timing synchronization pulses, which are provided to the TX timing distributor module by the RX timing distributor module ( 39) at line 54 and used to reset the TX delay circuit which in turn generates the TX time band mark. The time distribution of the TX clock is based on the internal 3.2 MHz clock.

The processor chip (12) also controls the TX delay and the TX time distribution circuits by providing TX data write control signals over the processor bus (25).

The TX time distributor module (40) provides a T / R control signal on line (30) to radio (20). This signal determines whether the radio is broadcasting or receiving data.

The TX time distributor module (40) also controls TX symbol offset, ROM addressing, accumulation time distribution, and storage of the I, Q product to provide DIF chip 17 at its output. .

The TX time distributor module (40) provides control signals on line (56) to keep the FIR TX filter (42) synchronized with symbol times and TX time bands. This synchronization is made according to the time distribution mark of the TX time bands. After a reset, the TX time distributor module 40 actively generates control signals for line 56 once a TX time band has started.

TX FIR filter (42) includes a ROM, which performs an FIR filter, providing data products I and Q in response to the ROM being addressed for consideration by a combination of TX symbols received from processor chip (12) through of the processor bus line (25) and for sine and cosine coefficient counting provided by a counter inside the FIR TX filter module (42). 0 The FIR TX filter (42) accumulates six sequential I and Q data products and stores output results for the DIF chip 17 via line 24a.

The minimum frequency required for FIR TX filter operation (42) is determined by the symbol rate (16 KHz) times the number of samples I and Q (2), times the number of coefficients (10), times the number of leads (6) = 1.92 MHz. The 3.2 MHz motherboard meets this minimum frequency requirement. Waiting periods are added to compensate for a faster execution time.

The TX time distributor module 40 receives clock pulses at a frequency of 3.2 MHz, which defines a state period. Because this clock frequency is greater than the minimum required (1.92 MHz), the FIR TX filter generates signals for the first 6 of 10 state periods.

Each new TX symbol must be loaded into a circular buffer in the FIR TX filter (42), with the frequency of 16 KHz. The new TX symbol and the previous five TX symbols are stored in the circular buffer. The oldest TX symbol is rejected when a new TX symbol is entered. The FIR TX filter (42) has a frequency output of 320 KHz. From each TX symbol ten data values ​​I and ten data values ​​Q are generated. The following Table 1 shows how I, Q and zero information can be derived from each 5-bit value:

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5

I &amp; Q LSB I &amp; QI MSB Q MSB ZERO

TABLE 1

The data in the circular buffer is rotated every 6 of the 10 states . A new Tx symbol and the five previous TX symbols reside in circular buffer for twenty of these ten state periods. The coefficient part of the ROM address is also increased every 6 of the 10 state periods. An accumulator in the FIR TX filter (42) adds the results of each data product I provided from the ROM for each of the six state periods. Accordingly, the accumulator recorder is cleared for the first addition, each result of successive additions being input by clock pulses into an accumulator feedback register so that it can be added to a reconsidered product. Once six additions have taken place, the result is entered into an output shift register. The same process is true for the same coefficients and the Q data products provided from ROM for each TX symbol.

ROM address lines allow sixty deco-sine coefficient searches and sixty sine coefficient searches for four possible data indices I, Q. This requires seven address lines for coefficients and two address lines for I, Q data. FIR filter output requires 10 bits. Two additional supplementary bits are required to maintain the precision of the decimal part of the observed value. As a result, the size of the ROM is 512 x 12. The MSB of data index I, Q is passed around ROM to the complement loop to 1 ,. which forces the ROM output to be inverted or not inverted.

If the ROM address symbol is a zero symbol, the zero bit controls four of the seven coefficient address lines. Since seven address lines are used to search for coefficients, this provides 128 positions. Only 120 coefficients are required. This leaves eight unused positions. At these positions zeros are inscribed, so that zero information can be provided at ROM output easily.

A complement function for 2 is performed using a complement for 1 and carrying a logical 1 to the next adder. The output of the adder is either returned to the adder input for successive additions or outputs via an MUX to an output offset register. The output is rounded using only the upper 10 bits.

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The circular buffer memory outputs of the FIR TX filter are set to zero after a reset. This allows null information to be processed until new TX symbols are loaded. First process data I, followed by data Q.

TX clock interrupt signal only occurs during a TX time range. The processor does not know when a TX time range begins or ends except by responding to this interrupt. The signal has a short active duration of a 3.2 MHz clock cycle to ensure that the interrupt is not active once it is answered. TX clock interruption occurs at alternating symbol times (16 KHZ / 2).

RX watch interruptions occur in a complete frame. The processor chip 12 masks this interruption, using the time slot mark RX as a mask. RX clock interruption has a short active duration of a 3.2 MHz clock cycle. RX clock interruption starts every 11.25 ms, and has a short active clock cycle duration of 3 2 MHz.

Each interrupt signal is forced to the idle state upon a reset.

Encoder-decoder time-distributing module (44) generates synchronization pulses and outputs the necessary clock signal through lines (29) to the SLIC and encoder-decoder circuit (11) to make them transfer 8 bits of data between the encoder-decoder and the processor at a frequency of 8 KHz. Encoder-11 receives and outputs 8 data bits at the 8 KHz rate. 0 encoder-decoder time-distributing module (44) outputs an encoder-decoder clock signal on line (29a) and an encoder-decoder synchronization signal on line (29b). The encoder-decoder clock signal on line 29a is generated at a frequency of 1.6 MHz, dividing the advance 3.2 MHz clock by two. 8 KHz pulses from a 3.2 MHz period are received from the RX time distribution circuit (39) and are set on another clock to occur over a 1.6 MHz period, thus ensuring that they occur in relation to the rising flanks of the watch

1.6 MHz. With these two signals, PCM data is transferred between the encoder-decoder (11) and the processor chip (12). This allows subscriber PCM data to synchronize with base station PCM data.

call current generator control module (45) responds to a call current activation control signal originating from the processor chip (12) and providing from the control and status register (36) on the bus line (48) generating a 20 Hz square wave signal on line (31a) and two 80 KHz phase control signals, PHASEA on line (31b) and PHASEB on line (31c), and emitting these signals to the calling current generation circuit (21). The 20 Hz square wave signal on line 31a controls the polarity of the draw current voltage provided by the draw current generator circuit (21) to the telephone interface circuit (10). The 80 kHz phase signals on lines 31b and 31c control the pulse-modulated power source in the draw current generator circuit 21.

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A SLIC reset or command signal on line 29c from the SLIC portion of the SLIC circuit 11 and encoder-decoder shuts off or overlaps these signals on lines 31a, 31b ) and (31c) after the call-current activation signal originating from the processor chip 12 has switched on. This ensures that the call current generator is turned off if a reset occurs or the handset is lifted from the cradle.

As the loop current generator circuit 21 generates a high voltage and consumes a lot of power, this voltage is only generated when requested by the processor chip 12.

external address decoding module (37) generates microprocessor selections on the processor bus (25) that are used by processor microprocessor (12) to access DIF microprocessor (17), UART media and slow memory EPROM ( 14), in separate segments of different addresses. Processor chip 12 provides eight lines of MSB address, data space and data space signals. These are decoded to generate the appropriate chip selections.

surveillance time distributor module 38 generates a 50 ms reset pulse of the media on line 51 which resets all modules of the FIR chip 16 and the subscriber unit modules of FIG. 1. Surveillance pulse distributor module (38) generates a pulse, if not reset within 512 ms by the guard circuit synchronization signal provided by the bus line (48), by the data registers (36).

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tf control and states.

DIF chip 17 is interfaced with processor chip 12 by bus line 25, FIR chip 16 by lines 23 and 24 with DAC 18 by line (71) and with an oscillator in the radius (20) along the line (72).

The oscillator on the radio 20 provides a 21.76 MHz mother clock signal on line 71 of the DIF chip 17.

With reference to fig. 3, the DIF chip 17 includes a clock generator 60, a processor decoding module 61, an interface module 62 with the FIR chip, an interpolator 63, a command register (3). 64), tuning registers (65), a DDS phase accumulator (66), sine and cosine generation DDS kidney module (67), a modulator (68) and a noise signal conformer (69) ). In combination, the DDS phase accumulator 66 and the sine and cosine DDS generator 67 form a direct digital synthesizer (DDS) for digitally synthesizing a digital intermediate frequency signal.

DIF chip 17 is an ASIC chip which is configured as processor data memory.

The DIF chip 17 operates in one of two modes: a modulated carrier generation mode and a pure carrier mode. In modulated carrier generation mode, baseband data is entered into the I, Q domain, and this data is used to modulate the pure carrier generated by the DIF chip DDS function (17). In Pure Carrier Generation Mode, baseband data inputs are ignored and an unmodulated DDS carrier for DAC (18) is provided.

- 30 • ζ

The clock pulse generator 60 generates all the timing and clock signals within the DIF chip 17 and also generates the 3.2 MHz clock signal and the 3.2 clock signal. MHz, which are provided to the FIR chip 16 on lines 23a and 23b. The two primary time distribution signals used within the DIF chip 17 are a 21.76 MHz clock signal and a 2.56 MHz interpolation gate signal. The 3.2 MHz clock signal is used internally to shift data I and Q on line 24a of FIR chip 16 to FIR interface module 62.

clock generator (60) temporarily memorizes the 21.76 MHz clock received by line (72) of the oscillator in radio (20) and provides a 21.76 MHz clock signal stored in line (71a). Such temporary memorization is made to provide sufficient drive capability for internal functions and to minimize clock drift. The memorized 21.76 MHz clock also provides a clock for the DAC (18) and other external circuits.

Clock generator 60 provides the 3.2 MHz clock signal by dividing the 21.76 MHz clock by 6, and by 8, in the following sequence: 6-8-6-8-6, which results in a average divisor of 6.8 (21.76: 6.8 = 3.2). The effect of this variation per cycle is a minimum of 276 ns and a maximum of 368 ns. An advanced version of the 3.2 MHz clock signal is also generated as an early 3.2 MHz clock signal on line 23b. Both clocks are identical except that the ROM signal selected on line 23b is in a 21.76 MHz loop in advance of the 3.2 MHz clock signal on line 23a.

Clock signal generator 60 provides the 2.56 MHz gate signal on internal line 74, dividing the 21.76 MHz clock by 8 and 9 in a sequence (8-9-8-9). -...) pair, which results in an average splitter of 8.5 (21.76: 8.5 = 2.56 MHz). This signal is used by interpolator 63 and modulator 68.

Processor decoding module (61) allows the processor to control all internal functions of the DIF chip (17). 0 processor decoding module (61) decodes processor addresses and processor synchronization pulses received from data space on the processor bus (25) to provide internal write synchronization pulses, which are provided on the internal bus line ( 76) in the control register (64) and the tuning registers (65) to enable the processor chip (12) to enter command and configuration data. At any given time, only one output of the processor decoding module (61) is active. Processor addresses determine which output is generated. If a function is chosen within the address space of the DIF chip 17, a chip select signal 24c from the FIR chip 16 becomes active.

FIR interface module (62) receives samples I and Q from FIR chip 16 on line 24a in a serial format and

<img file="PT94975B_D0012.tif" />

converts them to 10-bit parallel format, in which they are supplied to the interpolator module at line (77). The gate signal I, Q, on line 24b from the FIR chip 16 is used to distinguish I data from Q data. The FIR interface module 62 also subtracts previous I and Q samples from current samples to form samples Al and Aq, which are then shifted to the right by 4 places (: 16) to form the correct increment for the interpolator module on line (78). As the FIR interface module 62 provides data to interpolator 63, a synchronization signal is sent from the FIR interface module 62 to the clock generator 60 to synchronize the 2.56 port pulse. MHz provided on line (74).

Interpolator 63 accumulates Δχ, Q at a frequency of 160 MHz x 16 = 2.56 MHz and provides interpolated I and Q samples for modulator 68 on lines 80 and 81 respectively. Interpolator 63 performs linear x16 interpolation to reduce the 160 KHz sample tracks present in the basic band data received from FIR chip 16.

Interpolator (63) successively accumulates samples Δΐ and Aq to generate an output at the frequency of 2.56 MHz. At the end of an accumulation cycle (16 iterations), the interpolator output would be equal to the current I and Q samples. This is critical as the next accumulation cycle begins with current data. To ensure that the data is correct, during the last accumulation cycle the current I and Q data are entered directly into the interpolator output register instead of the adder output (which should have the same data).

The command registers 64 are used to control and configure the DIF chip 17 and to select operating modes. All control registers (64) are loaded by the processor chip (12) through the processor bus (25).

There are three control registers (64). The first control register records a CW MODE signal, an AUTO TUNE HL signal and an AUTO TUNE LH signal. The second control register records a SIGN SELECT signal, an OUTPUT CLOCK signal, a PHASE SELECT signal, a signal. INTERPOLATOR ENABLE, a SERIAL PORT CLOCK SELECT signal, a SERIAL / PARALEL MODE SELECT signal, and a QUADRATURE ENABLE signal. The command functions associated with these signals will be described later, at the conclusion, of the description of the other modules of the DIF chip 17.

The third control register activates and specifies the noise signal modeler coefficients (69).

There are three 8-bit tuning registers (65) for storing 24 bits of phase increment data to specify the frequency of the DDS. This provides a 24-bit tuning word that allows a frequency resolution * 94 94 ~ of (sampling frequency) / 2 = 21.76 MHz / 2 - 1.297 Hz. The DDS output frequency equals the resolution multiplied by the 24-bit tuning word.

The tuning registers (65) are loaded by the processor chip (12) through the processor bus (25). The ememorial tuning word doubled

<img file="PT94975B_D0013.tif" />

tuning registers 65 so that processor chip 12 can write data to these registers freely without affecting the ongoing DDS operation.

The tuning word is loaded from the buffer tuning registers to the output tuning registers whenever a TUNE command is issued. The TUNE command is synchronized with the 21.76 MHz clock to provide a synchronous transition.

phase accumulator DDS (66) performs an accumulation - modulo 2 of the phase increment provided on line (82) by synchronization registers (65). The output of the phase accumulator (66) represents a digitized phase value that is provided on line (83) to the sine and cosine DDS generator (67). The sine and cosine generator (67) generates a sinusoidal function. A DDS operates on the principle that a digitized waveform can be generated by accumulating phase shifts at a high frequency.

The tuning word, which will be different for different subscriber units, represents a phase variation for the accumulator (66). The output of the accumulator 66 can be from 24 to 2 -1. This range represents a phase change of 360 degrees. Although accumulator 66 operates at normal torque, this digitized phase representation can be fed into a waveform generator to produce any arbitrary waveform. In DIF chip 17, sine and cosine DDS generators 67 produce sine and cosine functions at lines 84 and 85, respectively.

The period of the waveform function is based on the

<img file="PT94975B_D0014.tif" />

time required to sum up to the upper limit 24 of the accumulator (2 -1). This means that if a large phase increment is provided then this limit will be reached sooner. Conversely, if a small increment is given then a longer time is required. The phase accumulator 66 makes a simple sum of the input phase increments and can be represented by the following equation:

T

<img file="PT94975B_D0015.tif" />

<img file="PT94975B_D0016.tif" />

where n is the number of interactions and 0. simply represents the data provided on line (82) from the tuning registers (65).

In the embodiment of the DIF chip 17 described herein, the value is limited by the length of the accumulator to a maximum of 2. Therefore, the current phase can be described by:

v ^ tl ⁺ 2²⁴

<img file="PT94975B_D0017.tif" />

As the accumulation clock is determined to be the 21.76 MHz output parent clock, it follows that a complete cycle takes 2/2 incisions over a 1 / 21.76 MHz period per iteration. Thus, the complete cycle takes the following total time:

21.76 MHz. 0 me

Since this period represents a 360 ° cycle, the inverse .24

36 of this expression represents a frequency. The DDS frequency is therefore

21.76MHz * 0.

inc ^fDDS

<img file="PT94975B_D0018.tif" />

In the DDS SEN generation module, COS (67), sine and cosine waves are generated so that complex mixing can be performed on the modulator. Each is generated by two table queries, which represent a fine estimate and a rough estimate of the waveform. The two values ​​are added to form on lines (84) and (85) 12-bit composite data output signals, complementing 2's of sin and cos. Lookup tables are made in ROM that are addressed by the fourteen most significant bits of the signal on line (83) from the DDS phase accumulator (66).

You want the highest possible phase and amplitude resolution possible. In the design of the DIF chip 17, 14 phase input bits and 12 amplitude data output bits are provided in the wave generation section. If a brute-force solution were adopted to generate this data then large tables would be needed to generate all phase and amplitude values ​​(eg 16 K-words x 12 bits each). To minimize table size, DIF chip 17 uses quadrant symmetry and trignometric decomposition of the output data.

Since the sine and cosine curves have symmetry in the quadrants, the two most significant bits of phase data are used to obtain the symmetric data of the single quadrant with respect to the X and Y axes. For the sine function, the The amplitude of the curve in the interval (tr, 2if) is precisely the negative value of the curve (erv, 'Τί). For the cosine function, the amplitude in the curve in the range (tf / 2,37 (/ 2) is precisely the negative value of the amplitude in the range (31 // 2,4 ^ / 2). The two phase accumulator MSBs specify the quadrant (00— ^ 1.01— ^ 2.10-&gt; 3,

11-4). For the sine function, the phase data MSB is used to negate the positive data generated for the first two quadrants. For the cosine function, the OR EXCLUSIVE combination of the two phase data MSBs is used to negate the positive data generated for quadrants 1 and 4.

The prior art reduces memory requirements by 1: 4. Dal also results in the need for 4K words x 12 bits of memory. To further reduce the dimensions of the table, a trignometric decomposition is performed at the angles. The following trignometric identities are used:

sen 0 = §θη (0ι + 0?) * = sen ^ cos # ^ + senj ^ cos ^ ⁴J

Putting 0₂&lt;&lt; ^are taken to the following complete approach:

It is not necessary to use all bits of 0 ^ when calculating the second term of the equation as it is a subset of 0 ^.

To generate the cosine function, the same approximation can be used, since sen0 = sen / ^^ + sen0₂cos0j

Eq cosô = sen (0 + Tf / 2)

- 3frEq. 6)

This results in a modification of variables 0 ^ and 0 ^ when calculating the cosine function. The data stored in the cosine RAM will incorporate this angle modification, so no phase data changes are required.

Modulator 68 mixes the interpolated samples I and Q on lines 80 and 81 with the intermediate frequency digital signal represented by the complex data of the sine and cosine functions on lines 84 and 85 to produce a signal. frequency modulated digital signal on the line (87).

Interpolated samples I, Q and DDS output are digitally mixed by two 10 x 12 multipliers. The outputs of the mixing process are then summed by a 12-bit adder to form a modulated carrier. It is possible to change the operation of modulator 68 by forcing I input for all zeros and Q input for all ones. The effect of this is that one multiplier will output all zeroes and the other will output the signal from generator DDS SEN, COS only. The sum of these two signals provides an unmodulated intermediate frequency digital signal.

modulator 68 creates an intermediate frequency digital modulated signal on line 87 according to the following equation:

f (t) = I. cos / 0 (t) J + Q. Sen [0 (t)]. 7 ^

The 12-bit output of DDS SEN, COS generator 67 is multiplied by the 10-bit interpolated I and Q samples from interpolator 63 to generate two 12-bit products. The two products are then added (combined) to generate 12-bit modulated output on line 87.

Since both multiplier I and multiplier Q generate 12-bit products, overfilling may occur when their outputs are combined. It is therefore necessary to ensure that the amplitude of the vector generated by I and Q never exceeds 1 (assuming that bl - | q | are fractional numbers less than 1 or equal to 1). If this is not ensured, an overflow in the modulator adder is possible.

Noise modulator (69) provides an intermediate frequency filtered modulated or unmodulated signal at line 71b for DAC 18. Noise modulator 69 is calculated to decrease the noise power in the output spectrum caused by the amplitude quantization error.

Noise filter 69 works on the basis that quantization noise is not a normal random process and the process power spectrum density has a flat curve over the frequency range. The desired output signal is superimposed on this quantization noise base. The noise shaping device is a single FIR filter with multiple rejection points. 0 This filter creates a zero that decreases the power of quantization noise in a certain part of the frequency band. When the desired signal is superimposed on the filtered noise spectrum, the effective SQNR increases.

The transfer function of the FIR filter is given by

H (z) = 1 + bz¹ + z • 5 • Eq

- _ζ40 // /

yes

<img file="PT94975B_D0019.tif" />

A two-adder stage creates a second derivation value of b in the range from +1.75 to -1.75 (in binary weights of 0.25, 0.50, 1.0) that will offset the filter zero across the output frequency band so that it can be placed as close as possible to the output frequency. desired for maximum SQNR.

The zero frequency can be calculated by determining the roots of the previous equation in the z plane. Roots are a conjugate complexes that lie in the unit circle. Zero is given by the relation:

f = - f zero 360 ° * sampling where Θ is the root angle in the upper semiplane. The root will give a reflected zero around the frequency.

Table 2 lists the zero frequencies generated by the second weighted binary derivation. If b ^, b ^ and b ^ correspond to the weights 1,0, 0,5, 0,25, a + symbol means that the derivation is equal to its weight, a symbol means that the derivation is equal to the symmetrical of its weight and 0 means that the lead has no weight. Some of the zero frequencies are the same as other combinations simply because the possible combinations sometimes overlap (for example 1.0 + 0.5 - 0.25 = 1.0 +0.0 - 0.25).^fsample pair of

The freq Eq. Nyquist conjugate is 1.00.

<td>^B3</td><td>^H2</td><td>^Bl</td><td>f (zero)</td><td>f (random)</td>

<td> 0</td><td> 0</td><td> 0</td><td> 0,250</td><td> 0,750</td>

<td> 0</td><td> 0</td><td> -</td><td> 0,269</td><td> 0,731</td>

<td> 0</td><td> 0</td><td> +</td><td> 0,230</td><td> 0,770</td>

<td> 0</td><td> +</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td> 0</td><td> +</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td> 0</td><td> +</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td> 0</td><td> -</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> 0</td><td> -</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td> 0</td><td> -</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td> +</td><td> 0</td><td> 0</td><td> 0,167</td><td> 0,833</td>

<td> +</td><td> 0</td><td> -</td><td> 0,188</td><td> 0,812</td>

<td> +</td><td> 0</td><td> +</td><td> 0,143</td><td> 0,857</td>

<td> +</td><td> +</td><td> 0</td><td> 0,115</td><td> 0,885</td>

<td> +</td><td> +</td><td> +</td><td> 0,080</td><td> 0,420</td>

<td> +</td><td> +</td><td> -</td><td> 0,143</td><td> 0,857</td>

<td> +</td><td> -</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td> +</td><td> -</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td> +</td><td> -</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td> -</td><td> 0</td><td> 0</td><td> 0,333</td><td> 0,667</td>

<td> -</td><td> 0</td><td> -</td><td> 0,357</td><td> 0,643</td>

<td> -</td><td> 0</td><td> +</td><td> 0,312</td><td> 0,688</td>

<td> -</td><td> +</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> -</td><td> +</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td> -</td><td> +</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td> -</td><td> -</td><td> 0</td><td> 0,385</td><td> 0,615</td>

<td> -</td><td> -</td><td> +</td><td> 0,357</td><td> 0,643</td>

<td> -</td><td> -</td><td> -</td><td> 0,420</td><td> 0,580</td>

<td></td><td></td><td></td><td>TABLE 2</td><td></td>

The entire time distribution is derived from the 21.76 MHz clock signal on line 71a.

The functions associated with signals in

Control (64) will now be described.

When the CW MODE signal is set, the input I to the respective multiplier in the modulator 68 is forced to all zeros, and the respective input Q is forced to all 1. The net effect is that an unmodulated carrier is generated. . This function is stored twice in buffers and the loaded data will not become active until a TUNE command is issued.

INTERPOLATOR ENABLE signal activates interpolator x16 in samples I, Q. If the. INTERPOLATOR ENABLE signal is not established, then the I, Q data are input directly into the multiplier.

The external memory required for the operation of the processor chip (12) is provided by a fast memory (13) and a lens memory (14). The fast memory (13) is accessed by an address decoder (15). Fast memory 13 is a cache memory made in RAM that has null wait states. Slow memory 14 is a large memory held in an EPROM with two standby states. Slow memory (14) is coupled to processor chip (12) to store processing codes used by processor chip (12) when such codes need not be operated with null wait states; and the flash memory is copied to the processor chip 12 to temporarily store processing codes used by the processor chip 12 when said codes are operated with zero wait states. When procedures with null wait states have to be performed, the code can be downloaded from memory.

7's

<img file="PT94975B_D0020.tif" />

(14) into the fast memory (15) and be processed from it. Such procedures include interrupt service routines, symbol demodulation, RCC acquisition, BPSK demodulation, and voice and data signal processing.

The processor chip 12 includes a single digital signal processor, model TMS320C25, which performs four main tasks, a subscriber control task (SCT) (91), a channel control task (CCT) (92), a signal processing task (SPT) 93 and a MODEM processing task MPT 94 as shown in FIG. 4. These four tasks are controlled by a supervisory code (95). SCT handles the telephone interface and high level call processing. The CCT controls the modem and RELP operation and time distribution and makes power level and time distribution TX adjustments according to requests from the base station. SPT performs RELP, echo suppression, and acoustic signal generation functions. The supervisor calls these four tasks sequentially and communicates them through control words.

The SCT (91) provides the high level control function within the subscriber unit and has three fundamental modes of operation: rest, vocal and abortion.

The SCT enters sleep mode after the power is turned on and remains in this state until effective voice communication is established. While in standby mode, the SCT monitors the subscriber's phone interface for

<img file="PT94975B_D0021.tif" />

and responds to requests from the base station received via the radio control channel (RCC).

The primary function of the SCT is to drive the subscriber unit by establishing and disconnecting voice communications on the radio channel. Before the unit can make any type of call, however, it must find the correct base station. The SCT determines which RCC frequency to use, and outputs the frequency information to the CCT. The description of the initialization of a communication channel between the subscriber unit and the base station is contained in U.S. Patent Application No. 07/070 970, filed July 8, 1987.

Once the subscriber unit has achieved RCC sync, it can establish a call by exchanging messages, by the RCC channel, with the base station and by surveillance and signaling on the material equipment means at the telephone interface. .

The following description briefly shows the events that occur during call setup.

Normal call setup for outgoing calls begins with the subscriber lifting the handset to initiate a service request. The SCT issues a CALL REQUEST message to the base station. The SCT receives a CALL CONNECT message. The SCT signals to CCT for synchronization on the assigned vocal channel via the CALL CONNECT message. CCT achieves vocal channel timing. The subscriber receives the dial tone from the central station. The 45-

<img file="PT94975B_D0022.tif" />

<img file="PT94975B_D0023.tif" />

call setting. The central station provides the remaining support for call termination.

Normal establishment of incoming calls is as follows: The SCT receives a PAGE message from the base station. The SCT responds with a CALL ACCEPT signal. The SCT receives a call connect message. The SCT signals to CCT to achieve synchronization on the assigned vocal channel via the CALL CONNECT message. CCT achieves vocal channel timing. The SCT starts the call signal generator to apply the call signal to the local loop. 0 subscriber picks up the phone and lifts it from the rest. The calling current is interrupted. The vocal communication is completed.

The SCT performs call setup and shutdown operations as a finite state machine.

If a vocal channel is successfully picked up, SCT switches to vocal mode and performs a very limited set of support functions. The SCT processor load is kept to a minimum at this time to give the processor greater availability for RELP conversion signal compression, echo suppression, and modem processing algorithms.

The SCT enters abort mode as a result of a call originating from a failed attempt or an unexpectedly interrupted sequence. During abort mode, a counterorder is sent to the handset. The SCT oversees the subscriber phone interface to detect a hang-up (standby phone for an extended time) when the subscriber unit enters sleep mode. Requests received from the base station via the radio control channel (RCC) are rejected until disconnection is detected.

The CCT 92 operates as a link-level channel controller in the baseband programming means. CCT has three fundamental states: RCC operation, refinement, and vocal operation.

When power is turned on, the CCT enters the RCC operating state to fetch, and then maintain, the RCC channel. RCC operation includes the following functions: AM hole control, synchronization status and modem task monitoring, radio channel time distribution adjustment, RX RCC message filtering, TX RCC message formatting, buffer 1 monitoring / 0 of PCM and processing cfe information in the connection circuits.

After voice communication is established, the CCT enters the refinement state for fine tuning of fractional modem time distribution. Refinement includes the following functions: interpretation and response to refinement data sequences, creation and formatting of TX refinement data sequences, sending SCT messages as appropriate, modem state monitoring, and buffer monitoring 1/0 of PCM.

Following refinement, CCT initiates vocal operation, which includes the following functions: codeword signaling support, bit fault recovery, modem status and synchronism monitoring, and memory monitoring

<img file="PT94975B_D0024.tif" />

.1 PCM buffer 1/0.

The CCT (92) has three fundamental states of operation: rest, refinement and vocal. The following is an excursion through the transitions involved in a CCT operation.

After resetting, the CCT goes to sleep and remains idle until a channel assignment instruction is given by SCT. The SCT provides the CCT with a frequency by which it searches for the radio control channel (RCC). The CCT then instructs MPT to synchronize the receiver to the given frequency and to fetch an AM hole. Failure to detect an AM hole within a predetermined time interval causes the CCT to ask for another frequency to search from the SCT. This continues indefinitely until successful detection of an AM hole.

Following successful detection of an AM hole, CCT begins to scan incoming data for a single word. A small window is explored around the nominal position of the single word, as the AM hole detection process may be off during the time of some symbols. Once the single word is found and found to be correct for the error detection word, the exact time distribution of the received symbols can be determined. The TDM frame marks are then adjusted to the correct alignment and normal RCC support is initiated. If the single word cannot be found, AM hole detection is considered false and CCT requests a new frequency assignment by SCT

During RCC operation, CCT filters incoming RCC messages. Most base station RCC messages are zero combinations, and these combinations are rejected after the link circuit information has been read from the link octet. RCC messages containing information; are sent back to the SCT for processing. If the RCC sync is lost, the CCT again requests a new frequency from the SCT. The SCT will respond at the correct frequency according to the RCC frequency search algorithm.

When SCT initiates a telephone call, SCT is assigned a voice channel and a time range. CCT activates the subscriber unit in accordance with this assignment and begins the refinement process. During refinement, the base and subscriber units transmit a BPSK signal specifically designed to assist the modem in acquiring fractional bit time. The CCU base station repeats for the subscriber unit backwards the time offset of the bits as a complement value to 2 of the adjustment. The CCT maintains an average value over time of these forwarded deviations backwards. Once the CCT determines that the fractional time value is within the required tolerance, it accordingly adjusts the subscriber unit emission times. 0 The mean time value is determined dynamically as a function of the variance of the fractional time samples. After a time distribution time adjustment, the time average is reset and the procedure is repeated.

Once the base station detects that the base unit is

The subscriber is within an acceptable time tolerance, the refinement process ends and vocal operation begins. The length of the refinement process is dynamically determined as a result of successful subscriber unit time adjustments. The distribution of power times and integer symbols are also monitored and adjusted as needed during the refinement process. If the subscriber unit does not find the base station refinement data sequences after a certain time interval, or if the refinement process cannot provide an acceptable time distribution, communication is interrupted and CCT returns to RCC operation. .

Following successful refinement, CCT enters vocal operation at the assigned modulation level. Voice operating tasks include RELP and MPT control operations, establishing vocal timing, and continuous monitoring of voice code words sent from the base station. Local loop control variations, signaled through the code words, are reported to the SCT as they occur. Incremental variations in power and fractional times are also determined from the code words. The transmitted vocal code words are formulated by CCT based on the local loop control provided by CCT and the channel connection quality communicated by the modem. The CCT returns to the RCC when the SCT executes a call interrupt sequence.

If vocal sync is lost, the CCT will start a 50 -

<img file="PT94975B_D0025.tif" />

fading recovery ration. After ten seconds of failure to re-establish a good telephone connection, CCT informs the SCT of the condition, initiating a call break. This returns the CCT to sleep.

During a channel test operation, a sequence of vocal data with channel test data is reset. When a data sequence has been accurately received, it is parsed for bit errors. The number of counted bit errors is passed to the base station via data sequences in the reverse channel.

The SPT 93 performs all digital signal processing (DSP) tasks within the subscriber unit. The various DSP functions are invoked as required under the control of the supervisory module (95).

The SPT includes a RELP module, which runs from high speed RAM. The RELP module performs RELP Speech compression and expansion with echo suppression. The RELP module transforms blocks of 180 octets of 64 Kbps PCM vocal data to and of 42 octets of compressed vocal data using the RELP algorithm.

The SPT also includes a signal processing control module (SPC), which determines whether to generate acoustic or RELP signals. If it is RELP, SPC determines whether to call the synthesis routine or the analysis routine. The synthesis routine returns a parity error count, which is handled by the SPTCTL routine. If acoustic signal generation is required, determines whether to provide silent output

Z 51 A or new order.

The SPT is controlled by commands from the SCT and CCT. These commands invoke and control the operation of the various functions within the SPT as requested by the subscriber unit. RELP programming and echo suppression means, for example, are only activated when the subscriber unit is active on a telephone call. Acoustic signals during call progress are generated whenever the subscriber unit receiver is off-hook and RELP is not active. Acoustic signals include silence and new order. Except for IDLE mode, the interrupt service routine that processes the PCM encoder-decoder operates continuously, as a foreground process, filling the circular PCM buffer.

Control and modem functions are performed between analysis and synthesis processing.

The MPT (94) demodulation procedure is divided into two procedures: DEMODA and DEMODB, thus allowing RELP synthesis to be performed on the RX data in buffer (A), precisely after the DEMODA procedure is completed. After DEMODA all internal RAM variables must be stored in external RAM and then reloaded into internal RAM before performing DEMODB. This is because RELP uses the

Internal RAM.

When the RXCLK interrupt on line 26e is received by processor chip 12, MPT reads four received RX data samples and then places them in a

<img file="PT94975B_D0026.tif" />

circular buffer for processing by the demodulation procedure. This allows other tasks to be performed while receiving RX samples.

The MPT receives the interrupt signal RXCLK on line 26e from chip 62 of 62.5 in 62.5 microseconds during the receive time range. The interrupt signal RXCLK is masked by the microprocessor microprocessor means of the processor during standby or the emission time bands.

The MPT receives the TXCLK interrupt signal on line (26f) of the FIR chip. (16) Only during the emission time range. TXCLK interrupt signal tells processor chip 12 when it issues new TX symbol to chip

FIR

The MPT reads four samples from the RX sample buffer (35) on the FIR chip (16) during each RXCLK interrupt on line (26e). MPT resets the buffer input and output counters at the beginning of the received time range.

The MPT outputs TX symbols to the TX symbol memory (36) in the FIR chip (16).

MPT provides the data for the fractional time circuit in the RM time distribution module (39) in the FIR chip 16 which is used to align the RXCLK interrupt signal on line 26e with the base station output.

MPT also synchronizes the DDS frequency with the base station output frequency.

<img file="PT94975B_D0027.tif" />

Referring to fig. 5, the MPT includes the following modules: a supervisor module (101), a training module (102), a frequency acquisition module (103), a bit synchronization module (104), a signal demodulation module (105), a symbol receiving module (106), and a broadcasting module (107).

The supervisor module 101 is the MPT task supervisor. It reads the MPT control word (CTRLO) from RAM and calls other routines according to the control word.

The training module 102 comprises a vector of 28 complex FIR filter coefficients. It activates in sleep mode after power is turned on and about every three hours. A training transmitter performed by the MPT is activated in a loopback mode to emit a certain sequence of symbols. This sequence returns through the closed loop to a training receiver performed by the MPT, in a normal mode, in early and late time modes, and in adjacent upper and lower channels.

The training receiver uses it. the input wave samples to create a symmetric diffuse positive matrix (A) of order 28. A 28 word V vector is also created from the input samples. The vector of coefficients C is given by:

C = A^-1 V ^ Eq. 10

The coefficient B is then calculated according to the algorithm B = A \ given A.

The training transmitter is activated in closed loop mode to emit five identical pairs of sequences. Each pair consists of the following two sequences:

Sequence I: 9 zero symbols, i, 22 zero symbolsSequence Q :: 9 zero symbols, j, 22 zero symbols.

i can be any symbol. 0 j is a symbol that differs from i by 90 °.

The receiver processing tasks are:

Adjust the AGC so that the signal peak in normal mode is 50 to 70% of the maximum. AGC is increased from 23 dB for 4- and 5-modes.

Read and store input samples. The first 32 samples are discarded and the next 64 samples are stored for each sequence.

Form matrix A (28.28). The following process is performed in normal mode:

A (I, J) = A (I, J) + c (4N-1) · X (4N-J) summation is for all Ns satisfying:

/ = 4N-1 &lt;64 and 0 4N-J &lt;64 ^ Eq. 12 J

For advanced or delayed sequences, the same process as the resulting N = 8 term is not added. In the sequence of channels adjacent to the upper and lower channels, the following procedure is performed:

A (I, J) = A (I, J) + 1 X (2N-I). X (2N-J)

The addition is for all Ns that satisfy:

&lt;= 2N-I &lt;64 and 0 &lt;= 2N-J &lt;64

Create the vector V (1:28) from the samples of the first pair of sequences:

^ Eq. 11

Eq. 13 ^ Eq. 14 J

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Re ^ Vd) ^ = X (32-I), where X are samples of the first sequence (I).

Im = V (I) ^ = X (32-I), where X are samples of the second sequence (Q).

Determine the coefficient vector C solving the equation

A x C - V = 0 ^ Eq. 15

These processing steps are described in more detail in U.S. Patent 4,646,561, issued February 17, 1987, to Eric Paneth David N.

Critchlow and Moshe Yehushua.

frequency acquisition module (103) functions upon reception of the control channel to synchronize the subscriber unit's RX frequency with the base station's broadcast frequency. This is done by adjusting the DDS CW output until the energies of the two sidebands of the received signal are equal. Then the DDS TX frequencies are adjusted according to the calculated frequency offset.

If the procedure fails to find frequency synchronism, an appropriate error code is placed in the status word.

Bit sync module 104 functions upon receipt of the RCC and upon completion of frequency acquisition. A given pattern is emitted from the first 44 symbols in the RCC emission from the base station, and is used by this module to calculate the RXCLK deviation from the correct sampling times. This deviation is used to adjust the RXCLK times.

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vocal signal demodulation module 105 is activated to demodulate a vocal time range. It resides in slow memory EPROM and its functions are divided into two processes DEMODA and DEMODB.

DEMODA functions include initialization parameters for symbol reception module (106), calling the symbol reception module to process symbols for buffer (A) and storing variables in external RAM before exiting.

DEMODB functions include loading variables from external RAM to internal RAM, calling the symbol-receiving module to process the symbols received into memory (B), and determining link circuit quality and other information. , after receiving all symbols in the time range.

The symbol receiving module 106 is loaded up into RAM when the CCT goes into voice mode. It is called by DEMODA or DEMODB to do the following: 1) read samples X and Q from the circular buffer; 2) filter on the FIR filter samples I and Q; 3) determining the emitted symbols and placing them in a buffer; 4) performing a phase locked ring to synchronize the DDS with the input signal; 5) execute the bit tracking algorithm; 6) calculation of AGC; and 7) accumulate data for the calculation of the quality of the connection circuit.

The emitting module (107) includes the interrupt service routine for the TXCLK interrupt signal received on line (26e) of FIR chip 16 which is checked once per

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/ two symbols during the broadcast time range. The functions of the emission module (107) include: 1) removing the emission symbol from the RELP memory; 2) perform an inverse Gray coding on it; 3) add it to the previously transmitted phase (because of the DPSK transmission); and 4) outputting it to the TX buffer in the FIR chip (16).

MPT's interface with basic band tasks is accomplished through control and status words and data buffers in shared memory. Procedures that require fast execution are loaded into cache when needed. These procedures include service routines, symbol demodulation, RCC acquisition, and BPSK demodulation.

The MPT supervisor does not wait for RXSOS to read and decode the control word, but does so immediately when called.

The TMS320C25 goes into a power reduction mode when executing the IDLE instruction. To save energy, microprogramming means will be in standby mode most of the time when no telephone call is in progress. Thus, after a reset, the supervisor acquires RCC timing, then goes into IDLE mode until a predetermined interruption causes a corresponding service routine to be executed. When operated in low power mode, the TMS320C25 goes into a dormant state and only requires a fraction of the power normally required to power the device. Although in low power mode, all internal content

- 58 (Processors are maintained to allow operation to remain unchanged when the low power mode is terminated. Upon receipt of an interrupt, the processor chip (12) terminates the low power mode temporarily and resumes normal operation during a minimum time of one cycle of the main ring. Reduced power mode requirements are checked at the end of each main ring period to determine whether or not the subscriber unit should return to reduced power mode.

Time bands clock is based on the timing distribution of time bands in the material media. When a timestamp triggers a switch, the routine increments the clock by one tick. Each tick of the clock represents a time of 11.25 ms.

The UART receive and transmit functions are not interrupt-driven, but are controlled by the basic programming means (these control the processor load and prevent breakout conditions from escaping). The processing code supports the XON / XOFF protocol by intercepting these characters directly and immediately enabling or disabling UART broadcast as appropriate. The speed of the receive and transmit operation is calculated to be selective by a DIP switch device.¹ exterior. Typical reception data rate is 9600 baud. A circular buffer is used to control UART emission. Basic software periodically checks the queue and starts broadcasting if it is not empty. It does this by issuing octets to UART one octet at a time until the queue is emptied. The switch hook is exploited with the TMS320C25 internal time distributor interrupt routine. To simulate DC signaling, a sampling period of 1.5 ms is used. This interruption is aligned with frame times at the beginning of each frame, so its frequency is phase locked with the base station to prevent deficits or excesses in the switch buffer. For each interrupt, a bit representing the switch hook detection signal (from SLIC) is inserted into the 60-bit switch error scanning (SSB) memory. SSB is examined by SCT once every 45 ms during normal operation. This interrupt is activated by the program means at any time.