Subscriber set for cordless, digital subscriber communication system

The subject of the invention is a subscriber apparatus of a wireless digital communication system.

The known subscriber apparatus, described in U.S. Patent No. 4,825,448, includes elements for transcoding the digital input speech signal, elements for filtering with a finite impulse response of the input digital symbols, elements for obtaining an analog input signal with an intermediate frequency from filtered digital symbols, means for obtaining a combination of an intermediate analog input signal with a radio frequency carrier, for radio transmission to a base station, elements for demodulating the output signal received from the base station, for obtaining digital output symbols, and elements for the synthesis of an output digital speech signal from digital output symbols . The subscriber's apparatus comprises a baseband processor integrated circuit and a modem processor integrated circuit. Both processors are of the TMS 32020 type, designed for digital signal processing. The baseband processor integrated circuit transcodes the input digital speech signal, synthesizes the output digital symbols, and performs various control functions in the baseband. The integrated circuit of the modem processor performs filtration with a finite impulse response of digital input symbols, and demodulation of the received base station input signal, which processor works as a processor managing the subscriber's apparatus. The known subscriber apparatus, which uses an analog signal as an intermediate frequency signal, can be used in the base station used in the communication network of the subscriber apparatus, described in US Patent No. 4,777,633.

U.S. Patent No. 4,644,561 discloses the use of a digital intermediate frequency in a radio receiver. The radio receiver uses a radio frequency synthesizer that produces multiple frequency signals to ensure conversion to the correct transmission frequency.

In international publication No. WO 86/02726 (international patent application No. PCT / US85 / 02168) a digital speech coding device using the RELP coding method is implemented, based on a digital signal processor.

In turn, U.S. Patent No. 4,697,261 discloses a linear predictive echo cancellation system connected in one piece to a digital speech coding device using the RELP coding method. In addition, this patent describes the use of RELP synthesis and analysis for speech signal processing. The subscriber apparatus of the wireless digital communications system according to the invention comprises a processor which is connected to a processor generator and, via a subscriber circuit / codec coupling system and a telephone interface,

166 789 for a standard telephone set. The apparatus also contains a filter system with a finite impulse response, which is attached to the processor, analog-to-digital converter, radio transceiver and, via the external circuit, to the telephone interface. The processor bus in the camera is attached to the processor, to the filter system with a finite impulse response, to fast memory, to slow memory and to an address decoder. The address decoder is also connected to the fast memory, and the radio transceiver is connected to an analog-to-digital converter and a digital-to-analog converter. The subscriber apparatus according to the invention is characterized in that it comprises a digital intermediate frequency circuit which is connected to a filter circuit with a finite impulse response, a digital to analog converter, a radio transceiver and to a processor bus.

The digital intermediate frequency system according to the invention comprises tuning registers, control registers and a decoder module connected to the processor bus. The tuning registers are connected to the modulator via the phase battery and direct digital synthesis generator. The control registers, decoder module and tuning registers are also attached to the second internal bus of the digital intermediate frequency system. The digital intermediate frequency system also includes an interface module attached to the filter system with a finite impulse response, and, via an interpolator, to a modulator. The clock generator is attached to the radio transceiver system, to the interpolator, to the filter system with a finite impulse response and to the digital-to-analog converter. The modulator is then connected, via a noise reduction system, to the D / A converter, while the decoder module is also connected to the filter system with a finite impulse response.

The direct digital synthesis generator, according to the invention, contains two permanent memories constituting lookup tables for the production of rough and accurate sinus and cosine waveforms.

A filter system with a finite impulse response, according to the invention, comprises a transmitting filter, transmitting timing module, control and status registers, receiving timing module, receiving symbol buffer, internal address decoder and external address decoder connected to the processor bus. In addition, the filter system with finite impulse response includes the first internal bus connected to the transmission timing module, to control registers and status, to the receiving symbol buffer, to the receiving timing module, to the internal address decoder, to the external control module and to the siren, and the connection buffer system subscribers attached to a digital intermediate frequency circuit. The receiving timing module is also attached to the receiving symbol buffer, sender timing module, codec timing module, analog-to-digital converter and to the processor. The transmission timing module is also attached to the radio transceiver, processor and transmission filter. The subscriber connection buffer system is also attached to the codec timing module, to the transmission filter and to the siren. The codec timing module is also connected to the codec subscriber circuit coupling system, to which system and to the external circuit is also connected an external control module. Then the receiving symbol buffer is also attached to the analog-to-digital converter. The siren is also connected to the reset inputs of the camera modules. A transmission filter is also attached to the digital intermediate frequency system. The external address decoder is also connected, via the processor bus, to the digital intermediate frequency system, the universal asynchronous processor receiver-transmitter and to free memory.

The radio transceiver system according to the invention comprises a fixed frequency local generator.

The advantage of the invention is to add new functional features to the subscriber's apparatus, which do not exist in known subscriber's apparatus, and consist in the fact that, thanks to direct digital synthesis, very flexible tuning of the subscriber's apparatus is possible. In known subscriber apparatus, tuning was limited to a finite set of channels with 167 789 bands differing in frequency by 25 kHz. Also the frequency difference between transmission and reception was defined as 5 MHz. The direct digital synthesis function of the digital intermediate frequency system removes these restrictions by allowing the use of other channel frequency differences, i.e. shifts between transmission and reception, with minimal or no modifications to the subscriber's apparatus.

Accordingly, the digital intermediate frequency circuit generates a fully modulated digital intermediate frequency signal that can be digitally synthesized on one of many different, predetermined intermediate frequencies, and high resolution tuning can be used to enable tracking the frequency of the signal received from the base station. Due to these two features, the radio part of the subscriber's apparatus can only contain a fixed frequency pattern and does not have to meet the requirements for a radio frequency synthesizer. These two advantageous features also allow the use of a fixed primary frequency standard in the subscriber's apparatus with all tuning adjustments made by the digital intermediate frequency system. The digital intermediate frequency generator used in the subscriber apparatus of the invention is capable of producing the required digital intermediate frequency based on the selected communication channel, thereby eliminating the need for a variable frequency generator. The use of a variable digital intermediate frequency generator and a fixed radio frequency generator is a new solution in digital communication systems and significantly reduces the costs and complexity of a subscriber's apparatus for a wireless digital communication system.

In the present invention, the direct digital synthesis synthesizer is stable and easy to make. The requirements for phase noise are met without the need for expensive and complex phase synchronization loops in the synthesizer. In addition, the synthesizer allows easy modification of the intermediate frequency when switching to other bands.

Another advantage of the invention is the fact that the filter system with a finite impulse response includes means for generating clock signals for synchronizing transcoding operations and synthesis operations of the output digital contract signal in the processor. The processor demodulates the output signal received from the base station, regardless of the timing signals generated by the filter system. The processor receives the output signal synchronously with the timing signals generated by the filter system and stores in the buffer memory the received output signal for demodulation, so that the processor can perform this demodulation when it is not engaged in transcoding and synthesis operations.

The invention allows a further reduction in manufacturing costs by utilizing a combination of not very fast processor-coupled memory for storing codes processed by the processor when they do not need to be processed without any waiting time, and a fast memory connected to the processor for temporary storage of processed codes used by the processor when these codes require work without waiting. Fast RAM and fast EPROMs with the same packaging of the integrated circuit structure are very expensive. In order to reduce costs, processor codes are stored in free EPROM memory, and when procedures need to be performed without waiting times, the code is overloaded from slow to fast memory and downloaded for processing.

The subject of the invention is shown in the embodiment in the drawing, in which Fig. 1 shows a block diagram of a subscriber's apparatus, Fig. 2 - block diagram of a filter system with a finite impulse response included in the apparatus of Fig. 1, Fig. 3 - block diagram of a digital system the intermediate frequency contained in the apparatus of Fig. 1, Fig. 4 - tasks performed by the processor of the system of Fig. 1 in the form of separate modules, and Fig. 5 - the processing procedures contained in the modem processing task shown in Fig. 4, as well as in the form of modules.

According to figure 1, a standard telephone set 32 ​​is connected to a subscriber's set according to the invention, via a telephone interface arrangement 10. The arrangement

166 789 of the telephone interface 10 is then connected, via a coupling circuit of the subscriber / codec 11, to the processor 12, to which the processor generator 22 and the processor bus 25 are connected. The processor bus 25 connects the processor 12 with fast memory 13, free memory 14, with an address decoder 15 and a filter circuit with a finite impulse response 16 and a digital intermediate frequency circuit 17. An address decoder 15 is attached to the fast memory 13, the filter system 16 and the digital intermediate frequency system 17 are connected to each other by lines 23 and 24. In addition, the filter circuit 16 is connected to the processor 12 via line 26, to the analog-digital converter 19 via line 27, to the subscriber / codec coupling circuit 11 via line 29, to the transceiver 20 via line 30, and to the external circuit 21 via line 31 , wherein the external circuit 21 is connected to the telephone interface system 10. In turn, the digital intermediate frequency system 17 is connected via line 71 to the digital-to-analog converter 18 and then to the radio transceiver 20, which is then connected to the analog-digital converter 19 and by line 72 to the digital intermediate frequency system 17.

In the subscriber's apparatus, the subscriber circuit / codec 11 coupling system is connected to the telephone interface system 10 to convert the speech input from the standard telephone 32 into a digital baseband input signal which is fed to processor 12. Processor 12 is a TMS320C25 type processor for digital signal processing, which recodes the digital baseband input signal, in accordance with the RELP encoding algorithm, to obtain digital transmission signals on the processor bus 25. Filter system 16 filters digital input symbols and provides data symbols I, for phase signals, and data symbols Q, for quadrature signals, to digital intermediate frequency 17 via line 24. The digital intermediate frequency circuit 17 interpolates the filtered digital input symbols and modulates the digital intermediate frequency signal with the interpolated input symbols to obtain a modulated digital input signal. The DAC 18 then converts the modulated digital input signal into the modulated analog output signal and feeds it to the radio transceiver 20, which transmits the modulated analog signal to the base station and receives and demodulates the modulated analog signal from the base station. In turn, the analog-to-digital converter 19 converts the received analog signal into an output digital signal containing output digital symbols. Processor 12 synthesizes the output digital baseband signal from the output digital symbols. The subscriber circuit / codec 11 interface converts the digital baseband output signal into a speech output signal which is fed, via the telephone interface circuit 10, to a standard telephone apparatus 32.

In a practical embodiment, the filter circuit 16 integrates all system functions into one integrated circuit with a very large integration scale in order to reduce the cost of manufacturing a subscriber's apparatus by eliminating many separate elements of the medium integration scale.

The filter system shown in Figure 2 with a finite impulse response 16, included in the subscriber apparatus of Figure 1, includes the following blocks attached to the processor bus 25: transmission filter 42, transmission timing module 40, control and status registers 36, receiving timing module 39 , receiving symbol buffer 35, also connected via line 27a to the analog-to-digital converter 19, internal address decoder 34 and external address decoder 37. The external address decoder 37 is connected, via this bus 25, to the processor 12. The filter system 16 has a first internal bus 48, which is connected to the transmission timing module 40, control registers and state 36, the receiving symbol buffer 35, the receiving timing module 39, the internal address decoder 34 and to the external control module 45 and the siren 38. Transmission timing module 40 is connected by line 56 to the transmission filter 42, line 30 to the radio transceiver 20 and line 26a to the processor 12. Transmission filter 42 is connected by line 47 to the buffer system 33 connecting 166 subscribers, and lines 24a and 24b to the intermediate digital frequency circuit 17. Receiving timing module 39 is connected by line 54 to transmission timing module 40, lines 26b and 26c to processor 12, line 27b to analog-to-digital converter 19, line 52 to coding module codec 44 and line 49 to receiving symbol buffer 35. The second input of the codec timing module 44 is connected via line 47, the buffer system 33 of subscribers' connections, with the outputs of this module 44 connected by lines 29a and 29b to the system coupling the subscriber / codec circuit 11. The inputs of the subscriber's system 33 connection are connected lines 23a and 23b to the digital intermediate frequency 17 and to output line 51 of signaling device 38. The second input of the external control module 45 is connected via line 29c to the subscriber circuit / codec 11 coupling, and the outputs of this module are connected via lines 31a, 31b and 31c to the external circuit 21.

The filter system 16 separates two five-bit transmit symbols at a frequency of 8 kHz and converts the transmit symbols into 10-bit data symbols I and Q and filters them at a frequency of 160 kHz. The data symbols I and Q are interleaved and sent to the processing system 17 at a frequency of 320 kHz. The filter system 16 also separates receiving data samples at a frequency of 64 kHz, with the processor 12 collecting four samples at a frequency of 64 kHz. Clock signals are generated by the filter circuit 16 from the main clock signal 3.2 MHz supplied to it. The processor 12 is synchronized by the interrupt corresponding to the interruptions and symbols generated by the filter system 16. The strobe signal 8 kHz coupling the circuit of the subscriber / codec 11 and the processor 12, and the clock signal of this system are generated by the filter system 16 and synchronized with the moment of arrival of receiving samples . The filter system 16 also generates control and timing signals to control the shape and time parameters of the external voltage generated by the external circuit 21. The signaling device 38 provides a reset signal in the event of the processor 12 executing instructions incorrectly.

The subscriber connection buffer system 33 amplifies the main clock signal 3.2 MHz received from the digital intermediate frequency system 17 on line 23 and the reset signal received from the signaling device 38. Unlike the previously discussed, all clock signals in the filter system 16 are obtained from the main clock signal 3.2 MHz on line 23a. The 3.2 MHz clock signal on the 23b line accelerated in phase ahead of the 3.2 MHz clock signal on the 23a line by one cycle of the 21.76 MHz reference signal available inside the intermediate frequency system 17. The 3.2 MHz clock signal is generated from the reference signal 21.76 MHz in the digital intermediate frequency 17 system and therefore its minimum pulse width is 276 nanoseconds. The 3.2 MHz clock signal in phase 23b accelerated in phase is fed from buffer system 33, via internal line 47, to transmission filter 42 and codec clock module 44. All filter system blocks 16 are fed from buffer system 33 line 50, main clock signal 3.2 MHz and line 55 reset signal. Transmitting filter 42 is implemented in part by ROM, which is a pseudostatic memory and requires that its enable input be deactivated with an accelerated clock signal of 3.2 MHz on line 47, between successive available ones. The reset signal on line 51 resets all internal circuits of the filter system 16 and causes a system reset for the modules of Fig. 1. Internal clock signals are obtained either by isolating the main clock signal 3.2 MHz received on line 23a or by dividing it.

The internal address decoder 34 allows the processor 12 to access the internal functions of the filter circuit 16 to control these functions and determine their current conditions. The internal address decoder 34 receives the processor 12 addresses and strobe signals through the processor bus 25 and forwards the output signals to the first internal bus 48. The output signals on this bus 48 from the internal address decoder 34 include: read enable signal for the receiving symbol buffer 35, write control signal and read status signals for control and status registers 36, write signal for transmit filter 42, pause signal and write clock for receiving timing module 39, a recording signal for the transmitting timing module 40 and signals

166 T89 controlling for the transmission filter 42 and the receiving symbol buffer 35 and the strobe signal AM, which causes the reset of the receiving timing module 39 to restart the pause timing. At any time, only one of the write or read signals is active on the first internal bus 48 for the internal address decoder 34.

The receiving symbol buffer 35, in each bar of the receive symbol, receives four samples from the analog-to-digital converter 19 via line 27a, at a frequency of 64 kHz. It remembers up to two data symbols, which consists of a total of eight samples, and then sends these data samples to processor 12, via processor bus 25. The receiving symbol buffer 35 is made in two-page RAM. This buffer receives the read permission signal, via the first internal bus 48, from the internal address decoder 34, and the strobe signal, via line 49, from the receiving timing module 39.

The control and status registers 36 allow the processor 12 to control the internal functions of the filter system 16 and to read the filter transmitting state 42 and receiving symbol buffer 35 and other internal signals. The control signals fed from processor 12 via processor bus 25, as well as status information, come from various internal modules of filter circuit 16. Status information is fed to processor 12 via processor bus 25. The status information is: beginning of the frame, beginning of the receiving pause, clock signal of the sending symbol, clock signal of the receiving symbol, excess in the transmission filter 42, and underflow and excess in transmission and reception.

The control signals provided by the control and status registers 36 to the internal circuits via the first internal bus 48 include the signals: transmit permission, modulation level, call enable, program reset, third state and supervision strobe. The transmit enable signal indicates the start of a transmit pause, which is based on the delay value specified in the transmit timing module 40. The modulation level signal is applied to the timing receiving module 39 and determines the moment when the pause length is 180 or 360 characters. The program reset signal allows the internal functions in the filter circuit to be reset 16. The third state signal allows the processor 12 to deactivate the filter system inputs 16. The enable signal allows the processor 12 to turn on and off the external circuit 21. This signal controls two and four second series of ringing signals. The supervisory strobe signal enables the processor 12 to reset the supervisory clock module to prevent the possibility of erasing camera blocks.

Processor 12 receives the interrupt signal of the receive clock signal from the receiving timing module 39 via Unia 26c, when the data is already entered into the first four cells of the two-page RAM of the receiving symbol buffer 35. Processor 12 then reads the received samples from the first four cells of the two-page RAM, after via the processor bus 25. At the same time, with a frequency of 64 kHz, samples are introduced into the next four cells of two-page RAM. The final 16 kHz frequency is derived from the 64 kHz frequency used to synchronize read and write processes. This ensures that no read / write processes occur in any of the memory locations at the same time, and ensures appropriate response times for processor 12.

The transmit symbol buffer in the transmit filter 42 via the processor bus 25 receives transmit symbols from the processor 12 and distribute them in an amount of up to two. Processor 12 receives an interrupt signal when two new symbols are written to the transmit symbol buffer. The transmit symbol buffer in the transmit filter 42 receives a write signal via the first internal bus 48 from the internal address decoder module 34.

After each 8 kHz signal on the 26a transmission clock interrupt line, processor 12 sends two five-bit transmission symbols for recording. The data is in differential phase keying format in Gray code. The transmit symbol buffer enters symbols at a frequency of 16 kHz for processing in the transmit filter 42. The data is separated twice because of the lack of synchronism between the filter system 16 and the processor 12.

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The last data is processed until the next ones are entered. Zero data can also be repeated in the same way. The transmit symbol buffer is reset with a reset signal.

During operation, the processor 12 sends a fixed symbol sequence to the filter system 16. The filter system 16 digitally filters these symbols and sends a pair of data symbols I, Q to the processing system 17.

The radio transceiver 20 transmits the data in the loop back to the analog-to-digital converter 19. The samples are read by the processor 12 in real time and the pickup coefficients are set to the processor 12. The only critical timing signals are the signals generated by the timing modules: receiving 39 and sending 40.

The receiving timing module 39 generates all reference and strobe clock signals for processing the reception symbols. The timing is corrected by processor 12 so that processing can be synchronous with reception samples received from the base station via line 27a. The receiving timing module 39 includes a partial timing circuit of the receiving clock and a timing circuit of the receiving pause. The task of these two circuits is to synchronize the modem reception clock inside the processor 12 with the samples received on the line 27a from the base station and via the analog-to-digital converter 19, as well as the adjustment of the transmission timing module 40 and the codec timing module 44.

The receiving timing module 39 is clocked with a 3.2 MHz clock signal and receives, via the processor bus 25, the following input control signals from processor 12; AM strobe signal, receive pause timer recording signal and receive bit tracking signal.

The receiving timing module 39 produces several output signals. On line 49 a 64 kHz signal is added to sum the record, to control recording in the receiving symbol buffer 35. On line 27b there is a 64 kHz weakening signal for the analog-to-digital converter 19 to synchronize its operation. Via line 52, an 8 kHz tuning signal is also transmitted to the codec clock module 44. The processor 12 is provided with a 16 kHz interrupt signal for the receiving timing clock on line 26c and an interrupt signal corresponding to the start of the interruption on reception on line 26b. A strobe signal is fed to timing transmitter 40 along line 54 and designating a reception break in advance.

The partial timing circuit in the receiving timing module 39 is set by the processor 12 to produce an interrupt signal for the start of the receiving pause on line 26b. Processor 12 determines the position of the lack of modulation amplitude of the strobe signal AM, transmitted by the base station during connection. When processor 12 detects the strobe signal AM, the timing signal pausesⁱⁿ receiving timing module 39 is reset with processor reset signal 12. This aligns the frame and gap markers with the strobe signal AM. The frame marker is a pulse with a duration of 62.5 / μsec, appearing every 45 milliseconds or every 22.5 milliseconds when working with quadrature phase keying.

The incoming receive symbols are demodulowaeb by the processor 12 and, if necessary, the timing continues to be equalized. In order to equalize the signal of the receiving clock, processor 12 forces the partial clocking circuit (bit tracking) to shorten or lengthen the 64 kHz strobe signal to within fifty, i.e. 3.2 MHz.

Processor 12 controls the relationship between the receiving and timing symbols of the frame, and fine-tunes the receiving clock. When tuning the receive clock, the positions of the pause markers and the frame also change because they are derived from the reception clock signal.

In order to maintain a constant number of code-pulse modulation (PGM) signal samples fed to the frame-synchronizing circuit

166 789 subscriber / codec 11, or derived from it, the receiving timing module 39 controls the timing module of the codec 44.

The transmission timing module 40 includes a transmission delaying circuit and a control timing circuit. These circuits generate a signal for interrupting the transmission clock, which is fed to processor 12 via line 26a. The transmit timing module 40 is synchronized with the receiving timing module 39 by the forward strobe timing of the receive pause, which is fed to the timing transmitting module 40 by the receiving timing module 39 on line 54 and is used to reset the transmit delay circuit, which in turn produces a pause flag. broadcasting. The clock transmission clock is based on a 3.2 MHz internal clock signal.

Processor 12 also controls the transmission timing delay and transmission timing circuits by feeding, via the processor bus 25, the recording control signals of the transmission data.

The transmission timing module 40 has sent a transmission / reception control signal to line 30 to the radio system 20. This signal determines when radio systems transmit and when they receive data. The transmit timing module 40 also controls the shifting of transmit symbols, addressing the ROM, accumulation timing, and remembering the products of the data symbols I, Q fed into the digital intermediate frequency system 17. The transmission timing module 40 sends control signals to the line 56 to synchronize the transmission filter 42 with respect to the transmit and timing symbol. This synchronization takes place in relation to the transmit pause flag. After clearing, the transmission timing module 40 begins to send control signals on line 56 once at the beginning of the transmission pause.

Transmission filter 42, containing ROM, gives the products of data symbols I and Q, depending on the address of the ROM, to select the combination of transmission symbols received from processor 12 via processor bus 25, and the sine and cosine coefficients counted by the meter, also included in this transmission filter 42. Transmission filter 42 collects six consecutive products of data symbols I and Q and stores the results for transferring them to the digital intermediate frequency system 17 via line 24a.

The required minimum operating frequency of the sending filter 42 is determined by the product: the frequency of downloading symbols (16 kHz) multiplied by the number of data symbols I and Q (2) by the number of coefficients (10) and by the number of repetitions (6) = 1.92 MHz. The main clock signal with a frequency of 3.2 MHz meets this requirement for a minimum frequency. Waiting measures are added to compensate for the higher speed of the operation.

The transmission timing module 40 is clocked with a 3.2 MHz clock signal that determines the length of the state period. Because the clock frequency is greater than the required minimum of 1.92 MHz, the transmit filter 42 produces signals corresponding to the first six of the ten status periods.

Each new transmit symbol must be entered at 16 kHz into the annular buffer in transmit filter 42. The annular buffer stores the new transmit symbol and the previous five transmit symbols. The oldest transmission symbol is skipped when entering a new symbol. The resulting operating frequency of the filter 42 is 320 kHz. Ten data symbol values ​​I and ten data symbol values ​​Q are generated from each transmission symbol. Table 1 below shows how the data symbols I, Q and the zero value can be read from each five-bit value.

Table 1

<td>BIT 1</td><td>ΒΓΓ 2</td><td>BIT 3</td><td>BIT 4</td><td>BIT 5</td>

<td>IQLSB</td><td>IQ</td><td>And MSB</td><td>QMSB</td><td>ZERO</td>

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The data in the ring buffer are changed into 6 out of 10 states. In the ring buffer for twenty such ten-state periods there is one new symbol and five previous ones. The part of the ROM address specifying the coefficients is also changed in six out of ten status periods. The battery in the transmitting filter 42 sums up all the products of the data symbols I obtained from the ROM in each of the six status periods. Therefore, the battery register is reset before the first total and the result of each subsequent total is saved in the battery feedback register so that it can be added to the last searched product. After six summations, the result is saved in the output shift register. The process is the same for the same coefficients and products of Q data symbols downloaded from ROM for each transmission symbol.

ROM address lines allow you to search for sixty cosine coefficients and sixty sine coefficients for the four possible indexes of data symbols I, Q. This requires seven address lines for coefficients and two address lines for data symbols I, Q. Exit from the above filter requires 10 bits. To increase accuracy, two additional bits of the fractional part of the search value are needed. This gives a ROM size of 512 x 12. The MSB bit (the oldest significant bit) of the symbol index of the given I, Q is passed, bypassing the ROM, to the two's complement circuit, which determines whether the value on the ROM output is inverted or not inverted. If the ROM addressing symbol is a zero symbol, the zero bit controls the seven address lines corresponding to the factor. Using seven address lines for factor search gives access to 128 cells. Only 120 coefficients are needed. Eight unused cells remain. Zero values ​​are stored in these cells, so you can easily achieve zero values ​​at the ROM output.

The function of determining the complement to two is carried out by applying complement to one and entering logical one into the next adder. The totalizer output is cyclically connected to its input in order to make subsequent summations or to be output by the multiplexer to the output shift register. The output result is rounded off by using only the upper bits.

The outputs of the filter send ring buffer 42 are cleared after reset. This gives zero information for processing until new transmit symbol values ​​are entered. The symbol for given I is processed first, Q - next.

The transmission timer interrupt signal appears only during the transmission interval. Processor 12 does not know when the transmission interruption begins or ends except when it responds to the interruption. The signal has an active low state with a clock cycle of 3.2 MHz, which ensures that the interrupt signal is not active after one use. Interrupting the transmission clock occurs every period of time corresponding to the appearance of a new symbol (16 kHz / 2).

The interruption of the receive clock occurs throughout the entire frame. Processor 12 masks this interruption, using a receive break marker as the mask. The interruption of the receiving clock is active low, with a clock cycle of 3.2 MHz. The interrupt corresponding to the beginning of the receiving break occurs every 11.25 milliseconds and has an active low state, with a clock cycle of 3.2 MHz.

When resetting, all interrupt signals are set to the inactive high state.

The codec clock module 44 produces strobe timing signals and transmits the needed clock signal via line 29 to the subscriber / codec 11 circuit to transmit 8 data bits between the subscriber / codec 11 coupling circuit and the processor 12, at a frequency of 8 kHz. The subscriber / codec 11 coupling circuit receives and transmits

166 789 data bits with a frequency of 8 kHz. The codec clock module 44 transmits the clock signal via line 29a and the synchronization signal via line 29b. The clock signal of line 29a is generated at a frequency of 1.6 MHz obtained by dividing the frequency of 3.2 MHz of the advance clock signal by two. The 8 kHz pulse with a duration of one 3.2 MHz period received from the receiving clock system 39 is again strobe with a 1.6 MHz clock signal, which ensures its appearance synchronously with the rising edges of the 1.6 MHz clock signal. Data transmission between the subscriber circuit / codec 11 coupler and processor 12 is accomplished using these two signals. This allows PCM subscriber data to be synchronized with the PCM base station.

The overhead control module 45 responds to the enable control signal generated in processor 12 and fed from control and state registers 36 to the first internal bus 48. It generates a 20 Hz square wave signal on line 31a and two 80 kHz phase control signals; phase A signal on line 31b and phase B signal on line 31c. Then sends these signals to the external circuit 21. The 20 Hz rectangular signal on line 31a controls the polarity of the voltage supplied by the external circuit 21 to the telephone interface system 10. The 80 kHz phase signals on lines 31b and 31c control the power source with pulse width modulation in the external circuit 21.

The external reset signal controlling the subscriber line interface circuit, on line 29c, from the coupling part of the subscriber / codec circuit 11 disables or forcibly changes, signals on lines 31a, 31b and 31c, set as a result of an external enable signal initiated by processor 12. This ensures that if the handset is deleted or removed from the cradle, the external signal is turned off. Due to the fact that the external circuit 21 generates high voltage and dissipates a lot of power, this voltage is generated only at the request of processor 12.

The external address decoder 37 generates device selection signals on the processor bus 25, used by processor 12 to access the intermediate frequency digital circuit 17, universal asynchronous processor transceiver 12 and free memory 14, in clearly separated address segments. Processor 12 has eight older address lines and data and program area selection signals. They are decoded to produce the appropriate device selection signals.

Signaling device 38 generates fifty milliseconds of system resetting pulses, on line 51, resetting all filter system modules 16 and all modules of the subscriber apparatus in Fig. 1. Signaling device 38 generates an impulse if it is not reset in a period of 512 milliseconds by the supervision strobe signal, given on first internal bus 48, via control and status registers 36.

The digital intermediate frequency system 17 is coupled to the processor 12 via the processor bus 25, the filter system 16 via lines 23 and 24, the analog-to-digital converter 18 via line 71, and to the local generator in the radio transceiver 20 via line 72. The local generator in this radio system 20 provides the main clock signal with a constant frequency of 21.76 MHz via line 72 to the processing system 17.

The digital intermediate frequency system 17 shown in Figure 3 contained in the subscriber apparatus of Figure 1 includes tuning registers 65, control registers 64 and a decoder module 61 of processor 12 connected to the processor bus 25 and to the second internal bus 76, the decoder module 61 is connected via line 24c to filter system 16. The output of tuning registers 65 is connected by line 82 to the phase 66 battery of the direct digital synthesizer, which then line 83 is connected to the direct digital synthesis generator 67. Interface module 62 of the intermediate frequency digital system 17 is connected by lines 24a and 24b to the transmission filter 42 and lines 77 and 78 to interpolator 63. The interpolator outputs 63 on lines 80 and 81 and the direct digital synthesis generator outputs 67 on lines 84 and 85 are connected to modulator 68. Output

166 789 of the modulator 68 is connected via line 87 to the noise reduction circuit 69, which is then connected via line 71 to the D / A converter 18. The digital intermediate frequency system 17 also includes a clock generator 60, whose input is connected via line 72 to the radio transceiver 20, and the outputs are connected via line 74 to interpolator 63, lines 32a and 23b to the buffer system 33 connecting subscribers in the filter system 16, and line 71a to the D / A converter 18. Together, the phase 66 battery and the direct digital synthesis generator 67 form a direct digital synthesis synthesis for the intermediate frequency digital signal synthesis.

The digital intermediate frequency circuit 17 is a custom-made integrated circuit, addressed as a processor data memory 12. The digital intermediate frequency circuit 17 may operate in one of two operating states, in a modulated carrier generation state or in an unmodulated carrier generation state. In the mode of operation with the modulated carrier generation, the data in the baseband are entered as data symbols I, Q and are used for modulation of the unmodulated carrier, generated when working with direct digital synthesis of the intermediate frequency digital system 17. In the state of operation with the unmodulated carrier generation, the baseband input data are ignored and the unmodulated carrier from the direct digital synthesis device is fed to the D / A converter 18.

Clock generator 60 generates all clock and clock signals in the digital intermediate frequency circuit 17, as well as produces a 3.2 MHz clock signal and a 3.2 MHz advance clock signal fed to the filter circuit 16 by lines 23a and 23b. The two primary clock signals used within the intermediate frequency digital circuit 17 are a 21.76 MHz clock signal and a 2.56 MHz gate interpolation signal. The 3.2 MHz clock signal is used internally to move the I and Q data symbols on line 24a from the filter circuit 16 to the interface module 62. The clock generator 60 outputs the 21.76 MHz clock signal received on line 72 from the local generator signal in the radio transceiver receiving line 20 and then feeds this isolated 21.76 MHz clock signal onto line 71a. Extraction is performed to ensure adequate control capacity of internal functions and minimize the slope of clock pulses. The separated 21.76 MHz clock signal is also fed to the 18 DAC and the rest of the external blocks. Clock generator 60 produces a 3.2 MHz clock signal by dividing the 21.76 MHz clock signal by 6 and by 8 in the following order: 6-8-6-Ś-6, which results in an average divider of 6.8 (21.76 : 6.8 = 3.2). The result of this change every cycle is a minimum period of 276 ns and a maximum period of 368 ns. A leading clock signal of 3.2 MHz is also produced, fed as a leading clock signal of 3.2 MHz on line 23b. Both clock signals are identical, except that the signal disabling ROM on the 23b line is ahead of the 3.2 MHz clock on the 23a by one clock cycle of 21.76 MHz. Clock generator 60 generates a 2.56 MHz gating signal on internal line 74 by dividing the 21.76 MHz clock cycle by 8 and 9 in a uniform sequence (8-9-8-9 -...), which results in an average divider of 8 , 5 (21.76: 8.5 = 2.56 MHz). This signal uses interpolator 63 and modulator 68.

The decoder module 61 of the processor 12 allows the processor 12 to control all the internal functions of the digital intermediate frequency circuit 17. The decoder module 61 decodes the address and strobe signals of the processor 12, obtained from the data space via the processor bus 25, to determine internal strobe recording signals that are fed, via the second internal bus 76, to control registers 64 and tuning registers 65 to enable processor 12 for recording control and configuration data. At the same time, only one output from the decoder module 61.0 is active, the signal on the specific output is determined by the processor addresses 12. If the function from the address area of ​​the digital frequency system 17 is selected, the device output signal on line 24c from the filter system 16 is activated.

166 T89

Interface module 62 receives the I and Q data symbols from the filter system 16 via line 24a in serial format and converts them to a 10-bit parallel format in which they are fed to interpolator 63 via line 77. Gate signal of data symbols I, Q on line 24b with filter system 16 is used to distinguish between data symbols I and data symbols Q. Interface module 62 also subtracts the previous data symbols I and Q from the current symbols to create increments Ι I and IQ of these symbols, which are then shifted to the right by 4 places (: 16), to create on the line 78 correct increments for the interpolator 63 Data transfer from interface module 62 to interpolator is synchronized with 2.56 MHz gating pulses fed on line 74 from clock generator 60.

Interpolator 63 collects ΔΙ, ΔΟ increments with a frequency of 1 60 kHz x 16 = 2, 56 MHz and transfers to the modulator 68 the interpolated I and Q data symbols, the first via line 80 and the second via line 81. Interpolator 63 performs linear interpolation x 16 to reduce the interference of the 160 Wiz frequency signal from the sampling occurring in the baseband data received from the filter circuit 16.

Interpolator 63 successively collects Ii Q data symbols for output signal generation at 2.56 MHz. At the end of the accumulation cycle (16 interactions), the I and Q data symbols should currently appear at the output of the interpolator 63. This is critical because the next accumulation cycle begins with the actual data. To ensure that the data is correct, the current data symbols I and Q are directly entered into the output register of the interpolator 63 during the last accumulation cycle in place of the output information of the adder that should have the same data.

Control registers 64 are used to control and configure the intermediate frequency digital system 17 and to select the types of operation. All control registers are filled by processor 12 via processor bus 25.

There are three control registers 64. The first control register stores the carrier modulation signal, high-low automatic tuning signal and low-high automatic tuning signal. The second control register stores the character selection signal, the output clock phase selection signal, the inverter interpolator activity signal, the serial input clock selection signal, the serial / parallel operation selection signal and the quadrature signal. The control functions associated with these signals are described below at the end of the description of the other modules of the digital intermediate frequency system 17. The third control register activates the noise reduction system 69 and sets its parameters.

There are three 8-bit tuning registers 65 for storing 24 bits of data regarding phase increments for determining the frequency of direct digital synthesis. This gives a 24-bit tuning word to achieve a frequency resolution of: (sample rate) / 2²⁴ ~ 21.76 MHz / 2²⁴ 1.297 Hz. The output frequency of the direct digital synthesis device is equal to the resolution multiplied by the 24-bit tuning word. The tuning registers 65 are populated by the processor 12 via the processor bus 25. The tuning word is doubly separated by the tuning registers 65 so that the processor 12 can freely write data to these registers without disturbing the current digital synthesis operation. After passing the tuning order, the tuning word is entered from the buffer tuning registers to the output tuning registers. The tuning command is synchronized with a 21.76 MHz clock signal to synchronize the change of state.

Phase 66 accumulator accumulates phase increments given by line 82 from tuning registers

65. At the output of the phase 66 battery is the digital phase value represented by line 83 to the direct digital synthesis generator 67 which generates the sine function.

The tuning word, which will be different for different subscribers, represents the phase change in the phase 66 battery. The output status of the phase 66 battery can reach from 0 to (2²^ -1). This range represents a 360 degree phase change. Although the phase 66 battery operates in a standard binary system, it is possible to introduce this digital phase representation into a waveform generator to obtain a waveform with a predetermined shape. In the digital intermediate frequency system 17, the direct digital synthesis generator 67 generates the sine function on line 84 and the cosine function on line 85.

The period of the reconstructed waveform function depends on the time needed to perform the summation to reach the upper battery limit (2 ^ -1). This means that the larger the phase increment used, the earlier this limit will be reached. Conversely, the smaller the increase used, the more time is needed. The phase 66 battery performs a simple summation of the input phase increment, which can be represented by the following equation:

n ίΡΤ ⁼ V ^ Pinc i = 1 where n is the number of interactions a / «, .. are input phase increment data provided by line 82 from register _ A,

In the described embodiment, the system fj ^ '"l intermediate wall 17 the wartośćτ value is imposed by the phase 66 battery and can be a maximum of 2²⁴. The current phase can be saved as:

φ_ι = (y9_t_i + p_inC) module 2

Due to the fact that the 21.76 MHz fixed master clock is used as the phase 66 battery clock, the total cycle includes 2²⁴ / inc interaction with a interaction period of 1 / 21.76 MHz. So the whole cycle lasts:

2²⁴

21.76MHz 'iPinc

Because this period represents a 360 degree cycle, the inverse of this expression represents the frequency. Hence the frequency of digital synthesis is:

_f _ 21.76MHz · cPinc Isynt ^ 24

In the modulator 68, a complex mixing of sine and cosine waveforms generated in the direct digital synthesis generator 67 is made. Each of the waveforms is generated by viewing two tables representing the rough and accurate determination of the shape of the function. These two values ​​are represented as two composite output signals on lines 84 and 85. The tables are implemented in ROMs addressed by the fourteen oldest bits of the signal on line 83 from the phase battery

66.

It is desirable to obtain phase resolution and amplitude that occurs in practice. As a consequence of the digital intermediate frequency system 17, 14 phase input bits and 12 amplitude input bits are fed to the waveform generation section. With an extreme approach to the generation of such data, very large tables would be needed to generate all possible phase and amplitude values, i.e. 16K words x 12 bits each. To minimize the size of the arrays, the digital intermediate frequency system 17 uses quadrant symmetry and trigonometric output reduction.

Because sine and cosine waveforms have quadrant symmetry, the two oldest significant bits of phase data are used to mirror the data of a single quadrant relative to the X and Y axes. For the sine function, values ​​in the range of n to 2 are simply values ​​of the range 0 to 2 with an inverse sign. For the cosine function, the waveform values ​​in the range of π / 2 to 3% / 2 are the values ​​of the range 3 π / 2 o 2/2/2 and with a double sign. The two oldest bits of the phase 66 battery designate the quadrant (00-&gt; 1, 01-&gt; 2, 10-&gt; 4). For the sine function, the oldest significant bit of the phase data is used to negate the positive data generated for the first two squares. For the cosine function, the negative OR logic function and the two oldest bits of the phase data are used to negate the positive data generated for squares 1 and 4.

166 789

Using the above technique quadruples the memory volume requirements. Still, 4K memory capacity x 12 bits is required. In order to further reduce the memory size, trigonometric reduction is performed. The following trigonometric identity is used:

sin Θ = emn ^! 1+ φ2 = ein φ \ coe e&gt; e + sne coe φφ assuming φι &lt;&lt; φ2 leads to the approximation:

sinO = sin yą + sinae 2 cos φ \

When calculating the second word of the equation, it is not necessary to use all bits of the value of φι, therefore φi is a subset of φl. When generating the function, the same approximation should be used, since cos Θ = sin (Θ + nt / 2)

This requires modification of the variables φι and undercutting the function ^ osir ^ r ^ s. The data contained in the ROM includes these modifications so that no phase data changes are needed.

Modulator 68 mixes zietbopolowneb data symbols I and Q, given on lines 80 and 81, with an intermediate frequency digital signal, represented by the data of complex sine and zosinηs functions, on lines 84 and 85, to produce on line 87 a modulated intermediate frequency signal . The back data symbols I, Q and the signal from the synthesizer output are digitally mixed in two 10 x 12 multipliers. The output waveforms of the mixing process are added together in a 12-bit adder to give a modulated carrier.

By forcing the output of the zoo itself and output Q of the ones only, you can change the operation of modulator 68. This will cause the zeros to appear at the output of one of the multialikatoo, and the output of the other - switching off the signal from the direct digital synthesis generator 67. The sum of both these signals give a low-frequency intermediate frequency digital signal.

Modulator 68 produces a modulated intermediate frequency digital signal on line 87, as follows:

f (t) = I · cos (φ (t)) u Q · sin (φ (t))

The 12-bit goeorntoon output value for direct digital synthesis 67 is multiplied by the 10-bit greenpolar data symbols I and Q from interpolator 63 to give two ^ bit products. These two products are then added together (in combination) to give a 12-bit output modulated on line 87. Because both the data symbol multialikator and the Q data symbol multiplier give 12-bit products, it is possible to create them excess. Therefore, it is necessary to ensure that the size of the vector formed by the data symbols I and Q will not exceed 1 (assuming that / I /, / Q / are numbers &lt;1). If this is not certain, then it is possible for the adder to overflow in modulator 68.

The noise reduction circuit 69 supplies the filtoogney, modulated or low-frequency intermediate frequency digital signal per line 71b to the digital-to-analog converter 18. The noise reduction circuit 69 is designed to reduce, in the output spectrum, the noise power caused by the amplitude quantization error. The noise reduction system 69 works using the fact that kwnntyzαzyjeyjost noise is a normal random process and that the spectral power density of this process is flat in the frequency band. A useful signal is superimposed on this basis of quantized noise. The 69 noise reduction system is a simple filter with a finite impulse response, with a multi-branch characteristic. This filter reduces the power of quetetic noise in some areas of the frequency band. If the useful wave is superimposed on the filtered noise spectrum, then the effective noise reduction factor is greater.

The filter transfer function is determined by:

H (z) = 1 + bz '¹ - from'²

Two degrees of sumαcyjeo give a dougi expression with a b value in the range from +1.75 to -1.75 (with binary weights 0; 0.25; 0.50; 1.0), which can cause the zero point of the filter to shift along the output frequency band . So you can put this zero place

166 789 as close as possible to the usable output frequency for obtaining the maximum signal-to-quantization noise ratio.

The value of the frequency of the zero position of the filter can be calculated by finding the roots of the above equation in the z plane. The roots form complex conjugate pairs arranged on a unit circle. The zero frequency value is determined by the relationship:

fzero -

360 ° o ^ sampling where O is the angular coordinate of the root on the upper half-plane. The conjugate elements will give symmetrical zeros relative to the Nyguist frequency.

Table 2 presents the values ​​of frequency of zero places corresponding to the values ​​of the second word as the sum of weights. Let b3, b2 and bl correspond to weights 1.0; 0.5; 0.25, the symbol + means that the word is equal to this weight, the symbol '¹- means that the word is equal to the negation of this weight, and 0 means that the word has no weight. Some of the frequency values ​​corresponding to zero places are equal for some different combinations simply because the possible combinations sometimes overlap (e.g. 1.0 + 0.5 - 0.25 = 1.0 + 0.0 + 0, 25). sample size is 1.00

Ta bale a 2

<td> 03</td><td> 02</td><td> 01</td><td>f (zero)</td><td>f (alias)</td>

<td> 0</td><td> 0</td><td> 0</td><td> 0,250</td><td> 0,750</td>

<td> 0</td><td> 0</td><td> -</td><td> 0,269</td><td> 0,731</td>

<td> 0</td><td> 0</td><td> +</td><td> 0,230</td><td> 0,770</td>

<td> 0</td><td> +</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td> 0</td><td> +</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td> 0</td><td> +</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td> 0</td><td> -</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> 0</td><td> -</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td> 0</td><td> -</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td> +</td><td> 0</td><td> 0</td><td> 0,167</td><td> 0,833</td>

<td> +</td><td> 0</td><td> -</td><td> 0,188</td><td> 0,812</td>

<td> +</td><td> 0</td><td> +</td><td> 0,143</td><td> 0,857</td>

<td> +</td><td> +</td><td> 0</td><td> 0,115</td><td> 0,885</td>

<td> +</td><td> +</td><td> +</td><td> 0,080</td><td> 0,420</td>

<td> +</td><td> +</td><td> -</td><td> 0,143</td><td> 0,857</td>

<td> +</td><td> -</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td> +</td><td> -</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td> +</td><td> -</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td> -</td><td> 0</td><td> 0</td><td> 0,333</td><td> 0,667</td>

<td> -</td><td> 0</td><td> -</td><td> 0,357</td><td> 0,643</td>

<td> -</td><td> 0</td><td> +</td><td> 0,312</td><td> 0,688</td>

<td> -</td><td> +</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> -</td><td> +</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td> -</td><td> +</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td> -</td><td> -</td><td> 0</td><td> 0,385</td><td> 0,615</td>

<td> -</td><td> -</td><td> +</td><td> 0,357</td><td> 0,643</td>

<td> -</td><td> -</td><td> -</td><td> 0,420</td><td> 0,580</td>

All measures are obtained from a 21.76 MHz clock signal on line 71 a. The functions associated with the signals in control register 64 are not currently described.

When the carrier modulation signal is active, then at the input of the data symbols and the corresponding multiplier in the modulator 68 are all zeros, and at the corresponding input of the data symbols Q - only ones. The final effect is generating an indecent one

166 789 dull carrier. This function is double buffered and the input data is not active as long as a tuning command is given.

The interpolator activity signal allows you to enable the interpolator for I, Q data symbols. If the interpolator activity signal is not active, the data symbols I, Q are entered into the multiplier.

Fast memory 13 and free memory 14 are used as external memory needed for processor 12 to work. Fast memory 13 is available through the address decoder

15. Fast memory 13 is dedicated memory, implemented in RAM memory with no waiting times. Free memory 14 is a mass memory implemented in EPROM having two waiting states. The free memory 14 is connected to the processor 12 in order to memorize operative codes active by pi ^ c ^ c ^^ and ^ c ^ i-12, the codes do not have to be executed without waiting states, and the fast memory 13 is connected to the processor 12, when the codes work without waiting states. When the procedure has to be performed without waiting states, you can overload the code from free memory 14 to fast memory 13 and run the procedure from it. Such procedures are interrupt handling routines, symbol demodulation, radio control channel search, demodulation of binary phase keying and speech and data processing.

Processor 12 performs, as shown in Figure 4, four main tasks, namely: subscriber control task (module 91), channel control task (module 92), signal processing task (module 93) and modem processing task (module 94). The main module 95 controls these four tasks. The subscriber control module 91 manages the telephone interface and the processing of high-level calls. The channel control module 92 controls the modem operation and the RELP coding algorithm and the timing, adjusts the power level and transmission timing, depending on the base station request. Signal processing module 93 performs functions in accordance with the RELP coding algorithm, echo suppression and tone generation. The main program invokes these four sequential tasks, communicating with them via control words.

The subscriber control module 91 performs high-level control functions inside the subscriber's apparatus and has three basic types of work: waiting, talking, interruption. This module goes into standby mode when the power is turned on and remains in this state until a new connection and conversation is made. While in a waiting state, module 91 monitors the subscriber's telephone interface for activity and responds to base station requests received via the radio control channel. The basic function of the subscriber control module 91 is to insert the subscriber's apparatus into the radio channel by connecting and disconnecting calls. Before the camera can establish any connection, it must find the correct base station. The subscriber control module 91 assigns the radio control channel frequency to use and sends the frequency information to the channel control module 92.

After the subscriber reaches synchronization with the radio control channel, it can establish connection by exchanging information in the control channel with the base station as well as by controlling and setting telephone interface signals. The following connection setup diagram briefly discusses the situations that may occur.

The normal calling process starts with the subscriber lifting the receiver from the hook to request service. The subscriber control module 91 sends a call request message to the base station and receives call joining information. In addition, it signals to the channel control module 92 an attempt to synchronize in the talk channel allocated in the called call information. The channel 92 control module receives a synchronization signal in the talk channel. The subscriber receives a dial tone from the control panel. Connection setup is complete. The control panel carries out the rest of the operations related to the call.

The normal process of joining an incoming call is as follows. The subscriber control module 91 receives call information from the base station. The subscriber control module 91 answers with the signal 'call accepted. Then it receives the call joining signal and signals, to the channel control module 92, a sync attempt on the talk channel assigned by the call joining information. The channel 92 control module receives a synchronization signal in the talk channel. The subscriber control module 91 starts a call generator to send a call signal to the local loop. The subscriber takes the phone off the hook. The call signal is switched off. Joining the call is completed.

The subscriber control module 91 performs connection setup and disconnection operations on the principle of a finite automaton. If the booking of the channel is successful, this module goes into the conversation state and performs a very limited set of auxiliary functions. The load on the processor of the subscriber control module 91 is kept to a minimum to give maximum processor accessibility to the speech compression functions of the RELP coding algorithm, echo suppression and modem processing algorithm.

The subscriber control module 91 introduces the type of interrupt operation as a result of unsuccessful call initiation or an unexpected interruption of the conversation. Feedback is sent to the handset in interrupt mode. This module monitors the subscriber's interface in order to disconnect it (replacing the handset), whereby the subscriber's phone goes into standby mode. Base station requests received via the radio control channel are skipped until there is no connection.

The channel control module 92, as the channel controller, operates at the link level in the baseband software. This module has three basic states: work in the radio control channel, adjustment and talkative work.

After turning on the power, the channel control module 92 enters the operating status of the radio control channel in order to search and operate this channel. Operation in the radio channel includes the following activities: control of the lack of signal amplitude modulation, monitoring of synchronization status and modem task, equalization of radio channel timing, filtering of receiving messages, formatting of transmission messages of the control channel, monitoring of the input / output buffer of PCM signals and processing of combined information. After the conversation is established, the channel control module 92 goes into the adjustment state to fine-tune the modem's partial clocking.

Justification includes the following functions: interpretation and response of adjustment pulses, creation and formatting of transmission adjustment pulses, transmission of relevant messages to the subscriber control module 91, monitoring of the modem status and monitoring of the input / output buffer of PCM signals. After removal, the channel control module 92 begins talking operation, including the following functions: support for codeword signaling, drop detection, monitoring of synchronization and modem status, and monitoring of the input / output buffer of PCM signals.

The 92 channel control module has three basic operating states: waiting, justification and conversation. The following is a description of the subsequent status changes when operating with channel control.

After resetting the channel control module 92, it goes into standby mode and remains inactive until receiving the channel allocation instruction by the subscriber control module 91. This module transmits to the channel control module 92 information on the frequency at which the radio control channel should be searched. Then the channel control module 92 issues for the modem processing task 94 a command to synchronize the receiver to a given frequency and search for the lack of modulation of the signal amplitude. Failure to detect the lack of modulation of the signal amplitude at a given time causes the channel control module 92 to request a different search frequency from the subscriber control module 91. This is repeated continuously until the search for a lack of signal amplitude modulation is successfully completed. After successfully detecting the lack of signal amplitude modulation, the channel control module 92 begins to check the received data for compliance with the highlighted word. A small window is analyzed around the nominal position of the highlighted word, due to the possibility of learning the process of detecting the lack of modulation of the signal amplitude for several symbols. Once you have located

166 789 the highlighted word is valid and the correctness of the cyclic checksum is checked, the exact receiving cycle of the symbol can be determined. The time division multiples markers are then tuned to exact values ​​and the normal operation of the radio control channel begins. If the highlighted word has not been located, then the detection of the lack of modulation of the signal amplitude is considered incorrect and the channel control module 92 requests from the subscriber control module 91 a new frequency allocation.

During operation of the radio control channel, the channel control module 92 filters the received messages of this channel. Most of the base station radio channel control messages are zero site patterns and are discarded after reading connection information from the connection byte. Control channel messages containing real information are forwarded for processing in subscriber control module 91. If synchronization has broken, the radio control channel again requests a new frequency from the subscriber control module 91. The module will respond with a correct frequency signal in accordance with the radio frequency control channel search algorithm.

When the subscriber control module 91 initiates a conversation, a talk channel and a time gap are allocated to the channel control module 92. This module activates the subscriber's apparatus in accordance with its allocation and starts the adjustment process. During justification, the base station and the subscriber's apparatus transmit a signal with binary phase keying, specially designed to help the modem find the bit time. The base station of the channel control unit forwards the bit timing offsets values ​​back to the subscriber's apparatus. The channel control module 92 determines the time-average of these feedback offsets. When this module determines that the partial timing is within the set tolerance, it tunes the timing of the subscriber's apparatus accordingly. The length of time averaging period is determined dynamically, depending on the variance of the partial clocking samples. After adjusting the timing, the average is reset and the procedure is repeated.

When the base station determines that the timing signal of the subscriber's apparatus is within the specified timing tolerances, it stops the adjustment process and talkative work begins. The length of the adjustment process is determined dynamically, depending on the success in adjusting the timing of the subscriber's apparatus. If necessary, the power is monitored and adjusted during adjustment, and the whole symbols are clocked.

If the subscriber's device is not able to find the adjustment pulses of the base station after a certain period of time or the adjustment process does not give due timing, then the connection is terminated and the channel control module 92 returns to the operation on the radio control channel. After successful adjustment, this module introduces talk work at the assigned modulation level. The task related to talk operations includes: controlling RELP coding and modem processing operations, establishing talk synchronization, and continuous monitoring of talk code words sent from the base station. Changes in local loop control, signaled by means of code words, after they appear, are transmitted to the subscriber control module 91. Incremental changes in power and partial timing are also determined based on the code words. Broadcast talk coded words are formulated by the channel control module 92 based on local loop control implemented by the subscriber control module 91 and the quality of the channel connection signaled by the modem. When the subscriber control module 91 executes the interrupt sequence, the connection of the channel control module 92 returns to the radio control channel.

If the talkative synchronization has been broken, then the channel control module 92 initiates the recovery operation after the decay. Ten seconds after the error, in order to re-establish a good talk connection, this module transmits to the subscriber control module 91 information about conditions, initiation and termination of the connection. This causes the channel control module 92 to go into standby mode.

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During the channel testing operation, the talk pulses are replaced with the channel test data. Immediately after receiving the pulse, it is analyzed for four bit errors. The number of bit errors is transmitted to the base station via feedback channel pulses.

Signal processing module 93 performs all tasks related to digital signal processing in the subscriber's apparatus. Various functions of digital signal processing are called as required, under the control of the main module 95.

Signal processing module 93 includes a module for implementing the RELP encoding algorithm, which is executed from fast RAM. The RELP coding module performs speech compression and the expansion and suppression of echoes. The RELP coding module converts 180-byte PCM talk blocks with 64Kbps into 42 bytes of compressed talk data and vice versa, using the RELP encoding algorithm. Signal processing module 93 also includes a signal processing control module that determines whether tone generation or RELP waveform generation is to be called. If the RELP waveform, then the signal processing control module determines whether to invoke synthesis or analysis programs. Synthesis programs return the parity error checksums subsequently processed by the program processing program. If a tone signal generation is required, it determines whether silence or signal should be output.

Signal processing module 93 is controlled by commands from subscriber control modules 91 and channel 92 control. These commands call and control the operation of various functions within the signal processing module 93 when the subscriber requests them. Programs related to RELP encoding and echo suppression are, for example, only carried out when the subscriber's apparatus is activated for the conversation. Dial tones are not generated when the handset is hung up and the RELP waveform is inactive. Tone signals include silence and a signal. Except for the standby state, the interrupt handler working with the PCM codec operates continuously as the primary process of filling the PCM signal buffer. Control and modem functions are performed in the intervals between the analysis and synthesis processes.

The domodulation procedure, implemented in the modem processing module 94, is divided into two procedures: DEMODA and DEMODB, which allows performing RELP encoding on the reception data in buffer A, immediately after completing the DEMODA procedure. After the DEMODA procedure, all variables from the internal RAM must be stored in the external RAM and then transcribed to the internal memory before performing the DEMODB procedure. This is needed because the RELP encoding process uses internal RAM.

After the processor 12 receives the interruption of the receiving clock signal on line 26c, the modem processing module 94 reads four received reception data samples and places them in a ring buffer to process them according to the demodulation procedure. This allows you to perform other tasks simultaneously with receiving reception samples.

Modem processing module 94 receives the interrupt signal of the receiving clock on line 26c from the filter system 16 every 62.5 μs during the receiving interval. This interrupt signal is masked by the processor software during a wait or transmission pause. This module receives the interrupt signal on line 26a from the filter circuit 16 only during the transmission pause. The interrupt signal instructs the processor 12 when to send a new transmit symbol to the filter circuit 16. The module reads four samples from the receiving symbol buffer 35 in the filter system 16 when the clock signal on the 26c line is interrupted. At the beginning of the receiving break, this module transfers the input and output counter states to this buffer. Modem processing module 94 sends transmit symbols to the receive symbol buffer 35 in the filter arrangement

16. This module also transmits to the partial timing circuit in the receiving timing module 39 in the filter circuit 16 data that is used to equalize the clock interrupt signal on line 26c for transmission from the base station. This module

166 789 also synchronizes the frequency of direct digital synthesis with the frequency of the base station.

According to Figure 5, the modem processing module 94 includes the following modules interconnected: main module 101, decay module 102, frequency search module 103, bit synchronization module 104, speech demodulation module 105, symbol receiving module 106 and transmitting module 107.

The main module 101 includes a program for managing the modem processing module 94. It reads the control word from RAM and calls other programs depending on the control word.

The run-up module 102 calculates the 28-min vector of complex filter coefficients. Runs in a waiting mode after turning on the power and every three hours. A take-off transmitter implemented in modem processing module 94 is activated in a closed loop for sending a certain sequence of symbols. This sequence is sent back to the run-down receiver implemented by this module, in the normal type of operation, in the work with accelerated and delayed timing types and in the adjacent, upper and lower channels.

The run-up receiver uses input waveform samples to create positive labeled symmetrical A matrices of the order of 28. So, from the input samples, a vector V 28 words is created. Coefficients of the vector C are determined by:

C = A -V

The B factor is calculated according to the algorithm: B = A⁴ for given A.

The take-off transmitter is activated in a loop to transmit five similar pairs of sequences. Each pair consists of the following two sequences:

Sequence of data symbols I: 9 zero symbols, and, 22 zero symbols.

Sequence of data symbols Q: 9 zero symbols, j, 22 zero symbols.

Symbol and can be any symbol. The symbol j is a symbol that differs from and by 90 degrees.

The tasks of receiving processing are:

Fine-tuning the automatic gain control so that the peak value of the signal under normal operating conditions is 50% to 70% of the maximum. The gain control value increases by 23 db for the 4th and 5th operation types.

Reading and remembering input samples. In each sequence, the first 32 samples are skipped and the next 64 samples are stored.

List of matrix A (28, 28). In the normal type of work, the process is carried out:

A (I, J) = A (I, J) + Σ X (4N-I) · X (4N-J)

Adding takes place for all N meeting the conditions:

0 &lt;= 4N-I &lt;64 and O &lt;= 4N-J &lt;64

For accelerated and delayed sequences, the same actions are performed, except that the calculated word for N = 8 is not added. On sequences broadcast in adjacent, upper and lower channels, the following actions are performed:

A (I, J) = A (I, J) + ΣX (2N-I) · X (2N-J)

Adding is performed for all N meeting the conditions:

0 &lt;= 2N-I &lt;64 and O &lt;= 2N-J &lt;64

A V (1:28) vector is created from samples of the first pair of sequences.

Re {V (I)} = X (32-I), where X are samples of the first sequence (I).

Im {V (I)} = X (32-I), where X are samples of the second sequence (Q)

The vector of coefficients C is found by solving the equation:

AXC-V = O

The frequency search module 103, used when receiving the control channel, synchronizes the reception frequencies of the subscriber's apparatus with the frequency of the transmitting base station. This is done by tuning the output carrier wave of direct digital synthesis until the power of both side bands equals. Next, the direct digital synthesis broadcast frequencies are tuned in accordance with the calculated frequency deviation. If the procedure does not lead to frequency synchronization, the appropriate error code is entered into the status word.

The bit synchronization module 104 operates during reception on the radio control channel and after frequency search. In the first 44 symbols, in the transmission on the control channel, a certain pattern is transmitted from the base station, which is used by this module to calculate the deviation of the receiving clock signal from the correct sampling cycle. The value of this deviation is used to fine-tune the clock signal.

The speech demodulation module 105 is activated to demodulate the talk break. It resides in free EPROM memory, its functions are divided between two procedures DEMODA and DEMODB.

The functions of the DEMODA procedure include initializing parameters for the symbol receiving module 106, calling the symbol receiving module 106 to process received symbols in the buffer, and storing variables in external RAM before exiting the procedure.

The functions of the DEMODB procedure include loading variables from external RAM to internal RAM, calling the symbol receiving module 106 to process the received symbols in buffer B, and determining the quality of the connection and other information after receiving all symbols in the pause.

The contents of the symbol receiving module 106 are rewritten into RAM when the channel control module 92 goes into a talkative mode of operation. It is called by the DEMODA or DEMODB procedures to perform the following actions: 1) reading the I and Q data symbols from the ring buffer, 2) filtering the I and Q data symbols, 3) determining the transmitted symbols and placing them in the buffer, 4) implementing the phase loop to synchronize the radio control channel with the input signal, 5) implementing bit tracking algorithm, 6) calculations for automatic gain adjustment and 7) data collection for assessing the quality of the connection.

Transmission module 107 includes a program for handling the interruption of the transmission clock signal received on line 26c from the filter circuit 16, which appears once every two symbols during the transmission break. The functions of the transmitting module 107 include: 1) removing the transmitted symbol from the RELP coding buffer, 2) performing its reverse coding in Gray code, 3) adding it to the previously assigned phase (due to the transmission with differential phase keying) and 4) sending it to the transmit buffer in the filter system 16.

The modem processing module 94 is coupled to baseband tasks via control words and status and data buffers in dedicated memory. Procedures that require quick execution are rewritten as needed into sequential memory. These procedures include interrupt handling programs, symbol demodulation, radio control channel search and binary phase keying demodulation.

The main program of the modem processing module 94 does not wait for the beginning of the interruption in reception with the reading and decoding of the control word, but does so immediately after being called.

The TMS320C25 processor, used in the apparatus according to the invention, during the execution of the instruction waits to the operating state with reduced power. To save power, this processor's software realizes the wait state most of the time when no phone calls are being made. Also after deleting, the main program, after synchronizing with the radio control channel, goes into the waiting mode until a predetermined interruption causes the corresponding operating program to be executed. When operating at reduced power, the TMS320C25 processor goes to rest and consumes only a portion of the power needed for its normal operation. When operating at reduced power, all information contained in the processor is maintained to allow operation to continue when the operation is reduced at reduced power. Upon receipt of the interrupt, processor 12 interrupts

166 789 temporarily work with reduced power and take the normal watt for at least one major cycle. At the end of the main cycle, the reduced power requirements are checked to see if the nboeoeckS should switch to reduced power or not.

The pause clock is based on the system generated pace. When an interrupt is triggered by the interrupt marker, the program increases the interruption by one tick. Each clock cycle is 11.25 ms.

The receiving and transmitting functions of the asynchronous receiver-transmitter are not controlled by interrupts, but by means of auxiliary software that controls the load on the processor and zαaobiogαjazogk conditions for skipping the interrupt. The processing codes follow the transmitter on / off protocol and the reception pose they directly and immediately control the appropriate on and off of the asynchronous odZniknik-eαdαjnikα. The speed of the sending and receiving processes can be selected using an external switch. Typical data reception speed is 9600 codes. A ring buffer is used to control the transmission of the asynchronous receiver-transmitter system. The helper software periodically checks the queue status and starts the transmission if it is not zero. It does this each time byte sending to asynchronous kdbikonikα-endąjeika until the queue is empty.

The fork condition is sampled by the TMS320C25 processor internal clock program. A sampling period of approximately 1.5 ms is used to simulate continuous-brain signaling. This interruption is aligned with the frame tact at the beginning of each frame, so to avoid the nminkmines and excess in the fork switch buffer, its frequency is consistent with the base station frequency. With each transition, a bit representing the fork switch detection signal from the subscriber line interface circuit is entered into the 60-bit fork switch sample buffer. The fork switch sample buffer is reviewed by the subscriber control module 91 at normal aonza every 45 ms. The program allows this interruption at all times.

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FIG. 4

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FIG. 5

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UP Department of Publications. Circulation of 90 copies

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