Subscriber unit for wireless digital subscriber communication system

(12) PATENT

NORWAY (19) NO (11) 307239 (13) Bl (51) Int Cl⁷ H 04 M 1/00, H 04 Q 7/32

NIPO

121) Application no

22) Starting day

24) Race day

41) Alm. avail.

45) Date announced

19903529

1990.08.10

1990.08.10

1991.02.15

2000.02.28 (86) Entering date and application number (85) Continuation day (3 O) Priority

1989.08.14, US, 394497

<td>(71) Patent holder</td><td>InterDigital Technology Corp., 913 Market Street, Suite 802, Wilmington, DE 19801, US</td>

<td>(72) Inventor</td><td>David Norton Critchlow, San Diego, CA, US Moshe Yehushua, San Diego, CA, US Graham Martin Avis, San Diego, CA, US Wade Lyle Heimbigner, Poway, CA, US Charles Joseph Johnson, Carlsbad, CA, US George Alan Wiley , San Diego, CA, US</td>

<td>(74) Agent</td><td>Bryns Patentkontor AS, 0106 Oslo</td>

- (54) Designation

Subscriber unit for wireless subscriber communication system (56) Published publications None (57) Summary

The wireless communication subscriber unit with a base station in a wireless subscriber communication system includes a FIR chip (16), a DIF (digital medium frequency) chip (17), a single processor chip (12) and a radio (20). The processor chip transcodes a digital speech input signal to glide digital input symbols, demodulate an output signal received from the base station to provide digital output symbols, and synthesize a digital speech output signal from the digital output symbols. The FIR tag FIR filters the digital input symbols and generates clock control signals for timing the transcoding and synthesizing operations of the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to produce a modulated intermediate frequency input signal. The radio also processes the modulated input signal for transmission to the base station.

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in

The present invention relates to subscriber communication systems and is particularly directed to an improved wireless subscriber unit with a base station in a wireless digital subscriber communication system.

A typical subscriber unit is described in US Patent 4,825,448 (David N. Critchlow et al). A base station used with such a subscriber unit 1 of a wireless digital subscriber communication system is described in U.S. Patent No. 4,777,633 (Thomas E. Fletcher, Wendellne R. Avis, Gregory T. Saffee and Karie J. Johnson). The subscriber unit described in application 06 / 893,916 includes means for transcoding a digital voice input signal to provide digital input symbols, means for FIR filtering the digital input symbols, means for deriving an analog intermediate frequency input signal from the filtered input signals, means for combining intermediate input sign als. with an RF carrier wave for radio transmission to the base station, means for demodulating an output signal received from the base station to provide digital output symbols, and means for synthesizing a digital speech output signal from the digital output symbols. The subscriber unit includes a baseband processor chip and a modem processor chip. Both are TMS32020 digital signal processors. The baseband processor chips perform the transcoding of the digital speech input signal, the synthesis of the digital output symbols, and various baseband control functions, and the modem processor chip performs the FIR filtering of the digital input symbols and the demodulation of the output signal is received from the base station. The modem processor chip generally acts as the main unit of the system.

The present invention provides a less expensive subscriber unit. The subscriber unit of the present invention includes means for transcoding a digital voice input signal to provide digital input symbols, means for FIR filtering the digital input symbols, means for modulating a digital intermediate frequency signal with filtered input symbols, to produce a modulated intermediate frequency input signal, to process the modulated input signal for transmission to the bass station, means for demodulating an output signal received from the base station for gliding digital output symbols, and means for synthesizing a digital output signal from the digital output symbols, characterized in that the subscriber unit includes an FIR chip for performing said FIR filtering of the digital input symbols. a DIF chip for digitally synthesizing said digital intermediate frequency signal and for performing said modulations of said digital intermediate frequency signal, and a single processor noise for performing said transcoding of said digital voice input signal, for performing said demodulation of said output signal received from the base station, and for performing said synthesis of the digital output symbols.

The FIR chip performs the FIR filtering function implemented by software in the modem processor according to the prior art subscriber unit described above. By moving the time consuming send FIR filtering function out of the modem processor and by performing the demodulation function with the same processor performing the baseband processing function, only one processor chip is required.

Means for digitally synthesizing the digital intermediate frequency signal is a direct digital synthesizer (DDS) which includes means coupled to the processor chip and accumulates phase data provided by the processor chip to indicate a predetermined intermediate frequency; and means for processing the accumulated phase data to generate said digital intermediate frequency signal at the predetermined intermediate frequency. The present invention therefore adds new functionality to the subscriber unit that did not exist in the prior art subscriber unit described above, in that direct digital synthesis enables extremely flexible tuning of the subscriber unit. In the prior art subscriber unit described above, tuning was limited to a particular set of channels separated by 25 KHz increments. Furthermore, the frequency difference between transmission and reception was fixed at 5 MHz. The DDS function of the DIF chip removes these limitations, allowing other types of channel distances or TX / RX offsets to be supported with minimal or no modification of the subscriber unit hardware.

Accordingly, the DIF chip provides a fully modulated digital IF signal which can be digitally synthesized on any of a plurality of different predetermined intermediate frequencies; and fine resolution frequency adjustment can be provided in the DIF chip to allow frequency tracking of the output signal received from the base station. These two features allow the radio in the subscriber unit to contain only a fixed frequency LO reference and eliminate the requirement for an RF synthesizer. These two features also allow the primary frequency reference in the subscriber unit to be fixed, with all the tuning adjustments made by the DIF chip.

A direct digital synthesizer is stable and easy to manufacture. Phase noise specifications can be met without the need for an expensive and complicated PLL RF synthesizer. The DDS feature provides frequency smoothness within the mid-frequency band and provides easier frequency modifications for the operation in other bands.

Another feature of the present invention is that the FIR chip includes means for generating timing signals to control the transcoding operation and synthesizing operation of the digital speech output signal by the processor chip.

However, the processor chip performs the demodulation of the output signal received from the base station regardless of the timing signals generated by the FIR chip. The processor chip receives said output signal according to the timing signals generated by the FIR chip and buffers the received demodulation output signal, thereby allowing the processor chip to perform said demodulation when not performing said transcoding and synthesis operations.

The present invention also reduces manufacturing costs by including a combination of a slow memory coupled to the processor chip for storing processing codes used by the processor chip when said codes do not need to operate with zero wait states and a fast memory coupled to the processor chip for temporary storing the processing codes used by the processor chip when said codes are operated with zero wait states. Fast RAM storage (with a zero waiting state) and fast EPROM storage with the same chip density are very expensive. To reduce costs, the processor code can be stored in a slow EPROM (with one or more wait states) and when procedures must be run with zero wait states, the code can be uploaded from the slow memory to the fast memory and run from there.

Further features of the present invention are described in relation to the description of the preferred embodiment.

Figure 1 is a block diagram of a preferred embodiment of the subscriber unit of the present invention.

Figure 2 is a block diagram of the FIR chip included in the embodiment shown in Figure 1.

Figure 3 is a block diagram of the DIF tag included in the embodiment shown in Figure 1.

Figure 4 illustrates the processing tasks performed by the processor chip shown in the embodiment of Figure 1.

Figure 5 illustrates the processing routines included in the modem processing task shown in Figure 4.

The following are definitions of abbreviations and acronyms used here:

<td>A / D AGC</td><td>Analog-to-Digital Automatic gain control</td>

<td>ASIC</td><td>Application-specific integrated circuit</td>

<td>BPSK</td><td>Binary phase shift keying</td>

<td>CCT</td><td>Channel Control Task</td>

<td>CCU</td><td>Channel Control Device</td>

<td>CRC</td><td>Cyclic redundancy check</td>

<td>DAC</td><td>Digital-to-analog converter</td>

<td>DDS</td><td>Direct digital synthesizer</td>

<td>DIF</td><td>Digital intermediate frequency</td>

<td>DIP</td><td>Double-step (in-line) package</td>

<td>DOOR</td><td>Data output ready</td>

<td>DPSK</td><td>Differenislalfasenskiftnøkling</td>

<td>DSP</td><td>Digital signal processing</td>

<td>EPROM</td><td>Erasable reading storage</td>

<td>FIR</td><td>Final impulse response</td>

<td>I / O LSB</td><td>Input / Output Least significant bit</td>

<td>MPT</td><td>Modem Manager Task</td>

<td>MSB</td><td>Most significant bit</td>

<td>MUX</td><td>multiplexer</td>

<td>PCM</td><td>Pulse Code Modulation</td>

<td>PLL</td><td>Phase-locked loop</td>

<td>PWM</td><td>Pulse width modulation on</td>

<td>QPSK</td><td>Quadrature phase shift keying</td>

<td>RAM</td><td>Direct stock</td>

<td>RCC</td><td>Radio Control Channel</td>

<td>RELP</td><td>Rest excited close to preaching</td>

<td>RF</td><td>radio Frequency</td>

<td>ROOM</td><td>reading Inventory</td>

<td>RX</td><td>reception</td>

<td>RXCLK</td><td>Reception clock</td>

<td>RXSOS</td><td>Receive Start of Slot Reception</td>

<td>SCT</td><td>Subscriber Control Task</td>

<td>SLIC</td><td>The subscriber line interface circuit</td>

<td>SPC</td><td>signal Management</td>

<td>SPT</td><td>signal Processing Task</td>

<td>SPTCTL</td><td>Signal Processing Task controller</td>

<td>SSB</td><td>Switch-fork sample buffer</td>

<td>TDM</td><td>Tidsdelingsmultipleksing</td>

<td>TX</td><td>sending</td>

<td>TXCLK</td><td>Shipping clock</td>

<td>UART</td><td>Universal asynchronous receiver transmitter</td>

<td>VLSI</td><td>Very large scale integration</td>

<td>XOR</td><td>Exclusive or</td>

Referring to FIG. 1, the preferred embodiment of the subscriber unit of the present invention includes a telephone interface unit 10, an SLIC and coding unit 11, a processor chip 12, a fast memory 13, a slow memory 14, an address decoder 15, an FIR chip 16 , a DIF chip 17, a DAC 18, an A / D converter 19, a radio 20, a ringer circuit 21, and an oscillator 22.

The FIR chip 16, which is an ASIC chip, is adapted to the DIF chip 17 by lines 23 and 24, to the processor chip 12 by processor bus 25 and line 26, to the A / Jumper 19 by line 27, to the SLIC and codec circuit. 11 by line 29, to radio 20 by line 30 and to ringer circuit 21 by line 31.

The telephone interface circuit 10 is adapted to a telephone 32 which converts sound waves into an input speech signal and converts an output speech signal to sound waves.

The SLIC and codec circuit 11 are connected to the telephone interface circuit 10 to convert the input speech signal into a basic digital input signal which is supplied to the processor chip 12.

In an alternate embodiment (not shown), the processor chip is also directly adapted to UART to alternatively receive digital input signals directly from and transmit digital output signals directly to a digital I / O device.

Processor chip 12 includes a model TMS320C25 digital signal processor which transcodes the baseband digital input signal according to a RELP algorithm to provide TX data digital input signals on the processor bus 25. The use of a digital signal processor to execute a RELP algorithm is described in International Patent Application No. PCT. US85 / 02168, International Publication No. WO 86/02726, published May 9, 1986.

FIR chip 16 FIR filters the digital input symbols and provides I, Q data to DIF chip 17 on lines 24.

The DIF chip 17 interpolates the filtered digital input symbols and modulates a digital intermediate frequency signal with interpolated input symbols to produce a modulated digital input signal.

DAC 18 converts the modulated digital input signal into a modulated analog input signal.

Radio 20 transmits the modulated analog input signal to the base station, and receives and demodulates a modulated analog output signal from the base station.

The oscillator 22 is a free-running oscillator, which provides clock signals for the processor chip 12.

A description of the relationship between the subscriber unit and the base station is found in U.S. Patent No. 4,777,633.

The A / D converter 19 converts the demodulated receiver analog output signal into a digital output signal containing digital output symbols.

The processor chip 12 synthesizes a baseband digital output signal from the digital output symbols. Synthesis of RELP transcoded symbols using a digital signal processor is also described in International Publication No. WO 86/02726. Processor chip 12 also performs echo canceling as described in US Patent No. 4,697,261 (David TK Wang and Philip J. Wilson).

The SLIC and the codec circuit 11 convert the baseband digital output signal to the output speech signal provided by the telephone interface unit of the telephone 32.

The FIR block 16 consolidates the circuit functionality of a VLSI device to reduce production cost in the subscriber unit by eliminating many separate medium scale integration portions.

Referring to Figure 2, the FIR chip 16 includes a branching (fanout) buffer 33, an internal decoding module 34, an RX sample buffer 35, control and status registers 36, an external address decoding module 37, a watchdog timer 38, an RX timing controller 39, a TX timing module 40, a TX FIR filter 42, a codec timing module 44, and a ring control module 45.

The FIR chip 16 provides 45 millisecond frame marker generation, 11.25 millisecond slot marker generation, 16 KHx symbol clock generation, timing control circuits, RX sample caching, TX symbol caching, 8 KHz codec time management generation, processor interface decoding, processor interface decoding, The FIR chip 16 buffers two 5-bit

TX symbols with an 8 KHz rate. The FIR chip 16 converts and filters the TX symbols into I and Q data symbols, with each such symbol equal to 10 bits at a rate equal to 160 KHz. The I and Q data are captured and output to the DIF chip 17 at a rate equal to 320 KHz. The FIR chip 16 also buffers RX data samples at a 64 KHz rate; and four RX data samples are read by processor chip 12 at a 16 KHz rate. Time control clocks and signals are generated by the FIR chip 16 from an incoming 3.2 MHz master clock signal. Processor chip 12 is synchronized to these data rates by hatch and symbol interrupt generated by FIR chip 16. The CODEK and processor's 8 KHz timing control and KODEK clock are generated by FIR chip 16 and synchronized to the time of incoming RX samples. The FIR chip 16 also generates control and timing signals for controlling the shape and timing of the ring voltage provided by the ring circuit 21. The watchdog timer module 38 provides a reset signal in the event that the processor chip 12 does not execute instructions properly.

The branch buffer 33 buffers a 3.2 MHz master clock signal received on line 23a from DIF chip 17, an advanced 3.2 MHz clock signal received on line 23b from DIF chip 17, and a reset signal received on line 51 from watchdog timer. 38. Unless otherwise indicated, all timing within the FIR chip 16 is derived from the 3.2 MHz clock signal on line 23a. The advanced 3.2 MHz clock signal on line 23b carries the 3.2 MHz clock signal on line 23a with a cycle of a 21.76 MHz reference signal present within the DIF chip 17. The 3.2 MHz clock signal is derived from the 21.76 MHz reference in the DIF chip 17 and minimum pulse width is therefore 276 nanoseconds. The advanced 3.2 MHz clock signal from line 23b is provided from buffer 33 via internal line 47 to TX FIR filter 42, and codec timing module 44. TX FIR filter 42 is partially realized by a ROM memory, which is pseudo-static and requires its preparation input to be disabled by the advanced 3.2 MHz clock signal on line 47 between successive accesses.

The HW reset signal on line 51 resets all internal circuits in the FIR chip 16 and provides a hardware reset to the modules of Figure 1.

The internal clocks are either cached versions of the 3.2 MHz main clock signal received on line 23a or divisions of this clock.

The internal address decoding module 34 allows the processor chip 12 to access the internal functions of the FIR chip 16 for the purpose of controlling such functions and determining their status. The internal address decoding module 34 receives processor addresses and processor strokes on bus 25. The internal address decoding module 34 provides output signals on item bus 48.

The output signals on bus 48 from the internal address decoding module 34 include a read ready signal to the RX sample buffer 35, a control write signal and status read signals to the control and status registers 36, a write signal to the TX FIR filter 42, , and control signals for the TX FIR filter module 42 and RX sample buffer are a 35 and an AM strobe signal, which causes the RX timing control module 39 to reset closing time control. Only one of the respective or beep signals on bus 48 from the internal address decoding module 34 is active at any time.

The RX sample buffer 35 receives four samples for each RX symbol time from the A / D converter 19 via line 27a at a 64 KHz rate, buffers up to two data symbols, which are eight samples in total, and then sends such data samples to the processor board 12 via the processor bus 25. RX sample buffer 35 is implemented in a dual-call (dual-page) RAM. The RX sample buffer 35 receives a read-ready signal on internal bus 48 from the internal address decoding module 34 and a write strobe signal on internal line 49 from the RX timing module 39.

The control and status registers 36 allow the processor chip 12 to control the internal functions of the FIR chip 16 and allow the processor chip 12 to read the status of the TX FIR filter 42 and the RX sample buffer 35, and other internal signals. The control signals are provided by the processor chip 12 via the processor bus 25 and the status indications are derived from various internal modules of the FIR chip 16. The status indications are delivered to the processor chip 12 via the processor bus 25. The status indicators are RX overflow, RX overflow, TX underflow, TX overflow, start-of-frame, RX hatch start, TX symbol clock, RX symbol clock and TX FIR filter overflow.

The control signals, which are provided by the control registers 36 to the internal circuits via the internal bus 48, include the following: TX provisioning, modulation level, caller preparation, software reset, three state, and watchdog strobe.

The TX enable signal indicates the beginning of a TX slot based on the TX delay established in the TX Timing Module 40.

The modulation level signal is supplied to the RX timing module 39 and determines whether a closing length is 180 or 360 symbols.

The software reset signal allows the processor chip 12 to reset internal functions within the FIR chip 16.

The tri-state signal allows the processor chip 12 to disable the outputs of a FIR chip 16.

The ringer enable signal allows the processor chip 12 to turn the ringer circuit 21 on and off. This signal provides a two-second and four-second cadence (clocking) for the ring signal.

The watchdog strobe allows the processor chip 12 to reset the watchdog timer module to prevent a hardware reset from occurring.

Processor chip 12 receives an RX clock interrupt (RXCLKINT) signal from RX timing module 39 via line 26c when data has been entered into the first four storage locations of dual call RAM in RX sample buffer 35. Processor chip 12 reads on the RX samples from the first four storage locations in double-call RAM via processor bus 25. At this point, samples are written into the next four storage locations in dual-call RAM at a 64 KHz rate. 16 The KHz event is a derivation of the 64 KHz event, which keeps the read and write events synchronized. This ensures that the read and write operations do not occur simultaneously in any memory location and also ensures adequate response time from the processor chip.

A TX symbol buffer in the TX FIR filter 42 receives TX symbols from the processor chip 12 via the processor bus 25 and buffers two TX symbols. Processor chip 12 is interrupted every other TX symbol time to enter two additional symbols into the TX symbol buffer.

The TX symbol buffer in TX FIR filter 42 receives a write signal via the internal bus 48 from the internal address decoding module 34.

After each TX clock interrupt (TXCLKINT) signal at 8 KHz on line 26a, processor chip 12 prints two 5-bit TX symbols. The data is in a DPSK gray code format. The TX symbol buffer outputs a symbol every 16 KHz for processing using the TX-FIR filter 42. This data is double-buffered due to an asynchrony between the FIR chip 16 and the processor chip 12. The last data value is repeated until new data is written. Zero data can be repeated in this way. The TX symbol buffer is deleted during a backflash.

During training, a fixed sequence of symbols is sent to FIR chip 16 by processor chip 12. FIR chip 16 performs FIR filtering on these symbols and outputs I, Q pairs to DIF chip 17.

The radio 20 returns data in loop to the A / D converter 19. The samples are read by the processor chip 12 such as in the direct-coupled mode and the coefficients of the processor RX filter realized in the processor chip are adjusted. The only time management critical for training is generated by the RX and TX time control modules 39, 40.

The RX timing module 39 generates all reference clocks and strobes for processing the RX symbols. The timing is adjusted by the processor chip 12 so that processing is synchronized to the RX samples received via line 27a from the base station. The RX timing module 39 includes an RX clock fraction timing circuit and an RX slot timing circuit. The purpose of these two circuits is to synchronize the modem's reception time control within the processor chip 12 to the RX samples received on line 27a from the base station, and via the A / D converter 19, and also regulate the TX timing module and the codec timing module 44.

The RX timing module 39 is clocked at a 3.2 MHz rate and receives the following control signal inputs from the processor chip 12 via the processor bus 25: an AM strobe signal, an RX slot clock write signal, and an RX bit tracking signal.

Multiple outputs are generated by the RX timing module 39. A 64 KHz write strobe is provided on line 49 to control write to the RX sample buffer 35. A 64 KHz A / DSYNC strobe signal is provided on line 27b to the A / D converter 19 to synchronize its operation. . An 8 KHz strobe signal is also provided to codec timing module 44 via line 52. A 16 KHz RX clock interrupt (RXCLKLINT) signal on line 26c and the RX start-off shutdown (RXSOSINT) signal on line 26b are output to processor chip 12. A pre-RX slot time control strobe is provided on line 54 to control TX timing module 40.

The fraction time control circuit in RX timing module 39 is set by processor chip 12 to generate the RX start of the close interrupt signal on line 26b. Processor chip 12 determines the storage location of an AM (strobe signal) transmitted by the base station during retrieval. When the processor chip 12 detects the AM strobe signal, the closing time control circuit in RX timing module 39 is reset by a reset signal from the processor chip 12. This aligns the frame and hatch markers of the AM strobe signal. The frame marker is a 62.5 psec pulse that occurs every 45 milliseconds. The closing cursor is a 62.5-second pulse that is repeated every 11.25 milliseconds, or 22.5 milliseconds when in QPSK mode.

The incoming RX symbols are demodulated by the processor chip 12 and timing is further adjusted if necessary. To adjust the 16 KHz RX symbol clock, the processor chip forces the fraction time control (bit tracking) circuit to shorten or extend the 64 KHz strobe with up to fifty 3.2 MHz cycles.

The processor chip 12 exceeds the ratio of the RX symbols to the frame control and makes adjustments to the 16 KHz RX clock associated therewith. When the RX clock is adjusted, the hatch and the frame markers also change because they are a derivation from the RX clock.

In order to keep the number of pulse code modulated (PCM) samples delivered to and from said SLIC and codec circuit 11 synchronized to the frame time control, RX timing module 39 controls codec timing module 44.

The TX timing module 40 includes a TX delay circuit and a TX control time control circuit. These circuits generate a TX clock interrupt (TXCLKINT) signal which is delivered to the processor chip 12 via line 26a. The TX Timer Module 40 is synchronized to the RX Timer Module 39 by the pre-RX Clock Timer, which is delivered to the TX Timer Module by the RX Timer Module 39 on line 54 and is used to reset the TX delay circuit, which in turn generates the TX slot marker. TX clock timing is based on the internal 3.5 MHz clock.

Processor chip 12 also controls TX delay and TX time control circuits by providing TX data write control signals over processor bus 25.

The TX timing module 40 provides a T / R control signal on line 30 to the radio 20. This signal determines whether the radio is transmitting or receiving data.

The TX Time Management Module 40 also controls TX symbol shifting, ROM addressing, accumulation time management, and I, Q product storage for output to the DIF chip 17.

The TX timing module 40 provides control signals on line 56 to keep the TX FIR filter 42 synchronized to the TX symbol and the closing time control. Such synchronization is performed according to the TX latch time control cursor. After a reset, the TX timing module 40 actively activates control signals on line 56 as soon as a TX hatch begins.

The TX FIR filter 42 module includes a ROM store, which implements an FIR filter by providing I and Q data products in response to the ROM storage being addressed for lookup using a combination of TX symbols received from the processor chip 12 via the processor bus 25 and the sine and cosine coefficient counts provided by a counter within the TX FIR filter module 42. TX FIR filter 42 accumulates six sequential I and Q data products and stores output for output to DIF chip 17 via line 24a.

The minimum frequency needed for operation of the TX FIR filter 42 is determined by the symbol rate (16 KHz) times the number of I and Q samples (2) times the number of coefficients (10) times the number of losses (6) = 1.92 MHz. The 3.2 MHz main clock meets this minimum frequency requirement. Waiting periods are added to compensate for the faster execution time.

The TX timing module 40 is clocked at a 3.2 MHz clock rate, which defines a state period. Due to this clock rate being greater than the desired minimum of 1.92 MHz, the TX FIR filter generates 42 signals for the first six out of ten state periods.

Each new TX symbol must be loaded into a scholarly buffer in TX FIR filter 42 at a rate equal to 16 KHz. The new TX symbol and the preceding TX symbols are stored in the circular buffer. The oldest TX symbol is dropped when a new TX symbol is moved. The output of the TX FIR filter 42 is 320 KHz. From each TX symbol, 10 I data values ​​are generated and ten Q data values ​​are generated. Table 1 below shows how I, Q, and null information can be derived from each 5-blt value.

<td>BIT 1</td><td>BIT</td><td> 2</td><td>BIT 3</td><td>BIT 4 BIT 5</td>

<td>I&amp;Q LSB</td><td>I &amp;</td><td>Q</td><td>In MSB</td><td>Q MSB NULL</td>

<td></td><td></td><td></td><td>TABLE 1</td><td></td>

<td>The data i</td><td>it</td><td>circular</td><td>buffer</td><td>rotated every 6 out of 10</td>

<td>conditions.</td><td>a</td><td>new TX-</td><td>symbol and</td><td>the previous five TX-</td>

symbols occur in the circular buffer during twenty of these ten state periods. The coefficient portion of the ROM address is also increased every six out of ten state periods. An accumulator in the TX FIR filter 42 adds the results of each I-data product supplied from the ROM memory for each of the six state periods. Therefore, the accumulator register is deleted for the first addition, and each successive addition result is clocked into a feedback register in the accumulator so that the newly created product can be added. As soon as six additions occur, the result is clocked into the output slider. The same process occurs for the same coefficients and Q data products provided from said ROM for each TX symbol.

The ROM address lines allow sixty COS coefficients and sixty SIN coefficient lookups for four possible 1.0 data indexes. This requires seven address lines for coefficients and two address lines for I, Q data. The output from the FIR filter requires 10 bits. Two additional bits are required to maintain the accuracy of the fraction in the lookup value. This makes the ROM size equal to 412 x 12. Said MSB for the I, Q data index is passed around a ROM memory to a complementary circuit of a 1 which forces the output of said ROM memory to be inverted or noninverted.

If the symbol addressing of said ROM is a null symbol, the null bit controls four of the seven coefficient lines. Since seven address lines are used for coefficient lookups, this provides 128 storage locations. Only 120 coefficients are needed. This leaves 8 unused storage locations. Zero values ​​are stored in these storage locations so that zero information can easily be output from the ROM storage.

A 2's complement function is realized by using a 1's complement and inserting a logical 1 into the subsequent adder. The output from the adder is wrapped around the input of the adder for successive additions or output through a MUX to an output shift register. The output is rounded using only the ten upper bits.

The circular buffer outputs for the TX FIR filter are set to zero after a reset. This allows null information and is processed until new TX symbol values ​​are loaded. Idata is first processed followed by Q data.

The TX clock interrupt signal occurs only during a TX slot. The processor does not know when a TX hatch will start or end, except to respond to this interrupt. The signal has an active low duration equal to a 3.2 MHz clock cycle to ensure that the interrupt is not active as soon as it has been operated. The TX clock interrupt occurs every other symbol time (16 KHz / 2).

The RX clock interrupt occurs for a full frame. Processor chip 12 washes out this interrupt by using the RX hatch marker as a mask. The RX clock interrupt has an active low duration equal to a 3.2 MHz clock cycle.

The RX start of hatch interrupt occurs every 11.25 milliseconds, and has an active low duration equal to a 3.2 MHz clock cycle.

Each interrupt signal is forced to an inactive high state when reset.

The codec timing module 44 generates timing controls and sends the necessary clock signal via lines 29 to the SLIC and codec circuit 11 to cause 8 data blades to be transmitted between said codec and processor at an 8 KHz rate. Codec 11 receives and transmits 8 data bits every 8 KHz. The codec timing module 44 sends a codec clock signal on line 29a and a codec synchronization signal on line 29b. The code clock signal on line 29a is generated at a rate equal to 1.6 MHz by dividing the advanced 3.2 MHz clock by two. An 8 KHz pulse of a 3.2 MHz period is received from the RX timing circuit and clocked to occur during a 1.6 MHz period, thus guaranteed to occur with the rising edges of the 1.6 MHz clock. With these two signals, PCM data is transferred between codec 11 and processor chip 12. This allows subscriber PCM data to be synchronized to the base station PCM data.

The ring control module 45 responds to a ring preparation control signal originating in the processor chip 12 and supplied from the control and status register 36 on internal bus 48 by generating a 20 Hz square wave signal on line 31a and two 80 KHz phase control signals, PHASEA on line 31b and PHASE and transmitting these signals to the ringer circuit 21. The 20 Hz square wave signal on line 31a controls the polarity of the ringer voltage supplied by the ringer circuit to the telephone interface circuit 10. 80 The KHz phase signals on lines 31b and 31c control the pulse width modulated power source in the ringer circuit 21.

A reset or SLIC ring command signal on line 29c from the SLIC portion of the SLIC and codec 11 cancels or overrides these signals on lines 31a, 31b and 31c after the ring enable signal originating in the processor chip 12 turns it on. This ensures that the ringer is off if a reset occurs or the telephone handset is taken off the fork.

Since the ringer circuit 21 generates a high voltage and consumes a great deal of power, this voltage is not generated except when required by the processor chip 12.

The external address decoding module 37 generates chip selection on the processor bus 25 which is used by the processor chip 12 to access the DIF chip 17, the UART hardware, and the slow memory EPROM memory 14 in separate distinct address segments. Processor chip 12 provides 8 MSB address lines, data rooms and program room signals. These are decoded to generate appropriate chip choices.

The watchdog timer module 38 generates a 50 millisecond hardware reset pulse on line 51 which resets all FIR chip 16 modules and all subscriber unit modules in Figure 1. The watchdog timer 38 generates a pulse if it is not reset within a 512 millisecond period of the watchdog strobe signal 48 of the control and status registers 36.

DIF chip 17 is adapted to processor chip 12 by processor bus 25, to FIR chip 16 by lines 23 and 24, to DAC 18 by line 71, and to an oscillator in radio 20 by line 72.

The oscillator in the radio 20 provides a 21.75 MHz main clock signal on line 71 to the DIF chip 17.

Referring to FIG. 3, DIF chip 17 includes a clock generator 60, a processor decoding module 61, a FIR chip interface module 62, an interpolator 63, a control register 64, the tuning register 65, a DDS phase accumulator 66, a DDS SIN and COS generation module 67, a modulator 68 and a noise generator 69. In combination, the DDS phase accumulator 66 and DDS SIN, the COS generator 67 form a direct digital synthesizer (DDS) for digitally synthesizing a digital intermediate frequency signal.

DIF chip 17 is an ASIC chip, which is mapped as processor data memory.

The DIF chip 17 operates in one of two operating modes, a modulated carrier generation mode and a pure carrier wave mode. In the modulated carrier generation mode, baseband data is input into the I, Q range and this data is used to modulate the pure carrier wave generated by the DDS function in the DIF chip 17. In the pure carrier generation mode, baseband data inputs are ignored and a second modulated carrier wave from to said DAC 18.

The clock generator 60 generates all timing and clocks within the DIF chip 17 and also generates the 3.2 MHz clock signal and the advanced 3.2 MHz clock signal delivered to the FIR chip 16 on lines 23a and 23b. The two primary timing signals used within the DIF chip 17 are a 21.76 MHz clock signal and a 2.56 MHz interpolation port signal.

The 3.2 MHz clock is used internally to displace I and Q data on line 24a from the FIR chip 16 into the FIR interface module 62.

The clock generator 60 buffers the 21.76 MHz clock received on line 72 from the oscillator in the radio 20 and delivers a buffered 21.76 clock signal on line 71a. Such buffering is undertaken to provide sufficient drive power for internal functions and to minimize clock bias. The buffered 21.76 MHz clock also provides a clock for said DAC 18 and other external circuits.

The clock generator 60 provides the 3.2 MHz clock signal by dividing the 21.76 MHz clock by 6 and by 8 in the following sequence: 6-8-6-8-6 which results in an average divider equal to 6.8 (21, 76 / 6.8 = 3.2). The effect of this per cycle variation is a minimum period equal to 276 ns and a maximum period equal to 368 ns. An advanced version of the 3.2 MHz clock signal is also generated as the advanced 3.2 MHz clock signal on line 23b. Both clocks are identical except that the ROM select signal on line 23b carries the 3.2 MHz clock signal on line 23a with a 21.76 MHz clock cycle.

The clock generator 60 delivers the 2.56 MHz gate control signal on internal line 74 by dividing the 21.76 MHz clock by 8 and 9 in a uniform sequence (8-9-8-9 -...), resulting in an average divider equal to 8.5 (21.76 / 8.5 = 2.56 MHz). This signal is used by interpolator 63 and modulator 68.

The processor decoding module 61 allows the processor to control all internal functions of the DIF chip 17. The processor decoding module 71 decodes processor addresses and processor strobes received from data compartments on the processor bus 25 to provide internal write strobes, which are delivered on internal bus 76 to the control register 64 and the tuning registers 65 12 capable of writing control and configuration data. Only one output from the processor decoding module 61 is active at any given time. The processor addresses determine which output is generated. If a function within the address space of the DIF chip 17 is selected, a chip selection signal on line 24c from the FIR chip 16 becomes active.

The FIR interface module 62 receives I and Q samples from the FIR chip 16 on line 24a in a serial format and converts these into 10-bit parallel format in which they are delivered to the interpolator module on line 77. The I, Q port signal on line 24b from the FIR chip 16 is used to separate I data from Q data. The FIR interface module 62 also subtracts the previous I and Q samples from existing samples to form Δ I and Δ Qsamples which are then shifted to the right 4 places (* 16) to form the correct increment for the interpolator module on line 78. Since the FIR interface module 62 provides data to the interpolator 63, a synchronization signal is sent by the FIR interface module 62 to the clock generator 60 to synchronize the 2.56 MHz port control pulse supplied on line 74.

Interpolator 63 accumulates Δ I, Q at a 160KHz x 16 = 2.56 MHz rate and delivers interpolated I and Q samples to modulator 68 on lines 80 and 81. Interpolator 63 performs a xl6 linear interpolation to reduce 160 KHz sampling annoyances. (spurs) present in the baseband data received from the FIR chip 16.

Interpolator 63 successively accumulates the Δ I and Δ Q samples to generate an output at a 2.56 MHz rate. At the end of an accumulation cycle (16 repetitions), the output of the interpolator should be equal to the existing I and Q samples. This is critical as the next accumulation cycle starts its cycle with the existing data. To ensure that the data is correct, during the last accumulation cycle, the existing I and Q data are fed directly to the interpolator output register instead of the output from the adder (which should have the same data).

The control registers 64 are used to control and configure the DIF chip 17 and to select the operation modes. All of the control registers 64 are loaded by the processor chip 12 via the processor bus 25.

There are three control registers 64. The first control register registers a CW mode signal, an AUTO tuning HL signal, and an AUTO tuning LH signal. The second control register registers a character selection signal, an output clock phase selection signal, an interpolator enable signal, a serial port clock selection signal, a serial / parallel mode selection signal, and a quadrature enable signal. The control functions associated with these signals are described later at the conclusion of the description of the other modules 1 DIF chip 17.

The third control register clarifies and specifies the coefficients for the noise attenuator 69.

There are three 8-bit poll registers 65 for storing 24 bits of phase increment data to specify the frequency of said DDS. This gives a 24-bit reconciliation word that allows a frequency resolution equal (sampling rate) / 2²⁴ = 21.76MHz / 2²⁴ = 1.297 Hz. The output frequency of said DDS is equal to the resolution multiplied by the 24-bit tuning word.

The polling registers 65 are loaded by the processor chip 12 via the processor bus 25. The polling word is double buffered by the polling registers 65, so that the processor chip 12 can write data to these registers freely without affecting the existing DDS operation.

The polling word is loaded from the buffer polling registers into the output polling registers when a polling command is issued. The tuning command is synchronized to 21.76 MHz clock to provide a synchronous transition.

The DDS phase accumulator 66 performs a modulo 2³^ accumulation of the phase increment provided on line 82 by the tuning registers 65. The output of the phase accumulator 66 represents a digitized phase value supplied on line 83 to the DDS SIN and COS generator 67. The DDS SIN and the COS generator 67 generate a sine function. A DDS works on the principle that a digitized waveform can be generated by accumulating phase changes at a higher rate.

The polling word, which will be different for different subscriber units, represents a phase change to phase accumulator 66. The output of accumulator 66 may range from 0 to 2.³^ -L. This range represents a 360 degree phase change. Although accumulator 66 operates in standard binary, this digitized phase representation can be input to a waveform generator to produce any arbitrary waveform. In DIF chip 17, DDS SIN and COS generator provide 67 SIN and COS functions on lines 84 and 85.

The period of the waveform function is based on the time required to summate the upper limit accumulators (2³^ -L). This means that if a large-phase increment is provided, then this limit will be reached earlier. Conversely, if a small increment is given, a longer time is required. The phase accumulator 66 performs a single summation of the input phase increment and can be represented by the following equation:

Φτ = ΣΥ₌₁ Φ1 ^ (similar to 1}

Where n is the number of repetitions and φ-j _nIs simply the data provided on line 82 from polling rules 65.

In the embodiment of the DIF chip 17 described herein, the value φγ is limited by the accumulator length to be a maximum of 2²⁴. Therefore, the existing phase can be described as:

φ-t = (Φ-tl + Φΐη ^ πιοΰυΐθ 2²⁴ (like 2}

Since the accumulation clock is fixed to be the main input clock of 21.76 MHz, this results in a complete cycle which takes 2²⁴/ Φ- ^_η^ repetitions at a per repetition period equal to 1 / 21.76 MHz. Thus, the entire cycle takes the following amount of time:

2²⁴

21.76 MHz = Φΐη

As this period represents a 360 degree cycle, reciprocal values ​​of this expression represent a frequency. Therefore, the DDS frequency is

21.76MHz * φ_{1η1 £}^fDDS ------------- (similar to 3} ₂24

In the DDS SIN, COS Generation Module 67, the SIN and COS waveforms are generated so that a complicated mix can be performed in the modulator. Each is generated by two lookup tables that represent a rough and fine estimate of the waveform. The two values ​​are added to form compound 12-blt character 2's complement SI and COS data output signals on lines 84 and 85. Lookup table Implemented in the ROM stores that are addressed by the fourteen most significant bits of the signal on line 83 from the DDS phase accumulator 66.

It is desirable to have as much phase and amplitude resolution as is convenient. In the DIF chip 17 configuration, 14 bits of phase input and 12 bits of amplitude data output are included in the waveform generation section. If a brutal force solution is taken to generate this data, then very large tables will be needed to generate all possible phases and amplitudes (eg 16K words x 12 bits each). To minimize the table size, the DIF chip 17 makes use of quadrant symmetry and trigonometric decomposition of the output data.

Since SIN and COS waveforms have quadrant symmetry, the two most significant bits in the phase data are used to mirror the one quadrant data around the X and Y axis. For the SIN function, the amplitude of the wave in the π to 2n interval is exactly the negative of the amplitude in the 0 to π interval. For the COS function, the amplitude of the wave in / 2 to 3n / 2 interval is exactly the negative of the amplitude in the 3n / 2 to n / 2 interval. The two MSBs in the phase accumulator indicate the quadrant (00-&gt;, 01-&gt; 2, 10-&gt; 3, 11-&gt; 4). For the SIN function, the MSB of phase data is used to put out the positive data generated for the first two quadrants. For the COS function, an XOR for the two phase data MSBs is used to reverse the effect of the positive data generated for quadrants 1 and 4.

The above technique reduces memory requirements by a factor of 4. This still results in a memory requirement of 4K words x 12 bits. To further reduce the table sizes, a trigonometric decomposition is performed on the angles. The following trigonometric identity is used:

Sin = δΐηίφ- ^ + ¢ 3) = 81ηφιβθ8φ2 + 81ηφ2θοβφ ^ (similar to 4}

Adding ¢ 2 &lt;&lt; Φι leads to the complete approximation as follows:

sin © = ειηφι + β1ηφ2θοεφ ^ {similar.5}

It is not necessary to use all bits of φ ^ while calculating the second expression of the equation, since φ ^ is a subset of φ ^.

To generate the COS function, the same approximation can be used as cos © = sin (© + n / 2) (similar to 6}

This results in modification of the φ ^ &amp; φ ^ variables while calculating the COS function. The data stored in the COS ROM bearings will incorporate this angular modification so that no changes to the phase data are needed.

The modulator 68 mixes the interpolated I and Q samples on lines 80 and 81 with the digital intermediate frequency signal represented by the complex SIN and COS function data on lines 84 and 85 to produce a modulated digital intermediate frequency signal on line 87.

The interpolated I, Q samples and DDS output are digitally mixed using two 10 x 12 multipliers. The output from the mixing process is then summed by means of a 12 bit adder to form a modulated carrier wave. It is possible to change the operation of modulator 68 by forcing the I input to only zeros and the Q input to only ones. The effect of this is that one multiplier will output only zeros and the other will output the signal from only DDS SIN, the COS generator 67. The sum of these two signals gives an unmodulated digital mid-frequency signal.

Modulator 68 generates a modulated digital medium frequency signal on line 87 according to the following equation:

f (t) = I * COS (4&gt; (t)) + Q. SIN (0 (t)) (similar to 7}

The 12-bit output from DDS SIN and COS generator 67 is multiplied by 10-bit interpolated I and Q samples from interpolator 63 to generate two 12-bit products. The products are then added (combined) to generate a 12-bit modulated output on line 87.

Since both the I multiplier and the Q multiplier generate 12-bit products, it is possible that an overflow could occur when their outputs are combined. Therefore, it is necessary to ensure that the size of the vector generated by I and Q never exceeds 1 (assuming that | l |, | Q | is fraction number &lt;1). If this is not ensured, then an overflow of the modulator adder is possible.

Noise canceller 69 provides a filtered modulated or unmodulated digital intermediate frequency signal on line 71b to DAC 18. Noise canceller 69 is designed to reduce the amount of noise power in the output spectrum caused by amplitude quantization errors.

The noise filter 69 is based on the fact that the quantization noise is a normal arbitrary process and the power spectral density in the process is flat over the frequency band. The desired output signal is superimposed on top of this quantization noise floor. The noise forming device is a single multi-output final pulse response (FIR) filter. The filter creates a zero which reduces the quantization noise effect in a certain part of the frequency band. When the desired signal is applied to the filtered noise spectrum, the effective SQNR increases.

The FIR filter transfer function is off

H (z) = 1 + bz^-l - z "² (Lign.8)

A two-adder stage creates a second bias or withdrawal value for the range from + 1.75 to -1.75 (in binary weights of 0, 0.25, 0.50, 1.0) which will move the zero in the filter over the output frequency band so that it can be positioned as close as possible to the desired output frequency for maximum SQNR performance.

The zero frequency can be calculated by solving for the roots of the above equation in the z-plane. The roots are a complex conjugate pair that depends on the unit circle. The zero frequency is given by the ratio:

Null f null ⁼ 'sampling (similar to 9}

360 ° where Θ is the angle of the root in the upper half plane. The conjugated root will give a zero reflection around the Nyquist frequency.

Table 2 lists the zero frequencies generated by the binary weighted second output. Let b3, b2 and bl correspond to weights 1.0, 0.5, 0.25, a + symbol means that the outlet or tap is equal to its weight, a - symbol means that the tap or tap is equal to the negative of its weight , and Ό * means that the taping has no weight. Some of the zero frequencies are similar to those of other combinations, simply because the possible combinations sometimes overlap (eg 1.0 + 0.5 - 0.25 = 1.0 + 0.0 +

0.25). fgample^is

<td></td><td>b3</td><td>b2</td><td>bl</td><td>f (zero)</td><td>f (aka</td>

<td></td><td> 0</td><td> 0</td><td> 0</td><td> 0,250</td><td> 0,750</td>

<td></td><td> 0</td><td> 0</td><td> -</td><td> 0,269</td><td> 0,731</td>

<td> 5</td><td> 0</td><td> 0</td><td> +</td><td> 0,230</td><td> 0,770</td>

<td></td><td> 0</td><td> +</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td></td><td> 0</td><td> +</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td></td><td> 0</td><td> +</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td></td><td> 0</td><td> -</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> 10</td><td> 0</td><td> -</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td></td><td> 0</td><td> -</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td></td><td> +</td><td> 0</td><td> 0</td><td> 0,167</td><td> 0,833</td>

<td></td><td> +</td><td> 0</td><td> -</td><td> 0,188</td><td> 0,812</td>

<td></td><td> +</td><td> 0</td><td> +</td><td> 0,143</td><td> 0,857</td>

<td> 15</td><td> +</td><td> +</td><td> 0</td><td> 0,115</td><td> 0,885</td>

<td></td><td> +</td><td> +</td><td> +</td><td> 0,080</td><td> 0,420</td>

<td></td><td> +</td><td> +</td><td> -</td><td> 0,143</td><td> 0,857</td>

<td></td><td> +</td><td> -</td><td> 0</td><td> 0,210</td><td> 0,790</td>

<td></td><td> +</td><td> -</td><td> +</td><td> 0,188</td><td> 0,812</td>

<td> 20</td><td> +</td><td> -</td><td> -</td><td> 0,230</td><td> 0,770</td>

<td></td><td> -</td><td> 0</td><td> 0</td><td> 0,333</td><td> 0,667</td>

<td></td><td> -</td><td> 0</td><td> -</td><td> 0,357</td><td> 0,643</td>

<td></td><td> -</td><td> 0</td><td> +</td><td> 0,312</td><td> 0,688</td>

<td></td><td> -</td><td> +</td><td> 0</td><td> 0,290</td><td> 0,710</td>

<td> 25</td><td> -</td><td> +</td><td> +</td><td> 0,269</td><td> 0,731</td>

<td></td><td> -</td><td> +</td><td> -</td><td> 0,312</td><td> 0,688</td>

<td></td><td> -</td><td> -</td><td> 0</td><td> 0,385</td><td> 0,615</td>

<td></td><td> -</td><td> -</td><td> +</td><td> 0,357</td><td> 0,643</td>

<td></td><td> -</td><td> -</td><td> -</td><td> 0,420</td><td> 0,580</td>

TABLE 2

All timing is derived from the 21.76 MHz clock signal to line

71a.

The functions associated with the signals in control register 64 are now described. When the CW mode signal is set, the I input of the respective multiplier in the modulator 68 is forced to only zeros, and the corresponding Q input is forced to only ones. The net effect is that an unmodulated carrier will be generated. This function is double cached and loaded data will not become active until a poll command is issued.

The interpolator preparation signal prepares the xl6 interpolator on the I, Q samples. If the interpolator enable signal is not set, the I, Q data is input directly to the multiplier.

External memory required for operation of the processor chip 12 is provided by a fast memory 13 and a slow memory 14. The fast memory 13 is accessed by an address decoder 15. The fast memory 13 is a buffer memory realized in a RAM having zero-waiting states. The slow memory 14 is a large-space memory realized in an EPROM, which has two waiting states. The slow memory 14 is coupled to the processor chip 12 for storing processing codes used by the processor chip 12 when said codes are not required to be operated with zero-waiting states, and the fast memory is coupled to the processor chip 12 for temporarily storing processing codes as used by the processor chip 12 when said. codes are operated with zero-wait states. When the procedures must be run with zero waiting states, the code can be uploaded from the slow memory 14 to the fast memory 15 and run from there. Such procedures include interrupt service routines, symbol demodulation, RCC retrieval, BPSK demodulation, and voice and data processing.

Processor chip 12 includes a single model TMS320C25 digital signal processor, which performs four main tasks, a subscriber control task (SCT) 91, channel control task (CCT) 92, a signal processing task (SPT) 93, and a modem processing task (MPT) 94, as shown in Figure 4. four tasks are controlled by a supervisor module 95. The aforementioned SCT applies to the telephone interface and the high-level call processing. The CCT controls the modem and RELP operation and timing, and performs power level and TX timing adjustments 1 according to base station requirements. SPT performs the RELP, echo cancellation and tone generation functions. The supervisor calls these four tasks sequentially and communicates with these five via control words.

SCT 91 provides the high-level control function within the subscriber unit and has three basic operating modes: free, voice and abortion.

SCT enters the idle mode after power supply and remains in that state until the current voice connection is made. While in idle mode, SCT monitors the subscriber telephone interface for activity and responds to the base station requirements received over the radio control channel (RCC).

The primary function of SCT is to guide the subscriber unit through the setup and demolition of the voice connections on a radio channel. Before the device can set up any call needs²⁰ It does, however, find the correct base station. The SCT determines which RCC frequency to use and sends the frequency information to said CPT. A description of the initialization of a communication channel between the subscriber unit and the base station is found in U.S. Patent Application No. 25 07 / 070,970 filed July 8, 1987.

Once the subscriber unit has achieved RCC synchronization, it can establish a call by exchanging messages over said RCC with the base station, and by monitoring and setting the machine³⁰ commodity signals on the telephone interface. The following walkthrough will briefly describe the events that occur during call setup.

Normal call setup for call origination begins with the 55 subscriber taking the handset off the fork to initiate a service request. The SCT sends a call request message to the base station. The SCT receives a call link message. SCT signals to CCT to attempt synchronization on the voice channel assigned through the call switch message. CCT achieves synchronization on the call channel. The subscriber receives a dial tone from the main switchboard. Call setup is complete. The main switchboard provides the remaining call termination support.

Normal call setup for call termination takes place as follows: Said SCT receives a call message from the base station. The SCT replies with a call reception. The SCT receives a call connection message. Said SCT signals to said CCT to attempt to synchronize on the voice channel assigned via the call connection message. The CCT achieves synchronization on the voice channel. Said SCT starts the ring generator to add ringing to the local loop. The subscriber takes the handset off the fork. The ringing is stopped. The voice connection is complete.

SCT implements the call setup and demolition operations as a final state machine.

If a voice channel capture is complete, said SCT switches to the speech mode and performs a very limited set of support functions. SCT processor loading is kept at a minimum at this time to give RELP speech compression, echo cancellation and modem processing algorithms maximum processor availability.

Said SCT enters the abortion mode as a result of an unsuccessful call origination attempt or an unexpected call tear sequence. During the abortion mode, a reorder is sent to the handset. The SCT monitors the subscriber telephone interface for a disconnect (extended fork), at which time the subscriber unit enters the idle mode. Base station claims received over the radio control channel (RCC) are rejected until the disconnection is detected.

Said CCT 92 operates as a connection level channel controller in the baseband software. The CCT has basic conditions: RCC operation, refining, and speech operation.

Upon power supply, said CCT enters the RCC operation mode to search for and then support the RCC channel. The RCC operation includes the following features: AM hole control; monitoring synchronization and modem task status; radio channel timing adjustment; RX RCC message filtering; TX RCC message formatting; monitoring of PCM buffer I / O; and 1ink information processing.

After a voice connection is established, the CCT enters the refining state to fine-tune the modem's fractional timing. Refining includes the following functions: interpretation and response to refining outbreaks, creation and formatting of TX refining outbreaks, transmission of messages to said SCT as appropriate, monitoring modem status, and monitoring PCM buffer I / O.

After refining, said CCT begins voice operation, which includes the following features: password signaling support, dropout retrieval, synchronization and modem status monitoring, and PCM buffer I / O monitoring.

The CCT 92 has three basic operating modes: free, refining and speech. The following is a review of the state transitions involved in CCT operation.

After a reset, the CCT enters the idle state and remains inactive until given channel assignment instructions by this SCT. Said SCT supplies said CCT with a frequency at which to search for the radio control channel (RCC). The CCT then instructs the MPT to synchronize the receiver to the given frequency and to search for an AM hole. Failure to detect an AM hole within a predetermined period of time causes said CCT to request another frequency at which it is to be sought from said SCT. This continues indefinitely until AM-hole detection is successful.

After successful hole detection, the CCT begins to check the received data for the unambiguous word. A small window around the nominal unambiguous word position is scanned as the AM hole detection process can be off-putting with a few symbol times. Once the unique word is located and the CRC error detection word is verified correctly, each accurate receive symbol time control can be determined. The TDM frame markers are then adjusted to the correct alignment and normal RCC support begins. If the unambiguous word cannot be located, the AM hole detection is considered to be false and said CCT requests a new frequency assignment from said SCT.

During the RCC operation, said CCT will filter received RCC messages. The majority of the base station RCC messages are the null pattern and these are discarded after link information is read from the link byte. RCC messages containing real information are forwarded to the SCT for processing. If RCC synchronization is lost, the CCT again requests a new frequency from the SCT. Said SCT will respond with the correct frequency 1 according to the RCC frequency search algorithm.

When SCT initiates a number call, CCT is assigned a voice channel and a time slot. Said CCT brings the subscriber unit active in accordance with this assignment and begins the refining process. During refining, the base station and the subscriber unit send a BPSK signal specially designed for the auxiliary modem in fraction bit time acquisition. The base station CCU transmits the bit-time offset back to the subscriber unit as a two's compliment adjustment value. The CCT maintains a time average of these feedback shifts. Once said CCT determines that the fractional timing value is within a desired tolerance, it adjusts the subscriber unit's transmission time control accordingly. The length of the time average is determined dynamically, depending on the variance of the fractional time samples. After a time management adjustment, the time average is reset and the procedure is taken.

As soon as the base station detects that the subscriber unit is within an acceptable time management tolerance, it finishes the refining process and voice operations begin. The length of the refining process is determined dynamically, depending on how successful the subscriber unit's time management adjustments are. Power and integer symbol time control are also monitored and adjusted as needed during the refining process. If the subscriber fails to find the base station refining outbreak after a period of time, or if the refining process cannot provide acceptable time management, the connection is broken and said CCT returns to the RCC operation.

After successful refinement, the CCT enters the speech operation at the assigned modulation level. The voice operation tasks include managing RELP and MPT operations, establishing voice synchronization and continuous monitoring via voice passwords sent from the base station. Local loop control changes, signaled via the passwords, are reported to the SCT as they occur. Power and fractional timing incremental changes are also determined by the passwords. Sent voice code words are formulated by said CCT based on the local loop control provided by said SCT and the channel link or connection quality reported by the modem. Said CCT returns to said RCC when SCT executes a call drive sequence.

If voice synchronization is lost, said CCT initiates a fade recovery operation. After ten seconds of failure to re-establish a good voice connection, said CCT informs said SCT of the condition and initiates a call drift. This brings the CCT back to the free state.

During a channel test operation, a voice outbreak is replaced with channel test data. When an outbreak has just been received, it is analyzed for bit errors. The bit error count is fed to the base station via the reverse channel burst.

SPT 93 performs all of the digital signal processing (DSP) tasks within the subscriber unit. The various DSP functions are invoked as needed, under the control of the monitoring module 95.

Said SPT includes a RELP module, which is executed from a high speed RAM memory. The RELP module performs RELP speech compression and echo cancellation expansion. The RELP module converts 180 bytes of 64 Kbps PCM voice data to and from 42 bytes of compressed speech data using the RELP algorithm.

Said SPT also includes a signal processing controller (SPC) module, which determines whether tone generation or RELP should be invoked. In the case of RELP, the SPC decides whether to call synthesis or assay routines. The synthesis routine returns a quantum trap count, which is handled by the SPTCTL routine. If tone generation is desired, it decides whether to silence or reorder output.

The SPT is controlled via commands from the SCT and CCT. These commands invoke and control the operation of the various functions within said SPT as they are needed by the subscriber unit. For example, RELP and echo cancellation software are performed only when the subscriber unit is active on a voice call. Voice progress tones are generated when the subscriber unit receiver is off the fork and RELP is not active. The tones include silence and order. Apart from the idle mode, the interrupt service routine that handles the PCM codec operates continuously as a foreground process, filling its circular PCM buffer.

The control and modem functions are performed between analysis and synthesis processing.

The MPT 94 demodulation procedure is divided into two procedures: DEMODA &amp; DEMODB, which allows RELP synthesis to be performed on the RX data in buffer A just after the DEMODA procedure is completed. After DEMODA, all internal RAM variables should be stored in external RAM, then reloaded to internal RAM before DEMODB is performed. This is because RELP uses the internal RAM.

When RXCLK interrupt on line 26e is received by processor chip 12, MPT causes four received RX data samples to be read and then placed in a circular buffer, for processing the demodulation procedure. This allows other tasks to be performed while receiving RX samples.

Said MPT receives the RXCLK interrupt signal on line 26e from the FIR chip 16 every 62.5 psec during the receive slot. The RXCLK interrupt signal is masked by the processor chip firmware during free or transmit slots.

Said MPT receives the TXCLK interrupt signal on line 26f from the FIR chip 16 only during the transmission slot. The TXCLK interrupt signal tells the processor chip 12 to send a new TX symbol to the FIR chip.

Said MPT reads four samples from RX sample buffer 35 in FIR chip 16 during each RXCLK interrupt on line 26e. The aforementioned MPT resets the input and output address counters to the buffer at the start of the reception slot.

Said MPT sends TX symbols to the TX symbol buffer 36 in the FIR chip 16.

Said MPT supplies data to the fractional timing control circuit in RX timing module 39 1 FIR chip 16 which is used to align the RXCLK interrupt signal on line 26e with the base station transmission.

The MPT also synchronizes the DDS frequency to the base station transmit frequency.

Referring to FIG. 5, the MPT includes the following modules: a monitoring module 101, a training module 102, a frequency acquisition module 103, a bit synchronization module 104, a speech modulation module 105, a symbol reception module 106, and a transmitting module 107.

Supervisor module 101 is the MPT task supervisor. It reads the MPT control word (CTRLO) from the RAM memory, and calls other routines according to the control word.

The training module 102 calculates a vector of 28 complex FIR filter coefficients. It is activated in idle mode after a power supply and approx. every three hours. A training transmitter implemented by said MPT is activated in a loop feedback mode to transmit a certain sequence of symbols. This sequence is looped back to a training receiver implemented by said MPT, in normal mode, in advanced and delayed timing modes, and in upper and lower enclosing channels.

The training receiver uses the samples in the input waveform to create a positive determined symmetric matrix A of magnitude 28. Also a 28-word vector V is created from the input samples. The vector C of the coefficients is given by:

C = A^_1V (similar to 10)

The B coefficient spring is then calculated according to the algorithm B = A^-1, where A is given.

The training transmitter is activated in loop feedback mode to transmit five similar pairs of sequences. Each pair consists of the following two sequences:

I sequence: 9 null symbols, i, 22 null symbols.

Q sequence: 9 null symbols, j, 22 null symbols.

can be any symbol, j is a symbol that deviates from i with 90 degrees.

The recipient processing tasks are:

Adjusting said AGC so that the signal peak in normal mode is 50 to 70 $ of maximum. The aforementioned AGC is increased by 23dB for the 4th and 5th modes.

Read and save the input samples. The first 32 word samples are discarded and the next 64 samples are stored for each sequence.

Build matrix A (28.28). The following process is performed in normal mode:

A (I, J) = A (I, J) + ΣΧ (4Ν-Ι) * X (4N-J) (similar to 11}

The addition is for all N satisfying:

0 &lt;= 4N-I &lt;64 &amp; 0 &lt;= 4N-J &lt;64 (like 12}

For the sequenced and delayed sequences, the same process is performed except that the expression due to N = 8 is not added. In the upper and lower adjacent channel channel sequences, the following process is performed:

A (I, J) = A (I, J) + ΣΧ (2Ν-Ι). X (2N-J) (equation 13}

The addition is for all N satisfying:

&lt;0 = 2N-I &lt;64 &amp; 0 &lt;= 2N-J &lt;64 (similar to 14)

<td>Create the vector sequences:</td><td>V (l: 28)</td><td>from</td><td>the samples in it first</td><td>e pair of</td>

<td>Re (V (I)) = sequence.</td><td>X (32-I);</td><td>there</td><td>X is the sampler in it</td><td>the first (I)</td>

<td>Im (V (I)} = sequence.</td><td>X (32-I);</td><td>there</td><td>X is the sampler in it</td><td>the second (Q)</td>

<td colspan="2">Find the coefficient vector</td><td colspan="2">C by solving the equation:</td><td></td>

<td>A x C - V</td><td>= 0 (similar to</td><td> 15}</td><td></td><td></td>

These processing steps are further described in U.S. Pat. 4,644,561 issued February 17, 1987 (Eric Paneth, David N. Critchlow and Moshe Yehushua.

The frequency acquisition module 103 is run when the control channel ²⁰ is received, to synchronize the subscriber unit's RX frequency to the base station's transmit frequency. This is done by adjusting the DDS CW output until the energies of the two sidebands of the received signal are equal. Then, the DDS TX frequencies are adjusted according to the calculated frequency deviation.

If the procedure fails to achieve frequency synchronization, an appropriate error code is placed in the status word.

The bit synchronization module 104 is run when said RCC is received 5 ° and after completing the frequency acquisition. A certain pattern is sent in the first 44 symbols in the RCC transmission from the base station and this is used by this module to calculate the RXCLK deviation from the correct sampling time. This deviation is used to adjust the RXCLK timing.

The voice modulation module 105 is activated to demodulate a voice slot. It resides in the slow EPROM memory and its functions are divided between two procedures DEMODA and DEMODB.

The DEMODA functions include initialization parameters for the symbol receiving module 106, calling the symbol receiving module to process the received symbols for buffer A, and storing the variables in the external RAM memory prior to excitation.

The DEMODB functions include loading the variables from external RAM to internal RAM, calling the symbol reception module to process the received symbols for buffer B, and determining link or connection quality and other information after receiving all symbols in the slot.

The symbol receiving module 106 is uploaded to said RAM memory when said CCT goes to voice mode. It is called by DEMODA or DEMODB to perform the following: (1) read I and Q samples from the circular buffer, (2) FIR filtering of the I&amp;Q samples, (3) read the sent symbols and then put these in a buffer, (4) performing a phase-locked loop to synchronize said DDS to the incoming signal, (5) executing the bit tracking algorithm, (6) AGC calculation, and (7) accumulating data for 1 quality calculation.

The transmit module 107 includes the interrupt service routine for the TXCLK interrupt signal received on line 26e from the FIR chip 16, which occurs once per two symbols during a transmit slot. The functions of the transmit module 107 include: (1) extracting the transmit symbol from the RELP buffer, (2) performing an inverse GRAY coding thereon, (3) adding it to the previous transmitted phase (due to the DPSK transmission), and (4) transmitting this to the TX buffer in the FIR chip 16.

The adaptation of said MPT to the baseband tasks is via control and status words and data buffers in the shared memory. Procedures that require fast execution are uploaded into the buffer storage when needed. These include interrupt service routines, symbol demodulation, RCC retrieval, and BPSK demodulation.

The MPT monitor will not wait for the RXSOS to read and decode the control word, but would do so immediately when called.

The TMS320C25 goes into a power-down mode when the free instruction is executed. To maintain power, the firmware will be in idle mode most of the time, as there is no phone call in progress. After a reset, the monitor will then obtain RCC synchronization, and then go into idle mode until a predetermined interrupt causes a corresponding service routine to be performed. When operated in power-down mode, the TMS320C25 enters a dormant state and requires only a fraction of the power normally needed to power the device. While in a power or power-down mode, all of the internal content of the processor is maintained to allow operations to continue unchanged when the power-down mode is exited. Upon receiving an interrupt, the processor chip 12 temporarily exits the power-down mode and resumes normal operation for a minimum period of one main loop cycle. The power-off mode requirements are checked at the end of the main loop each time to determine whether the subscriber unit should return to the power-down mode.

The door clock is based on the hardware-generated clock time management. When a hatch marker triggers an interruption, the routine increments the clock with a tick. Each clock represents 11.25 ms in time.

The receiving and sending functions of the UART are not interrupt driven, but are controlled by the background software (this controls processor loading and prevents escaped interrupt conditions). The processing code supports the XON / XOFF protocol by cutting off these characters directly and immediately preparing or suspending the UART transmission function as appropriate. The rate of reception and transmission operation is designed to be selective by means of an external DIP switching device. The typical data reception rate is at 9600 baud. A circular buffer is used to control the UART transmission. The background software periodically checks the queue and initiates transmission if it is not empty. It does this by sending bytes to the UART one byte at a time until the queue is empty.

The switch fork is sampled with said TMS320C25 internal timer interrupt routine. To simulate DC signaling, a 1.5 ms sample period is used. This interrupt is set to frame time management at the beginning of each frame. Therefore, its frequency is phase locked to the base station to prevent overflow or overflow of the switch fork buffer. For each interrupt, a bit representing the switch fork detection signal (from said SLIC) is introduced into the 60-bit switch fork sample buffer (SSB). Said SSB is reviewed by said SCT once every 45 ms during normal operation. This interruption is always made clear by the software.