Method of and apparatus for preventing rounding errors during reversed transformation of coefficients of a transform representing a moving image signal

The present invention relates to a method and apparatus for processing a set of transform coefficients representing a moving image signal, in particular for performing an inverse orthogonal transform and for compressing an information signal and for expanding it.

Orthogonal transforms are used in various applications and in various digital signal processing methods. Orthogonal transforms allow signal processing in the frequency domain. Of the orthogonal transformations, Fast Furier Transform (FFT - Fast Fourier Transform) and Discrete Cosine Transformation (DCT - Discrete Cosine Transform) are widely known. Orthogonal transformation allows, for example, to split a signal in the time domain by converting it into frequency components, changing depending on the function used in the orthogonal transformation, and presenting the spectrum, i.e. the distribution of energy as a function of frequency, a fragment of the original signal in the time domain. By processing various methods of frequency components, usually called transform coefficients, obtained by orthogonal processing of the signal fragment, you can reduce redundan4

173 287 in this fragment of the original signal. Thus, due to the orthogonal transformation of the original signal fragment, and processing of the obtained transform coefficients, the original signal fragment can be represented using fewer bits than used to represent the original signal fragment. In addition, it is possible to reproduce this original signal fragment in the time domain by applying inverse orthogonal transformation of the transform coefficients.

The device for compressing the moving image signal and for expanding the compressed signal are known examples of digital signal processing devices using orthogonal transformation processing.

It is known that the power of signals with a high degree of correlation is concentrated in the lower ranges of the frequency area. As the concentration of signal strength increases along a given coordinate axis, for example along the frequency axis, it is possible to gradually reduce the signal's redundancy and compress it more effectively.

Since a moving image signal is usually highly correlated, both spatially and temporally, orthogonal transformation can be used to concentrate the signal strength along a specific coordinate axis and achieve effective compression of the moving image signal.

When using the NTSC television standard, for example, a very large amount of information is needed to represent a moving image. For this reason, recording of moving image signals requires the use of a recording medium with a very large storage capacity if this medium is to provide an acceptable long recording time. Furthermore, the size of the information stream with which the moving image signal is recorded and read using such a medium is very large. Physically large magnetic tapes or optical disks are needed to store the moving image signal.

If it is desired to record the moving image signal on a more compact medium with an acceptable recording time, the moving image signal should be compressed to reduce the amount of information necessary for storage. In addition, there is a need for a device suitable for use in expanding the compacted signal of a moving image reproduced from a compact recording medium.

In order to meet the described requirements, various methods of video compression were proposed, using correlations within and between parts of the video signal representing the moving images constituting the image signal. For example, the image compression method proposed by the Moving Picture Experts Group MPEG is widely known.

The description often refers to the term image. Since the described signal processing techniques relate to image signal processing representing moving images, the word image is generally used and refers to a portion of the video signal representing one of the images of the moving image sequence. In addition, the video signal may represent an image from a moving image sequence in the form of a frame or field. Unless otherwise stated, the word image means field or frame. At the beginning, the MPEG standard determines the differences between the images that make up the moving image, in order to reduce the image signal redundancy in the time domain. Then, in the MPEG standard, the image signal redundancy is reduced in the spatial domain, by applying orthogonal transformation to blocks of time-domain image differences. The MPEG standard uses discrete cosine DCT cosine transformation as an orthogonal transformation. By reducing redundancy in both time and space, extremely efficient compaction of the moving image signal is achieved. The compressed image signal obtained from the described compression process may then be recorded on a recording medium or transmitted by a suitable transmission means.

When reproducing the compressed video signal from the recording medium, or after receiving it from the transmission medium, blocks of transform coefficients obtained from the DCT transformation are separated from the compressed video signal. Transform coefficients are processed using inverse orthogonal transformation, i.e. inverse discrete cosineusoidal IDCT transformation (in MPEG standard: - Inverse Discrete Cosine Transform), in order to reproduce blocks of inter-picture differences when reconstructing images of the original image signal.

The odd parity processing used in MPEG does not protect against the occurrence of a cumulative mismatch error if non-zero values ​​have two or more DCT coefficients. In addition, the process of giving parity in MPEG1 reduces the resolution of the quantized transform coefficients with a multiplier of 2, because it is not possible to obtain even coefficients. This reduces image quality. The problem arises if higher image quality is needed. It clearly follows that it is desirable to develop a better way to prevent cumulative mismatch errors than the method proposed in the MPEG1 standard.

The method of the invention is intended for processing a set of transform coefficients representing a moving image signal, each of which has parity, to obtain an error-tolerant set of transform coefficients for performing an inverse orthogonal transformation in which an error-resistant set of coefficients is resistant to rounding errors when subjected to inverse orthogonal transformation. The method of this type is characterized in that the coefficients of the set of transform coefficients are added to obtain the parity of the sum, the parity of the sum is checked, and if the sum is even, the parity of one of the transform coefficients is inverted to obtain the inverse parity transform coefficient, which causes the oddness of the sum . In addition, a fault-tolerant set of transform coefficients is combined, including a transformed parity transform coefficient.

It is preferred that the transformation coefficient processing obtained from the two-dimensional discrete cosine transform is used, where the set of transform coefficients contains a coefficient representing a constant component, and in the parity reversal step of one of the transform coefficients, the parity reversal of one of these coefficients, other than the coefficient representing the constant component is performed . The set of transform coefficients also contains the transform coefficient representing the highest frequency component, and in the parity reversal step of one of the transform coefficients, the parity reversal of the coefficient representing the highest frequency component is carried out. Each of the transform coefficients in the set is represented by a binary number with the least significant bit, and in the step of inverting the parity of one of the transform coefficients, the least significant bit of one of the transform coefficients is inverted. Each of the transform coefficients in the set has a specific polarity, and during the inversion of the parity of one of the transform coefficients, the polarity of this transform coefficient is determined, and if this polarity is negative, a specific odd value is added to this transform coefficient, and if the polarity is positive, the specified odd value is subtracted from this transform coefficient.

It is beneficial to additionally perform the step of collecting the transform coefficients of the set in the next order, where the set of transform coefficients includes the last downloaded transform coefficient, and in the parity reversal step of one of the transform coefficients, the parity reversal of the last downloaded transform coefficient is performed.

All transform coefficients in the set have values ​​other than zero. Each of the transform coefficients in the set is represented by a binary number with the least significant bit, and in the stage of summing the transform coefficients, only the least significant bit of each of the transform coefficients is summed up.

It is beneficial to additionally select the assembly transform coefficients from the transform coefficient block.

The device according to the invention is adapted for pre-processing a set of transform coefficients representing a moving image signal, each of which has parity, to obtain a fault-tolerant set of transform coefficients for performing an inverse orthogonal transformation in which the fault-tolerant set

173 287 coefficients are resistant to rounding errors when subjected to inverse orthogonal transformation. This device is characterized by the fact that it is equipped with a battery for taking over the transform coefficients of the set and collecting their sum with parity, which is connected with the parity check system of the received sum, which is attached to the parity inverter to reverse the parity of one of the transform coefficients and ensuring parity sums if the sum is even. The parity inverter, in turn, is attached to the output cosine-inverse transformation system that provides a fault-tolerant set of transform coefficients, including the inverse parity transform coefficient, which system is the output system of the odd parity system.

It is preferred that the system of giving the odd parity is a system for processing transform coefficients obtained from a two-dimensional discrete cosine transform, which set of transform coefficients contains a coefficient representing a constant component, the parity inverter contains elements for inverting the parity of one of the transform coefficients, other than the coefficient representing the component constant.

In the event that the transform coefficient set also includes a transform coefficient representing the highest frequency component, the parity inverter includes means for inverting the parity of the coefficient representing the highest frequency component.

In the case where each of the transform coefficients in the assembly is represented by a binary number with the least significant bit, the parity inverter contains elements for inverting the least significant bit of one of the transform coefficients.

In the case where each of the transform coefficients in the assembly is represented by a binary number with the least significant bit, the battery is equipped with elements of summing only the least significant bit of each of the transform coefficients.

The system making the odd odd total is additionally equipped with a memory selector for the selection of the transform transform coefficients from the transform coefficient block.

The solution according to the invention effectively prevents the occurrence of cumulative mismatch errors when performing inverse orthogonal transformation of the transform coefficients, with no reduction in the resolution of the transform coefficients. In addition, there is no mismatch error problem and rounding errors are prevented during the inverse transformation of transform coefficients.

According to the invention, it is sufficient to change the parity of only one of the coefficients of the discrete cosineusoidal DCT transformation to give their odd parity. According to MPEG1, all coefficients of discrete cosine DCT transformation are given oddity, which, with a multiplier of 2, reduces the resolution of coefficients subjected to inverse IDCT cosine transformation. The procedure for preventing matching errors according to the invention, however, envisages giving parity to the sum of the discrete cosine DCT cosine transformation coefficients in a way that does not significantly reduce the accuracy of the input and output values ​​of the discrete cosine ID cosine transformation. When using the inventive method in a moving image signal compressor, a compressed image signal expander or a compressed image signal transmission device, image quality degradation is minimized.

In addition, when using the method of the invention in the MPEG standard, the minimum quantization step may be 1, as opposed to the known method in which the minimum quantization step was 2.

The subject of the invention is shown in the embodiments of the drawing, in which Fig. 1 shows a conventional device according to the MPEG standard for compressing a moving image signal in the form of a block diagram, Fig. 2 - a conventional device according to the MPEG standard for the expansion of the compressed moving image signal in the form of block diagram, Fig. 3 - compression sequence of a moving image signal, in the MPEG standard, Fig. 4 - a real example of DCT discrete cosine transformation coefficients, Fig. 5 - processing steps used for inverse quantization, both intra-intra- and non-intra-blocking in a conventional MPEG1 system, Fig. 6 - configuration of the first embodiment of the device for compressing the moving image signal according to the invention, in the form of a block diagram, fig. 7 - a method of reading a block of coefficients of discrete cosineoid transformation DCT using zigzag viewing, Fig. 8 - the first practical variant of the implementation of the system 14 giving the odd odd sum, in the device shown in Fig. 6, in the form of a block diagram, Fig. 9 - a flowchart showing operations the odd odd sum shown in Fig. 8, Fig. 10A - a second embodiment of the odd odd sum system shown in Fig. 6, in the form of a block diagram, Fig. 10B - version of the second embodiment of the odd-numbered system illustrated in Fig. 6, Fig. 11 - first version of the implementation of the parity inverter shown in Fig. 8, in the form of the block diagram, Fig. 12 - flowchart explaining the operation of the second version of the parity inverter, Fig. 13 - the second version of the parity inverter, in the form of a block diagram, Fig. 14 - flowchart explaining the operation of the third version of the parity inverter, Fig. 15 - the third version of the parity inverter, in the form of a block diagram, Fig. 16 - flowchart explaining the operation of the fourth version of the parity inverter, Fig. 17 - the fourth version of the parity inverter, in the form of a block diagram, Fig. 18 - a third embodiment of the odd-numbered sum system shown in Fig. 6, in the form of a block diagram, Fig. 19 - configuration of the first embodiment of the device for the expansion of the compressed moving image signal according to the invention, in the form of the diagram, Fig. 20 - the inversion quantizer and the odd parity system in the device for the expansion of the compressed moving image signal shown in Figure 19 is a diagram, Figure 21 is a time chart explaining the operation of the inversion quantizer and the odd parity total system; 22 - the configuration of the second variant of the device for compressing the moving image signal according to the invention in the form of a block diagram, Fig. 23 - the first variant of the implementation of the odd odd system, in the second variant of the device for compressing the moving image signal of Fig. 22 in the form block diagram, fig. 24 - a second variant of making the odd parity total system, in a second embodiment of the device for compressing the moving image signal shown in Fig. 22 in the form of a block diagram, fig. 25 - a third variant of making the total odd system in the second variant of the compression device the moving image signal shown in Fig. 22 in the form of a block diagram, Fig. 26 - a variant of the implementation of the parity inverter in the odd odd total systems shown in Figs. 23-25, in the form of a block diagram, Fig. 27 - the first variant of the parity inverter shown in Fig. 26, Fig. 28 - the second variant of the parity inverter shown in Figs. 26, Fig. 29 - third variant of the parity inverter shown in Fig. 26, and Fig. thirty - a configuration of a second embodiment of the device for expanding the compressed moving image signal according to the invention in the form of a diagram.

Advantageous embodiments of the method of performing inverse discrete cosine transformation, a device for inverse cosine transformation, a device for compressing a moving image signal, a device for expanding a compressed moving image signal, a recording medium and a transmitting device will be presented.

The solution according to the invention is applicable to a hybrid coding method in which predictive coding, displacement compensation and discrete DCT cosine transform are combined. This hybrid coding standard is described in z. 261 ISO-ffiC / JTC1 / SC2 / WG11 (commonly called MPEG) publications of the Advisory Committee on International Telegraphy and Telephony (CCITT), which is an international committee established to promote standards, including compression of moving image signals and compression of moving images before recording on a recording medium .

Predictive coding with displacement compensation is a way of redundancy of a moving image signal by using the correlation of the moving image signal in the time domain. Prediction with displacement compensation of the current image, i.e. the coded one, is made using another, already decoded image of the image sequence

173 287 moving as reference image. The resulting displacement predictive errors are contained in the compressed signal along with the displacement vector, prediction mode, etc. This significantly reduces the amount of information in the compressed moving image signal necessary to represent the live image.

The prediction error signal of the displacement compensation is compressed using a signal compressor using the geometric correlation of each image in the moving image sequence. The differential signal compressor typically includes an orthogonal transformation system, for example a DCT discrete cosine transformer system and a quantizer. The DCT cosine transform is a type of orthogonal transformation that focuses the power of signals in specific frequency components as a result of intra-picture (intra-frame or intra-field) two-dimensional image correlation. In this way, the compressed signal only contains concentrated coefficients and distributed coefficients included in the compressed signal either directly or after additional compression. This further reduces the amount of information contained in the compressed moving image signal necessary to represent the current image.

Predictive coding with inter-image displacement compensation can be performed between image frames of the moving image signal. Also, if the moving image signal is an interlinear signal, then the predictive coding with displacement compensation for the predictive coding can take place between fields. In addition, with intra-image coding with predictive displacement compensation, adaptive switching from inter-frame to cross-field coding can take place, depending on the properties of the moving image.

An embodiment of the known apparatus for the reconstruction of moving images, based on the MPEG standard, is shown in Fig. 1. In the compressor shown in Fig. 1, the digital video signal is fed to the block formatting system 101, where it is converted from a standard video format, e.g. NTSC video, using a block format that provides a blocked video signal. In this signal, each image of the moving image signal is divided into geometric areas, i.e. horizontally and vertically, into macroblocks, for example 16x16 image points. The macroblocks are also divided into 8 x 8 points.

The device shown in Fig. 1 compresses each signal image block by block until all the blocks making up the image are processed. The device then processes another image of the image signal, which may or may not be the next image of the image sequence constituting the moving image. In the following description of the device of Fig. 1, the compression of one block of points in one image will be described. The compressed block of points is the current image block, which is the block of the current image. The blocked video signal is transmitted to the displacement predictor 102. Displacement predictor 102 gives the current image, including the current S1 image block, block by block to the system 103 for calculating difference blocks.

When the difference block calculation system 103 receives the current image block 51 from the displacement predictor 102, it also receives the matching block S2 corresponding to this current image block 51 from the displacement predictor 102. The matching block 52 is obtained from the reproduced images stored in the image memory block 112 by the predictor 113. The difference block calculation system 103 determines point by point differences between the current image block S1 and the corresponding matching block S2. The resulting block of S3 differences is fed to the orthogonal transformation system 104.

Orthogonal transformation system 104, which is usually a discrete cosineusoidal DCT transformation system, performs processing by means of orthogonal transformation into a block of differences S3 and transfers the resulting block of transform coefficients to the quantizer 105. Quantizer 105 quantizes the block of transform coefficients to obtain a block of quantized transform coefficients. The variable length encoder 106 subjects a block of quantized transform coefficients from the quantizer 105 to variable length coding, e.g., Huffman coding or current length coding, etc.

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The received block of coded transform coefficients is then fed, for example, to the digital transmission path via the output buffer 107.

The control signal indicating the number of bits stored in the output buffer 107 is fed back to the quantizer 105. The quantizer 105 adjusts the amount of the quantization step depending on the control signal in order to protect the output buffer 107 against overflow or flushing. Increasing or decreasing the quantization step accordingly decreases or increases the number of bits fed to output buffer 107.

A block of quantized transform coefficients is also supplied from the quantizer 105 to the inversion quantizer 108, which is part of the local decoder used in the compressor to obtain from the quantized transform coefficients of restored images used in predictive coding. Inverse quantizer 108 performs the inverse quantization of a block of quantized transform coefficients by performing complementary machining to the quantization process performed in quantizer 105. The resulting transform coefficient block is fed to the inverse orthogonal transformation system 109, where it is processed according to the inverse orthogonal transformation in a process complementary to the machining during orthogonal transformation performed by the orthogonal transformation system 104. The resulting reconstituted block of 54 differences is fed to adder 110.

Adder 110 receives from one of the group 112 memories also the matching block S2, selected by the predictor 113. The adder 110 sums up, point by point, the differences from the restored block S4 from the system 109 of inverse orthogonal transformation and the matching block S2 from group 112 of image memory to obtain the reconstructed S5 image block. The reconstructed image block 55 is fed to one of the image memories 112A -112D selected by the selector 111, where it is saved.

The reconstructed image block is saved in the selected image memory, where it is one block (corresponding to the current block) of the reconstructed image obtained block by block from the reconstructed image blocks in the selected image memory. Upon completion, the reconstructed image is used to obtain matching blocks for predictive coding purposes to compress other images of the image signal.

The displacement predictor 102 determines, for each live image block, the displacement vector between the current image macroblock and other macroblocks of the remaining images of the image signal stored therein. The displacement predictor 102 also gives the sum of the absolute differences (the sum of the absolute differences) between the image points of each macroblock of the current image and the different macroblocks of other images. Each difference in absolute sum values ​​indicates the degree of matching between each macroblock of the current image and the macroblocks of the other images. Displacement predictor 102 transmits each displacement vector and the corresponding difference in absolute sum values ​​to the prediction mode determination system 115.

Prediction mode determination system 115 uses the data obtained from displacement predictor 102 to determine a prediction mode that should be used for predictive coding of a live image relative to one or more other reconstructed images. The current image can be predictively coded using any of the prediction modes, which include first of all:

- intra-picture mode, in which the picture is compressed in itself, without reference to other pictures, and the picture encoded in this mode is called the picture I; Secondly

- forward prediction mode, in which the prediction is made with respect to the reconstructed image obtained previously, in a sequence of moving images, and the image encoded in this mode is called the P image; Thirdly

- Bidirectional prediction mode, in which block by block prediction is made with reference to a reference block obtained from a reconstructed image previously found in a sequence of moving images, from a reconstructed image obtained later in a sequence, or by performing a linear operation point by point for example, calculating

173 287 average value between the previously reconstructed image and the later reconstructed image, the image encoded in this mode is called the B image.

In other words, image I is an image in which intra-image coding was performed. The P image is obtained predictively from the reconstructed I image or P image previously in the moving image sequence. Image B is a predictively obtained, block by block, image using the earlier or later reconstructed I or P images, or using a block obtained by performing a linear operation using the reconstructed I and / or P images previously found in the image sequence and the reconstructed I images and / or P, occurring later in this sequence.

The prediction mode determination system 115 transmits the prediction mode and the corresponding displacement vector to the predictor 113 and to the readout address generator 114. The readout address generator 114 provides readout addresses for the image memory block 112, depending on the displacement vector, which results in reading from each of the image memories 112A-112D of the reconstructed image block stored therein. The position of the read block in the reconstructed image is determined by the displacement vector. The predictor 113 selects one of the read blocks from the image memories 112A-112D, depending on the prediction mode signal received from the prediction mode determination system 115. The selected reading block is the matching block S2 for the current block S1. When the current block is part of the B image, the predictor also performs linear operations on the blocks read from image memories 112A-112D to obtain the needed matching block. The predictor passes the S2 matching block to the difference block calculation system 103, and to the adder 110.

Fig. 2 shows an example of a condensed image signal expander operating on the basis of the MPEG standard. In this device, the compressed video signal, obtained directly from the compressor or by playing it from the recording medium, is bit fed to the output buffer 121, where it is temporarily stored. The compressed digital signal contains blocks of coded transform coefficients, including a block of coded transform coefficients representing the current block, and information about the prediction mode, quantization step size and displacement vector for each block.

The compressed image signal is read from the input buffer 121, one image each, and fed to the reverse variable length IVLC encoder 122. The reverse variable length encoder 122 performs the operation of the inverse variable length coding on the compressed image signal and separates the compressed image signal into its components, including blocks of quantized transform coefficients, prediction mode information, step size information, and displacement vector information for each block.

Each block of coded transform coefficients is fed to an inverse quantizer 123, which uses step size information to invert quantize the block of quantized transform coefficients to obtain a transform coefficient block. Inverse orthogonal transformation system 124 performs inverse orthogonal transformation operations, usually IDCT, on a transform coefficient block to obtain a reconstructed block of differences. The inversion quantizer 123 and inverse orthogonal transformation system 124 perform complementary processing to those used in quantizer 105 and orthogonal transformation system 104 in the compressor shown in Figure 1, respectively.

The generator of 130 read addresses gives the read addresses to the 128A-128D image memories, in response to the displacement vector for the current block received from the inverse variable-length encoder 122. Depending on the read addresses, the reconstructed, stored block is read in each of the 128A-128D image memories in her a picture. The predictor 129 selects one of the blocks read from the 128 A-128D image memories in response to the prediction mode signal, also obtained from the inverse variable length encoder 122. The selected reading block is a block matching the reconstruction of the current block. When the current block is part of an image encoded as a B image, the predictor also performs line operations on blocks read from image memories

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128A - 128D to obtain the matching block. The predictor 129 passes the matching block to adder 125.

Adder 125 performs, point by point, the reconstructed block of differences from the inverse orthogonal transformation system 124 and the matching block from the predictor 129 to reconstruct the current image block of the current image. Selector 126 feeds the reconstructed live image for storage to one of the 128A-128D image memories in which the live image is reconstructed. The reconstructed current image block is stored in the selected image memory in the place corresponding to the current block in the reconstructed current image. When all reconstructed live image blocks are already stored in the selected 128A-128D image memory, the reconstructed live image is ready to be read as well as to be used as a reference image for the reconstruction of other images that appeared earlier or later in the moving image sequence.

The reconstructed images stored in the 128A-128D image memories are read as the image output signal via the selector 126, depending on the read addresses generated by the display address generator 127. A sweep converter (not shown) converts the input video signal read from 128A-128D image memories to the raster format of the desired signal standard, for example NTSC. The resulting image output signal can then be displayed on a suitable display device, e.g., a cathode ray tube, etc. In this example, the synchronization signal generator 131 is connected to an external synchronization source, and periodically generates a frame synchronization signal fed to the display address generator 127. The display address generator 127 generates read addresses synchronously with the frame synchronization signal.

Described examples of orthogonal transformation, for example, discrete cosineusoidal DCT transformation systems and inverse cosineusoidal IDCT transformation, used in the compressor and expander. perform arithmetic operations on light point values ​​and process coefficients represented by integers with a finite number of bits. Thus, orthogonal transformation operations performed by orthogonal transformation systems can cause a number of bits to be cut off. For this reason, differences in the accuracy of orthogonal transformation operations using real numbers, or differences in the configuration of the system used to perform orthogonal transformation operations may result in changes in the result of the transformation operation. It can lead to a mismatch between the compressor and the expander and to a mismatch between the expanders expanding the common compressed signal.

For example, in a compressor, a block of differences obtained from an image signal is subjected to orthogonal transformation and specific processing for the obtained quantized transform coefficients when generating a compressed image signal. Then in the expander, if the actual value of the accuracy of the operation or configuration of the inverse orthogonal transformation does not correspond to the transformation in the compressor, it is possible that the output signal of the expander will be different from the input signal to the compressor. Thus, the output signal in the expander may depend on the accuracy and configuration of the device used in the expander.

The accuracy of the operation or the configuration of the inverse orthogonal transformation may vary, depending on the device used to perform the transformation. For example, inverse transformation of a transform block using two different constructions of the same type of inverse orthogonal transformation system may give different results. This kind of result difference is sometimes called the inverse orthogonal transformation fit error (fit error).

The MPEG standard specifies the accuracy with which DCT and IDCT transformations should be performed, but the methods of processing and configuration are not specified. This is because methods and systems for performing DCT and IDCT transformations during the MPEG standard establishment were under development.

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In the MPEG standard, as described above, the compressor performs on an image signal, for example, predictive coding with intra-image motion displacement compensation. At the same time, the moving image signal is divided into blocks, a block of differences is obtained, from the current image block and the matching block obtained by applying displacement compensation to the restored image, orthogonal transformation of the difference block occurs using discrete cosineusoidal DCT transformation, the resulting transform coefficients are quantized, quantized transform coefficients are subject to variable length coding, and encoded transform coefficients are collected together with prediction mode information, quantization step information, and displacement vectors to obtain a compressed image signal.

The expander performs inverse variable-length coding on coded transform coefficients, inverse quantization of quantized transform coefficients obtained by inverse variable-length coding, and processing using inverse IDOS cosine transformation on transform coefficients obtained from inverse quantization. The resulting reproduced block of differences is added to the matching block obtained by applying displacement compensation to the reconstructed image according to the displacement vector. The resulting reconstructed image block is stored as a reconstructed image block constituting one image from the image output signal and usable as a reference image.

The compressor includes a local decoder, which receives reconstructed images from quantized transform coefficients for use in predictive coding. The local decoder contains an inversion quantizer and a reverse orthogonal transformation system.

If the IDOS reverse cosine transformation system in the compressor local decoder is different from the configuration of the IDCT reverse cosine transformation in the compressor, it happens that the reconstructed images produced by the local decoder in the compressor differ from the reconstructed images produced by the expander. The dependence of IDCT inverse cosine transformation transformation on implementation can cause problems when a compressed imaged signal generated by a compressor conforming to the MPEG standard is recorded on a carrier, e.g. an optical disk, etc. for wide dissemination. When the compressed image signal reproduced from the optical disk is expanded with the help of expanders produced and sold by various manufacturers, the reproduced image may differ from the original image. In addition, the differences may depend on the specific expander used. Similar incompatibilities between different expanders may arise when the compressed image signal is distributed in a broadcasting system, e.g. terrestrial or satellite, via a telephone network, ISDN system, cable or optical network, etc.

Mismatch errors are a special problem when performing predictive cross-image coding. The predictive cross-picture coding can be cross-field or cross-frame coding. Cross-picture predictive coding can cause cumulative mismatch errors to affect reconstructed images in a fatal way.

When compressing the image signal performed in the MPEG standard, each video sequence is divided into Groups of Pictures (GOP), consisting of, for example, eight or twelve images. Each image is classified as image I, image P, image B as described above. Image B is not used as a reference image for performing displacement prediction. Therefore, the mismatch error in image B does not cause errors in other images. When the mismatch error occurs in the P image, the image with the mismatch error is stored in the image memory for use in predictive coding. Accordingly, when predictive cross-image coding is performed, the P image error in image memory gradually spreads to P images and B images obtained from it as a result of predictive coding. The error accumulates until the image is replaced by another I or P image in which the error does not occur.

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Similarly, when a mismatch error appears in the I image, the reconstructed image with the mismatch error is stored in the image memory for use in predictive coding. Accordingly, when predictive cross-image coding is performed, the image error I stored in the image memory spreads to P images and B images obtained therefrom as a result of predictive coding.

The error accumulates until the image is replaced by a new image and deprived of this error. The accumulation of errors is shown in Fig. 3. In Fig. 3, if the mismatch error in decoding the picture I is El, and the mismatch error in decoding the picture P1, type P is EP1, then the error value in the reconstructed picture P1, type P is EI + EP1. Then, when the mismatch error when decoding the P2 image of the P type is EP2, the error value in the reconstructed P2 image of the P type is EI + EP1 + EP2. Even if the individual mismatch errors are small, the gradual accumulation of these errors results in a large error.

Mismatch errors arising during IDCT processing used in MPEG decoders, both in the compressor and expander, can be divided into two different types. The first type is: errors resulting from insufficient accuracy of operations, and the second - errors resulting from systematic differences in rounding.

The MPEG standard specifies the requirement for the accuracy of operations. However, this requirement is not stringent enough to guarantee that no mismatch error will occur. Thus, the mismatch error of the said first type can even occur between inverse IDOS cosineoid transformation devices whose accuracy of operation meets the MPEG requirements.

The output of IDCT inverse cosine transformation is integers. Therefore, after IDCT processing using real numbers, it is necessary to round the resulting numbers. Usually, the processing results are rounded to the nearest whole number. However, a problem arises when the processing result is * .5, where * is an integer. The MPEG standard does not specify how to process a result of * .5. Some devices round * .5 up and others IDCT down. Also, in some cases, rounding up or down depends on the sign of the result. Mismatch errors resulting from systematic rounding errors belong to the latter type.

The first type mismatch errors differ from the second type mismatch errors in that the first type errors occur randomly, while the second type errors are systematic. Since the first type of errors are random, positive and negative errors occur with almost equal probability. Thus, when performing predictive coding over a longer period of time, it can be assumed that mismatch errors of the first type will be compensated.

However, since the second type of errors are systematic and do not correlate with the IDCT processing itself, such errors have the same tendency. Accordingly, when performing predictive coding over a long period of time, the mismatch error will accumulate in one direction. Although the second mismatch error is only +1 or -1, if many mismatch errors accumulate in one direction, the cumulative mismatch error may be large.

Since mismatch errors of the first type, although they occur temporarily, they tolerate themselves in the long run, so the errors of the first type are not troublesome. However, since mismatch errors of the second type accumulate in one direction, these errors are a problem. For this reason, it is desirable to prevent second type cumulative errors.

In order to prevent the occurrence of mismatch errors of the second type, the MPEG1 system was proposed to perform pre-processing before performing the IDCT transformation. In this processing, the transform coefficients for all coefficients are set to an odd value, except for the component transform coefficient (0.0) of the intra-image coded macroblock (intra - macroblock - intra-image macroblock). In the intra-image macroblock, the component (0,0) is a constant component. As shown in Fig. 4, for example, all the component coefficients (0.1), (7.1), (2.3),

173 287 (5.3), (1.5), (6.5), (3.7) and (4.7) are initially 568. Because it is an even number, all these coefficients are set in the pretreatment to an odd value, such as 567. When using an IDCT transform for pre-processing transform coefficients, fractional results never occur.

Because the intrinsic macroblock constant component is very important for the appearance of the image obtained from the compressed image signal, its accuracy is limited to only eight bits. It is not processed into an odd number because it would reduce the accuracy of this important component. On the other hand, all transform coefficients obtained by processing the image-coded macroblock (non-Bintramacroblock) are subjected to a process similar to the processing of component coefficients, other than the constant component, different from the process used for the constant component, in order to limit transform coefficients only to odd values.

Processing in which the transform coefficient values ​​undergo IDCT transformation is preset to odd values ​​is called odd processing.

By using odd processing, IDCT transformation will be rounded according to one principle in both the compressor and expander. This makes it possible to maintain the same image quality for different expanders.

However, despite the processing with the aforementioned oddity, the described cumulative errors of the second type still arise in the MPEG processor, because in the IDCT transformation the results * .5 can still be generated, where * is an integer. The circumstances leading to the * .5 result will be described using, as an example, the two-dimensional IDCT 8x8 transformation used in the MPEG system.

The two-dimensional IDCT 8x8 is expressed by the following equation:

t / foy) = 4 Σ Σ ^F(«’^v) something _something ((2y + Dvyn) u = 0 v = 0 (1) u, ​​v, x, y = 0, 1, ..., 7

<img file="PL173287B1_D0001.tif" />

= 1 (u, N * 0)

In the equation above, F (u, v) denotes the discrete cosine cosine transformation coefficients of DCT subjected to two-dimensional IDCT transformation. In equation (1), each IDCT result is a real number, i.e. a rational or irrational number. Because * .5 is a rational number, providing an IDCT output value as an irrational number will prevent a cumulative mismatch error. At the same time, when the output is a rational number, it is possible to occur as a result of the value * .5.

DCT F (0.0), F (0.4), F (4.0), F (4.4) are special DCT coefficients. When one of these DCTs is nonzero, the IDCT result is a rational number. The output values ​​from IDCT in this case are expressed by equations (2).

f (x, y) = ^ -F (0.4) cos ^ -K

ΥΓ3 287 ^f(M) = ^ W) cos ^ K f (x, y) = F (4,4) cos 71 cos 71 where cos ^ p7l = ± ^ (2)

So, when only one of the special factors DCT F (0.0), F (0.4), F (4.0), F (4.4) has a non-zero value, which is a multiple of 4, but is not a multiple of 8, the output value is *. 5.

When these four special DCT coefficients are the only non-zero coefficients, the IDCT output value is expressed by the equation (3) f (x, y) = | F (0.0) + F (0.4) cos TT + + ^ 2 F (4.0) cos ~ τρΤΤ + + © (4,4) cos-²"TT cos TT (3)

With different combinations, x and y, F (x, y) in equation (3) can have the following values:

| [F (0, 0) + F (0, 4) + F (4.0) + F (4.4)] j [F (0.0) + F (0.4) - F (4.0 ) - F (4,4)] j [F (O, O) -F (O, 4) + F (4, 0) -F (4,4)] | [F (0,0) - F (0, 4) - F (4, 0) + F (4, 4)] (4)

Thus, when the values ​​of these four special coefficients are such that any of the expressions in equation (4) is a multiple of 4, but is not a multiple of 8, gives the result * .5.

Thus, when the four special coefficients have nonzero values, it is very likely that the DCT output value will be * .5.

An output value of * .5 can also be given by various symmetrical pairs of DCT coefficients with non-zero values, other than the special coefficients discussed:

(1) when the pair of coefficients X (2n + 1, 2m + l), X (2m + 1, 2n + l) has the same non-zero value, being a multiple of 4, and not being a multiple of 8, or (2) when a pair of coefficients X (2n + 1, 2n + 1), X (8-2n-1, 8-2n-1) has the same non-zero value, being a multiple of 4, not a multiple of 8.

In the above expressions, X (i, j) is the transform coefficient of one of the components of the two-dimensional DCT 8x8 transform.

When the real moving image signal is compressed with an MPEG-compliant compressor, DCT non-zero coefficients are often found in

173 287 configurations discussed, which can give output values ​​* .5. In addition, the values ​​of these four special factors are most often non-zero.

Because the most common cause of the * .5 result is a configuration of DCT coefficients in which the values ​​of four special coefficients are non-zero, preventing mismatch error occurring in response to these four special coefficients will significantly reduce the likelihood of mismatch error.

Fig. 5 shows a processing method in which the intra-imaging macroblock and the non-intra-imaging macroblock are quantized inversely in MPEG1. In Fig. 5, QAC (i, j) is the coefficient (i, j) -th transform DCT Wi (ij) Wi (i, j) is (i, j) -th element of the weighting matrix, mqant quantization coefficient, and rec (i, j) is (i, j) the inverse quantized DCT coefficient. The processing method is written in the C programming language. The syntax for this language is known.

The quantized DCT coefficients are subjected to inverse quantization, and the resulting DCT coefficients are then subjected to EDCT processing. In MPEG1, +1 or - l are added to even DCT coefficients to ensure that all IDT transformed DCT coefficients have odd values. As a result of this operation, for example, when only one of the four special factors F (0.0) is nonzero, it is because the mismatch error only occurs when F (0.0) is a multiple of 4 but is not a multiple of 8 , if the DCT coefficients are processed so that they all have odd values, the result after subjecting the DCT coefficient to the IDCT transformation cannot be equal to * .5. Similarly, when only one of the other special factors F (0.4), F (4.0), F (4.4) has a non-zero value, a mismatch error cannot occur. However, if more than one of these four coefficients has a non-zero value, as shown in Figure 4, or when there are pairs of symmetrically spaced coefficients, making all DCT coefficients odd does not protect against mismatching errors.

We will now present the principle on which the invention prevents cumulative mismatch errors.

Analysis of equation (4) shows that mismatch errors occur when the expressions in the equation give (2n + 1) / 2, where n is any integer.

Equation (4) can be expressed as:

f (x, y) = 1/8 ACC where ACC is the sum of all coefficients.

The most common mismatch configuration is:

f (x, y) = 1/8 ACC = (2n + 1) / 2 = 1/8 (4 * (2n / + 1))

On this basis, it can be seen that if ACC becomes an odd number, a mismatch error will never occur.

Accordingly, the invention uses a certain approach scheme for inverse quantization of DCT coefficients and then, before IDCT processing, to calculate sums of DCT coefficients. If the sum of the DCT coefficients is an even number (i.e. its parity is 0), then the parity of one of the DCT coefficients is changed in order to make the sum of the DCT coefficients odd, i.e. giving it parity 1. In order to give parity to the sum of DCT coefficients, it is enough to change the parity of only one coefficient. In addition, you can change the parity of the coefficient that has the least effect on the IDCT result. Thus, according to the invention, by changing the parity of the DCT coefficients before IDCT processing and, if the sum is even, by changing the parity of one of the DCT coefficients to render the DCT sum of the parity, mismatch errors are effectively prevented.

Fig. 6 shows a practical configuration of a moving image compression apparatus to which the present invention relates. In the device shown in Fig. 6,

173 287 the moving image signal is divided into individual images and is subjected to image-by-image compression. Each image is divided into image blocks, and is compressed block by block. The compressed image block is called the current block 51. The current image block is an image block called the current image.

A moving image signal, usually a video signal, is fed to the first group 2 of image memory, where multiple sequence images are temporarily stored. The memory controller 3 controls the reading of images from the first and second groups of image memory. The memory controller 3 also provides the SS start layer signal and the macroblock BS start signal to the 5 layer / macroblock counter. The memory controller properly provides these signals synchronously with the reading for compression of each layer and each of the macroblocks of each image, e.g. the current image from the first memory group 2. The layer is a horizontal row of blocks covering the width of the image.

Displacement predictor 6 performs displacement prediction by matching blocks of the current image and multiple blocks of the previous and later stored in the first group 2 of image memory. Block matching takes place on blocks of, for example, 16 x 16 image points. The reference image indicator signal for displacement prediction generated by the memory controller 3 selects blocks of previous and next image stored in the first group 2 of image memory as fitted to the current block. The displacement predictor 6 then gives the displacement compensator 7 as the displacement MV vector the position of the block in one of the previous or next images stored in the first or second image memory group, for which the differences between this block and the current image block, i.e. displacement prediction errors, reach a minimum .

In response to the displacement MV vector, the displacement compensator 7 reads a block of each of the reconstructed images stored in the second image memory group 4 as a potentially matched block. The positions of the reconstructed images from which the potentially matched blocks are read are specified using the MV displacement vector. The reference signal indicator signal for displacement compensation from the memory controller 3 then selects one of the potentially matched blocks read from the second group of picture memory 4 as a block matched to the current block. The reconstructed images stored in the second group of 4 image memories are images that have been reconstructed by local decoding of quantized DCT coefficients produced by the encoder 9 difference blocks.

The selection of the matched block of the reconstructed image via the reference image indicator signal for displacement compensation depends on the prediction mode of the current image. In forward prediction mode, the matched block is selected from a previously reconstructed image, from a future reconstructed image, or it can be generated in a linear operation, e.g. calculating the average value, on blocks previously reconstructed and reconstructed in the future. Finally, when the current image is encoded in the intra-picture coding mode, i.e. the image is encoded without prediction, a zero block is used as the matching block in which all point values ​​are set to zero. The matching blocks read from the second group of 4 image memories are adaptively modified so that an optimal matching block is selected for each moving image signal block.

The displacement compensator 7 selects the prediction mode for each image by pre-calculating for each point the sums of absolute values ​​of the differences between the current image block and potential matching blocks generated in different prediction modes. Then the displacement compensator 7 selects the prediction mode for which the sum reaches the minimum value. The displacement compensator 7 provides the MM signal of the prediction mode, which passes the prediction mode selection to the variable length encoder 17. The displacement compensator 7 also causes the second group 4 of image memory to provide the S2 block matching the selected prediction mode to the difference generation system 8.

The system 8 for generating differences receives the current S1 image block from a moving image signal read from the first image memory group 2 and calculates the point-by-point differences

173 287 between the live image block S1 and the matching block S2. The difference generation system 8 provides the resulting S3 difference block to the 9 difference block encoder. The differential block encoder 9 compresses the S3 difference block to form a block of quantized SC transform coefficients. The block of quantized SC coefficients of the transform is fed to the local decoder 10, where it is quantized to obtain the reproduced S4 block of differences. The local decoder 10 in the image signal compression device has a configuration similar to the device for expanding the compressed moving image signal.

The difference block encoder 9 and local decoder 10 will now be described. The difference block encoder 9 consists of DCT circuit 11 and quantizer 12, as shown in Figure 6. DCT circuit 11 uses DCT processing to orthogonal transformation of the S3 block of differences 8 from the 8 generation system. block of differences. System 11 DCT gives the resulting block of coefficients of discrete cosineusoidal transformation DCT to quantizer 12. Quantizer 12 quantizes the blocks of DCT coefficients, obtaining blocks of quantized SC DCT coefficients.

The local decoder 10 consists of an inversion quantizer 13, odd odd total system 14, and IDCT inverse cosine transformation system 15, as shown in Figure 6. Inverse quantizer 13 uses quantization tables to invert quantize blocks of quantized SC DCT coefficients from quantizer 12. The odd parity operation performs the parity inversion operation of the resulting DCT discrete cosine transform coefficient block when the sum of these coefficients is not an odd number. This prevents the occurrence of a mismatch error in reverse orthogonal transformation of DCT coefficients subjected to oddity. Inverse cosine IDID inverse transformation system 15 on the DCT cosine transformation odd discretion coefficients block from the odd parity system 14 to obtain a reconstructed block of differences.

The quantization performed by the quantizer 12 is described below. Each block of 8x8 DCT coefficients is quantized. Each block of an image compressed in the intra-picture coding mode (I picture) is called an in-picture macroblock. Each block compressed in cross-image coding mode is called a non-image macro block. In orthogonal transformation of the intra-image macroblock, the DCT component factor (0.0) is the constant component factor. The constant component coefficient is quantized by dividing, rounded, the constant component factor by 8, if the quantization is carried out with an 8-bit accuracy, by 4 if the quantization is carried out with a 9-bit accuracy, by 2, if the quantization is carried out with an accuracy of 10- bit by 1 if quantization is done with 11-bit accuracy. The constant component of the intra-image macroblock is quantized according to the following equations, which were written in the syntax of the C programming language:

QDC = dc // 8 (8 bits)

QDC = dc // 4 (9 bits)

QDC = dc // 2 (10 bits)

QDC = dc // 18 (11 bits) (5) where dc is the constant component ratio (DC) and QDC is the quantized constant component factor.

DCT coefficients other than the constant component coefficient obtained from the orthogonal transformation of the intra-image macroblock (variable components) are quantized by determining the quantization coefficients ac (i, j) when weighing the DCT ac (i, j) coefficients using the weighting matrix Wi, in accordance with the following equation:

ac '(ij) = (16 * ac (i, j)) // Wi (i, j) (6)

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The weighting matrix coefficients Wi are as follows:

Wi = 8 16 19 22 26 27 29 34 16 16 22 24 27 29 34 37 19 22 26 27 29 34 34 38 22 22 26 27 29 34 37 40 22 26 27 29 32 35 40 48 26 27 29 32 35 40 48 58

27 29 34 38 46 56 69

29 35 38 46 56 69 83 (7)

Then, using the following equation, the quantization coefficients ac '(i, j) are quantized to determine the levels of QAC quantization (i, j) of the respective variable component coefficients (AC).

QAC (i, j) = ac (i, j) + sign (ac (i, j) * ((p * mquant / q) (2 * mquant) (8)

In the above equation, piq are any integers, for example p = 3, aq = 4, while the quanta is a quantization factor.

DCT coefficients obtained from the orthogonal transformation of the intra-picture coding macroblock (non-inter-picture macroblock) are quantized by determining the quantization coefficients ac '(i, j) when weighing all DCT coefficients obtained by transforming the non-intra-picture macroblock using the Wn weighting matrix according to the following equation:

ac (ij) = (16 * ac (i, j)) // Wn (i, j) (9)

The weighting matrix Wn coefficients are as follows:

GE = 16 17 18 19 20 21 22 23

18 19 20 21 22 23 24

19 20 21 22 23 24 25

20 21 22 23 24 26 27

21 22 23 25 26 27 28

22 23 24 26 27 28 30

23 24 26 27 28 30 31

24 25 27 28 30 31 33 (10)

Then, using the equation below, the quantization coefficients ac '(i, j) are quantized to determine the levels of QAC quantization (i, j) of the variable components (AC)

QAC (i, j) = ac '(i, j) / (2 * mquant) if (mquant = odd) = (ac' (i, j) + l) / (2 * mquant) if (mquant == even AND ac- <0) = (ac '(i, j) -l) / (2 * mquant) if (mquant == even AND ac-> 0) (11)

The resulting QAC (i, j) quantization levels are fed to the variable length encoder 17 and to the local decoder as the block of quantized SC DCT coefficients described above.

The variable length encoder 17 encodes a block of quantized DCT coefficients obtained by quantizing the DCT coefficient blocks. Variable length encoder 17

173 287 determines the differences between the quantized transform coefficients in the four luminance blocks that make up each macroblock and the constant component coefficient of the corresponding intra-picture macroblock. The variable length encoder then uses the variable length coding tables to code the obtained difference values. In this method, it uses a large degree of correlation between neighboring luminance blocks, which means that the values ​​of the constant components have basically the same value. The variable length encoder 17 also determines the differences between the quantized coefficients of the two differential color blocks and uses the variable length coding tables to encode the resulting difference values. The variable length coding table for luminance coefficients and for differential colors are different from each other.

The variable length encoder 17 performs the variable length coding of a block of quantized DCT coefficients by reading blocks of quantized DCT coefficients in a zigzag order, starting from the DCT component coefficient (0.0), as shown in Fig. 7. The block of quantized DCT coefficients is read in a zigzag order DCT coefficients arising from DCT processing are usually concentrated in the vicinity of the component (0.0). Thus, reading DCT coefficients in a zigzag order increases the performance of variable length coding by increasing the speed of running through successive zero DCT coefficients between non-zero coefficients.

The variable length encoder 17 reads the DCT results in zigzag order and determines the value (in other words the level) of each non-zero DCT coefficient, and the number of the series of zero coefficients preceding it. It performs two-dimensional, variable-length coding of a DCT coefficient block. After coding, the coefficients in the block are expressed by pairs consisting of serial number and level. The variable length encoder also introduces a two-bit code, EOB, which indicates the last non-zero DCT. The variable length encoder 17 gives the address converter (not shown) the address of the last non-zero coefficient in the zigzag order. The address converter converts the address in a zigzag order to the address, EOB. adrs, in the order of raster dials. The variable length encoder gives the EOB address. adrs to the 14 odd odd system.

The total odd odd arrangement 14 stores EOB adrs in the raster dial order in register 25 described below, for example in Fig. 8.

Inversion quantizer 13 receives a block of quantized DCT SC coefficients from the differential block encoder 10, inversely quantizes this block of quantized DCT coefficients to obtain a block of DCT coefficients. In practice, the inversion quantizer 13 inverse quantizes the quantized constant component coefficients obtained from the orthogonal transformation of the intra-image macroblock using the processing determined by equation (12) to obtain the appropriate constant component coefficients. Quantizer 13 inversely quantizes the coefficients of the variable components, obtained from the orthogonal transformation of the intra-image macroblock, using the processing procedure determined by equation (13). Finally, quantizer 13 inversely quantizes all quantized coefficients obtained from the orthogonal transformation of the non-intra-imaging macroblock using the processing procedure defined by equation (14).

rec (0,0) = 8 * QDC rec (0,0) = 4 * QDC (9 bits) rec (0,0) = 2 * QDC (10 bits) rec (0,0) = 1 * QDC (11 bits) (12) rec (i, j) = (mquant * 2 * QAC (i, j) * Wi (i, j)) / 16 if (QAC (i, j) == 0) rec (i, j ) = 0 (13)

173 287 if (QAC (i, j)> 0) rec (i, j) = ((2 * QAC (i, j) + 1) * mquant * Wn (i, j)) / 16 if (QAC (i, j) <0) rec (i, j) = ((2 * QAC (i, j) -l) * mquant * Wn (i, j)) / 16 if (QAC (i, j) == 0) rec (i, j,) = 0 (14)

The resulting DCT coefficient block is fed from the inversion quantizer 13 to the odd parity total system 14, the practical embodiment of which is shown in Figure 8.

The total odd parity system 14 comprises a 23A battery, the parity check system 21, and the parity inverter 28. The battery 23A determines the sum of DCT coefficients block of DCT coefficients obtained from the inversion quantizer 13. The parity check system 21 checks whether the sum of DCT coefficients determined by the battery 23A is even or odd number (i.e. the parity of the sum of DCT coefficients is zero or one). Only when the parity check system determines that the sum of the DCT coefficients is even, the parity inverter changes the parity of at least one of the DCT coefficients in the block to render the sum of the DCT coefficients odd, i.e. the process of making the DCT sum coefficient odd. This prevents the occurrence of a mismatch error in the reverse orthogonal transformation of the DCT coefficient block with the given oddity of their sum, from the oddity system 14 in the IDOS cosine reverse inverse transformation system 15.

Counter 20 counts the number of DCT coefficients obtained from the inversion quantizer 13, and reports coeff_adrs of the counting result to the parity check system 21 to the memory selector 22.

Battery 23A is equipped with adder 23 and logical sum register 24. Adder 23 adds each DCT coefficient block of DCT coefficients received from the inversion quantizer 13 to the sum of previously received DCT coefficients of blocks stored in the logical sum register 24. This register 24 is reset after calculating the sum for each block of DCT coefficients. The resulting sum of DCT coefficients is given from the adder 23 to the logical sum register 24 and to the parity check system 21. In order to obtain a result suitable for use in the parity check of the sum of DCT coefficients, the battery only needs the sum of the least significant bits of DCT coefficients.

The parity check system 21 checks whether the sum of the coefficients in the DCT coefficient block is even or odd, in response to the coeff_adrs value obtained from the counter 20. When all DCT coefficients are given to the 23A battery, the coeff_adrs value indicates that the battery has calculated the sum of all DCT coefficients in the block. In response to the counted value of coeff_adrs, the parity check system 21 checks whether the sum of DCT coefficients from the 23A battery is even or odd. For example, in the case of two-dimensional DCT 8x8 transformation, the parity check system 21 checks whether the sum of DCT coefficients from battery 23A is even or odd, when coeff_adrs indicates that all 64 block coefficients have been given to battery 23A.

In practice, for example, when each of the DCT coefficients is represented by a binary number, the parity check system 21 examines the least significant bit LSB of the sum of DCT coefficients obtained from the battery. An LSB bit of zero indicates that the sum is even. In this case, the parity check circuit 21 provides the signal REQ1 of the processing request to the parity inverter 28 to cause the inverter to parity operation. In response to the processing request signal REQ1, the parity inverter 28 changes the parity of at least one (i.e., an even number thereof) of the DCT coefficients in order to give the odd parity to the sum of the DCT coefficients. At the same time LSB = 1 indicates that the sum is odd. In this case, the parity check system 21

173 287 does not produce the REQ1 signal of the processing request and the parity inverter 21 leaves the parity of all DCT coefficients in the block unchanged.

In the practical arrangement shown, the DCT coefficients of the inversion quantizer 13 are stored in memory, first 26 or second 27, via the memory selector 22. Memory selector 22 operates in response to the counted state received from counter 20 coeff_adrs. Thus, for example, when the memory selector 22 determines that all DCT coefficients in a block have been stored in the first memory 26, it selects the second memory so that the DCT coefficients of the next block are stored in the second memory &lt;27. Thus, subsequent blocks of DCT coefficients are stored alternately in the memories of the first 26 and the second 27. After all DCT coefficients of the block are stored in the first and second memories 27, the memory in which all the DCT coefficients are stored gives the FULL1 or FULL2 signal of the memory full to the parity inverter.

When the parity inverter 28 receives a memory full signal, FULL1 or FULL2 gives the enable signal Rd_EN1 or RD_EN2 to the memory containing the full signal. This causes the DCT coefficient block to be given from the memory that generated the full signal to the parity inverter. The parity inverter processes the block of DCT coefficients read from memory in one of two ways, depending on whether the parity check circuit 21 has generated the processing request signal REQ1. The parity inverter identifies the DCT coefficient, which parity can be inverted, using the address of the DCT coefficients, which parity can be inverted, stored in register 25. For example, Figure 8 shows the address of the last non-zero coefficient, EOB_adrs given to comparator 62. So in this example DCT, whose parity can be inverted, is the last non-zero coefficient. After the invert 28 of the DCT parity inversion, whose parity can be inverted, the parity of the sum of the non-zero coefficients of the block, from the first to the last, is made odd. The parity inverter 28 provides all DCT coefficients, except the LSB inverse coefficient, to the IDCT 15 with the unchanged state of their LSB bits. The parity inverter 28 also provides a DCT, whose parity can be inverted, to the IDCT, with the state of their LSB bits depending on whether the parity inverter received the processing request signal REQ1.

The parity inverter 28 can also be implemented using a computer or a digital signal processing processor operating, for example, in accordance with the flowchart of Fig. 9. In this example, the DCT, whose parity can be inverted, is the last non-zero coefficient. In step S1, the parity inverter 28 · based on the EOB_adrs address, is the processed DCT coefficient a coefficient whose parity can be inverted by changing its LSB bit or not. If the result of step S1 is YES, then proceeds to step S2. Otherwise, the user proceeds to step S5.

At step S2, the parity inverter 28 determines whether a REQ1 signal has been received, processing requests. If the result of step S2 is YES, which indicates that the processing request signal REQ1 has been received, it proceeds to performing step S3. Otherwise, when no processing request is received, it proceeds to performing step S5.

In step S3, the parity inverter 28 inverts the DCT bit LSB, whose parity can be inverted, to reverse its parity, and thus change the parity of the sum of the DCT coefficients. Then proceeds to the implementation of step S4, in which the DCT inverse parity is fed to the IDCT system (Fig. 10A). It returns to step S1, in which the next DCT coefficient is processed.

When the processed DCT coefficient is not a coefficient whose parity can be inverted, or when the parity of the DCT coefficient transmitted to the inverter is not to be inverted, that is, when the processing request REQ1 signal has arrived, the process proceeds to the execution of step S5. At step S5, the DCT coefficient is fed to the DDCT system without modification. Then comes back to step S1, where the processing of the next DCT coefficient begins.

173 287

When the DCT coefficients are represented in the form of a two-complement, the above-mentioned LSB bit is a two-complement LSB bit. However, when DCT coefficients are expressed as an absolute sign, the LSB bit mentioned above is the LSB bit value.

The structure of the total oddity system 14 is not limited to the structure shown in Fig. 8. For example, in the system shown in Fig. 10, a LSB bit detector 29 has been added, and the Exclusive-OR gate 30 has replaced the adder 23 of the system shown in Fig. 8. The elements in the arrangement shown in Fig. 10A corresponding to the elements of the arrangement in Fig. 8 are indicated with the same reference numerals.

The LSB bit detector shown in Fig. 10A checks the LSB bit of each LSB coefficient in the DCT coefficient block. The Exclusive-OR gateway performs Exclusive-OR action between each of the DCT coefficients in the block and the only logical sum stored in the register of 24 LSB bits of the DCT coefficients of the block just being processed. Thus, the Exclusive-OR gateway 30 performs the Exclusive-OR operation, and register 24 generates a logical exclusive of the LSB bits and DCT coefficients of each block. The 30 Exclusive-OR gate combination can be considered a DCT counter having an LSB bit equal to 1. Then, when all the coefficients in the block have been received, the output status of the 30 Exclusive-OR gate indicates whether the number of DCT coefficients having the LSB bit equal to 1 is even or odd. If the number of DCTs having an LSB bit equal to 1 is even, then the parity check circuit 21 then generates the processing request signal REQ1.

Fig. 10B shows another structure that replaces the Exclusive-OR gate and register 24. In this configuration, the least significant bit of each DCT coefficient obtained from the inversion quantizer 13 is fed from the LSB detector 29 to the 88 AND gate. The AND gate only lets LSB bits equal to 1 into counter 89. The counter at the beginning of each DCT coefficient block is reset and counts all LSB bits received with a value of 1. The LSB bit of the COUNT state from the counter 82 is fed to the parity check system 21. At the end of each block, the parity check determines the parity of the LSB bit of the COUNT state from counter 89. If the COUNT state is odd (the LSB bit of the COUNT variable is 1), it indicates that the block has an odd number of coefficients having an LSB bit of 1, and that the sum of DCT coefficients in the block is odd. However, if the COUNT state is even (i.e. the LSB bit of the COUNT variable is zero), it indicates that there has been an even number of DCT coefficients, with an LSB bit of 1, and that the sum of the DCT coefficients is even.

Referring to Fig. 11, a practical configuration of the first variant embodiment of the parity inverter 28 for the odd-numbered sum systems shown in Figs. 8 and 10A is described. The parity inverter 28 includes a read counter 61, address comparator 62, LSB 63 inverter, AND gates 64, 65, 67, 68 and OR gates 66, 69, and inverters 71, 72.

The parity inverter 28 works as follows. When the 61 readings counter receives the FULL memory full signal from the first 26 or second 27 memory, it gives the RD_EM signal allowing the read to the first 26 and second 27 memory. The read permission signal causes the appropriate memory to provide the DCT coefficient block stored in it first AND gate 67 via the path marked RDATA.

The FULL memory full signal also causes the meter to start 61 readings, counting the received DCT coefficients and giving it a counted value indicating the number of received DCT coefficients. Comparator 62 compares the counted value with the address obtained from register 25 to determine whether the DCT coefficient received via the first AND gate 67 is a coefficient dCt whose parity can be inverted, i.e. the coefficient which LSB can be inverted. In the example shown in Fig. 11, the DCT coefficient, whose parity can be inverted, is the last non-zero DCT coefficient, indicated by the address EOB_adrs, stored in the comparator register 62. When the counted value equals the address of the DCT coefficient, whose parity can be inverted, EOB_adrs, comparator 62 states , whether the DCT coefficient is a DCT coefficient, whose parity can be inverted, and changes the signal at the input from zero to one.

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The output of the comparator 62 is fed directly to the second AND gate 68 and, via inverter 72 to the first AND gate 67. Thus, when the count value is not equal to the EOB_adrs address, the first AND gate 61 is open and the second AND gate 68 is closed. Therefore, the DCT coefficients pass unchanged through the first AND AND gate 69 and the 69 OR gate to the IDC cosine inverse transformation circuit.

However, when the DCT discrete cosine transformation coefficient supplied to the parity 28 inverter is a coefficient whose parity can be inverted, and the value of the counter state is equal to the address of the coefficient whose parity can be inverted, in this example EOB_adrs, the output of the comparator 62 changes the state method already described. This closes the first 67 AND gate and opens the second 68 AND gate. As a result, the DCT inverted LSB coefficients, received via the 66 OR gate, are fed via the second AND gate 68 and 69 OR gate to the IDOS cosine reverse inverse transformation system.

The discrete cosineus DCT inverted LSB transformation coefficient is fed selectively to the IDCT cosine reverse inverting system in response to the processing request REQ1 signal when feeding the DCT coefficients received on the RDATA path to the third AND 64 gate and LSB 63 bit inverter. The processing request REQ1 signal is fed from the parity check system 21 directly to the fourth AND gate 65 and via the inverter 71 to the third AND gate system 64. The LSB 63 inverter inverts the LSB bit of each DCT coefficient obtained via the RDATA path and the resulting DCT discrete cosine transform coefficient is fed with the LSB bit inverted to the fourth AND gate 65.

The absence of a processing request REQ1 signal, i.e. when the processing request signal is 0, indicates that the DCT, whose parity can be inverted, is to be fed to the IDCT without inverting its LSB. The processing request signal assuming state 0 opens the third AND 64 gate and closes the fourth 65 AND gate. This results in a DCT coefficient, whose parity can be inverted, with the LSB bit unchanged, from the RDATA path to the IDCT via the third 64 AND gate, 66 OR gate, second AND gate 68 and 69 OR gate.

In contrast, the presence of the processing request REQ1 signal, i.e., when the processing request REQ1 signal is at state 1, indicates that the DCT coefficient whose parity can be inverted is to be transmitted with the LSB bit reversed to change the parity of the sum of the DCT coefficients. The processing request signal REQ1 at state 1 closes the third AND gate 64 and opens the fourth AND gate system 65. This results in a DCT coefficient, whose parity can be inverted, with its LSB bit inverted from the 63 LSB inverter to the 15 cosine IDID inverse transformation system via fourth gate 65 AND, gate 66 OR, gate 68 AND and gate 69 OR.

With reference to Fig. 12, a second embodiment of the parity inverter 28 is described. When the parity inverter 28 in the second embodiment receives the processing request signal REQ1, it gives oddity to the sum of DCT coefficients by adding 1 to the DCT coefficient whose parity can be inverted.

The parity inverter 28 in the second embodiment can be implemented by means of a computer or a digital signal processing processor operating in accordance with the flowchart shown in Fig. 12. The flowchart shown in Fig. 12 is similar to the flowchart shown in Fig. 9, with except for the operation performed in step S3. In step S3, in the second embodiment, the parity inverter 28 gives oddness to the sum of DCT coefficients by adding 1 to the DCT coefficient, whose parity can be inverted, instead of inverting the LSB bit of such DCT coefficient. The DCT, whose parity can be inverted, can be, for example, the last non-zero coefficient in the block or the DCT coefficient of the highest frequency component in the block.

With reference to Fig. 13, a practical configuration of the parity inverter system is described in the second embodiment in which 1 is added to the DCT coefficient, which

173 287 parity can be inverted to give parity to the sum of DCT coefficients in the block.

The parity inverter in the second embodiment shown in Fig. 13 is similar to the parity inverter 28 in the first embodiment shown in Fig. 11. The elements in the arrangement shown in Fig. 13 corresponding to the elements of the arrangement in Fig. 11 are designated with the same reference numerals.

The parity inverter shown in Fig. 13 includes an adder 73 adding unity instead of the LSB 63 inverter shown in Fig. 11. The adder 73 adding unity increases by 1 each DCT coefficient read from memory, first 26 or second 27, and obtained via RDATA paths. In response to the REQ1 signal of the processing request, one of the DCT coefficients is added with unity added to give oddity to the sum of the DCT coefficients.

The operation of the parity inverter shown in Fig. 13 is identical to the inverter of Fig. 11 except that the unity adder 73 increases by 1 each DCT coefficient obtained via the RDATA path. Also, when the processing request signal REQ1 is present, and a factor whose parity can be inverted has been detected, the DCT coefficient with unity added to it is given from the unity addition system to the 15 cosine IDoid inverse transformation system via the fourth AND 64 gate, gate 66 OR, second goal 68 AND and goal 69 OR.

With reference to Figures 14 and 15, a third embodiment of the parity inverter 28 is described. When the parity inverter in the third embodiment receives the processing request signal REQ1, it transmits the odd DCT sum sum by exchanging the DCT coefficient whose parity is to be inverted, to the inverse parity block by subtracting the unity, if the polarity of the DCT coefficient is positive, and by adding unity, if the DCT polarity is negative. This processing method not only causes the DCT parity inversion to be reversed, whose parity is to be inverted, but also reduces its absolute value, i.e. it causes the DCT coefficient values ​​to approach closer to zero. The processing applied to the coefficient whose parity is to be inverted can be determined by the following equation:

if (rec> 0) rec = rec - 1 if (rec <0) rec = rec + 1, (15) where rec is the DCT coefficient, whose parity should be inverted.

The third embodiment of the parity inverter 28 is preferably implemented by means of a computer or a digital signal processing processor operating in accordance with the flow chart shown in Fig. 14. In step S1, the parity inverter 28 checks, based on the EOBB_adrs address, whether DCT is a DCT coefficient, whose parity can be inverted, for example the parity inverter 28 checks if the DCT is the last non-zero coefficient. If the result in step S1 is YES, and the DCT coefficient is a DCT coefficient, whose parity can be inverted, then proceeds to the execution of step S2.

In contrast, when the DCT factor is not a factor whose parity can be inverted, it proceeds to step S8.

At step S2, the parity inverter 28 checks whether the processing request REQ1 signal has been received. If the result of step S2 is YES, indicating that the processing request REQ1 signal has been received, then proceeds to the execution of step S3. Otherwise, if no processing request is received, it proceeds to performing step S8. Because the TAK result in step S2 can only occur if the TAK result in step S1 is received, the TAK result in step S2 indicates that the DCT coefficient is a coefficient whose parity should be inverted.

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In step S3, the parity inverter 28 determines the polarity of the DCT coefficient, which parity should be inverted. If a YES result was obtained in step S3, indicating that the DCT polarity is positive, then proceeds to the implementation of step S4. However, when the DCT polarity is zero or negative, it goes to step S6.

In step S4, the parity inverter 28 subtracts from the DCT coefficient whose parity is to be inverted, i.e. unity is added to it - 1, after which it goes to step S5, where the DCT coefficient with inverse parity is fed to the inverse 15 IDCT cosine transformer system (Fig. 10A). Returns to step S1 in which the transition to processing of the next DCT coefficient takes place.

Otherwise, in step S6, the parity inverter 28 adds unity to the DCT coefficient whose parity is to be inverted, after which it proceeds to step S7, where the DCT coefficient with inverse parity is fed to the IDOS inverse cosineoid transformation. Returns to step S1 in which the transition to processing of the next DCT coefficient takes place.

If the DCT factor is not a factor whose parity can be inverted or when the DCT factor whose parity can be inverted is not to be inverted as to parity, i.e. when no processing request REQ1 signal has been received, then proceeds to performing step S8. At step S8, the DCT is transferred to the IDOS cosineoid inverse transformation system without modification. Then proceeds to the implementation of step S1, where it starts to process the next DCT factor.

Figure 15 shows the practical configuration of the parity inverter system 28 in the third embodiment in which the parity inversion is performed with a decrease in the absolute value of the dCt coefficient, whose parity should be inverted, i.e. with a coefficient whose value after the parity inversion is closer to zero.

The parity inverter shown in Fig. 15 is similar to the parity inverter 28 shown in Fig. 11. The elements in the arrangement shown in Fig. 15 corresponding to the elements of the arrangement in Fig. 11 have the same reference numerals. The parity inverter shown in Fig. 15 differs from the parity inverter shown in Fig. 11 in that it includes an absolute value reduction system 80 instead of the LSB 63 bit inverter.

The absolute value reduction system 80 determines the polarity of each DCT coefficient obtained from memory, first 26 or second 27, via the RDATA path. If the DCT polarity is positive, the absolute reduction system subtracts the unity from the DCT coefficient, while if the DCT polarity is zero or negative, it adds unity to the DCT coefficient. The parity inverting system shown in fig. 15, gives the odd DCT sum of the block coefficients by selecting the DCT coefficient whose parity has been inverted from the absolute value reduction system 80, and inserting this DCT coefficient with the inverse parity and the reduced absolute value instead of the DCT coefficient whose parity should be inverted.

The absolute value reduction system 80 includes polarity detection system 81 that directly controls the fifth gate 84 AND and the sixth gate 85 AND through the inverter 87. The absolute value decrease system 80 also includes a system 82 that subtracts unity and a system 83 for adding unity, which respectively, they subtract unity and add unity to each of the DCT coefficients obtained by the RDATA path. In response to the output signal of the polarity checking system 81, the state of the system 82 subtracting the unity or the output state of the adder adding the unity is selected via the fifth gate 85 AND or the sixth gate 85 AND. The output states of gates 84 and 85 AND are given to gate 86 OR, which passes the selected DCT coefficient with reduced absolute value to the fourth gate 65 AND. When the parity of the sum of DCT coefficients in the block requires inversion, the fourth AND 65 gate selects, inverted in parity and reduced in absolute value, the output state of system 80

173 287 decreasing the absolute value to be fed to the IDCT cosine inverse transformation system instead of the DCT coefficient whose parity is inverted.

The polarity checking system 81 checks the polarity in the DCT coefficient block obtained by the RDATA path, and sets its output state to 1 or 0, depending on whether the DCT coefficient polarity is positive or negative. If the polarity check system 81 determines that the DCT polarity is positive, the output of the polarity check system opens the fifth gate 84 AND and the sixth gate 85 AND closes. This results in the output state of the subtraction system 82, i.e. the DCT coefficient, reduced by one, to the fourth AND gate 65 via the fifth gate AND and gate 86 OR.

In contrast, when polarity recognition system 81 determines that the DCT coefficient polarity is negative or equal to zero, the output state of polarity recognition system 81 closes the fifth AND gate and opens the sixth AND 85 gate system. This results in the output state of the adder 83 adding the unity, i.e. the DCT coefficient, to which the unity has been added, to the fourth AND gate 65 via the sixth gate 85 AND the gate 86 OR.

The fourth AND gate 65 passes the inverted absolute lower DCT coefficient of the absolute value reduction circuit 80 to the second AND gate 68 in response to the processing request signal REQ1. When the comparator 62 determines that the DCT coefficient obtained by the RDATA path is a DCT coefficient, which parity can be inverted, from the absolute value reduction system 80 the DCT coefficient reduced in amplitude and reversed in polarity is given to the IDOS cosine reverse transformation system (fig 10A) as described above with reference to Fig. 11. On the other hand, when the inverter shown in Fig. 15, no processing request REQ1 signal received, DCT coefficient, whose parity can be inverted, is given to IDC cosine inverse transformation 15 as unchanged.

When the sum of DCT coefficients requires making it odd, the parity inverter 28 in the third embodiment, shown in Fig. 15, passes the DCT coefficient DCT whose inverse parity has been inverted by subtracting the unity when its polarity is positive to the IDC 15 reverse cosineoid transformation system, or passes the DCT coefficient inverse to the IDCT 15 which its parity is reversed if its polarity is negative or if it is zero. The treatment causes a parity reversal and reduces the value of the DCT coefficient inverted parity range and gives the DCT sum of the odd parity.

A fourth embodiment of the parity inverter 28 is described with reference to Figs. 16 and 17. When the parity inverter in the fourth embodiment receives the processing request signal REQ1, it transmits the odd DCT sum sum by exchanging the DCT coefficient whose parity is to be inverted, to the block with the inverse parity by adding unity, if the sign of the DCT coefficient is positive, and by subtracting the unity, if the sign of the DCT coefficient is negative. This processing method not only causes the parity of the DCT coefficient to be reversed, whose parity is to be inverted, but also increases its absolute value, i.e. it causes the DCT coefficient values ​​to move farther away from zero. The processing applied to the coefficient whose parity is to be inverted can be determined by the following equation:

if (rec> 0) rec = rec + 1 if (rec <0) rec = rec - 1, (16) where rec is the DCT coefficient whose parity should be inverted.

The fourth embodiment of the parity inverter 28 can be implemented by means of a computer or a digital signal processing processor operating in accordance with a flowchart

173 287 of Fig. 16. At step S1, the parity inverter 28 checks, based on the EOBB_adrs address, whether the DCT is a DCT, whose parity can be inverted or not. For example, the parity inverter 28 checks if the DCT is the last non-zero coefficient. If the result in step S1 is YES, and the DCT coefficient is a coefficient whose parity can be inverted, then proceeds to the execution of step S2. In contrast, when the DCT factor is not a factor whose parity can be inverted, it proceeds to step S8.

At step S2, the parity inverter 28 checks whether the processing request REQ1 signal has been received. If the result of step S2 is YES, indicating that the processing request REQ1 signal has been received, then proceeds to performing step S3. Otherwise, if no processing request is received, it proceeds to performing step S8. Because the TAK result in step S2 can only occur if the TAK result in step S1 is received, the TAK result in step S2 indicates that the DCT coefficient is a coefficient whose parity should be inverted.

At step S3, the parity inverter 28 determines the DCT polarity. If a YES result was obtained in step S3, indicating that the DCT polarity is positive, then proceeds to the implementation of step S4. However, when the DCT polarity is zero or negative, it goes to step S6.

In step S4, the parity inverter 28 adds unity to the DCT coefficient followed by a step to step S5, where the DCT with inverse parity is fed to the IDOS inverse cosine transformer system (Fig. 10A). Returns to step S1, where processing of the next DCT coefficient begins.

Otherwise, in step S6, the parity inverter 28 subtracts the unity from the DCT coefficient (i.e., adds -1 to it), followed by the transition to step S7, in which the DCT coefficient with inverted parity is given to the system of inverse cosineusoidal transformation IDCT. Returns to step S1, where processing of the next DCT coefficient begins.

If the DCT coefficient is not a parity that can be inverted or when the DCT parity that can be inverted is not to be inverted as to parity, i.e. when no processing request REQ1 signal has been received, proceed to step S8. In step S8, the DCT coefficient is passed to the IDOS cosine inverse transformation system without modification. It returns to step S1, where it starts to process the next DCT.

Figure 17 shows the practical configuration of the parity inverter system 28 in the fourth embodiment, in which the parity inversion is performed with an increase in the absolute value of the DCT coefficient subjected to the parity inversion, i.e. with a coefficient whose values ​​after the parity inversion are more distant from zero.

The parity inverter shown in Fig. 17 is similar to the parity inverter 28 shown in Fig. 11. The elements in the arrangement shown in Fig. 17 corresponding to the elements of the arrangement in Fig. 11 have the same references and will not be discussed again. The parity inverter shown in Fig. 17 differs from the parity inverter shown in Fig. 11 in that it includes an absolute value increasing system 90 instead of the LSB 63 bit inverter.

The absolute value increment system 90 determines the polarity of each DCT coefficient obtained from memory, first 26 or second 27, via the RDATA path. If the DCT polarity is positive, then the absolute increase system adds unity to the DCT coefficient, whereas if the DCT polarity is zero or negative, it subtracts the unity from the DCT coefficient. The parity inverting system shown in fig. 17, gives parity to the sum of DCT coefficients in the block by selecting the DCT coefficient whose parity has been inverted from the absolute value increase system, and inserting this DCT coefficient with inverted parity and reduced absolute value instead of the DCT coefficient whose parity should be inverted.

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The absolute value increment system 90 includes a polarity recognition system 91 that directly controls the fifth AND gate 94 and the sixth AND gate 95 via the inverter 97. The absolute value increase system 90 also includes an adder 92 adding unity and a subtractor 93 subtracting unity, which respectively add unity and subtract unity from each of the DCT coefficients. In response to the output state of the polarity recognition system 91, a selection is made, via the fifth gate 94 AND or the sixth gate 95 AND, or the output state of the adder 92 adding unity, or the status of the untractor 93. The output states of goals 94 and 95 AND are given to gate 96 OR, which passes the selected DCT coefficient with increased absolute value to the fourth gate 65 AND. When the parity of the sum of DCT coefficients in the block requires inversion, the fourth AND gate selects, inverted in parity and reduced in absolute value, the output state of the absolute value increase system 90 to be fed to the IDOS inverse cosine transformation system instead of the DCT coefficient, which parity is inverted.

The polarity recognition system 91 checks the polarity in the DCT coefficient block obtained by the RDATA path, and sets its output state to 1 or 0, depending on whether the DCT polarity is positive or negative. If the polarity recognition system 91 determines that the DCT coefficient polarity is positive, then the output state of the polarity recognition system 91 opens the fifth gate 94 AND and the sixth gate 95 AND closes. This results in an initial state that adds 92 unity, i.e. a DCT coefficient, increased by one, to the fourth AND gate 65 via the fifth gate AND AND gate 96.

In contrast, when the polarity recognition system 91 determines that the DCT coefficient polarity is negative or the factor is zero, the output state of the polarity recognition system 91 closes the fifth gate 94 AND and opens the sixth gate 85 AND. This results in the output state of the subtractor 93 subtracting the unity, i.e. the DCT coefficient from which the unity was subtracted, to the fourth AND gate 65 via the sixth gate AND AND gate 96.

The fourth AND gate 65 passes the inverted absolute value DCT coefficient of the absolute value boost system 90 to the second AND gate 68 in response to the processing request signal REQ1. When comparator 62 determines that the DCT coefficient obtained by the RDATA path is a DCT coefficient, which parity can be inverted, from the absolute value increasing system 90 the DCT coefficient increased in amplitude and reversed in polarity is given to the IDOS cosine reverse transformation system (fig 10A) as described with reference to Figure 11.

On the other hand, when the parity inverter in Fig. 17 has not received the processing request signal REQ1, the DCT, whose parity can be inverted, is given to the IDOS cosine inverse transformation system as unchanged.

When the sum of DCT coefficients requires making it odd, the parity inverter 28 in the fourth embodiment shown in Fig. 17, passes the DCT coefficient DCT whose inverse parity has been inverted by adding the unity when its polarity is positive to the IDC cosineusoid transformation 15 system, and gives the DCT coefficient whose inverse parity has been inverted by the IDCT system 15 if its polarity is negative or if it has zero value. The processing causes an inversion of parity and reduces the value range of the DCT coefficient subjected to the inverse parity, and gives the oddness of the sum of DCT coefficients.

The parity inverters 28 shown in Figs. 11,13,15 and 17, and operations according to the flowchart shown in Figs. 9, 12, 14 and 16 can be modified by odding the sum of DCT coefficients when the DCT coefficient changes other than the last non-zero coefficient read at zigzag browsing. For example, in a two-dimensional DCT 8x8 transform you can change the parity of one of the co-numbers

173 287 DCT constant component factors, DCT component factor (7.7), i.e. the highest frequency component, component factor (7, 0), upper right corner of the image, or DCT component (0.7) lower left corner. Since, in particular, the component factor (7, 7), which is the highest frequency component, has little effect on image quality, this component is particularly suitable for the chosen parity reversal factor.

In the parity inverters shown in Figures 11, 13, 15 and 17, other DCT coefficients can be selected than the DCT coefficient, whose parity can be changed by substituting the DCT coefficient address for the EOB_adrs address given to the comparator 62. In contrast, if the parity of the DCT coefficient with the highest frequency is to be changed, then you can omit the 61 reading counter and comparator 62, and to identify the DCT coefficient with the highest frequency as the coefficient whose parity can be changed, you can use the FULL signal memory full.

According to another possibility, the odd parity 14 systems shown in Figures 6, 8 and 10 may determine the sum of special DCT coefficients, e.g. DCT coefficients of the components (0, 0), (4, 0), (0, 4) and (4, 4). Then the odd parity system could do the parity reversal to give the sum of these special DCT coefficients. Fig. 18 shows a variant of the odd oddity system 14 of Fig. 8. In this system, the sum of special DCT coefficients is determined to determine if parity inversion is necessary. The elements of the system shown in Fig. 18 corresponding to the elements of the system of Fig. 6 are designated with the same reference numerals.

In the total oddity system shown in Fig. 18, the selector 51 breaks the connection between the inversion quantizer 13 and the battery 23A. The selector 51 also receives from the counter 20 the count state value coeff_adrs, which indicates the number of DCT coefficients in the block received from the inversion quantizer 13.

Depending on the received value of the coeff .adrs of the counter 20, the selector 51 determines whether each of the DCT coefficients obtained from the inversion quantizer 13 is one of these special DCT coefficients or not and therefore whether it is to be included in the sum determined by the battery 23 A. Thus, for example, the selector determines whether the state value coeff_adrs is a value corresponding to (0, 0), (4.0), (0.4) or (4.4). If the selector 51 determines that the DCT coefficient is one of the special DCT coefficients, then it provides this DCT coefficient to the 23 A battery. Accordingly, the odd odd total system shown in Fig. 18 determines the sum of the special DCT coefficients of the block and if the sum is even, it changes the parity of at least one of the coefficients to give the sum of parity. The total odd parity system shown in Fig. 18 then reports a block of coefficients with corrected parity to the IDOS inverse cosine transform system.

The embodiment shown in Fig. 18 can be modified in a manner similar to the embodiment shown in Fig. 10A to provide the system with the ability to determine the exclusive logical sum of LSB bits of special DCT coefficients. The circuit in Fig. 18 is modified by replacing the adder circuit 23 with the LSB bit detector and the Exclusive-OR gate shown in Fig. 10A.

The DCT coefficients, according to Figure 6, in the DCT coefficient block are reported from the odd odd system 14 to the cosine inverse IDCT inverse transformation system 15 described above. The sum of the DCT coefficients from the total odd oddity system 14 is an odd number. If the sum of the DCT coefficients from the inversion quantizer was an even number, then the odd parity 14 system changes the parity of at least one of the DCT coefficients in order to render the sum of the DCT coefficients fed to the IDOS cosine reverse inverse transformation system 15. The IDCT system on the DCT discrete cosine transform coefficients of the block performs the processing of the inverse IDCT cosine transform to obtain the reproduced S4 block of differences. The reconstructed block S4 of differences is fed to the adder 16.

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Adder 16 performs point-by-point summation of the reconstructed block S4 of differences and matching block S2 obtained from the second group 4 of image memory. The resulting reconstructed S5 image block is fed to the image memory group 4, where it is a block of the reconstructed image stored in one of the image memories designated by the memory controller 3.

The variable length encoder 17 performs variable length coding, e.g. Huffman coding, etc. on each block of quantized SC DCT coefficients from the difference block encoder 9 and encodes its displacement MV vector, MM displacement compensation mode, quantization table data, etc. The variable length encoder 17 also collects the variable length encoded data with start codes and header information of the respective layers according to the MPEG standard to form a compressed moving image signal.

The 5 layers / macroblock counter counts the SS start layers signals and the BS macroblock start signals when reading images from the first group 2 of image memory during processing. When its state reaches the set value, the 5 layers / macroblock counter generates the SO start signal, which is fed to the variable length encoder 17.

In response to the start signal, the variable length encoder 17 feeds the compressed moving image signal to the output buffer 19, where it is stored temporarily. Then, the compressed image signal is read from the output buffer 19 in the form of a data stream with the assumed capacity. The bit stream of the compressed moving image signal is fed to the complementary expander via a transmission path or by recording this bit stream of the compressed moving image signal on a suitable recording medium, e.g. an optical disk.

The recording medium is the medium on which the compressed signal obtained from the moving image signal is recorded, by predictive coding and processing by means of discrete cosine susceptional transformation. Each block of each reconstructed image used as a reference image in predictive coding is reproduced by inverse quantization of the block of quantized DCT coefficients included in the compressed moving image signal, by odding the sum of DCT coefficients in the resulting DCT coefficient block and the reverse orthogonal transformation of the DCT coefficient block subjected to the transmission process their oddities total.

The transmission device preferably comprises the described compressor according to the invention. It may turn out that it would be better to perform the odd parity operation in the compressor 9 block encoder. The operation of giving the odd parity to the sum could cause that the sum of DCT coefficients in each block of quantized DCT coefficients included in the compressed motion image signal would be an odd number. It may turn out that giving the oddness of the total DCT coefficients in the expander will be unnecessary. However, with this solution, after quantizing the DCT coefficients in the compressor and after their inverse quantization in the expander, the sum of the DCT coefficients reaching the IDCT system in the expander may no longer be an odd number. Thus, the total odd odd operation must be performed before IDCT processing in the expander to ensure that there is no mismatch error.

Referring to Fig. 19, an expander of a compressed moving image signal is described. In Fig. 19, the compressed moving image signal is received as a bit stream via a transmission line, from a compressor, or by playing back the compressed mobile signal from a suitable recording medium, e.g. an optical disk. The bit stream is fed to the input buffer 31, where it is subject to temporary storage, and where the image after the image is read to the inverse variable length encoder IVLC 32. The inverse variable length encoder 32 extracts from the compressed image signal the header information of the respective MPEG encoding layers and extracts the PH information from the header information. for controlling image decoding, which is fed to the memory controller 33.

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The IVLC 32 encoder performs inverse variable-length coding on DCT coefficient variable-length coded blocks to obtain blocks of quantized DCT coefficients containing the current block of quantized DCT quantized Cb coefficients. A block of quantized Cb DCT coefficients is delivered to the decoder 34 of the difference block. The difference block decoder 34 decodes a block of quantized DCT Cb coefficients to obtain the reconstructed Cb block of differences, and transfers the reconstructed block of differences to adder 39.

The IVLC encoder 32 extracts from the compressed image signal the MV displacement vector and the MM displacement compensation mode for the block of quantized Cb DCT coefficients, and feeds it to the displacement compensator 37. The displacement compensator 37 causes a readout of the matching block for the reconstructed BS of differences from the group 38 of image memory.

An image memory block consists of several image memories, each of which stores one of the already reconstructed images. The BS matching block is a reconstructed image block in one of the image memories at the address determined by the displacement MV vector. The image memory in the image memory group 38 storing the reconstructed image from which the matching block is read is determined by the memory controller 33.

As already mentioned, the image can be encoded with a prediction, based on a previously reconstructed image, by prediction based on a later reconstructed image, or by prediction based on a block obtained by performing, point by point, a linear operation on a previously reconstructed image and on a later reconstructed image . In addition, the image can be encoded without any prediction. In this case, the matching block provided by the image memory group 38 is a zero block, i.e. a block in which the values ​​of all image points are set to zero. The displacement-compensating matching blocks provided by image memory group 38 are adaptively modified, and the optimal mode is selected for each block. This process is performed using a block of 16x16 image points.

Each of the matching blocks provided by the image memory group 38 is fed to the adder 39. Adder 39 sums, point by point, the reconstructed BS of difference differences obtained from the difference block decoder 34 and the matching block obtained from image memory group 38. The result of this summation is the reconstructed image block, stored in one of the image memory groups designated by the memory controller 33. The reconstructed image blocks produced by the adder 39 are saved one by one in the selected image memory, replacing successively the reconstructed images previously stored in this memory, creating a new reconstructed image. The reconstructed images stored in the image memory group 38 are read in a sequence controlled by a signal indicating the output image provided by the memory controller 33. The read images are given in the form of a reproduced moving image signal to a suitable image display, for example a video monitor. The display produces moving images according to the reproduced moving image signal.

Fig. 19 shows a difference block decoder 34. The difference block decoder 34 includes an inversion quantizer 40, a system for odd odd total 35, and a system of inverse discrete cosine transformations. For the inverse quantization of the block of quantized transform coefficients Cb obtained from the inverse variable length encoder 32, the inversion quantizer 40 uses a quantization table. The odd parity total system 35 receives the resulting DCT coefficient block from the inversion quantizer 40 and prevents mismatch errors from IDCT processing in the IDCT system 36. The IDCT system 36 performs IDCT processing on the block of coefficients given their odd parity, obtained from the odd parity total 35.

Fig. 2θ shows an example of the construction of an inversion quantizer 40. The main components of an inversion quantizer are: 41 layers / levels decoder, address counter 47, address converter 48, selector 49, first memory block 42, second memory block 43 and inversion quantization system (system IQ) 46.

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The 41 layer / level decoder receives a block of quantized Cb DCT coefficients from the inverse variable length coder 32. The layer / level decoder decodes data regarding the type of layer / level coding that has been applied to the quantized DCT coefficients in the variable length compressor encoder. The resulting block of quantized DCT coefficients is fed to the first 42, or second 43, block memory in a zigzag order. Then, each of the block memories, 42 and 43, stores a block of quantized DCT coefficients.

The address counter 47 and the address converter 48 generate respectively: write addresses and read addresses for block memory, first 42 and second 43. Blocks of quantized DCT coefficients are alternately entered and read from the first block memory and the second block memory. Each block of quantized DCT coefficients is entered into one of the block memories in the zigzag order, according to the addresses provided by the address counter 47, and is read from the block memory in the raster order, according to the addresses provided by the address converter 48. Different address order when writing and when read, it results in the conversion of the order of quantized DCT coefficients in the block from zigzag to raster.

The address counter 47 generates entry addresses in a zigzag order. The address converter 48 receives the zigzag order addresses from the address counter and uses the address conversion table to process these addresses into addresses in the raster browsing order. The addresses generated by the address counter 47 and the address converter 48 are selected by the selector 49 to enter into block memories, the first 42 and the second 43, as the addresses adrsl and adrs2. When the block of quantized DCT coefficients from the decoder 41 layers / levels is already written to the block memory, first 42 or second 43, the counter 47 generates and transmits via the selector 49 the appropriate addresses adrs 1 and adrs2, in zigzag order. When reading the quantized DCT coefficients from the first or second block memory 42 to the inversion quantizer 46, the appropriate addresses, adrs1 and adrs2, are given pr: ^^ t ^: of 48 via 49 in raster viewing order.

When all the quantized DCT coefficients in the block have been stored in block memory, first 42 or second 43, the DCT coefficient block is read in raster order to the inverse quantizer IQ 46. The inverse quantizer IQ 46 inverse quantizes the quantized DCT coefficients in the block and reports the DCT coefficient result block to the total odd parity 35. The inverse quantization performed by the IQ 46 inversion quantizer is the same as the inverse quantization performed by the inversion quantizer 13 at the local decoder of the moving image signal compressor shown in Fig. 6.

When the odd parity total system finds that the sum of the DCT coefficients in the coefficient block from the inversion quantizer 4 is even, it processes at least one of the DCT coefficients to give the sum of the DCT coefficients in the odd parity block. The odd odd totaling system 35 provides the DCT coefficient block with the odd total to the IDCT system 36. The sum odding operation 35 carried out by the sum odding system 35 is identical to the operation performed by the sum odding system 14 at the local decoder, the mobile circuit signal compressor shown in Fig. 6.

The IDOS cosine reverse inverse transformation system 36 performs IDCT processing on the DCT coefficient block with the sum oddity given to obtain the reproduced block of differences Bs, which is fed to the adder 39.

The operation of Fig. 20 and the practical operation of the inversion quantizer 40 are illustrated by the flow chart of Figs. 21A-21I. The inverse variable length encoder 32 extracts a block of quantized Cb coefficients from the compressed moving image signal. The variable length encoder generates the EV_EN result enable signal shown in Fig. 21 A, which gives the decoder command 41 layers / levels of reading the block of quantized DCT coefficients. Quantized coefficients

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DCT in a block of quantized DCT Cb coefficients are coded by layers / levels.

The IVLC 32 inverse variable length encoder also generates the EVENT_NO result number signal to the 41 layers / levels decoder as shown in Fig. 21B. The result number signal indicates the number of layer / level pairs in the block of quantized Cb coefficients, i.e. the number of data pairs indicating the layer and level.

When the layer / level decoder 41 receives the result number signal ΕΫΕΝΤ_ΝΟ, it gives the read request signal RE_REQ for each layer / level pair, back to the inverse variable length encoder 32, as shown in Fig. 21C. Each time a read request RE_REQ signal is received, the inverse variable length encoder 32 provides the layer / level 41 pairs / levels with the number of layer / level pairs corresponding to the number of read request signals received.

The 41 layer / level decoder decodes the layer / level encoded quantized DCT coefficients to give their block in zigzag order as WDATA to the first block memory, as shown in Fig. 21G. At the same time, as shown in Fig. The 21F address counter 47 counts the quantized DCT coefficients from the layer / level decoder and provides the adrsl address signal in a zigzag order, indicating the entry address of each of the quantized DCT coefficients, via selector 49 to the first block memory 42.

When the 41 layer / level decoder receives the EOB code from the IVLC 32 inverse variable length encoder, indicating that the last non-zero DCT coefficient has been passed, the 41 layer / level decoder sets the quantized DCT coefficient corresponding to the EOB code, and sets all subsequent DCT quantized coefficients to zero, and gives these zero DCT coefficients to the first block memory 42.

Also, after receiving the EOB code, the 41 layer / level decoder provides the EOB_EN signal to the position register (POS_REG) 44.45 as shown in Fig. 21H. The EOBJEN signal indicates to position registers that an EOB code has been received. The position registers also receive from the address counter 47 via the address converter 48 the address of each quantized DCT coefficient given to the block memories, first 42 and second 43. When the layer / level decoder receives the EOB code, the address generated by the address meter 47 is the address of the last non-zero coefficient. The EOB_EN signal causes the entry of addresses, EOPJPOS, of the last non-zero coefficient, processed into an address in the raster order, using the address converter, to the block memory register positions into which the block of quantized DCT coefficients is entered. Thus, one of POS registers 44 and 45 stores the address of the last non-zero coefficient of the block of quantized DCT coefficients.

After the decoder gives 41 layers / levels of a full block of quantized DCT coefficients to the block memory, first 42 or second 43, the address counter 47 gives the BANK bank switching signal to block memories, the first 42 and second 43. The BANK signal switches the block memory mode, yes that the first block memory that originally worked in write mode is switched to read mode and the second block memory is switched to write mode. Thus, when the layer / level decoder 41 decodes the next quantized DCT coefficient, the resulting quantized DCT coefficients will be written to the second block memory 43. The BANK signal also switches the selector 49 so that the addresses given to the block memory in the write mode are addresses in the zigzag order from the address counter 47, and the addresses given to the block memory in the read mode are the addresses in the raster order from the address converter 48.

Also, when the decoder 41 layers / levels fed the first block of quantized DCT coefficients to the first block memory 42, the first memory block 42 transmits the memory full signal FULL1 to the inversion quantizer 46. The memory full signal indicates that all quantized DCT coefficients in the block have been recorded. When the inverse quantizer IQ 46 receives the FULL1 signal when the memory is full, it passes the read request signal RD_EN to the first block memory 42. The read request signal causes the first block memory to read the quantized DCT coefficients stored in it, corresponding to the addresses 1 adrs given in the raster order by the raster converter 48 via the selector 49. Consequently, the quantized DCT coefficients of the block are read from the first memory. DCT readings for each address are given to the inversion quantizer 46.

Simultaneously with the reading of the quantized DCT coefficients of the block from the first block memory 42, the quantized coefficients of the next block are stored in a zigzag order in the second block memory 43, according to the addresses from the address counter 47.

The inversion quantizer 46 inverse quantizes the quantized DCT coefficients in the block in a similar manner to the inversion quantizer 13 in the moving image signal compressor already described with reference to Figure 5. The resulting DCT coefficient block is given to the odd parity total system 35.

If the sum of the DCT coefficients in the block is an even number, then the total odd parity system affects at least one of the DCT coefficients of the block to render the sum of the block coefficients odd in a similar way as the odd parity system 14 in the moving image signal compressor described. The resulting block of odd-giving coefficients is fed to the 36 cosine IDoid inverse transformation system.

For example, the system for assigning total oddness can be implemented in the form of POS position registers 44.45 and determine whether the current DCT coefficient is the last non-zero coefficient in the zigzag order or not, so that the total oddness system can change the parity of this non-zero coefficient in to obtain the odd parity of the sum of DCT coefficients in the block. In contrast, the odd odd totaling systems 35 can do this by affecting the DCT coefficient of the highest frequency component. It is advantageous to reverse the oddness of the DCT coefficient of the highest frequency component, because the highest frequency component has a small effect on image quality, it is not necessary to determine which DCT coefficient is the last non-zero coefficient. This is also important if the viewing order is other than zigzag.

It should be emphasized that in order to avoid mismatch errors, the system for making the odd parity in the compressor and in the signal expander must be identical.

Fig. 22 shows the configuration of the moving image signal compressor in the second embodiment. Fig. 23 shows the configuration of the odd odd system 50 in the signal compressor in Fig. 22. The elements of the second embodiment of the signal compressor corresponding to the elements of the first example in Fig. 6 are indicated by the same reference numerals. The second embodiment differs from the first total odd odd system 50. The odd parity total system 50 of Figure 23 includes a counter 20 counting the coefficients obtained from the inversion quantizer 13 and reporting the obtained value coeff_adrs to the parity check system 21.

Battery 23A is equipped with adder 23 and register 24. Adder 23 adds each coefficient in the block of coefficients received from the inversion quantizer 13 to the sum of the DCT coefficients already received of the block stored in register 24. Register 24 is reset after determining the sum of all DCT coefficients. The resulting sum of DCT coefficients is given from the adder 23 to register 24 and to the parity check system 21. To obtain a result suitable for the parity checker of the sum of the coefficients, battery 23 only needs the sum of the least significant bits of DCT coefficients in the block.

The parity check system 21 operates according to the count value coeff_adrs obtained from the counter 20 as follows. When the counted value indicates that all block coefficients have already been summed up in battery 23A, the parity check system 21 determines whether the sum of the coefficients obtained from the battery 23A is even or odd. For example, in the case of the two-dimensional DCT 8x8 transformer, when the status value indicates that the sum of all 64 block coefficients has already been determined, the parity check system determines whether the sum of the coefficients obtained from the battery is even or odd.

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In practice, when the DCT coefficients are represented by binary numbers, the parity check circuit 21 checks the least significant bit LSB of the sum of the coefficients from the battery. An LSB bit of 0 indicates that the sum is even. In this case, the parity check circuit 21 sends a processing request signal REQ1 to the parity inverter for it to perform a parity inversion 53. In response to the processing request signal REQ1, the parity inverter 53 changes the parity of at least one (i.e., their odd number) of the coefficients in the block to render their sum. In contrast, LSB = 1 indicates that the sum is odd. In this case, the parity check circuit 21 does not send the processing request signal REQ1, and the parity inverter 53 leaves all block coefficients unchanged because their sum is already odd.

The DCT coefficient block is fed from the inversion quantizer 13 not only to the battery 23A, but also to the parity inverter 53 via the delay system 52. The delay system 52 delays the DCT coefficients in the block by a time corresponding to the processing time of the 23A battery and the parity check system 21, so that the last DCT coefficient, i.e. the highest frequency coefficient, e.g. component ratio (7, 7) in the 8x8 DCT transform, reaches the inverter 53 parity simultaneously with the processing request signal REQ1.

Thus, the parity inverter 53 transmits all the coefficients, except the highest frequency coefficient, to the IDOS cosine inverse transformation in unchanged form. If the parity check system 21 has not generated the processing request signal REQ1, then the parity inverter 53 and the highest frequency coefficient also provide unchanged to the IDOS inverse cosine transforming system 15. The parity inverter 53 inverts the highest frequency coefficient LSB and provides an inverse parity coefficient to the IDCT inverse cosine transform system only if the parity check system 21 has generated a processing request signal REQ1.

Thus, when the parity check system 21 indicates that the sum of the DCT coefficients in the block is even, the parity inverter 53 affects the highest frequency DCT coefficient, e.g. the DCT component (7, 7) in the 8x8 DCT transform in the block. The parity inverter 53 inverts the parity of the highest frequency DCT component, i.e. it gives the oddity to the sum of the coefficients in the coefficient block given to the IDOS inverse cosine transform system. Thus, the sum of DCT coefficients in the block is always odd. The DCT factor of the component (7, 7) is the factor that has the least effect on the IDCT output values.

Practical examples of the preferred embodiment of the odd odd total 50 are described below. Fig. 24 shows an example in which the LSB bit detector 29 and the Exclusive-OR gate (EXOR) replace the adder 23 in Fig. 23. The components of the system shown in Fig. 24 corresponding to the components of the system shown in Fig. 23 same references. The LSB bit detector 29 examines each LSB bit of each block coefficient, and the EXOR gate 30 and logical sum register 24 together determine the exclusive logical sum of the LSB bits of the DCT coefficients in the block. The parity of the exclusive logical sum is determined by the parity check system 21 in the manner described with reference to Figs. 10A and 23.

In contrast, also the Exclusive-OR gate and register 24, shown in figure 24, can be replaced by gate 88 AND and counter 89, shown in figure 10B.

Fig. 25 shows another embodiment. In this example, a selector 51 is inserted between the inversion quantizer 13 and the battery 23 in the odd odd total system 50 shown in Fig. 23. The elements of the system shown in Fig. 25 corresponding to the elements of the system shown in Fig. 23 are marked with the same links. The system shown in fig. 25, calculates the sum of DCT coefficients based solely on special coefficients, e.g. component (0.0), (4.0), (0.4) and (4.4) to determine whether it is necessary to give oddity to the sum. Selector 51 takes the count value coeff_adrs from counter 20 to determine if each set of DCT coefficients obtained from the quantizer

173 287 inverse 13 is one of the special factors or not, and therefore is to be added together. When the selector determines that the DCT coefficient is one of the special coefficients and is to be added up, i.e. the count value coeff_adrs has a value corresponding to, for example, the component (0.0), (4.0), (0.4) or (4.4) ), the selector 51 gives the coefficient for the 23A battery. The selector 51 causes the odd parity system to determine the sum of FIG. 25, determining the sum of special coefficients. Then, the parity inverter 53, if necessary, changes one of the special DCT coefficients to make the sum of these coefficients an odd number. The block of coefficients, the sum of which has been made odd, is then fed to the IDOS inverse cosine transformation system.

In another embodiment, the selector 51 shown in Fig. 25 can be inserted in the line between the inversion quantizer 13 and the LSB bit detector 29 in the system shown in Fig. 24. The system thus modified, shown in Fig. 24, determines the exclusive sum logical LSB bits of special DCT coefficients selected by the selector.

In another embodiment, the odd parity total system 50 when the last DCT coefficient received from the inversion quantizer 53 is a DCT constant component, that is, when the raster viewing order is opposite to the one mentioned above, the DCT coefficient on which the parity inversion operation is performed does not corresponds to the highest frequency component, but is a DCT constant component.

In the example related to Fig. 26, an example of practical configuration of the parity inverter 53 is discussed. The parity inverter 53 is a simplified version of the described parity inverter 28 shown in Fig. 11. The parity inverter 53 is equipped with an LSB 63 bit inverter, AND gates, third 64 and fourth 65, gate 66 OR and inverter 71.

In the 53 parity inverter, the LSB 63 inverter inverts the LSB bit of each DCT coefficient in the coefficient block obtained from that obtained from the inversion quantizer 13. It performs the parity inversion of each DCT coefficient. Usually the processing request signal REQ1 does not occur so that the parity inverter forwards each of the received DCT coefficients to the IDC inverse cosine transform (Fig. 25) via the third AND 64 gate and 69 OR gate.

If the odd parity total system 53 (Fig. 23) received the highest frequency DCT coefficient in the block, the value of coeff_adrs from the counter 20 indicates the parity check system 21 that the value obtained by this system is the sum of all DCT coefficients in the block. In response to this, the parity determination system checks whether the sum of the coefficients is even or not.

If the parity check system 21 determines that the sum of the DCT coefficients in the block is even, it provides the processing request signal REQ1 to the parity processing inverter 53. The processing request signal reaches the parity inverter 53 via the delay 52 simultaneously with the highest frequency DCT. The processing request REQ1 signal changes the state of AND gates 64, and 64 gates 65. This transfers the inverted LSB coefficient from the 63 LSB inverter to the IDCT system via the fourth AND 65 gate and 69 OR gate. The highest frequency coefficient with inverted LSB bit is fed to the IDCT system in place of the normal highest frequency coefficient in order to give oddity to the sum of the coefficients fed to the IDCT system.

However, when the parity check system finds that the sum of the coefficients is odd, it does not produce a processing request signal. The parity inverter 53 supplies the normal DCT coefficient of the highest frequency to the IDCT system via the 64 AND gate 69, because the odd parity of the sum of the block coefficients is not needed.

Figures 27-29 show practical modifications of the parity inverter 53 shown in Fig. 26. Fig. 27 shows the +1 adder system similar to Fig. +1 in Fig. 13 replacing the 63 LSB inverter in the parity inverter shown in Fig. 26 .

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In addition, the layout is not changed. The parity inverter modified as shown in Fig. 27 inverts the parity of each of the DCT coefficients in the block by adding unity to it. Thus, when the parity check system 21 reports. the processing request signal REQ1 to the parity inverter, the parity inverter to the IDCT system gives the highest frequency DCT coefficient with unity added instead of the normal high frequency DCT coefficient. This substitution makes the sum of DCT coefficients in the block odd.

As shown in Fig. 28, the absolute value reduction system 80 shown in Fig. 15 can be replaced with the LSB bit 63 inverter from the system shown in Fig. 26. The system shown in Fig. 26 also does not change. The parity inverter shown in Fig. 26, modified as shown in Fig. 28, gives oddness to the sum of DCT coefficients according to equation (15). When the parity check system 21 generates the processing request REQ1 signal, the total DCT coefficients of the block are given an odd parity by providing the highest frequency coefficient to the inverse cosine IDID inverse transform parody. The parity of the highest frequency DCT coefficient is changed in one of two ways: either the subtractor 82 is subtracted from the highest frequency DCT coefficient when the highest frequency DCT coefficient is positive, or the unity is added to this coefficient in adder 83, when the highest DCT coefficient frequency is zero or negative.

As shown in Fig. 29, the absolute value increase system 90 shown in Fig. 17 replaces the LSB bit inverter 63 in the system shown in Fig. 26. The system shown in Fig. 26 also does not change. The parity inverter shown in Fig. 26, modified as shown in Fig. 29, causes the odd parity of the DCT coefficients to be given according to equation (16). When the parity check circuit 21 generates the processing request REQ1 signal, the total DCT coefficients of the block are given an odd parity by providing the highest frequency coefficient to the IDCT inverted parity. The parity of the highest frequency DCT coefficient is changed in one of two ways: either the subtractor 93 is subtracted from the DCT coefficient of the highest frequency when the highest frequency DCT coefficient is zero or negative, or the unity is added to this coefficient in the adder 92 when the coefficient The highest frequency DCT is positive.

A second embodiment of the compressed moving image signal expander will now be described. In this second embodiment of the compressed moving image signal expander, the odd parity total system 50 has been replaced with the total odd odd system 35, from the first example of a compressed decoder of a moving image signal shown in Fig. 19. The arrangement shown in Fig. 19, otherwise change. In this second embodiment of the compressed moving image signal, the odding of the sum of the coefficients of the block is performed in a similar manner to the process performed by the oddity totaling system in the second embodiment of the moving image signal compressor shown in Fig. 22. In this second embodiment of the compressed moving image signal expander, it is not necessary to provide the EOB_adrs address from the inverse variable length encoder 32 to the total odd parity system 50.

The solution according to the invention makes it possible to implement a method of inverse discrete cosine transformation and a device for inverse discrete cosine transformation, a moving image signal compressor, a compressed moving image expander, and a transmission device for a compressed moving image signal in which there is a danger of mismatch error occurring while performing a discrete cosine transformation, to to this degree virtually no mismatch errors.

If a discrete cosinusoidal transformation is used to compress the moving image signal, and inverse discrete cosineusoidal transformation is used for expansion,

173 287, the invention allows the prevention of mismatch errors of discrete cosine transformations. This prevents image degradation. Accordingly, in the case of the moving image signal compressor and this signal expander, there is no danger that the locally decoded images in the compressor and the images reconstructed by the expander will be different. Thus, it is ensured that high image quality is obtained.

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