Inverse discrete cosine transform method, inverse discrete transform apparatus, coding apparatus for moving picture, decoding apparatus for moving picture, information recording medium, and transmitting apparatus

INVERSE DISCRETE COSINE TRANSFORM METHOD, INVERSE DISCRETE TRANSFORM APPARATUS, CODING APPARATUS FOR MOVING PICTURE, DECODING APPARATUS

FOR MOVING PICTURE, INFORMATION RECORDING MEDIUM, AND TRANSMITTING APPARATUS

Field of the Invention

This invention relates to an inverse discrete cosine transform method, an inverse discrete transform apparatus, a coding apparatus for moving picture, a decoding apparatus for moving picture, an information recording medium, and a transmitting apparatus, and more particularly to an inverse discrete cosine transform method, an inverse discrete cosine transform apparatus, a coding device for moving picture, a decoding apparatus for moving picture, an information recording medium, and a transmitting apparatus which are suitable for data compression of a picture signal.

Description of the Prior Art

Orthogonal transformation is used in various uses in diverse digital signal processing systems. Orthogonal transformation permits implementation of signal processing in the frequency region. As the orthogonal transformation, Fast Fourier Transform (FFT), and Discrete Cosine Transform (DCT), etc. are widely known. These orthogonal transformations decompose a time series signal into different frequency components (varying in dependency upon an orthogonal function system applied) to indicate what frequency components constitute the original time series signal. By implementing various processing to these frequency components, e.g., redundancy can be reduced. Further, by carrying out inverse transform processing, original signal can be obtained.

As an example of digital signal processing systems using such orthogonal transform processing, there are a coding apparatus for a picture signal and a decoding apparatus therefor.

For signals having higher correlation, it is known that signal powers concentrate in a lower frequency region on the frequency axis (base). According as the degree of concentration of signal power on a specific coordinate axis (e.g., frequency) is higher, reduction of redundancy can be made to much more degree, resulting in more improved coding efficiency.

Since picture signals generally have higher correlation, orthogonal transform processing is carried out to concentrate powers on a specific coordinate axis, thereby making it possible to realize efficient coding.

Hitherto, a moving picture signal represented by a video signal in the NTSC television system has an extremely great information quantity. In order to record/reproduce such a moving picture signal for long time as it is, the data transmission rate was extremely high, and a large capacity of a recording medium was required. In more practical sense, a recording device using, e.g., a magnetic tape or an optical disc as a recording medium became large-sized.

In view of the above, in the case of recording a video signal onto a more compact recording medium for a long time, it is indispensable to implement efficient coding or higher compressive coding to a video signal to record a coded signal, and to efficiently decode the signal read out. To meet such a requirement, various systems have been proposed as an efficient coding system utilizing correlation between frames or fields of a video signal. Interframe correlation will be mainly described below. In actual terms, e.g., so called MPEG (Moving Picture Experts Group) system is widely known. Since this MPEG system has been already widely introduced in various literatures, the detailed explanation thereof is omitted here.

In accordance with this MPEG system, an approach is employed to first take a difference between frames of a video signal to thereby lower redundancy in a time axis (base) direction thereafter to lower redundancy in a spatial axis direction by using Discrete Cosine Transform (hereinafter referred to as DCT) processing which is a sort of orthogonal transform processing. In this way, a video signal is extremely efficiently coded. Further, in the case of recording the video signal efficiently coded in this way onto a recording medium, e.g. , an optical disc, etc. to reproduce the coded signal therefrom, an approach is employed to decode DCT coefficients obtained by the DCT processing by using Inverse Discrete Cosine Transform (IDCT) processing to reproduce the video signal.

A coding apparatus for a moving picture based on the MPEG system is constructed as shown in Fig. 1, for example.

In this coding apparatus, a picture signal is inputted to a block format circuit 101, at which conversion from the standard format, e.g., the NTSC system, etc. to a block format, e.g., every macro block of 16x16 pixels is carried out. The picture signal converted into the block format is delivered to a motion predictive circuit (predictor) 102. Further, an output of the motion predictor 102 is delivered to a difference detector 103.

The difference detector 103 is supplied with a motion-compensated picture signal, as a reference picture signal, from a group of field memories 112 of field memories 112A to 112D through a predictive element (predictor) 113. The difference detector 103 detects a difference between the both picture signals to deliver a difference signal to a DCT circuit 104 for carrying out DCT processing as orthogonal transform processing.

The DCT circuit 104 implements DCT processing to the difference signal to deliver DCT coefficients to a quantizer 105. The quantizer 105 quantizes the DCT coefficients. A coded signal from the quantizer 105 is caused to undergo variable length coding at a variable length encoder 106 for carrying out variable length coding, e.g., so called Huffman coding or run length coding, etc., and is then transmitted to, e.g., a digital transmission path as a variable length code through a buffer 107.

It is to be noted that a signal corresponding to data storage quantity is fed back to the quantizer 105 for the purpose of preventing overflow or underflow. The quantizer 105 determines so called a quantizing step so that data storage quantity does not overflow or underflow, in correspondence with the above-mentioned signal.

The coded signal outputted from the quantizer 105 is delivered to an inverse quantizer 108, at which an inverse quantizing processing complementary to the quantizing processing at the quantizer 105 is carried out. As a result, DCT coefficients are reproduced. The DCT coefficients thus reproduced are delivered to an IDCT coefficient 109. The IDCT circuit 109 carries out IDCT processing complementary to DCT processing at the DCT circuit 104 to reproduce a difference signal. The difference signal thus reproduced is delivered to an adder 110.

The adder 110 is supplied with the picture signal from the field memory group 112 motion-compensated at the predictor 113. Accordingly, the adder 110 adds the difference signal from the IDCT circuit 109 to the picture signal from the field memory group 112 to reproduce a picture signal. The picture signal thus reproduced is delivered to any one of field memories 112A to 112D through a selector 111, and is stored thereinto.

On the other hand, the motion predictor 102 detects, every macro block, e.g., a motion vector between frames and a sum of absolute values of differences between respective pixels (hereinafter referred to as an absolute value difference sum) to deliver these data (motion vector and absolute value difference sum) to a predictive mode determinating circuit 115.

The predictive mode determinating circuit 115 determines, on the basis of these data, a predictive mode indicting which frame is used for obtaining a picture signal as a reference picture signal, e.g., any of predictive modes described below.

(1) Mode where no prediction is carried out to output I picture.

(2) Forward-predictive mode where prediction is carried out from a prior frame forward in point of time to output P picture.

(3) Bidirectionally-predictive mode where prediction is carried out from two frame of a prior frame forward in point of time and a later frame backward in point of time to output B picture (e.g. , a reference macro block from a prior frame and a reference macro block from a later frame are caused to undergo linear operation every pixel (e.g., average value calculation).

Namely, I picture is a picture in which intraframe coding completed within a frame, p picture is predicted from a frame forward in point of time (past) (I picture or P picture). B picture is predicted from a frame forward in point of time (past) (I picture or P picture) and a frame backward in point of time (future) (I picture or P picture).

The predictive mode determining circuit 115 delivers the determined predictive mode and motion vector to the predictor 113 and a readout address generator 114. The readout address generator 114 varies readout address of the field memory group 112 on the basis of the motion vector. The predictor 113 selects any one of picture signals from field memories 112A to 112D on the basis of the predictive mode. Thus, a motion-compensated picture signal is delivered to the difference detector 103 as a reference picture signal from the predictor 113.

A decoding apparatus for a moving picture based on the MPEG system is constructed as shown in Fig. 2, for example.

In this decoding apparatus, a variable length code from the coding apparatus or a variable length code obtained by reproducing a recording medium is inputted to a buffer 121 as a bit stream along with a predictive mode and a motion vector, and is temporarily stored thereinto.

This.variable length code is read out from the buffer 121, and is then delivered to an inverse variable length coder (IVLC) 1222. The variable length coder 122 implements inverse variable length coding (variable length decoding) to the variable length code thus to reproduce a coded signal.

This reproduced coded signal is delivered to an inverse quantizer 123. The inverse quantizer 123 inverse-quantizes the coded signal every block on the basis of a quantization step taken out from the bit stream to reproduce DCT coefficients. An IDCT circuit 124 implements IDCT processing to the DCT coefficients to reproduce a difference signal. Namely, the inverse quantizer 123 and the IDCT circuit 124 operate complementarily with respect to quantizer 105 and DCT circuit 104 shown in Fig. 1, respectively.

A readout address generator 130 varies each readout address of field memories 128A to 128D on the basis of the motion vector delivered from the inverse variable length coder 122. A predictor 129 selects any one of picture signals from the field memories 128A to 128D on the basis of the predictive mode. Thus, a motion-compensated picture signal is delivered from the predictor 129 to an adder 125.

The adder 125 adds the difference signal from the IDCT circuit 124 to the picture signal from the predictor 129 to reproduce original picture signal. The picture signal thus reproduced is stored into any one of field memories 128A to 128D as a next reference picture signal.

Picture signals stored in field memories 128A to 128D are read out by readout addresses that a display address generator 127 generates, and are outputted through a selector 126. The picture signal thus outputted is converted to a picture signal having a predetermined number of scan lines by a scan converter (not shown), etc., and is displayed on a display, e.g., so called CRT, etc. In this example, a synchronizing signal generator 131 generates a frame pulse signal as a periodic signal caused to be synchronized with an external period signal delivered from display, for example, thus to deliver it to the display address generator 127. The display address generator 127 generates a readout address in synchronism with the frame pulse signal.

Meanwhile, in an orthogonal transform device such as a DCT circuit (hereinafter referred to as a DCT device) used in the coding apparatus and decoding apparatus described above, since input/output data is an integer, operation is truncated at a finite word length. For this reason, if the accuracy or the configuration of the operation of real number varies, operation result varies, resulting in the problem that miss-match may take place.

Let now consider the case where, in the coding apparatus, after an input is orthogonally transformed, a predetermined processing is implemented thereto in the frequency region to encode the input thus processed to transmit it. In this case, in the decoding apparatus, if the real number operation accuracy or the configuration of the inverse orthogonal transform device is not in correspondence with that of the coding apparatus, there is the possibility that its output result may be varied. Namely, there occurs the problem that decoded result varies in dependency upon a decoding apparatus employed.

As the orthogonal transform processing, Fast Fourier Transform and DCT, etc. are widely known as described above. As a more practical example of orthogonal transform processing, DCT will now be described below. It is to be noted that it is needless to say that this invention may be similarly applied to other orthogonal transform processing within a scope which does not depart from the gist of this invention.

While explanation will be given in the case where DCT is applied to a coding apparatus for moving picture (particularly apparatus employing the MPEG system), this י invention may be similarly applied in other digital signal processing systems, and is effective. It is now assumed that the MPEG system includes both MPEG1 system and MPEG2.

Also in the case of IDCT, there are instances where the operation accuracy or the configuration may vary in dependency upon an IDCT device employed. For example, there is the possibility that a signal decoded by a certain IDCT device and a signal decoded by another IDCT device may. be different from each other. This is called an IDCT miss-match error (hereinafter simply referred to as a miss-match error).

In the MPEG system, the operation accuracy of DCT, IDCT is prescribed,, but the operation method and the configuration are not prescribed by any means. This is because the DCT device and the IDCT device have been developed before the standard of the MPEG system is determined.

In the MPEG system, as described above, the coding device implements, e.g., interframe motion compensating predictivecoding to a picture signal to form a difference signal between frames to implement DCT transform processing to the difference signal to implement quantizing processing and variable length coding to DCT coefficients thus obtained to transmit a variable length code to a decoding device, or to record it onto a recording medium.

On the other hand, the decoding device implements inverse variable coding and inverse quantizing processing to an inputted variable length code to implement IDCT processing to DCT efficient thus obtained to reproduce (decode) an interframe difference signal to add the difference signal to a picture signal of a predetermine frame already decoded to thereby obtain an original picture signal.

Namely, the coding device includes therein so called a local decoding unit for carrying out predictive coding (comprised of inverse quantizer 108 and IDCT circuit 109, etc. shown in Fig.

1).

If the configuration of IDCT unit of the coding device and IDCT unit of the decoding device are different from each other, there are instances where a . local decode picture signal reproduced at the coding device and a reproduced picture signal obtained at the decoding device may be different from each other.

In other words, there are instances where if variable length codes generated by a coding device in conformity with the MPEG are recorded onto recording media such as an optical disc, etc. to sell them to reproduce those optical discs by decoding devices manufactured and sold by various makers, the picture quality of a reproduced picture may be different from the original one independency upon a decoding device used.

Further, in the case the coding device is used in broadcasting equipment, etc., there are instances where the picture quality of a reproduced picture may be different from the original one in dependency upon a receiving device used.

Such miss-match error is particularly of problem in the case where interfield or interframe predictive-coding is carried out. Interframe prediction will be mainly described below. In the interframe predictive-coding, there is the possibility that such miss-match errors may be gradually accumulated, giving rise to fatal failure in a reproduced picture signal.

Meanwhile, in the above-described coding based on the MPEG system, one so called video sequence is divided into GOP (Group of pictures) with eight or twelve frames being as a unit, and each frame is classified into three kinds of frames as described above.

Namely, there kinds of frames are respectively called I picture, P picture and B picture. I picture is intraframe coding frame, P picture is a frame for carrying out motion compensating prediction (prediction with motion compensation) from a past frame, and B picture is a frame for carrying out motion compensating prediction from past and future frames.

I picture is a picture independent by itself, and its missmatch error is completed within that picture.

On the other hand, B picture is a picture for carrying motion compensating prediction from both directions of past and future, but B picture itself is not referenced in motion compensating prediction. Namely, miss-match produced in B picture has not influence on other pictures.

However, in the case of P picture, when any miss-match error takes place, such miss-match error of P picture would be accumulated in a frame memory for carrying out predictive-coding. Accordingly, when interframe predictive-coding is carried out, error in the frame memory gradually becomes large. Such error is accumulated until refreshed by I picture.

In more actual sense, as shown in Fig. 3, when it is assumed that miss-match error produced in I picture is El, and miss-match error produced in decoding P picture P^ is EPl, an error included in a decoded (reproduced) picture signal of P picture P1 takes a value expressed as EI+EP1. Further, when miss match error produced in decoding P picture P. is assumed to be EP2, an error included in a decoded picture signal of P picture P2 takes a value expressed as EI+EP1+EP2. Even if individual miss-match errors are a small value, when those values are gradually accumulated, there results an error of a large value.

For miss-match error produced by the IDCT processing at this time, there exist two kinds of errors described below.

(1) Error resulting from insufficiency of operation accuracy.

(2) Error resulting from difference of method of round-off.

The operation accuracy is prescribed by the standard of MPEG. However, this standard is not sufficient to such an extent that any miss-match error does not takes place. Therefore, even between IDCT devices which satisfy this standard, there is the possibility that miss-match error may take place. The miss-match error of (1) results from the above.

Since an output of the IDCT device is an integer, after the real number operation of the IDCT processing is carried out, the operation result must be rounded. In general, the operation result is rounded into the nearest integer. However, it is the problem that number of *. 5 (* is an integer has taken place.

In the MPEG system, the operation method is not prescribed. Namely, in the case where number of *. 5 has taken place, its handling is not prescribed in any sense. Some IDCT devices carry out processing to round up this, and other IDCT devices carry out processing to round down this. Further, there are instances where rounding method may vary in dependency upon sign of positive or negative number. The miss-match error of (2) is a miss-match error produced by difference of the rounding method.

The difference of the property of the miss match errors of (1) and (2) will now be described. It is. considered that the miss-match error of (1) is generated at random in directions of +1, -1. Accordingly, it is considered that in the case where predictive-coding is repeated for a long time, those miss-match errors will be averaged.

On the other hand, since the miss-match error of (2) is a miss-match error inherent in the IDCT device itself, it results in a miss match error only in one direction of +1 or -1. Accordingly, when the predictive-coding is repeated for a long time, such miss match errors will be accumulated in one direction. Although individual miss-match errors are +1 or -1, if those errors are accumulated in one direction, the resultant miss match error takes a large value.

Namely, since miss-match errors of (1) will be averaged although temporarily generated, this miss-match error does not provide so great problem. On the contrary, since miss match errors of (2) are accumulated in one direction, this miss-match error provides great problem.

Namely, it is required to solve the miss-match error of (2) having accumulative property.

In order to solve the miss-match error of (2), it is proposed in the MPEG1 system to carry out such a rounding processing to allow all DCT coefficients to be odd number with respect to coefficients of components except for (0, 0) component which is DC component in intraframe coding macro block (hereinafter referred to as an intra macro block) prior to implementation of IDCT processing. As shown in Fig. 4, for example, DCT coefficients of (0, 1) component, (7, 1) component, (2, 3) component, (5, 3) component, (1, 5) component, (6, 5) component, (3, 7) component and (4, 7) component are all 568.

Since this number is even number, this number is caused to be e.g., 567. As the result of the fact that IDCT processing is implemented to the rounding-processed DCT coefficients, no fraction takes place at all times.

Further, since the DC component of the intra macro block is « a signal important from a visual point of view among picture signal, its accuracy is only limited to 8 bits without allowing it to be odd number. On the other hand, DCT coefficients of interframe coding macro block (hereinafter referred to as a non-intra macro block)are caused to undergo processing similar to that of DCT coefficients of components except for DC component of the intra macro block, thus to limit DCT coefficients only to odd number.

The processing for limiting a value inputted to the IDCT device to odd number in this way is called oddification processing.

By carrying out such an oddification processing, a coding device (encoder) and a decoding device (decoder) carry out rounding processing in accordance with a rule common thereto, thus making it possible to maintain compatibility of the picture quality.

However, oddification processing of the MPEF1 has not solved miss-match error having accumulative property in essence, and therefore cannot completely remove it.

Further, because of such oddification processing, quantizing step which is an interval of quantization level cannot be set to 1. Namely, this lowers the accuracies of respective frequency components of DCT, resulting in the cause of deterioration of the picture quality. In such cases that high picture quality is required, this is problem.

With the above in view, an object of this invention is to provide a method and an apparatus which effectively solve missmatch error having accumulative property described above, and such that accuracies of input coefficients, i.e., accuracies of respective frequency components of orthogonal transformation are not lowered.

Particularly, an object of this invention is to provide an inverse discrete cosine transform method and an inverse discrete cosine transform apparatus which effectively solve miss-match error.

In addition, an object of this invention is to provide a coding apparatus for a moving picture, a decoding apparatus for a moving picture, an information recording medium, and a transmitting apparatus which can allow deterioration of picture quality as minimum as possible, and effectively remove missmatch.

Summary of the Invention

The cause that the above-described accumulative miss-match error having accumulative property takes place results from the fact that *. 5 takes place in IDCT processing. Let consider the case where value of *. 5 takes place. Explanation will now be given by taking an example of two-dimensional DCT of 8x8 used in the MPEG system.

Two-dimensional IDCT of 8x8 is expressed by the following equation (1).

f(x,y)= 7־ΣΣ C(u)C(v)F(u,v) cos (12x71) cos () 4 u0־ v=0 16 16

U,v,x,y=o,l..7 --. (1)

C(u),C(v)= — (u,v=o) /2 =l(u,v*0)

In the above formula, F(u, v) is DCT coefficients in the two-dimensional DCT. By the above equation (1), an output value in the IDCT processing (hereinafter simply referred to as IDCT) is real number, i.e., rational number or irrational number. Because *. 5 is rational number, in the case where output value of IDCT is irrational number, the above-described accumulating type miss-match error does not take place. In contrast, in the case where that number is rational number, there is the possibility that output value may be *. 5.

At this time, F(0, 0) F(0, 4), F(4, 0), F(4, 4) are special coefficients where output value of IDCT is rational number in the case where only those coefficients have non-zero value. Output values of IDCT in this case is expressed by the following equation (2).

f(x,y)= 4f<00&#1523;>

f(x,y)= —— F(0, 4) cos-~:z 4/2 f(x,y)= —^-F(4,0) COS Χ+1π f(x,y)= cos--x^n-±~

2/&amp;#1490;

(2) &amp;#1470;.&amp;#1470;.

Thus, in the case where only F(0, 0),F(0, 4), F(4, 0), F(4, 4) respectively have non-zero value, output value is equal to *. 5 when that value is a value which is multiple of 4 and is not multiple of 8.

Let now consider the case where only the four coefficients have non-zero value. Output value in this case is expressed by the following equation (3).

f (x,y)= ±F(0,0) + —^-F(0,4) cos-27/1π.*.—— F(4,0) 4 4/2 4 4/2 2 + -F(4,4) cosncos-^&amp;#971;π

4 4 . (3)

The equation (3) is indicated by any expression of the following equation (4) by combination of (x, y) . (4)

[F(0,0)+F(0,4)+F(4,0)+F(4,4)] 8

A [F(0,0)+F(0,4)-F(4,0)-F(4,4) ]

&amp;#1505; i [F(0,0)-F(0,4)+F(4,0)-F(4,4) ] o &amp;#1498;

&amp;#1470;. [F(0,0)-F(0,4)-F(4,0)+F(4,4)] 8

Thus, in the case where the equation (4) is multiple of 4 and is not multiple of 8, . 5 takes place.

As stated above, in the case where non-zero coefficients take place in the above-mentioned four coefficients, there is high possibility that output value of IDCT is equal to *. 5.

Also except for the four coefficients, (1) in the case where non-zero values take place only in X(2n+1, 2m+l), X(2m+1, 2n+l), and those values are the same value and take a value which is multiple of 4 and is not multiple of 8, or (2) in the case where non-zero values take place in X(2n+1, 2n+l), X(8-2n-l, 8-2n-l), and those values are the same and take a value which is multiple of 4 and is not multiple of 8, etc., output value of IDCT is equal to * . 5 . in the above expressions, the X(i, j) is each frequency component in two-dimensional DCT of 8x8.

In the case where an actual picture signal is coded by the

MPEG system, when generation pattern of DCT coefficients where output value of IDCT is equal to *. 5 is examined, there are a large number of instances where non-zero coefficients exist in the above-mentioned pattern. Particularly, in the above-mentioned four coefficients, non-zero values take place in most cases. Accordingly, it is required to solve such a missmatch.

As described above, since *. 5 most frequently takes place in the pattern where four coefficients have non zero values, measure is taken for such case, thereby making it possible to lower generation probability of miss-match error.

. A method for inverse-quantizing intra macro block and non-intra macro block in the MPEG1 is shown in Fig. 5.

In this figure, QAC (i. j) is (i, j) component of DCT coefficient, Wi(i, j) is weight matrix, mquant is quantization coefficient, and rec (i, j ) is inverse-quantized DCT coefficient. Respective quantized DCT coefficients are inverse-quantized, and are then inputted to IDCT unit. At this time, in the case where DCT coefficient is even number, +1 or -1 is added thereto to carry out a processing so that a value inputted to IDCT is always odd number.

In accordance with this operation, in the case where, e.g. , only F(0,0) has non-zero value, when the fact that miss-match takes place when F(0, 0) is multiple of 4 and is not multiple of 8 is taken into consideration, the value which has undergone IDCT processing cannot be equal to *. 5.

Similarly, in the case where only any. one of F(0, 4), F(4, 0), F(4, 4) has non-zero value, miss match error does not take place. However, in the case where plural coefficients of the above-mentioned four coefficients have non-zero value or in such cases of (1),.(2) mentioned above, occurrence of miss match error cannot be prevented.

Namely, in the oddification processing of MPEG1, in the case where the number of DCT coefficients having non-zero value is two or more, occurrence of miss-match error cannot be prevented.

The object of this invention contemplates effectively and easily solving occurrence of miss-match error which could not be solved by the conventional system. A method of preventing missmatch in this invention will now be described.

When examination of the equation (4) is conducted, respective expressions of the equation (4) have the same parity (even/odd property). Namely, in the case where one expression is even number, all expressions will be even number.

Accordingly, in the case where one or plural coefficients of the above-mentioned four coefficients have non-zero value, or in the cases of (1), (2), sum of DCT coefficients when miss-match error takes place is even number. Namely, in the case where sum of DCT coefficients is even number, it is sufficient to carry out processing for preventing occurrence of miss-match error. For example, in two-dimensional DCT of 8x8, in the case where sum of inputted DCT coefficients is even number, there is the possibility that miss-match error may take place. Accordingly, by prohibiting this, occurrence of the miss-match error can be prevented. Namely, sum of coefficient inputted to IDCT is caused to be odd number at all times. Thus, occurrence probability of miss-match error can be lowered.

Namely, in this invention, a scheme is employed to inverse-quantize DCT coefficients prior to implementation of IDCT processing thereafter to calculate a sum of DCT coefficients to allow the sum of DCT coefficients to be always odd number thereafter to carry out IDCT processing.

In this case, as a method of oddification, it is enough to apply an operation only to one DCT coefficient to oddify its sum. Especially, it is sufficient to apply an operation to a coefficient which has least influence on output value of IDCT.

In other words, in this invention, by oddifying sum of DCT coefficients inputted to IDCT unit, occurrence of miss-match error can be effectively prevented. In regard to an operation to oddify sum of DCT coefficients, it is sufficient to apply an operation only one DCT coefficient. Oddifying individual DCT coefficients in MPEG1 implies that the accuracy of a value inputted to IDCT unit is equal to 1/2. The operation to oddify sum of DCT coefficients does not decrease the accuracies of input and output values when compared to the above. When this method is applied to a coding apparatus for a moving picture, a decoding apparatus for a moving picture, or a transmitting apparatus, deterioration . of the picture quality can be as minimum as possible.

In addition, in the case where this method is applied to the MPEG system, while minimum quantization coefficient (quantization step) was 2 in the MPEG1, minimum quantization coefficient can be equal to 1 in accordance with this invention.

Brief Description of the Drawings

Fig. 1 is a diagram showing the configuration of a coding apparatus for a moving picture of a conventional MPEG system.

Fig. 2 is a diagram showing the configuration of a decoding apparatus for a moving picture of the conventional MPEG system.

Fig. 3 is a view for explaining the sequence of moving picture proposed in the MPEG.

Fig. 4 is a view showing an actual example of DOT coefficient.

Fig. 5 is a view for explaining a method of inverse-quantizing a macro block of a conventional MPEG1 system.

.Fig. 6 is a diagram showing the configuration of a first embodiment of a coding apparatus for a moving picture according to this invention.

Fig. 7 is a view showing zigzag scan of DCT coefficient.

Fig. 8 is a view showing a more practical configuration of an oddification operation element constituting the coding apparatus for moving picture.

Fig. 9 is a flowchart for explaining a more practical operation of an oddification processor constituting the oddif!cation operation element.

Fig. 10 is a view showing another more practical configuration of the above-mentioned oddification operation element.

Fig. 11 is a view showing a more practical configuration of the above-mentioned oddification processor.

Fig. 12 is a flowchart for explaining another more practical operation of the above-mentioned oddification processor.

F1£. 13 is a view showing a further more practical configuration of the above-mentioned oddification processor.

Fig. 14 is a flowchart for explaining another actual operation of the above-mentioned oddification processor.

Fig. 15 is a view showing a further actual configuration of the above-mentioned oddification processor.

Fig. 16 is a flowchart for explaining an other actual operation of the above-mentioned oddification processor.

Fig. 17 is a view showing a further actual configuration of the above-mentioned oddification processor.

Fig. 18 is a view showing a still further configuration of the above-mentioned oddification operation element.

Fig. 19 is a diagram showing the configuration of a first embodiment of a decoding apparatus for a moving picture according to this invention.

Fig. 20 is a diagram showing an actual configuration of an oddification operation element constituting the above-mentioned decoding apparatus for moving picture.

Fig. 21 is a time chart for explaining the operation of the above-mentioned oddification operation element.

Fig. 22 is a diagram showing the configuration of a second embodiment of a coding apparatus for a moving picture according to this invention.

Fig. 23 is a view showing an actual configuration of an oddification operation element constituting the above-mentioned coding apparatus for moving picture.

Fig. 24 is a view showing another actual configuration of the above-mentioned oddification operation element.

Fig. 25 is a view showing a further actual configuration of the above-mentioned oddification operation element.

Fig. 26 is a view showing an actual configuration of an oddification processor constituting the above-mentioned oddification operation element.

Fig. 27 is a view showing another actual configuration of the above-mentioned oddification processor.

Fig. 28 is a view showing a further actual configuration of the above-mentioned oddification processor.

Fig. 29 is a view showing a still more further actual configuration of the above-mentioned oddification processor.

Fig. 30 is a diagram showing the configuration of a second embodiment of a decoding apparatus for a moving picture according to this invention.

Description of the Preferred Embodiment

Preferred embodiments of an inverse discrete cosine transform method, an inverse cosine transform apparatus, a coding apparatus for amoving picture, a decoding apparatus for a moving picture, an information recording medium, and a transmitting apparatus will now be described with reference to the attached drawings.

In this embodiment, this invention is applied to a hybrid coding system in which motion compensating predictive coding and Discrete Cosine Transform (DCT) are combined. This hybrid coding system is studied in H. 261 or ISO-IEC/JTC1/SC2/WG11 (popularly named MPEG) of CCITT (Consultative Committee International Telegraph and Telephone) which is an international committee for coding standardization of moving picture, and is also employed in coding of a moving picture for a storage media. This hybrid coding system is a popularly known system.

The motion compensating predictive coding is a method for reducing redundancy that a picture signal has, by making use of correlation in a time axis (base) direction of a moving picture signal. In accordance with this method, an approach is employed to conduct motion compensating prediction of a picture signal which is to be coded at present, from a picture signal already decoded to encode a motion-compensated predictive error thus obtained to transmit it along with a motion vector and a predictive mode, etc. at that time to thereby compress information quantity. «

As a circuit for encoding the motion-compensated predictive error signal, there is a difference signal encoder for carrying out coding by making use of correlation in a spatial axis direction. As an example of the difference signal encoder, a system in which DCT and quantization are combined is representative. DCT is a transform system which concentrates signal powers on a specific frequency component by intraframe (or intrafield) two-dimensional correlation that a picture signal has to transmit only concentrated and distributed coefficients, or to further implement coding thereto thus to compress information quantity. The motion compensating predictive coding may be carried out with a frame being as a unit. Further, in the case of a picture signal such as an interlaced picture signal, such motion compensating predictive coding may be carried out with a field being as a unit. In addition, the both coding systems may be adaptively switched in dependency upon the property of a picture signal.

First Embodiment

An actual configuration of a coding apparatus for a moving picture to which this invention is applied is shown in Fig. 6.

A picture signal (video signal) is delivered to a first group of field memories 2, and is temporarily stored thereinto. A memory controller 3 controls readout of the first group of field memories 2 and a second group, of field memories 4. Further, the memory controller 3 delivers a slice start signal SS and a macro block start signal BS to a slice/macro block counter 5 in synchronism with the leading portion of a picture or the leading portion of a macro block read out from the first field memory group 2 which is to be coded at present.

A motion predicting circuit (predictor) 6 implements motion prediction of pixels in a picture to.be coded at present to a picture signal stored (accumulated) in the first field memory group 2 by making reference to a past picture and a future picture. This motion prediction is block matching between a block picture signal in a picture to be coded at present and a block picture signal of a past picture or a future picture to be referenced, and the size of block is, e.g., 16x16 pixels. Past and future reference picture signals at this time are designated (specified) from the first field memory group 2 in accordance with a motion predictive reference picture indication signal outputted from the memory controller 3. The motion compensator 6 delivers, to a motion compensating circuit (compensator) 7, as a motion vector MV, a block position in a reference picture where a predictive error in the block matching is minimum.

The motion compensator 7 instructs output of a block picture signal positioned at an address specified by the motion vector MV from the second field memory group 4 in which picture signals already decoded are stored. A reference picture at this time is designated (specified) from the second field memory group 4 in accordance with a motion compensation reference picture indication signal outputted from the memory controller 3.

In actual terms, as the predictive mode, there are a predictive mode from a past reproduced picture, a predictive mode from a future reproduced picture, a predictive mode from both past and future reproduced pictures (a reference block from a past reproduced picture and a reference block from a future reproduced picture are caused to undergo linear operation every pixel) (e.g., average value calculation), and a mode with no prediction (i.e., intraframe (so called intra) coding mode, and an output of a block picture signal from second field memory group 4 is equivalently zero). Motion-compensated block picture signals read out from second field memory group 4 are caused to be an adaptively modified signal, and an optimum one is selected every block.

In switching of these predictive modes, e.g., a predictive mode in which a sum of absolute values of difference values every pixel between respective block picture signals outputted in the four kinds of modes and a block picture signal to be coded at present is minimum is selected. The predictive mode selected here is outputted to a variable length coder 17 which will be described later as a motion compensation mode signal MM.

A block picture signal SI to be coded at present delivered from first field memory group 2 and a block picture signal S2 delivered from second field memory group 4 are delivered to a subtracter 8. This subtracter 8 calculates a difference value every pixel to deliver a block difference signal thus obtained to a difference signal encoder 9. This -difference signal encoder 9 encodes the block difference signal S3 to form a coded signal SC. This coded signal SC is delivered to a difference signal decoder 10, at which it is decoded. Thus, a block reproduced difference signal S4 is reproduced. It is to be noted that difference signal decoder 10 in the coding apparatus for moving picture is generally called a local decoder, and has a configuration similar to a decoding apparatus for moving picture which will be described later, but is distinguished therefrom.

The difference signal encoder 9 and the difference signal decoder 10 will now be described.

The difference signal encoder 9 comprises, as shown in Fig. 6 mentioned above, a DCT circuit 11 and a quantizer 12 for quantizing an output of the DCT circuit 11. The DCT circuit 11 implements DCT processing to block difference signal S3 delivered from subtracter 8 to deliver DCT coefficients to quantizer 12. The quantizer 12 quantizes the DCT coefficients to output the coded signal SC.

The difference, signal decoder 10 comprises, as shown in Fig. 6 mentioned above, an inverse quantizer 13 for inverse-quantizing coded signal SC from quantizer 12 by using a quantization table, an oddification operation element 14 for carrying out an operation such that no miss-match error takes place in implementing IDCT (Inverse Discrete Cosine Transform) processing to an output of the inverse quantizer 13, and an IDCT circuit 15 for implementing IDCT processing to an output of the oddification operation element 14.

Actual quantization at the quantizer 12 will now be described. Quantization is carried out every block of 8x8 pixels. Initially, in intraframe coding macro block (so called an intra macro block, which will be simply referred to as intra), division with rounding is implemented to DCT coefficient of DC component (hereinafter referred to as DC coefficient) by 8 at 8 bit accuracy, 4 at 9 bit accuracy, 2 at 10 bit accuracy, and 1 at 11 bit accuracy as indicated by the following equation .(5), thus to determine a quantization level QDC.

<td> QDC = de // 8</td>

<td> QDC = de // 4 (9 bits)</td>

<td> QDC = de // 2 (10 bits) . (5</td>

<td> QDC = de // 1 (11 bits)</td>

QDC : quantized DC coefficient

With respect to respective DC coefficients except for the

DC component of intra (hereinafter referred to as AC components), quantization factor ac’(i, j) is determined by the following equation (6).

ac'(i,j) = (16 * ac(i,j)) // Wi(iJ) . (6)

In the above equation, Wi is intra quantization matrix and coefficients are indicated by the following equation (7).

<td> Wi = 8</td><td> 16</td><td> 19</td><td> 22</td><td> 26</td><td> 27</td><td> 29</td><td> 34</td>

<td> 16</td><td> 16</td><td> 22</td><td> 24</td><td> 27</td><td> 29</td><td> 34</td><td> 37</td>

<td> 19</td><td> 22</td><td> 26</td><td> 27</td><td> 29</td><td> 34</td><td> 34</td><td> 38</td>

<td> 22</td><td> 22</td><td> 26</td><td> 27</td><td> 29</td><td> 34</td><td> 37</td><td> 40</td>

<td> 22</td><td> 26</td><td> 27</td><td> 29</td><td> 32</td><td> 35</td><td> 40</td><td> ־(7) . 48</td>

<td> 26</td><td> 27</td><td> 29</td><td> 32</td><td> 35</td><td> 40</td><td> 48</td><td> 58</td>

<td> 26</td><td> 27</td><td> 29</td><td> 34</td><td> 38</td><td> 46</td><td> 56</td><td> 69</td>

<td> 27</td><td> 29</td><td> 35</td><td> 38</td><td> 46</td><td> 56</td><td> 69</td><td> 83</td>

Then, by the following equation (8), quantization factor ac~ (i, j) is quantized to determine quantization levels QAC of respective AC coefficients.

QAC(i.j) = [ac'(i,j)+sign(ac(i, j))* ((p*mquant)//q)j/(2*mquant). (8)

QAC : quantized AC coefficient

In the above equation, p and q are a fixed arbitrary integer, and p=3 and q=4 are used, for example.

On the other hand, in quantization of interframe coding macro block (so called non-intra macro block, which will be simply referred to as non-intra macro block, which will be simply referred to as non-intra), quantization factor ac’(i, j) is determined by the following equation (9) with respect to all DCT coefficients of non-intra.

ac’(i, j) = (16 ♦ ac(i,j)) // Wn(i,j) 9) .&amp;#1523;)

In the above formula, wn is non-intra quantization matrix and coefficients thereof are indicated by the following equation (10).

<td> Wn = 16</td><td> 17</td><td> 18</td><td> 19</td><td> 20</td><td> 21</td><td> 22</td><td> 23</td>

<td> 17</td><td> 18</td><td> 19</td><td> 20</td><td> 21</td><td> 22</td><td> 23</td><td> 24</td>

<td> 18</td><td> 19</td><td> 20</td><td> 21</td><td> 22</td><td> 23</td><td> 24</td><td> 25</td>

<td> 19</td><td> 20</td><td> 21</td><td> 22</td><td> 23</td><td> 24</td><td> 26</td><td> 27</td>

<td> 20</td><td> 21</td><td> 22</td><td> 23</td><td> 25</td><td> 26</td><td> 27</td><td> 28 .. (10)</td>

<td> 21</td><td> 22</td><td> 23</td><td> 24</td><td> 26</td><td> 27</td><td> 28</td><td> 30</td>

<td> 22</td><td> 23</td><td> 24</td><td> 26</td><td> 27</td><td> 28</td><td> 30</td><td> 31</td>

<td> 23</td><td> 24</td><td> 25</td><td> 27</td><td> 28</td><td> 30</td><td> 31</td><td> 33</td>

Then, by the following equation (11), quantization factor ac'(i, j) is quantized to determine a quantization level QAC.

QAC(i,j) = ac~(i,j) / (2*mquant) if (mquant==odd) = (ac'(i,j)+l / (2*mquant) if (mquant==even AND ac-<0). (11) = (ac~(i,j)-l / (2*mquant) if (mquant==even AND ac->0)

The quantization level QAC (hereinafter simply referred to as quantization level) thus obtained is delivered to Variable Length Code (hereinafter referred to as VLC) element 17 and difference signal decoder 10 as the above-described coded signal

SC.

The VLC element 17 implements variable length coding to the quantization level obtained by quantizing DCT coefficients, in a more practical sense, VLC element 17 determines differences of quantization levels of four luminance blocks for forming a macro block with respect to intra DC coefficient to implement variable length coding to the difference values thus obtained by using VLC table. This is because adjacent four luminance blocks have high correlation, so DC coefficients have substantially the same value. Further, VLC element 17 determines differences&amp;#1470; of quantization levels of color difference blocks to implement variable length coding to the difference value by using VLC table. It is to be noted that the VLC table for luminance and VLC table for color difference are different from each other.

On the other hand, VLC element 17 reads out quantization level by zigzag scan having (0, 0) component at its leading portion as shown in Fig. 7 with respect to intra AC coefficient to implement variable length coding thereto. Namely, in DCT processing, since values generally concentrate in the vicinity of (0, 0) component, such a path is employed, thereby making it possible to effectively carry out variable length coding. In actual terms, VLC element 17 determines, by zigzag scan, values (levels) of coefficients of non-zero and the number (run) of 0 coefficients preceding thereto to carry out two-dimensional variable length coding by combination of (run, level), ,thereafter to add code EOB comprised of 2 bits indicating that the non-zero coefficient is last after the last non-zero coefficient. Further, VLC element 17 delivers, to address converter (not shown), an address indicating the position of the last non-zero * coefficient in order of zigzag scan. This address converter converts address in zigzag scan to address EOB adrs in raster scan to deliver this address EOB adrs to oddification operation element 14.

This address EOB adrs is stored into a register 25 of oddification operation element 14 which will be described later.

The inverse quantizer 13 will now be described.

The inverse quantizer 13 inverse-quantizes quantization level delivered as coded signal SC from difference signal encoder 10 to reproduce (decode) DCT coefficients. In actual terms, inverse quantizer 13 inverse-quantizes quantization level by the following equation (12) with respect to intra DC coefficients to reproduce DCT coefficients. Further, inverse quantizer 13 inverse-quantizes quantization level by the following equation (13) with respect to intra DC coefficients to reproduce DCT coefficients. In addition, inverse quantizer 13 inverse-quantizes quantization level by the following equation (14) with respect to all DCT coefficients of non-intra.

rec (1,1) = 8 * QDC rec(1,1) = 4 *QDC (9 bits) rec(1,1) = 2 * QDC (10 bits) . (12) rec(l,l) = 1 * QDC (11 bits) rec(i,j) = (mquant * 2 * QAC(i.j) * Wi(i,j)) / 16 if(QAC(i,j) == 0) rec(i,j) = 0 . (13) if(QAC(i,j) >0) rec(i,j) = ((2*QAC(i,j)+1) mquant*Wn(i,j ) )/16 if(QAC(i,j) < 0) rec(i,j) = ((2*QAC(i,j)-1)*mquant*Wn(i,j))/16 if(QAC(i,j) == 0) . (14) rec(i,j) = 0

The DCT coefficients thus reproduced are delivered to oddification operation element 14.

The oddification operation element 14 comprises, as shown in Fig. 8, for example, an adder 23 for determining sum of plural DCT coefficients from inverse quantizer 13, an even/odd judge element 21 for judging whether sum of DCT coefficients from adder 23 is even number or odd number, and an oddification processor 28 such that when sum of DCT coefficients is even number as the result of judgment by even/odd judge element 21, it implements an operation to at least one input coefficient to oddify sum of

DCT coefficients. The oddification operation element 14 implements, in order to prevent occurrence of IDCT miss-match error, an operation to at least one DCT coefficient to oddify sum of DCT coefficients, thus to deliver the plural DCT coefficients caused to undergo such operation to IDQT circuit 15.

In actual terms, counter 20 counts the number of DCT coefficients delivered from inverse quantizer 13 to deliver the count value coeff adrs thus obtained to even/odd judge element 21 and memory selector 22.

The adder 23 adds DCT coefficient delivered from inverse quantizer 13 and sum of preceding DCT coefficients preserved in register 24 to deliver sum of DCT coefficients thus obtained to the register 24, and to deliver the sum of DCT coefficients to even/odd judge element 21. It is to be noted that addition at the adder 23 may be addition of LSBs (Least Significant Bits) of DCT coefficients.

The even/odd judge element 21 carries out even/odd judgment by making reference to count value coeff adrs delivered from counter 20. Namely, when all DCT coefficients are added in the adder 23, i.e., sum of 64 DCT coefficients is determined, e.g., in the case of two-dimensional DCT transform of 8x8, the even/odd judge element 21 judges whether sum of DCT coefficients from adder 23 is even number or odd number. In more practical sense, for example, when DCT coefficients is assumed to be represented by binary number, even/odd judge element 21 judges of LSB of sum of DCT coefficients delivered from adder 23, i.e., preserved in register 24. Since when LSB is zero, sum is even number, even/odd judge element 21 outputs processing request signal REQ1 to oddification processor 28 in order to carry out oddification operation. On the other hand, since when LSB is 1, sum is odd number, even/odd judge element 21 does not output processing request signal REQ1. The oddification processor 28 implements an operation to at least one DCT coefficient on the basis of processing request signal REQ1 to oddify sum of DCT coefficients.

In actual terms, DCT coefficients from inverse quantizer 13 are stored into a first memory 26 or a second memory 27 through memory selector 22. Namely, the memory selector 22 operates as follows on the basis of count value coeff adrs delivered from counter 20. Namely, for example, when all DCT. coefficients are stored into first memory 26, the memory selector 22 specifies memory so that DCT coefficients are stored into second memory 27 to carry out switching of memory for storing DCT coefficients. At this time, first and second memories 26 and 27 which have stored all coefficient data respectively output memory full signals FULL1, FULL2 to oddification processor 28.

When the oddification processor 28 receives memory full signal FULL1 or memory full signal FULL2, it reads thereinto DCT coefficients from a memory which has produced that memory full signal to operate as follows on the basis of presence or absence of processing request signal REQI from even/odd judge element 21.

Namely, when processing request signal REQI is delivered, the oddification processor 28 inverts LSB of last non-zero coefficient in zigzag scan that address EOB adrs stored in register 25 indicates. As a result, sum of non-zero coefficients from the beginning to the last is caused to be even number. It is to be noted that oddification processor 28 delivers other DCT coefficients to IDCT circuit 15 as they are. Namely,, this oddification processor 28 operates in accordance with the flowchart shown in Fig. 9, for example.

At step SI, oddification processor 28 judges on the address EOB adrs whether or not a corresponding DCT coefficient is a coefficient to be oddified. As a result, if so, the processing proceeds to step S2. If not so, the operation proceeds to step S5.

At the step S2, oddification processor 28 judges presence or absence of processing request signal REQI. As a result, when processing request signal REQ1 is present, the operation proceeds to step S3. In contrast, when that request is absent, the operation proceeds with step S5.

At the step S3, oddification processor 28 inverts LSB to allow the operation to proceed to step S4 . to output DCT coefficient of which LSB is inverted.

On the other hand, at the step S5, when DCT coefficient should not be oddified, or processing request signal REQI is absent, oddification processor 28 outputs DCT coefficient as it is. Then, the operation returns to the step SI.

It is to be noted that the above-mentioned LSB may be LSB in representation of 2&amp;#1523; complement, or in the case where number is represented in such a manner it is divided into sign (polarity) and absolute value, the above-mentioned LSB may be LSB thereof, i.e., LSB on the absolute value side.

Meanwhile, the configuration of oddification operation element 14 is not limited to the configuration shown in Fig. 8 mentioned above. For example, as shown in Fig. 10, in place of adder 23 constituting oddification operation element 14 shown in l

Fig. 8, there may be used a LSB detector 29 for detecting LSB of DCT coefficient ; and an exclusive logical sum (hereinafter referred to as EXOR) circuit 30 for exclusive logical sum of the LSB and an output of the register 24. In the oddification operation element 14 thus constructed, sum of LSBs of DCT coefficients is determined by EXOR circuit 30 and register 24. It is to be noted that the same reference numerals are respectively to the same circuits as circuits constituting oddification operation element 14 shown in Fig. 8 mentioned, and their explanation is omitted here.

An actual circuit configuration of oddification processor 28 will now be described.

Oddification processor 28 comprises, as shown in Fig. 11, for example, a plurality of gate circuits 64, 65, 67, 68; and logical sum (hereinafter referred to as OR) circuits 66, 69, thus to carry out oddification of sum of DCT coefficients.

Namely, when readout counter 61 receives a memory full signal FULL from first memory 26 or second memory 27, it starts count operation, and delivers a read enable signal RD_EN to first memory 26 or second memory 27 to caj;ry out readout of DCT coefficients from the first memory 26 or second memory 27. As a result, DCT coefficients are sequentially read out from first memory 26 or second memory 27, and are then delivered to first gate circuit 67.

Further, readout counter 61 delivers its count value to a comparator 62. The comparator 62 compares the count value and address EOB adrs delivered from register 25 to judge whether or not DCT coefficient delivered to first gate circuit 67 is a coefficient to be subjected to oddification operation. In actual terms, the comparator 62 operates so that when count value is in correspondence with address EOB adrs, this circuit judges a corresponding coefficient to be a coefficient to be subjected to oddification operation, it outputs 1, while when not so, it outputs 0.

Thus, when address EOB adrs and count value are not in correspondence with each other, first gate circuit 67 is opened, and second gate circuit 68 is closed. Thus, DCT coefficients are outputted to IDCT circuit 15 through OR circuit 69 as they are.

On the other hand, when address EOB adrs and count value are in correspondence with each other, first gate circuit 67 is closed and second gate circuit 68 is opened. As a result, oddified DCT coefficients delivered through OR circuit 66 are outputted to IDCT circuit 15. Namely, DCT coefficients read out from first memory 26 or second memory 27 are delivered to third gate circuit 64 and LSB inverter 63, and processing request signal REQI from even/odd judge element 21 is inputted to fourth gate circuit 65. This processing request signal REQI is also inputted to third gate circuit 64 through inverter 71. The LSB inverter 63 inverts LSB of DCT coefficient to deliver this DCT coefficient to the fourth gate circuit 65. When processing request signal REQI is absent, i.e., processing request signal is zero, third gate circuit 64 is opened and fourth gate circuit 65 is closed. As a result, DCT coefficient is delivered to IDCT circuit 15 through OR circuit 66, second gate circuit 68 and OR circuit 69 as it is.

On the other hand, when processing request signal REQI is present, i.e., processing request signal REQI is 1, third gate circuit 64 is closed and fourth gate circuit 65 is opened. As a result, DCT coefficient of which LSB is inverted by LSB inverter 63 is delivered to IDCT circuit 15 through OR circuit 66, second gate circuit 68 and OR circuit 69.

Another actual example of oddification processor 28 will now be described.

This oddification processor 28 is adapted so that when processing request signal REQI is inputted, it adds 1 to DCT coefficient of the highest frequency component (hereinafter referred to as highest frequency coefficient) to carry out oddification of sum of DOT coefficients.

In actual terms, this oddification processor 28 operates in accordance with the flowchart shown iq Fig. 12, for example. Namely, this oddification processor 28 adds 1 to the highest frequency coefficient at step S3 in place of inverting of LSB of last non-zero coefficient at step S3 of the flowchart shown in Fig. 9 mentioned above to thereby carry out oddification processing of DCT coefficients. Meanwhile, the highest frequency coefficient would be fluctuated by adding 1. However, since the highest frequency coefficient has extremely small influence on the picture quality, deterioration of the picture quality can be extremely small in this oddification processor 28.

Actual circuit configuration of oddification processor 28 adapted for adding 1 to the highest frequency coefficient to carry out oddification processing will now be described. This oddification processor 28 includes a +1 adder 73 for adding 1 in place of LSB inverter 63 constituting the oddification processor 28 shown in Fig. 11, and is adapted to add, at.this +1 adder 73, 1 to DCT coefficient read out from first memory 26 or second memory 27 to carry out oddification processing of sum of DCT coefficients. It is to be noted that the same reference numerals are respectively attached to the same circuits as circuits constituting oddification processor 28 shown in Fig. 11 mentioned above, and their explanation is omitted here.

A further actual example of oddification processor 28 will now be described.

This oddification processor 28 is such that when processing request signal REQI is inputted, it subtracts 1 when DCT coefficient is positive and adds 1 when DCT coefficient is negative so that the last non-zero coefficient becomes close to zero by the following equation (15), for example, to thereby carry out oddification processing of sum of DCT coefficients.

if(rec > 0) rec = rec - 1 if (rec < 0). _ (15), rec = rec + 1 rec: coefficient subject to oddification operation

In actual terms, this oddification processor 28 operates in accordance with the flowchart shown in Fig. 14, for example.

At step SI, oddification processor 28 judges on the basis of address EOB adrs whether or not a corresponding DCT coefficient is a coefficient to be oddified. As a result, if so, the operation proceeds to step S2. In contrast, if not so, the operation proceeds to step S8.

At the step S2, oddification processor 28 judges presence or absence of processing request signal REFI. As a result, when processing request signal is present, the operation proceeds to step S3, while when that signal is absent, the operation proceeds to step S8.

At the step S3, oddification processor 28 judges polarity of DCT coefficient. As a result, when DCT coefficient is positive, the operation proceeds to step S4, while when that coefficient is zero or negative, the operation proceeds to step

S6.

At the step S4, oddification processor 28 subtracts 1 from DCT coefficient (adds -1 thereto) thereafter to allow the operation to proceed to step S7 to output the 1 subtracted DCT coefficient.

On the other hand, at step S6, oddification processor 28 adds 1 to DCT coefficient thereafter to mallow the operation to proceed to step S7 to output 1 added DCT coefficient.

At step S8, when DCT coefficient is not a coefficient to be oddified or processing request signal is absent, oddification processor 28 outputs DCT coefficient as it is. Thus, the operation returns to the step SI.

Actual circuit configuration of oddification processor 28 adapted for carrying out oddification processing so that the last non-zero coefficient becomes close to zero will now be described.

The oddification processor 28 includes, as shown in Fig. 15, for example, a polarity judgment processing circuit 80 in place of LSB inverter 63 constituting the oddification processor 28 shown in Fig. 11.

This polarity judgment processing circuit 80 is operative so that when DCT coefficient is positive, it subtracts 1 from DCT coefficient read out from first memory 26 or second memory 27, while when DCT coefficient is 0 or negative, it adds 1, thus to carry out oddification processing of sum of DCT coefficients. It is to be noted that the same reference numerals are respectively attached to the same circuits as circuits constituting the oddification processor 28 shown in Fig. 11 mentioned above, and their explanation is omitted here.

The polarity judgment processing circuit 80 comprises, as shown in Fig. 15 mentioned above, a polarity judge element 81, a -1 subtracter 82 for subtracting -1, and a +1 adder83 &amp;#1523; for adding 1. The polarity judge element 81 judges polarity of DCT coefficient to output 1 when positive and to output 0 when 0 or negative.

Thus, when DCT coefficient is positive, fifth gate circuit 84 is opened and sixth gate circuit 85 is closed. As a result, DCT coefficient from which 1 is subtracted at -1 subtracter 82 is delivered to the above-described fourth gate circuit 65 through OR.circuit 86.

On the other hand, when DCT coefficient is negative or zero, fifth gate 84 is closed and sixth gate 85 is opened. Thus, DCT coefficient to which 1 is added at +1 adder 83 is delivered to the above-described fourth gate circuit 65 through OR circuit 86. As a result, from the oddification processor 28, DCT coefficient in which when DCT coefficient is positive, 1 is subtracted, while when DCT coefficient is negative 1 is added so that the last non-zero coefficient becomes close to zero is outputted to the above-described IDCT circuit 15. It is to be noted that, also in this oddification processor 28, when no processing request signal REQI is inputted, DCT coefficient is delivered to IDCT circuit 15 as it is.

A further actual example of oddification processing circuit 28 will now be described.

This oddification processor 28 is such that when processing request signal REQI is inputted, it adds 1 when DCT coefficient is positive and subtracts 1 when DCT coefficient is negative so that the non-zero coefficient is away from zero by the following equation (16), for example, to thereby carry out oddification processing of sum of DCT coefficients.

if(rec >0) rec = rec + 1 if(rec < 0). . (16) rec = rec - 1 rec: coefficient subject to oddification operation

In actual terms, this oddification processor 28 operates in accordance with the flowchart shown in Fig. 16, for example. Namely, the oddification processor 28 adds 1 at step S4 in place of subtraction of 1 at step S4 of the flowchart shown in Fig. 14 mentioned above, and subtracts 1 at step S6 in place of addition of 1 at step S6 of the flowchart shown in Fig. 14 mentioned above to thereby add 1 ' when DCT coefficient is positive and the subtract 1 when DCT coefficient is negative so that the last non-zero coefficient is away from zero, thus to carry out oddification processing of sum of DCT coefficients.

Actual configuration of oddification processor 28 adapted for oddification processing so that the last non-zero coefficient . is away from zero will now be described.

This oddification processor 28 comprises, as shown in Fig. 17, for example, a polarity judgment processing circuit 90 in place of LSB bit inverter 63 constituting oddification processor 28 shown in Fig. 11.

This polarity judgment processing circuit 90 is such that when DCT coefficient read out from first memory 26 or second memory 27 is positive, it adds 1 thereto, while when that DCT coefficient is zero or negative, it subtracts 1 therefrom, thus to carry out oddification processing of sum of DCT coefficients. It is to be noted that the same reference numerals are respectively attached to . the same circuits as circuits constituting oddification processor 28 shown in Fig. 11 mentioned above, and their explanation is omitted here.

The polarity judgment processing circuit 90 comprises, as shown in Fig. 17 mentioned above, a polarity judge element 91, a +1 adder 92 for adding 1, and -1 subtracter 93 for subtracting 1. The polarity judge element 91 judges polarity of DCT coefficient to output 1 when DCT coefficient is positive, and to output 0 when DCT coefficient is negative.

Thus, when DCT coefficient is positive, fifth gate circuit 94 is opened and sixth gate circuit 95 is closed. As a result, DCT coefficient to which 1 is added at +1 adder 92 is delivered to the above-described fourth gate circuit 65 through OR circuit 96.

On the other hand, when DCT coefficient is negative or 0, fifth gate circuit 94 is closed and sixth gate circuit 95 is opened. Thus, DCT coefficient from which 1 is subtracted at -1 subtracter 93 is delivered to the above-described fourth gate circuit 65 through OR circuit 96. As a result, from the oddification processor 28, DCT coefficient in which when DCT coefficient is positive, 1 is added, while when DCT coefficient is negative, 1 is subtracted so that the last non-zero coefficient is away from zero is outputted to the above-described IDCT circuit 15. It is to be noted that, also in this oddification processor 28, when no processing request signal REQI is inputted, DCT coefficient is delivered to IDCT circuit 15 as it is.

Further, as a further actual example of oddification processor 28, there may be employed an oddification processor such that DCT coefficients for carrying out oddification processing are coefficients which are not the last non-zero coefficient read out by zigzag scan. At the time of, e.g., two-dimensional DCT transform of 8x8, DCT coefficient of DC component, DCT coefficient of (7, 7) component of the highest frequency component, DCT component of (7, 0) component at the right and upper corner, or DCT coefficient of (0, 7) component at the left and lower corner may be employed. Since particularly DCT coefficient of (7, 7) component which is the highest frequency component has small influence on the picture quality, it is most satisfactory as a coefficient for carrying out oddification operation.

Further, for example, an approach may be employed to determine sum of specific coefficients, e.g., DCT coefficients of (0, 0) component, (4, 0) component, (0, 4) component and (4, 4) component to carry out oddification so that the sum is odd number. Namely, oddification operation element 14 for determining sum of specific coefficients to carry out oddification operation includes a selector 51 at the preceding stage of adder 23 shown in Fig. 8 mentioned above, as shown in Fig. 18, for example.

The selector 51 judges on the basis of count value coeff adrs delivered from counter 20 whether or not DCT coefficient delivered from inverse quantizer 13 is a coefficient to be added, whereby when that DCT coefficient is a coefficient to be added, i.e., count value is a value corresponding to (0, 0) component, (4, 0) component, (0, 4) component or (4, 4) component, it delivers the DCT coefficient to adder 23. Thus, the oddification operation element 14 determines sum of specific coefficients to implement an operation to at least one DCT coefficient so that the sum is odd number, thus to deliver the DCT coefficient which has undergone such operation to IDCT circuit 15.

It is to be noted that there may be employed a configuration such that, similarly to the embodiment of Fig. 10 mentioned above, the above-mentioned adder 23 is replaced by LSB detector 29 and EX0R30 to determine exclusive logical sum of LSBs of specific DCT coefficients.

DCT coefficients in which at least one DCT coefficient is caused to undergo operation so that sum of DCT coefficients is oddified in a manner stated above are delivered to IDCT circuit 15 as described above. Thus, IDCT circuit 15 implements IDCT processing to the DCT coefficients to reproduce a block reproduction difference signal S4 to deliver this block reproduction difference signal S4 to adder 16 as shown in Fig. 6 mentioned above.

The adder 16 adds, every pixel, block reproduction difference signal S4 and block picture signal S2 delivered from second field memory group 4 to reproduce block reproduction signal S5. This block reproduction signal S5 is stored into a field memory in second field memory group 4 specified by memory controller 3.

On the other hand, coded signal SC outputted from difference signal encoder 9, and motion vector MV, motion compensation mode MM and data of quantization table, etc. are subjected to variable length coding such as Human coding, etc. and are temporarily stored into a buffer memory (not shown). Thereafter, they are outputted at a predetermined transmission rate as, a bit stream. This bit stream is transmitted to a decoding apparatus for a moving picture through a transmission path, or is record onto an information recording medium. As information recording medium, optical disc is most suitable.

In more practical sense, slice/macro block counter 5 counts slice start signal SS and macro block start signal BS outputted from memory controller 3 in synchronism with a picture signal read out from first field memory group 2 which is to be coded at present. The slice/macro block counter 5 outputs start signal SO when its count value becomes equal to a value determined in advance. Responding to this, VLC element 17 output variable length codes with start codes of respective layers or header information thereof being added thereto.

Namely, the above-mentioned information recording medium is an information recording medium on which a picture signal which has undergone predictive coding and discrete cosine transform processing is recorded as a coded signal, wherein a reference picture signal at the predictive-coding is formed by oddifying sum of plural DCT coefficients for forming a coded signal to implement inverse discrete cosine transform processing to the plural DCT coefficients.

Further, a transmitting apparatus according to this invention can be realized by allowing it to be of the same structure of the above-described coding apparatus.

Meanwhile, when an approach is employed in difference signal encoder 9 constituting coding apparatus for moving picture to apply ah operation so that sum of DCT coefficients is odd number to transmit a bit stream obtained, or to record the bit stream onto an information recording medium, it may be considered that oddification operation of sum of DCT coefficients becomes unnecessary in decoding apparatus for moving picture. However, with such a configuration, sum of DCT coefficients may be even number in inverse quantization. Accordingly, it is impossible to prevent occurrence of DCT miss-match error.

A decoding apparatus for a moving picture to which this invention is applied will now be described with reference to Fig.

19.

A variable length code received as a bit stream through a transmission line from a coding apparatus for a moving picture, or a variable length code obtained by reproducing an information recording medium such as an optical disc, etc. as a bit stream is delivered to inverse VLC (hereinafter simply referred to as IVLC) element 32. The IVLC element 32 decodes header information of respective layers to deliver control information PH for picture decoding thus obtained to memory controller 33.

Further, IVLC32 implements inverse variable length coding (variable length decoding) to a variable length code to reproduce a coded block signal Cb to deliver the coded block signal Cb to a difference signal decoder 34. The difference signal decoder 34 decodes the coded block signal Cb to reproduce block reproduction difference signal BS to deliver the block reproduction difference signal BS to an adder 39.

Further, IVLC element 32 extracts motion vector MV, motion compensation mode MM from the bit stream to deliver them to a motion compensator 37. The motion compensator 37 makes a control such that, from a field memory group 38 in which picture signals of pictures (frames) already decoded and reproduced are stored, a block picture signal positioned at an address specified by motion vector MV is outputted. A reference picture at this time is specified from the field memory group 38 by memory controller 33.

In actual terms, as the predictive mode, there are a predictive mode from a past reproduced picture, a predictive mode from a future reproduced picture, a predictive mode from both past and future reproduced pictures (a reference block from a past reproduced picture and a reference block from a future reproduced picture are caused to undergo linear operation every pixel (e.g., average value calculation)), and a mode with no prediction (i.e., intra coding mode, and an output of a block picture signal from field memory group 38 is equivalently zero). Motion-compensated block picture signals out patted from second field memory group 38 are caused to be an adaptively modified signal, and an optimum one is selected every block. It is to be noted that the size of block is 16x16 pixels.

The block picture signal read out from the field memory group 38 in this way is delivered to adder 39. The adder 39 adds, every pixel, this block picture signal and block reproduction difference signal BS delivered from difference signal decoder 34. As a result, block reproduction signal is reproduced. This block reproduction signal is stored into a field memory in the field memory group 38 specified by memory controller 33.

Further, a reproduced picture signal stored in the field memory group 38 is read out on the basis of an output picture indication signal from memory controller 33, and is outputted to, e.g., a monitor image receiver. As a result, a picture image based oh the reproduced picture signal is displayed on the monitor image receiver.

The difference signal decoder 34 will now be described.

The difference signal decoder 34 comprises, as shown in Fig. 19 mentioned above, an inverse quantizer 40 for inverse-quantizing coded block signal Cb delivered from IVLC element 32 by using a quantization table, an oddification operation element 35 for allowing miss-match not to be produced in implementing IDCT processing to an output of the inverse quantizer 40, and an IDCT circuit 36 for implementing IDCT processing to an output of the oddification operation element 35.

More particularly, the inverse quantizer 40 comprises, as shown in Fig. 20, for example, an IZ element 41, a first memory

42, a second memory 43 and an inverse quantizing circuit (hereinafter simply referred to as IQ) 46, etc.

The IZ element 41 decodes data comprised of combination of * (run, level) delivered as a coded block signal Cb from the IVLC element 32 to deliver quantized DCT coefficients obtained (hereinafter referred to as coefficient data) to first memory 42 or second memory 43 in order of zigzag scan. Thus, the first memory 42 or the second memory 43 stores coefficient data.

When.all coefficient data are stored into the first memory 42 or the second memory 43, IQ46 carries out inverse quantization to deliver DCT coefficients thus obtained to oddification operation element 35. It is to be noted that inverse quantization at this IQ46 is the same as inverse quantization at inverse quantizer 13 constituting coding apparatus for moving picture shown in Fig. 6 mentioned above.

The oddification operation element 35 implements an operation to at least one DCT coefficient so that sum of DCT coefficients is odd number to deliver the DCT coefficient which has undergone such operation to IDCT circuit 36. It is to be noted that oddification operation at the oddification operation element 35 is the same as oddification operation at oddification operation element 14 constituting coding apparatus for moving picture shown in Fig. 6 mentioned above. Then, IDCT circuit 36 implements IDCT processing to the DCT coefficients to reproduce block reproduction difference signal BS to deliver this block reproduction difference signal BS to adder 39.

In actual terms, as indicated by the time chart of Fig. 21, for example, IVLC32 takes out data comprised of combination of * (run, level) from the bit stream, and outputs an event enable signal EV-EN indicating read enable (shown in Fig. 21A) to IZ element 41.

Further, IVLC32 outputs, as shown in Fig. 2IB, an event number signal EVEN indicating the number of data, i.e., the number of combination of (run, level) to IZ element 41.

When IZ element 41 receives this event number signal EVENT, it outputs a readout request signal RL-REQ to IVLC element 32 as shown in Fig. 21C. When this readout request signal RL-REQ is inputted, the IVLC element 32 outputs one set of (run, level) to IZ element 41 as shown in Figs. 21D, E. This operation is repeated by the number of events.

The IZ element 41 decodes data to deliver coefficient data which is quantized DCT coefficients to first memory 42 or second memory 43 in order of zigzag scan as shown in Fig. 21G. Simultaneously with this, as shown in Fig. 21F, the IZ element 41 delivers an address signal adrsl indicating a write address of coefficient data to first memory 42, and to output an address signal adrs2 to second memory 43. It should be noted that respective signals with respect to first and second memories 42 and 43 are simply referred to as, e.g., address signal adrs.

When code EOB is inputted, ID element 41 allows coefficient data of code EOB and coefficient data subsequent thereto to be all zero to deliver those coefficient data to first memory 42 or second memory 43. When ID element 41 have outputted- all coefficient data, it outputs a memory bank switching signal BANK to first memory 42 and second memory 43 to switch, e.g., destination of output of coefficient data from first memory 42 to second memory 43, or from second memory 43 to first memory 42.

. z ' '

When code EOB,is inputted, IZ elemental outputs, as shown in Fig. 21H, a signal EOB-EN indicating that a current code reaches code EOB to POS registers 44, 45, and outputs an address indicating the position of the last non-zero coefficient in order of zigzag scan to an address converter (not shown). Namely, id element 41 includes an address counter. Since when code EOB is detected, the address counter indicates address of the last non-zero coefficient, it delivers this value to the address converter. The address converter converts address in order of zigzag scan to address in order of raster scan to deliver it as address EOB-POS to POS registers 44, 45. Thus, POS registers 44, 45 store this address.

When first memory 42 and second memory 43 have stored all coefficient data, they output, to IQ46, a memory full signal indicating that all coefficient data are stored. When the IQ46 receives the memory full signal FULL, it sends readout request signal RD-ΕΝ to first memory 42 or second memory 43 to read out coefficient data. Meanwhile, this readout operation is controlled by readout address from the address converter. Namely, the address converter makes reference to address table for converting zigzag scan to raster scan to generate an address for reading out, by raster scan, coefficient data stored in the first memory 42 or the second memory 43. Coefficient data read out in accordance with this address is delivered to IQ46. It is to be noted that the direction of raster scan at this time is the same both in the case of longitudinal direction and in the case of lateral direction.

As described above, IQ46 inverse-quantizes coefficient data similarly to inverse quantizer 13 of coding apparatus for moving picture to deliver DCT coefficients thus obtained to oddification operation element 35.

Similarly to oddification operation element 14 of coding apparatus for moving picture as described above, the oddification operation element 35 implements an operation to at least one of DCT coefficients to oddify sums of DCT coefficients to deliver DCT coefficients in which sum is oddified to IDCT circuit 36.

Namely, for example, oddification operation element 35 makes reference to POS registers 44, 45 to carry out judgment as to whether or not a current coefficient is the last non-zero coefficient in order of zigzag scan to implement an operation to the DCT coefficient to carry out oddification of sum of DCT coefficients. Further, for example, oddification operation elements 35 implements an operation to DCT coefficient of the highest frequency component to oddify sum of DCT coefficients. Since particularly the highest frequency component has small influence on the picture quality, and there is no necessity of searching the last non-zero coefficient, it is most suitable. Also in the case where scan order is not zigzag scan,, this similarly applies. It is to be noted that it is needless to say that oddification operations at the coding apparatus for moving picture and the decoding apparatus for moving picture must be identical to each other.

Second Embodiment

The configuration of a coding apparatus for a moving picture in a second embodiment is shown in Fig. 22. The configuration of oddification operation element 50 constituting the coding apparatus for moving picture is shown in Fig. 23. Since the coding apparatus for moving picture in the second embodiment has the same components as those of the coding apparatus for moving picture of the first embodiment shown in Fig. 6 except for oddification operation element 50 as shown in Figs. 22 and 23, the same reference .numerals are respectively attached to the same circuits as those of the first embodiment, and their explanation is omitted here.

In the oddification operation element 50, as shown in Fig.

23, counter 20 counts the number of DCT coefficients delivered from inverse quantizer 13 to deliver a count value coeff adrs obtained to even/odd judge element 21.

Adder 23 adds DCT coefficient delivered from inverse quantizer 13 and sum of preceding DCT coefficients preserved in * register 24 to deliver a sum of DCT coefficients obtained to register 24, and to deliver the sum of DCT coefficients to even/odd judge element 21. It is to be noted that addition at adder 23 may be addition of LSBs of DCT coefficients similarly to the first embodiment.

Even/odd judge element 21 operates by making reference to count value coeff adrs delivered from counter 20 as follows. Namely, when all DCT coefficients are added at adder 23, i.e., when sum of 64 DCT coefficients is determined, e.g., in the case of two-dimensional DCT transform of 8x8, the even/odd judge element 21 whether sum of DCT coefficients delivered from adder 23 is even number or odd number. In actual terms, when e.g., DCT coefficient is. represented by binary number, even/odd judge element 21 judges LSB of sum of DCT coefficients delivered from adder 23, i.e., preserved in register 24. Since LSB is 0, sum is even number, even/odd judge element 21 outputs processing request signal REQ1 to oddification processor 53 in order to carry out oddification operation. On the other hand, when LSB is 1, sum is odd number, even/odd judge element 21 outputs no processing request signal REQI.

DCT coefficient from inverse quantizer 13 is sent to adder 23, and is also sent to oddification processor 53 through a delay circuit 52. This delay circuit 52 delays DCT coefficients by time corresponding to processing times at odder 23 and even/odd judge element 21 so that the last DCT coefficient, i.e., the highest frequency coefficient (e.g., DCT coefficient of (7, 7) component in 8x8 DCT transform) is inputted to oddification operator 53 when processing request signal REQ1 is inputted to oddification processor 53.

When processing request signal REQI is absent, oddification processor 53 outputs DCT coefficient as it is, while when processing request signal REQI is inputted, oddification processor 53 inverts LSB to output it. Namely, when processing request signal REQ1 is inputted, oddification processor 53 is supplied with the highest frequency coefficient. At this time, oddification processor 53 delivers DCT coefficients except for the highest frequency coefficient to IDCT circuit 15 as they are, and implements an operation to the highest frequency coefficient (DCT coefficient of (7, 7) component in 8x8 DCT transform) to oddify sum of DCT coefficients to deliver it to IDCT circuit 15. Thus, sum of DCT coefficients from the beginning to the last is odd number. Here, DCT coefficient of (7, 7) component is a coefficient having least influence on an output value of IDCT, and the invertor believes that this embodiment is the best mode.

Further actual example of oddification operation element 50 will now be described.

As shown in Fig.' 24, for example, a LSB detector 29 for detecting LSB of DCT coefficient and an EXOR circuit 30 for determining exclusive logical sum of this LSB and an output of the register 24 may be used in place of adder 23 constituting oddification operation element 50 shown in Fig. 23. The oddification operation element 50 thus constructed serves to determine sum of LSBs of DCT coefficients by EXOR circuit 30 and register 24. It is to be noted that the same reference numerals are respectively attached to the same circuits as circuits constituting oddification operation element 50 shown in Fig. 23 mentioned above, and their explanation is omitted here.

Further, as shown in Fig. 25, for example, there may be employed a configuration in which a selector 51 is provided at the preceding stage of adder 23 constituting oddification operation element 50 shown in Fig. 23. In this case, sum of DCT coefficients of only specific coefficients, e.g., (0, 0) component, (4, 0) component, (0, 4) component, (4, 4) component is determined to carry out oddification so that the sum is odd number. Namely, selector 51 judges on the basis of count values coeff adrs delivered from counter 20 whether or not a DCT coefficient delivered from inverse quantizer 13 is a coefficient to be added. As a result, when that DCT coefficient is the coefficient to be added, i.e., count value is a value corresponding to, e.g., (0, 0) component, (4, 0) component, (0,

4) component or (4, 4) component, the selector 51 delivers the DCT coefficient to adder 23. Thus, the oddification operation element 50 determines sum of specific coefficients to implement an operation to at least one DCT coefficient so that the sum is odd number to deliver the DCT coefficient which has undergone operation to IDCT circuit 15.

It is to be noted that, similarly to the embodiment shown in Fig. 24 mentioned above, there may be employed a configuration in which the above-mentioned adder 23 is replaced by LSB detector 29 and EXOR circuit 30 to determine exclusive logical sum of LSBs of specific DCT coefficients.

As a still further actual example of oddification operation element 50, in the case where the last DCT coefficient inputted from inverse quantizer 13 is DCT coefficient of DC component, i.e., in the case where the order of raster scan is opposite to that of the above-described embodiment, a coefficient to which oddification operation is implemented is not the highest frequency component, but DCT coefficient of DC component.

Actual circuit configuration of oddification processor 53 will now be described.

Oddification processor 53 is comprised, as shown in Fig. 26, for example, a portion of oddification processor 28 shown in Fig. 11 mentioned above, i.e., LSB inverter 63 to OR circuit 66, and inverter 71. In this oddification processor 53, LSB is inverted by LSB inverter 63 to carry out oddification of sum of DCT coefficients. It is to be noted the same reference numerals are respectively attached to the same circuits as circuits constituting oddification.processor 28, and their explanation is omitted here.

Modified actual examples of oddification processor 53 are shown in Figs. 27 to 29.

Namely, in place of LSB inverter 63 constituting oddification processor 53, +1 adder 73 shown in Fig. 13 mentioned above may be used as shown in Fig. 27. This oddification processor 53 is operative so that when processing request signal REQI is inputted, 1 is added to the highest frequency coefficient by +1 adder 73 to oddify sum of DCT coefficients.

Further, as shown in Fig. 28, polarity judgment processing circuit 80 shown in Fig. 15 mentioned above may be used in place of LSB inverter 63. This oddification processor 53 carries out oddification of sum of DCT coefficients on the basis of above-described formula (15). Namely, when processing request signal REQI is inputted, 1 is subtracted by -1 subtracter 82 when the highest frequency coefficient is positive, and 1 is added by + 1 adder when it is 0 or negative, thus to carry out oddification of sum of DCT coefficients.

Further, as shown in Fig. 29, polarity judgment processing circuit 90 shown in Fig. 17 mentioned above may be used in place of LSB inverter 63. This oddification processor 53 carries out oddification of sum of DCT coefficients on the basis of the above-described equation (16). Namely, when processing request signal REQI is inputted, 1 is added by +1 adder 92 when the highest frequency coefficient is positive, and 1 is subtracted by -1 subtracter when it is 0 or negative, thus to carry out oddification of sum of DCT coefficients.

It is to be noted that these oddification processors 53 are adapted to output an inputted DCT coefficient to IDCT circuit 15 as it is when no processing request signal REQI is inputted.

A second embodiment of a decoding apparatus for a moving picture will now be described.

The decoding apparatus for moving picture of the first embodiment is of a structure such that oddification operation element 50 constituting coding apparatus for moving picture of the second embodiment is used in place of oddification operation element 35 of the first embodiment. Namely, an operation to oddify sum of DCT coefficients is carried out similarly to the coding apparatus for moving picture of the second embodiment. Accordingly, address EOB adrs from IVLC element 32 to oddification operation element 50 becomes unnecessary.

As described above, in accordance with this invention, it is possible to realize an inverse discrete cosine transform method and an inverse cosine transform apparatus, and a coding device for a moving picture, a decoding apparatus for a moving picture and a transmitting apparatus using such inverse discrete cosine transform system in which the probability that miss-match error takes place in carrying out inverse discrete cosine transform is low and there is no miss-match error from a practical point of view. Further, it is possible to realize an information recording medium in which no miss-match error takes place from a practical point of view.

Namely, in .the case where discrete cosine transform is used in coding of a picture signal and inverse discrete cosine transform is used in decoding of a picture signal, it is possible to prevent occurrence of inverse discrete cosine transform miss-match error thus to reduce deterioration of picture quality. Accordingly, in a coding apparatus for a moving picture and a decoding apparatus for a moving picture to which this invention is applied, there is no possibility that local decode picture on the encoder side and reproduced picture on the decoder side differ from each other. Thus, high quality picture can be provided.