Decoding a block of quantized transform coefficients, wherein an even parity of the sum of the inversely quantized transform coefficients is set to an odd parity

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DESCRIPTION

Apparatus for avoiding rounding errors in the inverse transform of transform coefficients of a moving image signal.

Orthogonal transforms are used in various applications in many digital signal processing systems. Orthogonal transforms allow the performance of signal processing in the frequency domain. The fast Fourier transform (FFT - "Fast Fourier Transform") and the discrete cosine transform (DCT "discrete cosine transform"), etc., are well known types of orthogonal transforms. An orthogonal transform analyzes, for example, a fragment of a signal in the time domain to obtain frequency components (which vary depending on the applied orthogonal transform function) and indicate the spectrum (that is, the energy distribution as a function of the frequency) of the original signal fragment in the time domain. By treating the frequency components (usually referred to as transform coefficients) that result from the orthogonal transformation of the signal fragment in various ways, the redundancy of the original signal fragment can be reduced. In other words, by orthogonal transformation of the original signal fragment and processing the resulting transform coefficients, the original signal fragment can be represented with fewer bits than have been used to represent the original signal fragment. Furthermore, by performing the inverse orthogonal transform of the transform coefficients, the original signal fragment can be recovered in the time domain.

Apparatus for compressing a moving image signal and for expanding a compressed moving image signal are common examples of digital signal processing systems using orthogonal transform processing.

It is known that the signal power of signals having a high correlation is concentrated at the lower frequencies in the frequency domain. As the concentration of signal power increases on a specific coordinate axis (eg, the frequency axis), the redundancy of the signal can be progressively reduced, and the signal can be compressed more efficiently.

Since a moving picture signal is generally highly correlated, both spatially and in time, orthogonal transform processing can be applied to concentrate the signal power on a specific coordinate axis, and the moving picture signal can be compressed with high efficiency.

Until now, an extremely large amount of information has been required to represent moving images, using, for example, a video signal according to the NTSC standard. Because of this, the recording of a moving picture signal has required a recording medium with a very high storage capacity if the medium is to provide an acceptably long recording medium. Additionally, the information sampling rate at which the moving picture signal is recorded and reproduced by such medium has been very high. Magnetic tapes or optical discs of large physical dimensions have hitherto been required to store moving image signals.

If it is desired to record a moving picture signal on a more compact recording medium with an acceptably long recording time, signal compression must be applied to the moving picture signal to reduce the amount of information that needs to be stored. Additionally, there must be an apparatus that is capable of expanding the reproduced compressed motion picture signal from the compact recording medium.

To meet the requirements just described, various moving image signal compression systems have been proposed that exploit the correlation between and within the portions of the moving image signal that represent the images that constitute the image signal. with movement. For example, the moving picture signal compression systems proposed by the Moving Picture Experts Group (MPEG) are widely known. Since the MPEG system has been extensively described in various printed publications, a detailed explanation of such a system will not be repeated here.

The following description will often refer to an image. Since the signal processing techniques described herein refer to the processing of a moving image signal that represents a moving image, the word image, as it is generally used in the As used herein, it refers to a portion of a moving picture signal that represents an image of the moving picture. Furthermore, a moving picture signal can represent an image of the moving picture in the form of a frame or a field. Unless otherwise indicated, an image means a field or a box.

The MPEG system first determines the differences between the pictures that make up the moving picture signal to reduce the redundancy of the moving picture signal in the time domain. The MPEG system then reduces the redundancy of the moving picture signal in the spatial domain

ES 2 389 797 T3 applying treatment by orthogonal transform to blocks of differences between Images in the space domain. The MPEG system applies discrete cosine transform (DCT) processing as orthogonal transform processing. By reducing redundancy in both the time domain and the space domain, the moving image is compressed with extremely high efficiency. The compressed moving picture signal resulting from the compression process just described can then be recorded on a recording medium, or transmitted via a suitable transmission medium.

When the motion picture signal is reproduced from the recording medium, or received from the transmission medium, the blocks of transform coefficients resulting from the discrete cosine transform are extracted from the compressed motion picture signal. The transform coefficients are treated using an inverse orthogonal transform (an inverse discrete cosine transform (IDCT - "inverse discrete cosine transform") in the MPEG system) to recover blocks of differences between images in the course of the reconstruction of the images in the original motion picture signal.

Figure 1 shows an example of the construction design of a moving image signal compressor apparatus based on the MPEG system. In the compressor illustrated in Figure 1, a digital motion picture signal is applied to the block formatter circuit 101, where it is converted from a standard video format, for example, a video signal format according to the NTSC standard, to a block format to provide a moving picture signal in blocks. In this technique, each picture of the moving picture signal is divided in the space domain, that is horizontally and vertically, into macroblocks of, for example, 16 x 16 picture elements. The macroblocks are also subdivided into blocks of 8 x 8 pixel elements.

The apparatus depicted in FIG. 1 compresses each image of the moving image signal block by block until all the blocks constituting the image have been processed. The apparatus then processes another image of the moving image signal, which may or may not be the next image in the sequence of images constituting the moving image. In the following description of the apparatus illustrated in Fig. 1, the compression of a picture element block into one picture will be described. The pixel block being compressed is the current image block, which is a block of the current image. The block-organized motion picture signal is applied to motion predictor 102. The motion predictor 102 applies the current image, including the current image block S1, block by block to the difference block calculation circuit 103.

When the difference block calculation circuit 103 receives the current image block from the motion predictor 102, it also receives the adaptation block S2 corresponding to the current image block from the motion predictor 102. The adaptation block S2 is deduced from the reconstructed images stored in the image memory block 112 by the predictor 113. The difference block calculating circuit 103 determines the pixel-by-pixel difference between the current picture block S1 and its corresponding matching block S2. The resulting difference block, difference block S3, is applied to orthogonal transform circuit 104.

The orthogonal transform circuit 104, which is typically a discrete cosine transform (DCT) circuit, applies orthogonal transform treatment to the difference block S3, and inputs the resulting block of transform coefficients into the quantizer 105. The quantizer 105 quantizes the transform coefficient block to generate a quantized transform coefficient block. Variable-length encoder 106 subjects the block of quantized transform coefficients generated by quantizer 105 to variable-length encoding, such as Huffman encoding, moving window length encoding, and so on. The resulting block of coded transform coefficients is then input, for example, onto a digital transmission path, through the output buffer 107.

A control signal indicating the number of bits stored in output buffer 107 is fed back to quantizer 105. Quantizer 105 adjusts the quantization step size in response to the control signal to prevent buffer overflow. 107 exit. An increase or decrease in the magnitude of the quantization increment decreases or increases, respectively, the number of bits input into the output buffer 107.

The block of quantized transform coefficients is also transferred from quantizer 105 to inverse quantizer 108, which is part of the local decoder used in the compressor to derive reconstructed images used in predictive coding from the quantized transform coefficients. The inverse quantizer 108 inverse quantizes the block of quantized transform coefficients by performing a complementary treatment of the quantization treatment performed by the quantizer 105. The resulting block of transform coefficients is supplied to the inverse orthogonal transform circuit 109, where it is subjected to an inverse orthogonal transform by complementary treatment of the orthogonal transform treatment performed by the orthogonal transform circuit 104. The resulting restored difference block S4 is supplied to adder 110.

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The adder 110 also receives the adaptation block S2 corresponding to the current image block S1 of one of the image memories of the group 112 of image memories selected by the predictor 113. The adder 110 performs the addition of pixel by pixel between the restored difference block S4, generated by the inverse orthogonal transform circuit 109, and the adaptation block S2 from the image memory group 112 to obtain the block S5 reconstructed image. The reconstructed image block S5 is supplied to one of the memories 112A to 112D selected by the selector 111, where it is stored.

The reconstructed image block S5 is stored in the selected image memory, where it forms a block (corresponding to the current block) of the image being reconstructed, block by block, from the reconstructed image blocks stored in the memory. selected image. When complete, the reconstructed image will be used to obtain adaptation blocks to perform predictive coding to compress other images of the moving image signal.

The motion predictor 102 determines, for each macroblock of the current picture, a motion vector between the macroblock of the current pictures and different macroblocks of the other stored motion picture signal pictures. The motion predictor 102 also generates a sum of the absolute values ​​of the differences (the sum of the absolute values ​​of the differences) between the picture elements of each macroblock of the current picture and the different macroblocks of the other pictures. Each sum of absolute values ​​of differences indicates the degree of agreement between each macroblock in the current image and the macroblocks in the other images. Motion predictor 102 inputs each motion vector and its corresponding sum of absolute values ​​of differences into prediction mode determination circuit 115.

Prediction mode determining circuit 115 uses the data received from motion predictor 102 to determine the prediction mode that will be used for predictive coding of the current image relative to one or more other reconstructed images. The current image can be predictively encoded using any of the following prediction modes:

(1) Intra-image mode, in which the image is compressed by itself, without reference to any other images. An image encoded in this way is called an I-image.

(2) Advance prediction mode, in which the prediction is made with reference to a reconstructed image that occurs earlier in the moving image. An image encoded in this way is called a P-image.

(3) Bidirectional prediction mode, in which block-by-block prediction is performed with respect to a reference block deduced from a reconstructed image that appears earlier in the moving image and a reconstructed image that appears later in the moving image , or by performing a pixel-by-pixel linear operation (eg, a mean value calculation) between an earlier reconstructed image and a later reconstructed image. An image encoded in this way is called a B-image.

In other words, an I-picture is a picture in which intra-picture coding within the picture has been completed. A P-picture is obtained by prediction from an I-picture or a P-picture that appears earlier in the moving picture. A B image is obtained by block-by-block prediction using an earlier or later I-image or P-image or by using a block obtained by performing a linear operation using a reconstructed I-image or a reconstructed P-image that appears earlier in the moving image, and starting from a reconstructed I-image or a reconstructed P-image that appears later in the motion picture.

The prediction mode determining circuit 115 provides the prediction mode and the corresponding motion vector to the predictor 113 and the read address generator 114. The read address generator 114 provides read addresses to the image memory group 112 in response to the motion vector, which addresses serve to cause a block of the reconstructed image stored in each image memory 112A to 112D to be read. The position of the read block in the reconstructed image is designated by the motion vector. Predictor 113 selects one of the read blocks from image memories 112A to 112D in response to the prediction mode signal PM received from prediction mode determining circuit 115. The selected read block provides the adaptation block S2 for the current image block S1. When the current image block is part of a B image, the predictor also performs linear operations on the read blocks of image memories 112A to 112D to provide the required adaptation block. The predictor supplies the adaptation block S2 to the difference block calculation circuit 103 and to the adder 110.

Figure 2 shows an example of the construction design of a compressed motion image signal expander apparatus, based on the MPEG system. In this unit, the motion picture signal

The compressed ES 2 389 797 T3 obtained directly from the compressor or by reproducing it from a recording medium, is supplied as a string of bits to the input buffer 121, where it is temporarily stored. The compressed digital signal includes blocks of encoded transform coefficients (including a block of encoded transform coefficients representing the current block), and prediction mode information, quantization increment magnitude information, and a motion vector for each block.

The compressed motion picture signal is read from the input buffer 121 by individual pictures and is supplied to a variable-length inverse encoder 122 (IVLC - "inverse variable-length coder"). Variable-length reverse encoder 122 applies variable-length reverse encoding treatment to the compressed motion picture signal, and separates the compressed motion picture signal into its components, which include blocks of quantized transform coefficients and mode information. prediction, quantization increment magnitude information, and a motion vector for each block.

Each block of coded transform coefficients is input to inverse quantizer 123, which uses the quantization increment magnitude information for the block to inverse quantize the block of quantized transform coefficients to provide a block of transform coefficients. The inverse orthogonal transform circuit 124 applies an inverse orthogonal transform treatment, typically an inverse discrete cosine transform treatment, to the transform coefficient block to obtain a restored difference block. The inverse quantizer 123 and the inverse orthogonal transform circuit 124 apply, respectively, a complementary treatment to that applied by the quantizer 105 and the orthogonal transform circuit 104 in the compressor shown in FIG. 1.

The read address generator 130 provides a read address to the image memories 128A through 128D in response to the motion vector corresponding to the current block received from the variable length reverse encoder 122. In response to the read address, each of the image memories 128A to 128D reads a block of the reconstructed image stored therein. Predictor 129 selects one of the read blocks from image memories 128A to 128D in response to the prediction mode signal PM, also received from variable length reverse encoder 122. The selected read block provides the adaptation block to rebuild the current block. When the current block is part of an image coded as image B, the predictor also performs linear operations on the reading blocks of the image memories 112A to 112D to obtain the adaptation block. Predictor 129 supplies the adaptation block to adder 125.

Adder 125 performs pixel-by-pixel addition between the restored difference block generated by inverse orthogonal transform circuit 124, and the matching block generated by predictor 129 to reconstruct the current picture block from the image. in progress. The selector 126 supplies the reconstructed current image block for storage in the memory of the image memories 128A to 128D in which the current image is being reconstructed. The reconstructed current image block is stored in the selected image memory at the current image block position in the reconstructed current image. When all the reconstructed blocks of the current image have been stored in the selected image memories 128A to 128D, the reconstructed current image is ready for reading, and also to be used as a reference image to reconstruct other images that appear before or after. later in the moving picture.

The reconstructed images stored in image memories 128A through 128D are read as an output moving image signal through selector 126 in response to read directions generated by display address generator 127. A scan converter (not shown) converts the output motion picture signal, read from the picture memories 128A to 128D, into the frame format of the desired video signal format, for example the NTSC format. The resulting output moving image signal can then be displayed on a suitable display device, for example a CRT or cathode ray tube, etc. In this example, the sync signal generator 131 is synchronized with an external sync source, and periodically generates a frame sync signal to be applied to the display address generator 127. The display address generator 127 generates read addresses in sync with the frame sync signal.

The orthogonal transform circuits, for example the discrete cosine transform and inverse discrete cosine transform circuits used in the compressor and expander described above, respectively, perform arithmetic operations on pixel values ​​and transform coefficients represented by integers that have a finite number of bits. Thus, orthogonal transform operations performed by orthogonal transform circuits can truncate the number of bits. For this reason, a difference in the precision of the orthogonal transform operation using real numbers, or a difference in the configuration of the circuit used to perform the orthogonal transform operation, can change the result of the orthogonal transform operation. This can lead to a mismatch between compressor and expander, and mismatches between expanders expanding a common compressed signal.

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For example, in the compressor, the difference block derived from the Motion Picture signal is orthogonally transformed, and a predetermined processing is applied to quantize the resulting transform coefficients in the course of generating the compressed Motion Picture signal. . Then, in the expander, if the precision of the operations with real numbers or the configuration of the inverse orthogonal transform circuit does not correspond to that of the compressor, then it is possible that the output of the expander differs from the input to the compressor. Therefore, the output of the expander may depend on the accuracy and configuration of the apparatus used for the expander.

The operational accuracy or configuration of an inverse orthogonal transform may vary depending on the apparatus used to perform the inverse orthogonal transform. For example, the inverse transformation of a block of transform coefficients using two different constructive arrangements of the same type of inverse orthogonal transform circuit, can produce different results. Such a difference in results is called the inverse orthogonal transform mismatch error (mismatch error).

The MPEG system defines the operational precision with which the discrete cosine transform and inverse discrete cosine transform are to be performed, but does not define the operational method or configuration. This is because the circuits and methods for realizing discrete cosine transforms and inverse discrete cosine transforms were developed before the MPEG standards were established.

In the MPEG system, as described above, the compressor implements, for example, predictive coding between images with motion compensation to obtain the moving image signal. In this technique, the moving image signal is divided into blocks, a difference block is obtained from the current image block, and an adaptation block is obtained by applying motion compensation to a reconstructed image, the difference block is transformed orthogonally using the discrete cosine transform treatment, the resulting transform coefficients are quantized, the quantized transform coefficients are subjected to variable length encoding, and the encoded transform coefficients are assembled with prediction mode information, quantization increment magnitude information, and motion vectors, to provide the compressed motion picture signal.

The expander applies inverse variable length encoding to encoded transform coefficients, inverse quantization to quantized transform coefficients resulting from inverse variable length encoding, and inverse discrete cosine transform treatment to transform coefficients resulting from inverse quantization. . The resulting restored difference block is added to an adaptation block obtained by applying motion compensation to the reconstructed image in response to the motion vector. The resulting reconstructed image block is stored as a reconstructed image block, which provides an image of the output moving image signal, and is also available to be used as a reference image.

The compressor includes a local decoder that deduces, from the quantized transform coefficients, reconstructed images to be used in performing predictive coding. The local decoder includes an inverse quantizer and an inverse orthogonal transform circuit.

If the configuration of the inverse discrete cosine transform circuit in the local decoder is different from that of the inverse discrete cosine transform circuit used in the expander, there are cases in which the reconstructed images generated by the local decoder in the compressor are different. of the reconstructed images generated by the expander. The dependence of the inverse discrete cosine transform processing of the implementation can cause problems when the compressed motion picture signal generated by a compressor complying with the MPEG standard is recorded on a recording medium, such as an optical disk, etc. for distribution to the public. When the reproduced compressed motion picture signal from the optical disc is expanded by expanders manufactured and sold by different manufacturers, the reconstructed image may be different from the original image. Additionally, the differences may depend on the actual expander used. Similar incompatibilities between different expanders can occur when the compressed motion picture signal is distributed by a distribution system, such as a terrestrial or satellite broadcast system, a telephone system, an ISDN system (Integrated Services Digital Network - “Integrated Services Digital Network ”), a cable or fiber optic distribution system, etc.

Mismatch errors are particularly troublesome when performing inter-picture predictive coding. Inter-picture predictive coding can be inter-field coding or inter-frame coding. Predictive inter-image coding can cause mismatch errors to accumulate to the point that they produce fatal defects in reconstructed images.

In the compression of the moving image signal carried out by the MPEG system, each video sequence is divided into Groups of Pictures (GOPs - "Groups of Pictures") of, for example, eight or twelve images. Each image is classified as an I image, P image, or B image, as described above.

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A B image is not used as a reference image for motion prediction. Therefore, a mismatch error that occurs in image B does not cause errors in other images.

When a mismatch error occurs in a P-picture, the image containing the mismatch error is stored in image memory for use in predictive coding. Accordingly, when inter-picture predictive coding is performed, the error contained in the P picture stored in the picture memory is gradually distributed towards the P pictures and the B pictures deduced therefrom by the predictive coding. The error accumulates until the image is replaced by an I image or a P image that does not contain such an error.

Similarly, when a mismatch error occurs in an I image, the reconstructed image containing the mismatch error is stored in image memory for use in predictive coding. Accordingly, when inter-picture predictive coding is performed, the error contained in the I picture stored in the picture memory is distributed to the P pictures and B pictures deduced therefrom by the predictive coding. The error accumulates until the image is replaced by a new image I that lacks such an error.

The accumulation of error is illustrated in figure 3. In figure 3, if the mismatch error in decoding an image I is EI, and the mismatch error in decoding image P P1 is EP1, the value of the error in reconstructed P image P1 is EI + EP1. Additionally, when the mismatch error in decoding P image P2 is EP2, the error value in reconstructed P image P2 is EI + EP1 + EP2. Even if the individual mismatch errors are small, the gradual accumulation of these errors will result in one big error.

The mismatch errors produced by the inverse discrete cosine transform treatment used in MPEG decoders in both the compressor and the expander can be classified into two different types:

Type (1): Errors resulting from insufficient calculation precision.

Type (2): Errors resulting from systematic differences in rounding.

The MPEG standard establishes a requirement for the precision of operations. However, this requirement is not so stringent that it can guarantee that a mismatch error does not occur. Accordingly, a type (1) mismatch error may occur between inverse discrete cosine transform devices whose calculation precision satisfies the requirement of the MPEG standard.

The outputs of the inverse discrete cosine transform processing are integers. Therefore, after the inverse discrete cosine transform treatment is performed using real numbers, the results of the treatment should be rounded. In general, treatment results are rounded to the nearest whole number. However, a problem occurs when the result of the mathematical treatment is of the form * .5, where * is an integer. The MPEG standard does not define how a processing result of the form * .5 should be rounded. Some inverse discrete cosine transform devices round * .5 up, and other inverse discrete cosine transform devices round * .5 down. Additionally, there are cases in which rounding up or rounding down depends on the sign of the treatment result. The mismatch errors resulting from the systematic rounding errors just described are mismatch errors of type (2).

Mismatch errors of type (1) differ from mismatch errors of type (2) in that errors of type (1) occur randomly, while errors of type (2) are systematic. Because errors of type (1) are random, positive and negative errors occur with approximately the same probability. Therefore, when predictive coding is performed for a long time, it can be assumed that the type (1) mismatch errors are canceled.

On the other hand, since type (2) mismatch errors are systematic and inherent in the inverse discrete cosine transform treatment itself, such errors consistently have the same polarity. Consequently, when predictive coding is performed for a long time, the mismatch errors will be cumulative in one direction. Although each type (2) mismatch error is only + 1 or -1, if many mismatch errors are accumulated in one direction, the cumulative mismatch error will be large.

Since mismatch errors of type (1), although generated incidentally, cancel out over time, such errors do not present relatively problems. On the other hand, since type (2) mismatch errors accumulate in one direction, type (2) mismatch errors are problematic. Because of this, it is desirable to prevent cumulative mismatch errors of type (2) from occurring.

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It has been proposed in the MPEG1 system to perform the processing before the inverse discrete cosine transform calculations to avoid the occurrence of type (2) mismatch errors. The treatment sets the transform coefficients of all components to an odd value, except for the transform coefficient of the component (0,0) of a macroblock of an image encoded according to the intra-image system (an intra macroblock). In an intra macroblock, the component (0,0) is the continuous component. As shown in Figure 4, for example, the transform coefficients of the components (0,1), (7,1), (2,3), (5,3), (1,5), (6 , 5), (3,7) and (4,7) are all initially equal to 568. Since this is an even number, the pretreatment sets the values ​​of those coefficients to an odd value, for example 567. When inverse discrete cosine transform treatment is applied to the pretreated transform coefficients, fractional results are never produced.

Since the continuous component of the intra macroblock is very important for the appearance of the image obtained from the compressed motion picture signal, its precision is limited to only eight bits. This quantity is not converted to an odd value, since this would degrade the precision of this important component. On the other hand, all the transformation coefficients resulting from transforming a macroblock of a coded image using inter-image coding (a non-intra macroblock) are subjected to a treatment similar to that of the transform coefficients of the components, which do not correspond to the continuous component, of an intra macroblock to restrict transform coefficients only to odd values.

The treatment according to which the values ​​of the transform coefficients subjected to inverse discrete cosine transform treatment are all set to an odd value is called an odd value conversion treatment.

By applying the odd-value conversion treatment, the inverse discrete cosine transform treatment in both the compressor and the expander will perform rounding according to a common rule. This will make it possible to maintain consistent image quality between different expanders.

However, despite the odd-value conversion treatment described above, the cumulative type (2) mismatch errors described above will still occur in MPEG processors, because the inverse discrete cosine transform treatment can still produce results of the type * .5, where * indicates an integer. The circumstances leading to a result of * .5 will be described below using the 8 x 8 two-dimensional inverse discrete cosine transform used in the MPEG system as an example.

The 8 x 8 two-dimensional inverse discrete cosine transform is expressed by the following equation:

^{7 7}^{f (x,}y) = 4 ΣΣ ^{C (u) C (v) F (u, v)}⁴ u = 0 v = 0 cos

<td>(2x + 1) uxn</td><td>ΓΊΧΟ</td><td>(2y + 1) vyn</td>

<td> _ 16 _</td><td>LUb</td><td> _ 16 _</td>

u, v, x, y = 0,1, ..., 7

... (1)

C (u), C (v) ¡, ίιι.ν 0j = 1 (u, v 0)

In the above equation, F (u, v) denotes the discrete cosine transform coefficients subjected to the two-dimensional inverse discrete cosine transform. In equation (1), each output value of the inverse discrete cosine transform is a real number, that is, a rational number or an irrational number. Because * .5 is a rational number, making the output value of the inverse discrete cosine transform an irrational number will prevent the generation of a cumulative mismatch error. On the other hand, when the output value is a rational number, the output value may be * .5.

The coefficients F (0,0), F (0,4), F (4,0), F (4,4) of the discrete cosine transform are special discrete cosine transform coefficients. When any of these discrete cosine transform coefficients has a non-zero value, the output value of the inverse discrete cosine transform is a rational number. The output values ​​of the inverse discrete cosine transform in this case are expressed by equation (2).

ES 2 389 797 T3 f (x, y) = 1f (0,0) f (x, y) = XF (0,4) cos ^{2 + 1} π fh 4 ^F(x, y) = 4 ^ = ^{F (0.4) cos π}

1 2x +1 2y +1 f (x, y) = 4 ^ (4,4) cos —-— π cos - π,, 2x +1 1 where cos-π = + —¡ = ~ d2 (2)

Thus, when only one of the special coefficients F (0,0), F (0,4), F (4,0), F (4,4) of the discrete cosine transform has a non-zero value, which is multiple of 4, but not multiple of 8, the output value is of the form * .5.

When the four special discrete cosine transform coefficients are the only coefficients with a non-zero value, the output value of the inverse discrete cosine transform is expressed by equation (3).

F (x, y) = 'F (0,0)' 1F (), 4) cos ^{2 + 1} π + Xf (4,0) cos ^{2x +1} π

Fñ 4 Fñ 2

.. 2x +1 2y +1 + —F (4,4) cos-π cos —- π

4 4 (3)

With different combinations of x and y, the function f (x, y) of equation (3) can have the following values:

[F (0,0) + F (0,4) + F (4,0) + F (4,4)]

[F (0.0) + F (0.4) -F (4.0) -F (4.4)]

[F (0.0) - F (0.4) + F (4.0) - F (4.4)]

[F (0.0) - F (0.4) - F (4.0) + F (4.4)]

... (4)

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Thus, when the values ​​of the four special coefficients are such that any of the expressions stated in equation (4) is a multiple of 4 but is not a multiple of 8, a result of the form * .5 will be produced.

Thus, when all four special coefficients have nonzero values, there is a high probability that the output value of the inverse discrete cosine transform is of the form * .5.

Also, various symmetric pairs of discrete cosine transform coefficients with nonzero values, different from the four special coefficients just discussed, can produce an output value of the form * .5:

(1) when the pair of coefficients X (2n + 1, 2m + 1), X (2m + 1, 2n + 1) have the same non-zero values ​​and the value is a multiple of 4 but not a multiple of 8, or ( 2) when the pair of coefficients X (2n + 1, 2n + 1), X (8-2n-1, 8-2n-1) have the same non-zero values, and the value is a multiple of 4 but not a multiple of 8.

In the above expressions, X (i, j) is the one-component transform coefficient of an 8 x 8 two-dimensional discrete cosine transform.

When a real motion picture signal is compressed by the compressor in accordance with the MPEG system, non-zero discrete cosine transform coefficients are frequently generated in the just mentioned configurations, which can produce a transform output value of Inverse discrete cosine of the form *. 5. Furthermore, the values ​​of the four special coefficients are nonzero most of the time.

Since the most common cause of a * .5 result is the combination of discrete cosine transform coefficients in which the values ​​of the four special coefficients are not zero, avoiding a mismatch error in response to The four special coefficients will substantially reduce the probability of a mismatch error appearing.

Figure 5 shows the treatment method by which an intra macro block and a non-intra macro block are inversely quantized according to the MPEG1 standard. In figure 5, QAC (i, j) is the discrete cosine transform coefficient of order (i, j), Wi (i, j) is the element of order (i, j) of a weighting matrix, mquant is the quantization coefficient, and rec (i, j) is the inversely quantized discrete cosine transform coefficient of order (i, j). The treatment method is written in the syntax of the C programming language. The syntax of this language is exposed in the disclosure by Herbert Schildt: “Using Turbo C”, Osborne McGraw Hill (1988), especially in pages 83-87.

The quantized discrete cosine transform coefficients are inversely quantized, and the resulting discrete cosine transform coefficients are then subjected to inverse discrete cosine transform treatment. However, in the MPEG1 system, the discrete cosine transform coefficients having an even value are added +1 or -1 to ensure that the discrete cosine transform coefficients subjected to inverse discrete cosine transform treatment have all odd values. As a result of this operation, for example, when only the first of the four special coefficients F (0,0) has a non-zero value, because a mismatch error occurs when F (0,0) is a multiple of four but not is a multiple of eight, if the discrete cosine transform coefficients are treated so that they all have an odd value, the result, when the discrete cosine transform coefficient is subjected to inverse discrete cosine transform treatment, cannot be equal to *. 5. Similarly, when only one of the other four special coefficients F (0.4), F (4.0), F (4.4) has a non-zero value, a mismatch error will occur. However, when several of the four special coefficients have a non-zero value, as can be seen in figure 4, or when symmetrically arranged pairs of coefficients occur, as in cases (1) and (2) mentioned above, the fact making all the discrete cosine transform coefficients odd will not prevent a mismatch error from occurring.

Therefore, the odd-value conversion process of the MPEG1 system will not prevent a cumulative mismatch error from occurring when two or more of the discrete cosine transform coefficients have a non-zero value. In addition, the odd-value conversion treatment of the MPEG1 system reduces the resolution of the quantized transform coefficients by a factor of 2, since transform coefficients with even values ​​are not supported. This degrades the quality of the image. If high image quality is required, this is a problem. A better way to avoid cumulative mismatch errors than that proposed in the MPEG1 standard is clearly desirable.

The invention provides a summation odd-value conversion circuit, intended to receive a block of discrete cosine transform coefficients (DCT - "discrete cosine transform") and process them in order to output a block of transform coefficients. Discrete cosine converted to odd value in sum, in order to avoid that a mismatch error occurs when the discrete cosine transform coefficients converted to odd value in the sum are inverse orthogonal transformed by a

ES 2 389 797 T3 inverse discrete cosine transform processing, such that said circuit comprises: an accumulator for determining the sum of the discrete cosine transform coefficients of the block of discrete cosine transform coefficients; a parity determination circuit, adapted to judge or determine whether the sum of the discrete cosine transform coefficients determined by the accumulator is an odd number or an even number; and a parity inverter, intended to change the parity of at least one of the block's discrete cosine transform coefficients in order to make the parity of the sum of the discrete cosine transform coefficients odd only when the circuit determining parity determine that the parity of the sum of the discrete cosine transform coefficients is even.

How the invention avoids cumulative mismatch errors will now be described.

An examination of equation (4) shows that mismatch occurs when expressions in the equation yield a result of (2n + 1) / 2, where n is any integer.

Equation (4) can be summarized as:

f (x, y) = 1/8 ACC where ACC is the sum of all coefficients.

The most common mismatch configuration is:

f (x, y) = 1/8 ACC = (2n +1) / 2 = 1/8 (4 * (2n +1))

From this expression it can be deduced that if ACC becomes an odd number, a mismatch error will never occur.

Accordingly, this invention uses a scheme to inverse quantize the discrete cosine transform coefficients, and then, prior to inverse discrete cosine transform processing, to calculate the sum of the discrete cosine transform coefficients. If the sum of the discrete cosine transform coefficients are even valued (that is, the parity of the sum is even), the parity of one of the discrete cosine transform coefficients is changed to make the sum of the transform coefficients odd. discrete cosine (that is, to make the sum parity odd). It is enough to change the parity of only one of the discrete cosine transform coefficients to make the sum of the discrete cosine transform coefficients odd. Also, the parity of the coefficient having the least influence on the output value of the inverse discrete cosine transform can be changed. In other words, this invention, by checking the parity of the sum of the discrete cosine transform coefficients before the inverse discrete cosine transform treatment and, if the parity of the sum is even, by changing the parity of one of the Discrete cosine transform coefficients to make the sum of the discrete cosine transform coefficients odd, effectively avoid the occurrence of mismatch errors.

It should be emphasized that, according to the invention, it is sufficient to change the parity of only one of the discrete cosine transform coefficients to make the sum of the discrete cosine transform coefficients odd. The MPEG1 system odd all discrete cosine transform coefficients, which reduces the resolution of discrete cosine transform coefficients subjected to inverse discrete cosine transform processing by a factor of two. The mismatch error avoidance method according to the invention, on the other hand, makes the sum of the discrete cosine transform coefficients odd in such a way that the accuracies of the input and output values ​​of the transform do not substantially decrease. inverse discrete cosine. When the method according to the invention is applied to a moving picture signal compressor, a compressed motion picture signal expander, or an apparatus for transmitting a compressed motion picture signal, the degradation of image quality.

Additionally, when applying the invention to the MPEG system, the minimum quantization increment may be equal to 1, in contrast to the prior art method in which the minimum quantization increment was equal to 2.

The invention will be further described hereinbelow, with reference to the following discussion of exemplary embodiments and the accompanying drawings, in which:

Fig. 1 is a block diagram showing the configuration of a conventional moving picture signal compressor apparatus according to the MPEG system.

Fig. 2 is a block diagram showing the configuration of a conventional moving image signal expander apparatus according to the MPEG system.

Figure 3 illustrates the sequence in which a moving picture signal is compressed in the

ES 2 389 797 T3 MPEG system.

Figure 4 shows real examples of the values ​​of discrete cosine transform coefficients (DCT - "discrete cosine transform").

Figure 5 illustrates the processing operations used to inversely quantify both intra macro blocks and non intra macro blocks in the conventional MPEG1 system.

Fig. 6 is a block diagram showing the configuration of a first embodiment of a moving image signal compressor apparatus according to the invention.

Figure 7 illustrates how a block of discrete cosine transform coefficients is read using zigzag scanning.

Figure 8 is a block diagram of a first practical embodiment of the odd-sum conversion circuit 14 represented in Figure 6.

FIG. 9 is a flow chart illustrating the operation of the odd sum conversion circuit 14 depicted in FIG. 8.

FIG. 10A is a block diagram of a second embodiment of the sum odd conversion circuit depicted in FIG. 6.

Figure 10B shows a variant of the second embodiment of the odd-sum conversion circuit represented in Figure 6.

Figure 11 is a block diagram showing a first embodiment of the parity inverter depicted in Figure 8.

Fig. 12 is a flow chart for explaining the operation of a second embodiment of the aforementioned parity inverter.

Fig. 13 is a block diagram of the second embodiment of the aforementioned parity inverter.

Fig. 14 is a flow chart for explaining the operation of a third embodiment of the aforementioned parity inverter.

Fig. 15 is a block diagram of the third embodiment of the aforementioned parity inverter.

Fig. 16 is a flow chart for explaining the operation of a fourth embodiment of the aforementioned parity inverter.

Fig. 17 is a block diagram of the fourth embodiment of the aforementioned parity inverter.

Fig. 18 is a block diagram of a third embodiment of the sum odd conversion circuit depicted in Fig. 6.

Fig. 19 is a diagram showing the configuration of the first exemplary compressed motion picture signal decompressor apparatus according to the invention.

Fig. 20 is a block diagram of an inverse quantizer and odd-sum converter included in the compressed motion picture signal decompressor apparatus shown in Fig. 19.

Fig. 21 is a timing diagram explaining the operation of the aforementioned inverse quantizer and odd-sum converter.

Fig. 22 is a block diagram showing the configuration of a second exemplary image signal compressor apparatus in accordance with the invention.

Fig. 23 is a block diagram showing a first embodiment of the odd-number sum converter circuit pertaining to the motion picture signal compressor apparatus illustrated in Fig. 22.

Fig. 24 is a block diagram showing a second embodiment of the odd-sum converter circuit pertaining to the motion picture signal compressor apparatus illustrated in Fig. 22.

Fig. 25 is a block diagram showing a third embodiment of the odd-number sum converter circuit pertaining to the motion picture signal compressor apparatus illustrated in Fig. 22.

Figure 26 is a block diagram depicting one embodiment of the parity inverter included in the odd sum conversion circuits illustrated in Figures 23-25.

Figure 27 shows a first variant of the parity inverter represented in Figure 26.

Figure 28 represents a second variant of the parity inverter illustrated in Figure 26.

Figure 29 represents a third variant of the parity inverter illustrated in Figure 26.

Fig. 30 is a block diagram showing the configuration of a second exemplary compressed motion image signal expander apparatus in accordance with the invention.

Embodiments of an inverse discrete cosine transform method, an exemplary inverse discrete cosine transform apparatus, a moving image signal compressor apparatus, an image signal decompressor apparatus will now be described with reference to the drawings. with compressed movement, and a transmission apparatus.

ES 2 389 797 T3

The invention is applied to a hybrid coding system in which predictive coding with motion compensation is combined with discrete cosine transform (DCT) treatment. The hybrid coding system is described in ISO-IEC / JTC1 / SC2 / WG11 (popularly called MPEG). The basic configuration of the hybrid MPEG coding system is well known. The VG11 report includes a useful glossary of terms that is used herein.

Predictive coding with motion compensation is a method of reducing the redundancy of a moving picture signal by exploiting the correlation of the moving picture signal in the time domain. The prediction for motion compensation of the current image (that is, the image that is currently being encoded) is performed using another image, already decoded, of the moving image signal as a reference image. The resulting motion compensated prediction errors are included in the compressed signal along with a motion vector and prediction mode, etc. This greatly reduces the amount of information in the compressed motion picture signal that is required to represent the current picture.

The motion compensated prediction error signal is compressed using a signal compressor that exploits the spatial correlation of each image that constitutes the moving image. The difference signal compressor typically includes an orthogonal transform circuit, such as a discrete cosine transform computing circuit, and a quantizer. The discrete cosine transform is a form of orthogonal transform that concentrates signal power into specific frequency components as a result of two-dimensional intra-image (frame or field) correlation of the image. Thus, only the concentrated and distributed coefficients are included in the compressed signal, either directly or after further compression. This further reduces the amount of information in the compressed motion picture signal that is required to represent the current picture.

Predictive coding with inter-picture motion compensation can be performed between frames of the motion picture signal. Alternatively, if the motion picture signal is an interlaced signal, predictive coding with motion compensation can be performed between fields. Additionally, predictive coding with inter-picture motion compensation can be adaptively switched between inter-frame coding and inter-field coding, depending on the properties of the motion picture signal.

1. First Realization

Figure 6 shows the practical configuration of the moving image signal compressor apparatus to which the invention is applied as defined in the appended claims. In the apparatus shown in Fig. 6, the moving picture signal is divided into pictures, and it is compressed picture by picture. Each image is divided into image blocks, and the image is compressed block by block. The image block that is currently being compressed will be called the current image block. The current image block is a block of an image called the current image.

The moving picture signal, usually a video signal, is supplied to the first picture memory group 2, in which several pictures of the moving picture signal are temporarily stored. The memory controller 3 controls the reading of images from the first group 2 of image memories and the second group 4 of image memories. The memory controller 3 also supplies the block line start signal SS and the macro block start signal BS to the matrix line / macro block counter 5. The memory controller supplies these signals, respectively, in sync with each line of blocks and each macroblock of each image (eg, the current image) read from the first group 2 of image memories for compression. A block line is a horizontal row of blocks that covers the width of the image.

The motion predictor 6 performs the motion prediction by performing block matching between the current picture block and several blocks of the previous and next pictures stored in the first group 2 of picture memories. Block adaptation is done using blocks of, for example, 16 x 16 pixel elements. The motion prediction reference image indication signal generated by the memory controller 3 selects the blocks of the previous and next images stored in the first image memory group 2 to check their adaptation with the current block. The motion predictor 6 supplies to a motion compensator 7, as a motion vector MV, the position of a block in one of the previous or next images stored in the first group 2 of image memories, for which the differences are minimal. between the block and the current image block, that is, the motion prediction errors.

In response to the motion vector MV, the motion compensator 7 causes a block of each of the reconstructed images stored in the second image memory group 4 to be read as a potential adaptation block. The position in the reconstructed images from which the potential adaptation blocks are read is specified by the motion vector MV. The reference image indication signal with

ES 2 389 797 T3 motion compensation generated by the memory controller 3 then selects one of the potential adaptation blocks read from the second group 4 of image memories, as the adaptation block for the current block. The reconstructed images stored in the second image memory group 4 are images that have been reconstructed by locally decoding the quantized discrete cosine transform coefficients generated by the difference block encoder 9, which will be described later.

The reconstructed image, from which the adaptation block is selected by the motion-compensated reference image indication signal, depends on the current image prediction mode. In the advance prediction mode, the adaptation block is selected from a previous reconstructed image. In bidirectional prediction mode, the adaptation block is selected from a previous reconstructed image and a future reconstructed image, or it can be generated by performing a linear operation (for example, calculation of the mean value) on blocks of a previous reconstructed image and a future reconstructed image. Finally, when the current image is encoded in the intra-image encoding mode, that is, the image is encoded without prediction, a null block is used, in which all the pixel values ​​are set to zero, as a block of adaptation. The adaptation blocks read from the second picture memory group 4 are adaptively modified such that an optimally adapted adaptation block is selected for each block of the moving picture signal.

The motion compensator 7 selects the prediction mode for each image by first calculating the sum of the absolute values ​​of the pixel-by-pixel differences between the current picture block and the potential matching blocks generated in the different picture modes. prediction. The motion compensator 7 then selects the prediction mode for which this sum is minimal. The motion compensator 7 supplies the prediction mode signal MM, indicating the selected prediction mode, to the variable-length encoder 17 (to be described later). The motion compensator 7 also causes the second image memory group 4 to supply the difference generator circuit 8 with the adaptation block S2 corresponding to the selected prediction mode.

The difference generator circuit 8 also receives the current picture block S1 of the motion picture signal read from the first picture memory group 2, and calculates the pixel by pixel differences between the picture block S1 in course and adaptation block S2. The difference generator circuit 8 supplies the difference block encoder 9 with the resulting difference block S3. Difference block encoder 9 compresses difference block S3 to form quantized transform coefficient block SC. The quantized transform coefficient block SC is supplied to the local decoder 10, where it is expanded to provide the recovered difference block S4. The local decoder 10 of the motion picture signal compressor apparatus has a configuration similar to that of the compressed motion picture signal expander apparatus, which will be described later, but differs in details.

The difference block encoder 9 and the local decoder 10 will now be described.

Difference block encoder 9 comprises discrete cosine transform circuit 11 and quantizer 12, as shown in Figure 6. Discrete cosine transform circuit 11 uses discrete cosine transform processing to orthogonally transform block S3 difference provided by the difference generator circuit 8. The discrete cosine transform circuit 11 supplies the resulting block of discrete cosine transform coefficients to the quantizer 12. The quantizer 12 quantizes the block of discrete cosine transform coefficients to provide the block SC of quantized transform coefficients.

Local decoder 10 comprises inverse quantizer 13, odd-sum conversion circuit 14, and inverse discrete cosine transform circuit 15, as shown in Figure 6. Inverse quantizer 13 uses a quantization table to quantize inversely the block SC of quantized transform coefficients generated by quantizer 12. The summation odd conversion circuit 14 performs a parity inversion operation on the resulting block of discrete cosine transform coefficients when the sum thereof is not an odd number. This prevents a mismatch error from occurring when the block of discrete cosine transform coefficients whose sum has been converted to an odd value is subjected to an inverse orthogonal transform. The inverse discrete cosine transform circuit 15 (IDCT "inverse discrete cosine transform") performs an inverse discrete cosine transform treatment on the block of discrete cosine transform coefficients whose sum has been converted into an odd value and which are generated by summation odd conversion circuit 14 to provide a recovered difference block.

The quantization performed by quantizer 12 will now be described. Each 8 x 8 discrete cosine transform coefficient block is quantized. Each block of an image compressed in the intra-image coding mode (an I-image) is called an intra macroblock. Each block compressed in an inter-picture coding mode is called a non-intra macroblock. When an intra macroblock is orthogonally transformed,

ES 2 389 797 T3 the discrete cosine transform coefficient of the component (0,0) is the DC coefficient. The continuous coefficient is quantized by dividing said coefficient by 8, with rounding, when it is quantized with a precision of eight bits, by 4 when it is quantized with a precision of nine bits, by 2 when it is quantized with a precision of ten bits, and times 1 when quantized to eleven-bit precision. The continuous component of an intra macroblock is quantized according to the following equations, which are written in the syntax of the C programming language:

QDC = dc // 8 (8 bits)

QDC = dc // 4 (9 bits)

QDC = dc // 2 (10 bits)

... (5)

QDC = dc // 1 (11 bits) where dc is the DC coefficient and QDC is the quantized DC coefficient.

The discrete cosine transform coefficients, different from the continuous coefficient, resulting from orthogonally transforming an intra macroblock (the alternating components), are quantized by determining the quantization factors ac^-(i, j) by weighting the coefficients ac (i, j) of the discrete cosine transform by the weighting matrix Wi, according to the following equation:

ac^-(i, j) = (16 * ac (i, j)) // Wi (i, j) ... (6)

The coefficients of the weighting matrix Wi are as follows:

Wi = 8 16 19 22 26 27 29 34

16 22 24 27 29 34 37

22 26 27 29 34 34 38

22 26 27 29 34 37 40

26 27 29 32 35 40 48

... (7)

27 29 32 35 40 48 58

27 29 34 38 46 56 69

Then, using the following equation, the factors ac are quantified^-(i, j) of quantization to determine the QAC (i, j) levels of quantization of the respective alternating coefficients.

ac (i, j) + sign (ac (i, j)) * ((p * mquant) // q) (2 * mquant)

... (8)

In the above equation, p and q are arbitrary fixed integers, for example p = 3 and q = 4, and mquant is the coefficient of quantization.

The discrete cosine transform coefficients resulting from orthogonally transforming an inter-image coding macroblock (a non-intra macroblock) are quantized by determining the factors ac^-(i, j) of quantization by weighting all the discrete cosine transform coefficients obtained by transformation of the non-intra macroblock, by the weighting matrix Wn according to the following equation:

ac^-(i, j) = (16 * ac (i, j)) // Wn (i, j) ... (9)

The coefficients of the weighting matrix Wn are as follows:

Wn = 16 17 18 19 20 21 22 23

18 19 20 21 22 23 24

19 20 21 22 23 24 25

ES 2 389 797 T3

20 21 22 23 24 26 27

21 22 23 25 26 27 28

... (10)

22 23 24 26 27 28 30

23 24 26 27 28 30 31

24 25 27 28 30 31 33

Then, using the following equation, the factors ac are quantified^-(i, j) of quantization to determine the QAC (i, j) levels of quantization of the alternating coefficients.

QAC (i, j) = ac^-(i, j) / (2 * mquant) if (mquant == odd) = (ac^-(i, j) +1 / (2 * mquant) if (mquant == even AND ac- <0) ... (11) = (ac^-(i, j) -1 / (2 * mquant) if (mquant == even AND ac-> 0)

The resulting quantization levels QAC (i, j) are supplied to the variable-length encoder 17 and the local decoder 10 as the above-described block of quantized discrete cosine transform coefficients SC.

The variable length encoder 17 applies variable length coding to the block of quantized discrete cosine transform coefficients obtained by quantizing the block of discrete cosine transform coefficients. The variable length encoder 17 determines differences between the quantized transform coefficients in the four luminance blocks that make up each macroblock and the DC coefficient of the respective intra macroblock. The variable length encoder then uses a variable length encoding table to apply variable length encoding to the resulting difference values. This technique takes advantage of the high correlation between the four adjacent luminance blocks, which means that the DC coefficients have substantially the same value. The variable length encoder 17 also determines the differences between the quantized coefficients of two color difference blocks, and uses the variable length coding table to apply variable length coding to the resulting difference values. The variable length coding table for the luminance coefficients and the one for the color differences are different from each other.

Variable-length encoder 17 applies variable-length encoding to the block of quantized discrete cosine transform coefficients by reading the block of quantized discrete cosine transform coefficients in zigzag scan order, starting with the discrete cosine transform coefficient of the component (0,0), as shown in figure 7. The block of quantized discrete cosine transform coefficients is read zigzag because the nonzero discrete cosine transform coefficients resulting from the discrete cosine transform treatment are generally concentrated in the vicinity of the (0,0) component. Thus, reading the zigzag discrete cosine transform coefficients increases the efficiency of variable length encoding by increasing the field of consecutive null discrete cosine transform coefficients read between each of the non-discrete cosine transform coefficients. null.

Variable-length encoder 17 reads the zigzag discrete cosine transform coefficients and determines the value (in other words, the level) of each non-zero discrete cosine transform coefficient, and the number (in other words, the field of coverage) of the preceding null discrete cosine transform coefficients. This procedure performs two-dimensional variable length encoding of the block of discrete cosine transform coefficients. After coding, the block coefficients are expressed by the number of the coverage field and pairs of levels. Variable-length encoder 17 also adds a two-bit code (EOB) indicating the non-zero discrete cosine transform coefficient which is the last non-zero discrete cosine transform coefficient. The variable length encoder 17 supplies an address converter (not shown) with the address of the last non-zero coefficient in zigzag scan order. The address converter converts the address in zigzag scan order to an address, EOB_adrs, in frame scan order. The variable length encoder 17 supplies the address EOB_adrs to the odd sum conversion circuit 14.

ES 2 389 797 T3

The summation odd conversion circuit 14 stores the EOB_adrs address in frame scan order in the register 25 shown, for example, in FIG. 8, which will be described later.

The inverse quantizer 13 will now be described. The inverse quantizer 13 receives the block SC of quantized discrete cosine transform coefficients from the difference block encoder 10, and inverse quantizes the block of quantized discrete cosine transform coefficients to provide a block of discrete cosine transform coefficients. In practice, the inverse quantizer 13 inversely quantizes the quantized DC coefficients resulting from orthogonally transforming an intra macroblock using the treatment defined by equation (12) to provide respective DC coefficients. The inverse quantizer 13 also inverse quantizes the alternating coefficients resulting from orthogonally transforming an intra macroblock using the treatment defined in equation (13). Finally, the inverse quantizer 13 inversely quantifies all the quantized coefficients resulting from orthogonally transforming a non-intra macroblock using the treatment defined in equation (14).

rec (0, 0) = 8 * QDC rec (0, 0) = 4 * QDC (9 bits) rec (0, 0) = 2 * QDC (10 bits)

... (12) rec (0, 0) = 1 * QDC (11 bits) rec (i, j) = (mquant * 2 * QAC (i, j) * Wi (i, j)) / 16 if ( QAC (i, j) == 0) rec (i, j) = 0 ... (13) if (QAC (i, j)> 0) rec (i, j) = ((2 * QAC (i, j) +1) * mquant * Wn (i, j)) / 16 if (QAC (i, j) <0) rec (i, j) = ((2 * QAC (i, j) -1) * mquant * Wn (i, j)) / 16 if (QAC (i, j) == 0)

... (14) rec (i, j) = 0

The resulting block of discrete cosine transform coefficients is transferred from the inverse quantizer 13 to the odd-sum conversion circuit 14, a practical example of which is illustrated in FIG. 8.

The odd sum conversion circuit 14 comprises the accumulator 23A, the parity determination circuit 21, and the parity inverter 28. The accumulator 23A determines the sum of the discrete cosine transform coefficients in the block of discrete cosine transform coefficients received from the inverse quantizer 13. The parity determining circuit 21 judges whether the sum of the discrete cosine transform coefficients determined by the accumulator 23A is an odd number or an even number, that is, whether the parity of the sum of the discrete cosine transform coefficients is odd. or pair. Only when the parity determining circuit 21 judges that the parity of the sum of the discrete cosine transform coefficients is even, does the parity inverter 28 change the parity of at least one of the block's discrete cosine transform coefficients to make the parity of the sum of said coefficients odd, that is, the parity of the sum is made odd. This prevents a mismatch error from occurring when the block of discrete cosine transform coefficients whose sum parity has been converted to odd, from the odd sum conversion circuit 14, is subjected to an inverse orthogonal transform by the circuit 15 inverse discrete cosine transform.

Counter 20 counts the number of discrete cosine transform coefficients received from inverse quantizer 13, and supplies the count coeff_adrs to parity determining circuit 21 and memory selector 22.

Accumulator 23A comprises adder 23 and register 24. Adder 23 sums each discrete cosine transform coefficient into a block of discrete cosine transform coefficients received from the

ES 2 389 797 T3 inverse quantizer 13, to the sum of the discrete cosine transform coefficients already received in the block stored in register 24. Register 24 is reset after having determined the sum for each block of transform coefficients discrete cosine. The resulting sum of said coefficients is transferred from adder 23 to register 24, and to parity determination circuit 21. The accumulator 23A only needs to add the least significant bits of the block's discrete cosine transform coefficients to provide a suitable result for the parity determining circuit 21 to judge whether the parity of the sum of the discrete cosine transform coefficients is odd or even.

The parity determining circuit 21 judges whether the parity of the sum of the discrete cosine transform coefficients included in the block is odd or even in response to the count value coeff_adrs received from counter 20. When all the block's discrete cosine transform coefficients have been supplied to accumulator 23A, the count value coeff_adrs indicates that accumulator 23A has determined the sum of all block's discrete cosine transform coefficients. In response to the count coeff_adrs value, the parity determining circuit 21 judges whether the parity of the sum of the discrete cosine transform coefficients from the accumulator 23A is odd or even. For example, in the case of an 8 x 8 two-dimensional discrete cosine transform transform, the parity determination circuit 21 judges whether the parity of the sum of the discrete cosine transform coefficients from accumulator 23A is odd or even when the count coeff_adrs value indicates that the sixty-four discrete cosine transform coefficients of the block have been transferred to accumulator 23A.

In practice, for example, when each discrete cosine transform coefficient is represented by a binary number, the parity determination circuit 21 examines the least significant bit (LSB) of the sum of the coefficients of discrete cosine transform received from accumulator 23A. A null least significant bit indicates that the sum's parity is even. In this case, the parity determining circuit 21 supplies the treatment request signal REQ1 to the parity inverter 28 to cause this circuit to perform a parity inversion operation. In response to the treatment request signal REQ1, the parity inverter 28 changes the parity of at least one (i.e., an odd number) of the discrete cosine transform coefficients to make the parity of the sum of said coefficients odd. . On the other hand, a least significant bit equal to 1 indicates that the parity of the sum is odd. In this case, the parity determining circuit 21 does not generate the treatment request signal REQ1, and the parity inverter 28 does not modify the parity of all the discrete cosine transform coefficients of the block.

In the illustrated practical circuit, the discrete cosine transform coefficients from the inverse quantizer 13 are stored in the first memory 26 or in the second memory 27 through the memory selector 22. Memory selector 22 operates in response to the count coeff_adrs value received from counter 20. Thus, for example, when the memory selector 22 determines that all the discrete cosine transform coefficients of the block have been stored in the first memory 26, the memory selector 22 specifies the second memory, so that the transform coefficients of Discrete cosines of the next block are stored in the second memory 27. Thus, consecutive blocks of discrete cosine transform coefficients are alternately stored in first memory 26 and second memory 27. When all the discrete cosine transform coefficients of the block have been stored in the first memory 26 or in the second memory 27, the memory in which all the discrete cosine transform coefficients of the block are stored applies the signal FULL1 or FULL2 of memory full to parity inverter 28.

When the parity inverter 28 receives the memory full signal FULL1 or the memory full signal FULL2, it applies the read enable signal RD_EN1 or the read enable signal RD_EN2 to the memory that generated the memory full signal. This causes the block of discrete cosine transform coefficients to be transferred from the memory that generated the memory full signal to the parity inverter 28. The parity inverter 28 operates on the block of discrete cosine transform coefficients read from memory in one of two modes, depending on whether the parity determining circuit 21 has generated the treatment request signal REQ1. When the parity inverter 28 receives the treatment request signal REQ1, it inverts the least significant bit of one of the block's discrete cosine transform coefficients, eg, the last non-zero coefficient, in zigzag scan order. The parity inverter 28 identifies the discrete cosine transform coefficient whose parity can be inverted using the address of the discrete cosine transform coefficients whose parity can be inverted stored in register 25. For example, Figure 8 shows the direction of the last non-zero coefficient (address EOB_adrs), applied to comparator 62. Thus, in this example, the discrete cosine transform coefficient whose parity can be inverted is the last non-zero coefficient. When the parity inverter 28 reverses the parity of the discrete cosine transform coefficient whose parity can be inverted, the parity of the sum of nonzero coefficients in the block, from the first to the last, becomes odd. The parity inverter 28 supplies all discrete cosine transform coefficients, other than the coefficient with its least significant bit inverted, to the inverse discrete cosine transform circuit 15, with the state of its least significant bits unchanged. The parity inverter 28 also supplies the inverse discrete cosine transform circuit 15 with the discrete cosine transform coefficient whose parity can be inverted with the state of its least significant bit, depending on whether the parity inverter has received the request signal REQ1. treatment.

ES 2 389 797 T3

The parity inverter 28 can be implemented using a computer or digital signal processor that operates, for example, in accordance with the flow chart illustrated in Figure 9. In this example, the discrete cosine transform coefficient whose parity can be inverted is the last non-zero coefficient. In step S1, the parity inverter 28 judges, based on the address EOB_adrs, whether or not the discrete cosine transform coefficient being processed is the coefficient whose parity can be inverted by inverting its least significant bit. If the result of step S1 is affirmative, the execution sequence continues to step S2. In another case, execution proceeds to step S5, which will be described later.

In step S2, the parity inverter 28 determines whether the treatment request signal REQ1 has been received. If the result of step S2 is affirmative, indicating that the treatment request signal REQ1 has been received, the execution sequence continues to step S3. Otherwise, no treatment request has been received and execution continues to step S5.

In step S3, the parity inverter 28 inverts the least significant bit of the discrete cosine transform coefficient whose parity can be inverted to invert its parity, and hence to change the parity of the sum of the discrete cosine transform coefficients. The execution sequence proceeds to step S4, in which the inverted parity discrete cosine transform coefficient is supplied to the inverse discrete cosine transform circuit 15 (FIG. 10A). Next, the execution sequence returns to step S1, in which the next discrete cosine transform coefficient is processed.

The execution sequence goes to step S5 when the discrete cosine transform coefficient being processed is not the coefficient whose parity can be inverted, or when the discrete cosine transform coefficient whose parity is inverted is not going to have its parity, that is, when the treatment request signal REQ1 has not been received. In step S5, the discrete cosine transform coefficient is applied to the inverse discrete cosine transform circuit 15 without modification. Next, the execution sequence returns to step S1, where the next discrete cosine transform coefficient is processed.

When the discrete cosine transform coefficients are represented by a 2's complement representation, the least significant bit mentioned above is the least significant bit of the 2's complement representation. On the other hand, when the discrete cosine transform coefficients are represented by a sign and an absolute value, the least significant bit mentioned above is the least significant bit of the absolute value.

The configuration of the sum odd conversion circuit 14 is not limited to that illustrated in FIG. 8. For example, in the odd sum conversion circuit depicted in FIG. 10A, the sum detector 29 has been added. least significant bit, and the adder 23 has been replaced by the exclusive-OR gate 30 in the odd-sum conversion circuit shown in FIG. 8. The elements that appear in the circuit shown in Figure 10A corresponding to those of the circuit illustrated in Figure 8, are indicated by the same reference figures and will not be described again.

In FIG. 10A, the least significant bit detector 29 detects the least significant bit of each discrete cosine transform coefficient in the block of discrete cosine transform coefficients. Exclusive OR gate 30 performs an exclusive OR logical operation between each block's discrete cosine transform coefficient and the exclusive logical sum, stored in register 24, of the least significant bits of the block's discrete cosine transform coefficients that have already been treated. Thus, exclusive-OR gate 30 and register 24 obtain the exclusive logical sum of the least significant bits of the discrete cosine transform coefficients in each block. The combination of exclusive-OR gate 30 and register 24 can also be considered as a computational arrangement of the discrete cosine transform coefficients having a least significant bit equal to 1. Then, when all the block's discrete cosine transform coefficients have been received, the state of the exclusive-OR gate output indicates whether the count of discrete cosine transform coefficients having a least significant bit equal to 1 is odd. or pair. The parity determining circuit 21 then outputs the treatment request signal REQ1 when the count of the discrete cosine transform coefficients having a least significant bit equal to 1 is even.

Figure 10B shows an alternative configuration that can be used in place of exclusive-OR gate 30 and register 24. In this arrangement, the least significant bits of each discrete cosine transform coefficient received from inverse quantizer 13 are transferred from detector 29 least significant bit until AND gate 88. AND gate 88 passes to counter 89 only the least significant bits that have the value 1. Counter 89 resets to the beginning of each block of discrete cosine transform coefficients and counts each least significant bit of value 1 that it receives. The least significant bit of the COUNT count of the counter 89 is transferred to the parity determination circuit 21. At the end of each block, the parity determination circuit 21 determines the parity of the least significant bit of the COUNT count of the counter 89. If the parity of the COUNT count is odd (that is, the least significant bit of the COUNT count is a 1), this indicates that there is an odd number of discrete cosine transform coefficients with an equal least significant bit

ES 2 389 797 T3 to 1 in the block, and that the parity of the sum of said coefficients of the block is odd. On the other hand, if the parity of the COUNT count is even (that is, the least significant bit of the COUNT count is a 0), this indicates that there is an even number of discrete cosine transform coefficients with a least significant bit equal to 1 in the block, and that the parity of the sum of said block coefficients is even.

A practical configuration of a first embodiment of the parity inverter 28 included in the odd sum conversion circuits illustrated in Figures 8 and 10A will now be described with reference to Figure 11. The parity inverter 28 comprises the read counter 61, the address comparator 62, the least significant bit inverter 63, the AND gates 64, 65, 67 and 68, the OR gates 66 and 69, and the inverter gates 71 and 72.

The parity inverter 28 operates as follows. When the read counter 61 receives the memory full signal FULL from the first memory 26 or the second memory 27, it supplies the read enable signal RD_EN to the first memory 26 or the second memory 27. The read enable signal causes the respective memory to sequentially transfer the discrete cosine transform coefficients of the block of discrete cosine transform coefficients stored therein to the first AND gate 67 through the data path indicated as RDATA.

The memory full signal FULL also causes the read counter 61 to begin counting the received discrete cosine transform coefficients and provide the address comparator 62 with a count value indicating the number of received discrete cosine transform coefficients. The address comparator 62 compares the count value with the address received from register 25 and determines whether the discrete cosine transform coefficient received by the first AND gate 67 is the coefficient whose parity can be inverted, that is, the cosine transform coefficient. discrete whose least significant bit can be reversed. In the example illustrated in FIG. 11, the discrete cosine transform coefficient whose parity can be reversed is the last non-zero coefficient, identified by the address EOB_adrs stored in address comparator 62. When the count value is equal to the direction of the discrete cosine transform coefficient whose parity can be inverted, in this example the address EOB_adrs, the address comparator 62 determines that the discrete cosine transform coefficient is the coefficient whose parity can be inverted. , and changes the state of its output from 0 to 1.

The output of the address comparator 62 is applied directly to the second AND gate 68 and, through the inverting gate 72, to the first AND gate 67. Thus, when the count value is not equal to the EOB_adrs address, the first AND gate 67 opens and the second AND gate 68 closes. Thus, the discrete cosine transform coefficients pass unchanged, through the first AND gate 67 and OR gate 69, to the inverse discrete cosine transform circuit 15.

On the other hand, when the discrete cosine transform coefficient supplied to the parity inverter 28 is the coefficient whose parity can be inverted, and the count value is equal to the direction of the coefficient whose parity can be inverted, in this example the address EOB_adrs, the output of the address comparator 62 changes state as previously described. This change closes the first AND gate 67 and opens the second AND gate 68. As a result, the discrete cosine transform coefficient with its least significant bit inverted, received through OR gate 66, is supplied to inverse discrete cosine transform circuit 15 through second AND gate 68 and OR gate 69. .

The discrete cosine transform coefficient with its least significant bit inverted is selectively supplied to the inverse discrete cosine transform circuit 15 in response to the treatment request signal REQ1 by transferring the discrete cosine transform coefficients, received through the path. Data RDATA, to the third AND gate 64 and the least significant bit inverter 63. The treatment request signal REQ1 is supplied from the parity determining circuit 21 directly to the fourth AND gate 65 and, through the inverting gate 71, to the third AND gate 64. The least significant bit inverter 63 inverts the least significant bit of each discrete cosine transform coefficient received through the RDATA data path and supplies the resulting discrete cosine transform coefficient with its least significant bit inverted to the fourth AND gate. 65.

The absence of the treatment request signal REQ1, that is, when the treatment request signal is in its 0 state, indicates that the discrete cosine transform coefficient whose parity can be inverted has to be supplied to the inverse discrete cosine transform circuit without its least significant bit reversed. The treatment request signal REQ1 in its 0 state opens the third AND gate 64 and closes the fourth AND gate 65. Based on this combination, the inverted discrete cosine transform coefficient, with its least significant bit unchanged, is transferred from the data RDATA path to the inverse discrete cosine transform circuit 15 through the third gate AND 64, OR gate 66, second AND gate 68, and OR gate 69.

On the other hand, the presence of the treatment request signal REQ1, that is, the treatment request signal REQ1 in its state 1, indicates that the discrete cosine transform coefficient whose parity can

ES 2 389 797 T3 inverted is to be supplied to the inverse discrete cosine transform circuit with its least significant bit inverted to change the parity of the sum of the discrete cosine transform coefficients. The treatment request signal REQ1 in its state 1 closes the third AND gate 64 and opens the fourth AND gate 65. This transfers the inverted discrete cosine transform coefficient, with its least significant bit reversed, from the least significant bit inverter 63 to the inverse discrete cosine transform circuit 15 through the fourth AND gate 65, the gate OR 66, the second AND gate 68, and the OR gate 69.

A second embodiment of the parity inverter 28 will now be described with reference to FIG. 12. When the second embodiment of the parity inverter 28 receives the treatment request signal REQ1, it converts the parity of the sum of the discrete cosine transform coefficients into odd by adding 1 to the discrete cosine transform coefficient whose parity can be inverted.

The second embodiment of the parity inverter 28 may be implemented in a computer or digital signal processor operating in accordance with the flow chart illustrated in Figure 12. The flow chart depicted in Figure 12 is similar to the flow chart depicted in Figure 9, with the exception of the operation performed in step S3. In step S3, the second embodiment of the parity inverter 28 makes the parity of the sum of the discrete cosine transform coefficients odd by adding 1 to the discrete cosine transform coefficient whose parity can be inverted, instead of inverting the least significant bit of the discrete cosine transform coefficient whose parity can be reversed. The discrete cosine transform coefficient whose parity can be reversed may be, for example, the last non-zero coefficient in the block, or the discrete cosine transform coefficient of the highest frequency component in the block.

A practical circuit configuration of the second embodiment of the parity inverter will now be described with reference to Fig. 13, in which one unit is added to the discrete cosine transform coefficient whose parity can be inverted to make the parity of the sum of the discrete cosine transform coefficients in the coefficient block. The second embodiment of the parity inverter depicted in Figure 13 is similar to the first embodiment of the parity inverter 28 illustrated in Figure 11. The elements of the circuit depicted in Figure 13 that correspond to those of the circuit depicted in Figure 11 are indicated by the same reference figures, and will not be described again in this case.

The parity inverter depicted in Figure 13 includes the one-unit adder 73 in place of the least significant bit inverter 63 depicted in Figure 11. The one-unit adder 73 adds one unit to each discrete cosine transform coefficient read from the first memory 26 or the second memory 27 and received via the RDATA data path. One of the discrete cosine transform coefficients with a unit added in response to the treatment request signal REQ1 is selected to make the parity of the sum of the discrete cosine transform coefficients odd.

The operation of the parity inverter illustrated in Figure 13 is identical to that of the circuit depicted in Figure 11, except that the one-unit adder 73 adds one unit to each discrete cosine transform coefficient received through the path. RDATA data. Also, when the treatment request signal REQ1 is present, and the discrete cosine transform coefficient whose parity can be reversed is detected, the discrete cosine transform coefficient to which a unit has been added is transferred from the adder 73 of a unit. drive to inverse discrete cosine transform circuit 15 through third AND gate 64, OR gate 66, second AND gate 68, and OR gate 69.

A third embodiment of the parity inverter 28 will now be described with reference to Figures 14 and 15.

When the third embodiment of the parity inverter receives the treatment request signal REQ1, it makes the sum of the discrete cosine transform coefficients in the block odd by substituting the discrete cosine transform coefficient whose parity is to be inverted by the transform coefficient of discrete cosine whose parity is to be reversed, and from which one unit has been subtracted, when the sign of the discrete cosine transform coefficient is positive, and to which a unit has been added when the sign of said coefficient is negative. This treatment not only reverses the parity of the discrete cosine transform coefficient whose parity is to be inverted, but also reduces the magnitude of this discrete cosine transform coefficient, that is, it assigns a value closer to zero to the cosine transform coefficient. discrete whose parity is to be reversed. The treatment applied to the discrete cosine transform coefficient whose parity is to be inverted is defined by the following equation:

if (rec> 0) rec = rec - 1 if (rec <0) (15) rec = rec + 1

ES 2 389 797 T3 where rec is the discrete cosine transform coefficient whose parity is to be inverted.

The third embodiment of the parity inverter 28 can be implemented using a computer or digital signal processor that operates according to the flow chart depicted in Figure 14. In step S1, the parity inverter 28 judges, based on the address EOB_adrs, whether or not the discrete cosine transform coefficient is the coefficient whose parity can be reversed. For example, the parity inverter judges whether or not the discrete cosine transform coefficient is the last non-zero coefficient. If the result of step S1 is affirmative, and the discrete cosine transform coefficient is the coefficient whose parity can be reversed, the execution sequence continues to step S2. Otherwise, when the discrete cosine transform coefficient is not the coefficient whose parity can be reversed, the execution sequence continues to step S8.

In step S2, the parity inverter 28 determines whether or not the treatment request signal REQ1 has been received. If the result of step S2 is affirmative, indicating that the treatment request signal REQ1 has been received, the execution sequence continues until step S3. Otherwise, no treatment request has been received and the execution sequence continues to step S8. Since an affirmative result can only be produced in step S2 if an affirmative result has been obtained in step S1, the affirmative result of step S2 indicates that the discrete cosine transform coefficient is the coefficient whose parity is to be inverted.

In step S3, the parity inverter 28 determines the polarity of the discrete cosine transform coefficient whose parity is to be inverted. If the result of step S3 is affirmative, indicating that the polarity of the discrete cosine transform coefficient is positive, the execution sequence continues to step S4. Otherwise, the polarity of the discrete cosine transform coefficient is zero or negative, and the execution sequence continues to step S6.

In step S4, the parity inverter 28 subtracts one unit from the discrete cosine transform coefficient whose parity is to be inverted (i.e., adds -1 to said coefficient), after which the execution sequence proceeds to step S5 , where the discrete cosine transform coefficient with inverted parity is transferred to the inverse discrete cosine transform circuit 15 (FIG. 10A). Next, the execution sequence returns to step S1, where the next discrete cosine transform coefficient is processed.

In another case, in step S6, the parity inverter 28 adds one unit to the discrete cosine transform coefficient whose parity is to be inverted, after which the execution sequence continues to step S7, where the transform coefficient of Discrete cosine with inverted parity is transferred to inverse discrete cosine transform circuit 15. Next, the execution sequence returns to step S1, where the next discrete cosine transform coefficient is processed.

Execution proceeds to step S8 when the discrete cosine transform coefficient is not the coefficient whose parity can be inverted, or when the discrete cosine transform coefficient whose parity can be inverted must not have its parity inverted, that is, when the parity cannot be inverted. has received the treatment request signal REQ1. In step S8, the discrete cosine transform coefficient is transferred to the inverse discrete cosine transform circuit 15 without modification. Next, the execution sequence returns to step S1, in which the next discrete cosine transform coefficient is processed.

Figure 15 shows a practical example of the circuit configuration of the third embodiment of the parity inverter 28, in which the parity inversion is performed to reduce the magnitude of the discrete cosine transform coefficient whose parity is inverted, that is to say to make the discrete cosine transform coefficient whose parity is inverted closer to zero.

The parity inverter shown in figure 15 is similar to the parity inverter 28 shown in figure 11. The elements of the circuit shown in figure 5 corresponding to those of the circuit shown in figure 11 are indicated by the same reference figures, and will not be described again in this case. The parity inverter shown in FIG. 15 differs from the parity inverter shown in FIG. 11 in that it includes the magnitude reduction circuit 80 instead of the least significant bit inverter 63.

The magnitude reduction circuit 80 determines the polarity of the discrete cosine transform coefficient received from the first memory 26 or the second memory 27 via the RDATA data path. When the polarity of the discrete cosine transform coefficient is positive, the magnitude reduction circuit 80 subtracts one unit from the discrete cosine transform coefficient, while when the polarity of the coefficient is zero or negative, it adds one unit to the transform coefficient. discrete cosine. The parity inversion circuit shown in FIG. 15 makes the parity of the sum of the discrete cosine transform coefficients of the block odd by selecting the coefficient whose parity is inverted provided by the magnitude reduction circuit 80, and substituting the coefficient of Discrete cosine transform whose parity is to be inverted by the reduced magnitude inverted parity discrete cosine transform coefficient.

ES 2 389 797 T3

The magnitude reduction circuit 80 comprises the polarity determination circuit 81, which directly controls the fifth AND gate 84 and the sixth AND gate 85 through the inverting gate 87. The magnitude reduction circuit 80 also includes the subtractor o one-unit subtractor 82 and one-unit adder 83, which subtract one unit and add one unit, respectively, to each discrete cosine transform coefficient received over the RDATA data path. The output of one-unit subtractor 82 or the output of one-unit adder 83 is selected either by the fifth AND gate 84 or by the sixth AND gate 85 in response to the output of the polarity determination circuit 81. The outputs of AND gates 84 and 85 serve as inputs to OR gate 86, which provides the fourth AND gate 65 with the selected reduced magnitude discrete cosine transform coefficient. When it is necessary to invert the parity of the sum of the block's discrete cosine transform coefficients, the fourth AND gate selects the inverted parity and reduced magnitude output from the magnitude reduction circuit 80 to apply to the discrete cosine transform circuit 15. inverse, instead of the discrete cosine transform coefficient whose parity can be reversed.

The polarity determination circuit 81 judges the polarity of each discrete cosine transform coefficient in the block of coefficients received through the RDATA data path, and sets the status of its output to a 1 or a 0, depending on whether the discrete cosine transform coefficient polarity is positive or negative. When the polarity determining circuit 81 judges that the polarity of the discrete cosine transform coefficient is positive, the output of the polarity determining circuit 81 opens the fifth AND gate 84 and closes the sixth AND gate 85. This arrangement applies the output from the unit subtractor 82, that is the discrete cosine transform coefficient from which one unit has been subtracted, to the fourth AND gate 65 through the fifth AND gate 84 and OR gate 86.

On the other hand, when the polarity determining circuit 81 judges that the polarity of the discrete cosine transform coefficient is negative or null, the output of the polarity determining circuit 81 closes the fifth AND gate 84 and opens the sixth AND gate 85 . This arrangement transfers the output of one-unit adder 83, that is the discrete cosine transform coefficient to which one unit has been added, to the fourth AND gate 65 through the sixth AND gate 85 and OR gate 86.

The fourth AND gate 65 transfers the inverted parity reduced magnitude discrete cosine transform coefficient from the magnitude reduction circuit 80 to the second AND gate 68 in response to the treatment request signal REQ1. When the address comparator 62 determines that the discrete cosine transform coefficient received through the RDATA data path is the coefficient whose parity can be inverted, the inverted polarity reduced magnitude discrete cosine transform coefficient is transferred from the circuit. 80 reduction of magnitude to the inverse discrete cosine transform circuit 15 (FIG. 10A) as described above with reference to FIG. 11. On the other hand, when the third embodiment of the parity inverter illustrated in Fig. 15 does not receive the treatment request signal REQ1, the discrete cosine transform coefficient whose parity can be inverted is transferred unchanged to the discrete cosine transform circuit 15 reverse.

When the parity of the sum of the discrete cosine transform coefficients is to be converted to odd, the third embodiment of the parity inverter 28 shown in FIG. 15 transfers to the inverse discrete cosine transform circuit 15 the cosine transform coefficient discrete whose parity has been inverted by subtracting one unit from it when its polarity is positive, and transfers to the inverse discrete cosine transform circuit 15 the discrete cosine transform coefficient whose parity has been inverted by adding one unit to said coefficient when its polarity is zero or negative.

This treatment reverses the parity and reduces the magnitude of the discrete cosine transform coefficient whose parity is to be reversed, and makes the parity of the sum of the discrete cosine transform coefficients odd. A fourth embodiment of the parity inverter 28 will now be described with reference to Figures 16 and 17.

When the fourth embodiment of the parity inverter receives the treatment request signal REQ1, it makes the parity of the sum of the discrete cosine transform coefficients contained in the block odd by substituting the discrete cosine transform coefficient whose parity is to be inverted by the discrete cosine transform coefficient whose parity is to be reversed to which one unit has been added when the sign of the coefficient is positive, and from which one unit has been subtracted when the sign of the discrete cosine transform coefficient is negative. This treatment not only reverses the parity of the discrete cosine transform coefficient whose parity is to be inverted, but also increases the magnitude of this discrete cosine transform coefficient, that is, it makes the coefficient whose parity is to be inverted more different from zero. The treatment applied to the discrete cosine transform coefficient whose parity is to be inverted is defined by the following equation:

if (rec> 0) rec = rec + 1

ES 2 389 797 T3 if (rec &lt;0) (16) rec = rec - 1 where rec is the discrete cosine transform coefficient whose parity is to be inverted.

The fourth embodiment of the parity inverter 28 may be implemented using a computer or a digital signal processor operating in accordance with the flow chart illustrated in Figure 16. In step S1, the parity inverter 28 judges, based on the address EOB_adrs, whether or not the discrete cosine transform coefficient is the coefficient whose parity can be reversed. For example, the parity inverter judges whether or not the discrete cosine transform coefficient is the last non-zero coefficient. If the result of step S1 is affirmative, and the discrete cosine transform coefficient is the coefficient whose parity can be reversed, the execution sequence continues to step S2. Otherwise, when the discrete cosine transform coefficient is not the coefficient whose parity can be reversed, the execution sequence proceeds to step S8.

In step S2, the parity inverter 28 determines whether or not the treatment request signal REQ1 has been received. If the result of step S2 is affirmative, indicating that the treatment request signal REQ1 has been received, the execution sequence continues to step S3. Otherwise, the processing signal has not been received and the execution sequence continues to step S8. Since an affirmative result in step S2 can be produced only if an affirmative result has been obtained in step S1, the affirmative result of step S2 indicates that the discrete cosine transform coefficient is the coefficient whose parity is to be inverted.

In step S3, the parity inverter 28 determines the polarity of the discrete cosine transform coefficient. If the result of step S3 is affirmative, indicating that the polarity of the coefficient is positive, the execution sequence continues to step S4. Otherwise, the polarity of the discrete cosine transform coefficient is zero or negative and execution continues until step S6.

In step S4, the parity inverter 28 adds one unit to the discrete cosine transform coefficient, after which the execution sequence proceeds to step S5, where the inverted parity discrete cosine transform coefficient is transferred to the circuit. 15 of inverse discrete cosine transform (Figure 10A). then execution returns to step S1, where the next discrete cosine transform coefficient is processed.

In another case, in step S6, the parity inverter 28 subtracts one unit from the discrete cosine transform coefficient (i.e., adds -1 to said coefficient), after which the execution sequence continues to step S7, where the inverted parity discrete cosine transform coefficient is transferred to the inverse discrete cosine transform circuit 15. Next, the execution sequence returns to step S1, where the next discrete cosine transform coefficient is processed.

The execution sequence goes to step S8 when the discrete cosine transform coefficient is not the coefficient whose parity can be inverted, or when the discrete cosine transform coefficient whose parity can be inverted must not have its parity inverted, that is, when The treatment request signal REQ1 has not been received. In step S8, the discrete cosine transform coefficient is transferred to the inverse discrete cosine transform circuit 15 without modification. The execution then returns to step S1, where the next discrete cosine transform coefficient is processed.

Figure 17 shows a practical example of the circuit configuration of the fourth embodiment of the parity inverter 28, in which the parity inversion is performed to increase the magnitude of the discrete cosine transform coefficient whose parity is inverted, that is to say to make the discrete cosine transform coefficient whose parity is to be reversed more different from zero.

The parity inverter depicted in Figure 17 is similar to the parity inverter 28 depicted in Figure 11.

Elements of the circuit illustrated in Figure 17 that correspond to those of the circuit depicted in Figure 11 are indicated by the same reference numerals, and will not be described again in this case. The parity inverter depicted in FIG. 17 differs from the parity inverter depicted in FIG. 11 in that it includes the magnitude increase circuit 90 instead of the least significant bit inverter 63.

The magnitude increase circuit 90 determines the polarity of each discrete cosine transform coefficient received from the first memory 26 or the second memory 27 via the RDATA data path. When the polarity of the discrete cosine transform coefficient is positive, the magnitude-increasing circuit 90 adds one unit to that coefficient, while when the polarity is zero or negative, it subtracts one unit from the discrete cosine transform coefficient. The parity inverter circuit depicted in Fig. 17 makes the parity of the sum of the discrete cosine transform coefficients in the block odd by selecting the

ES 2 389 797 T3 coefficient whose parity is to be inverted of the magnitude-increasing circuit 90, and substituting the discrete cosine transform coefficient whose parity is to be inverted by the magnitude-increasing discrete cosine transform coefficient.

The magnitude increase circuit 90 comprises the polarity determination circuit 91, which directly controls the fifth AND gate 94 and the sixth AND gate 95 through the inverting gate 97. The magnitude increase circuit 90 also includes the adder 92 of a unit and the subtractor or subtractor 93 of a unit that add or subtract, respectively, one unit of each discrete cosine transform coefficient. Either the output of one-unit adder 92 or the output of one-unit subtractor 93 is selected by the fifth AND gate 94 or the sixth AND gate 95 in response to the output of the polarity determination circuit 91. The outputs of AND gates 94 and 95 are applied as inputs to OR gate 96, which transfers the selected magnitude-augmented discrete cosine transform coefficient to fourth AND gate 65. When it is necessary to invert the parity of the sum of the block's discrete cosine transform coefficients, the fourth AND gate selects the magnitude-increased and inverted-parity output of the magnitude-increase circuit 90 to apply to the discrete cosine transform circuit 15 inverse instead of the discrete cosine transform coefficient whose parity can be reversed.

The polarity determination circuit 91 judges the polarity of each discrete cosine transform coefficient in the block of coefficients received via the RDATA data path, and sets the state of its output to 1 or 0, depending on whether the polarity of the discrete cosine transform coefficient is positive or negative. When the polarity determination circuit 91 judges that the polarity of the discrete cosine transform coefficient is positive, the output of that circuit opens the fifth AND gate 94 and closes the sixth AND gate 95. This arrangement transfers the output of adder 92 from a unit, that is, the discrete cosine transform coefficient to which a unit has been added, to the fourth AND gate 65 through the fifth AND gate 94 and the OR gate 96.

On the other hand, when the polarity determination circuit 91 judges that the polarity of the discrete cosine transform coefficient is negative or null, the output of the polarity determination circuit 91 closes the fifth AND gate 94 and opens the sixth AND gate 95 . This logical arrangement transfers the output of one unit subtractor 93, that is, the discrete cosine transform coefficient from which one unit has been subtracted, to the fourth AND gate 65 through the sixth AND gate 95 and OR gate 96.

The fourth AND gate 65 transfers the inverted parity increased magnitude discrete cosine transform coefficient from the magnitude increase circuit 90 to the second AND gate 68 in response to the treatment request signal REQ1. When the address comparator 62 determines that the discrete cosine transform coefficient received through the RDATA data path is the discrete cosine transform coefficient whose parity can be reversed, the coefficient is transferred from the magnification circuit 90 to the inverse discrete cosine transform circuit 15 (FIG. 10A) as described above with reference to FIG. 11.

On the other hand, when the fourth embodiment of the parity inverter shown in Fig. 17 does not receive the treatment request signal REQ1, the discrete cosine transform coefficient whose parity can be inverted is transferred unchanged to the discrete cosine transform circuit 15 reverse.

When the parity of the sum of the discrete cosine transform coefficients is to be made odd, the fourth embodiment of the parity inverter 28 illustrated in FIG. 17 transfers to the inverse discrete cosine transform circuit 15 the discrete cosine transform coefficient whose parity has been inverted by adding one unit to said coefficient when its polarity is positive, and transfers to the inverse discrete cosine transform circuit 15 the discrete cosine transform coefficient whose parity has been inverted by subtracting one unit from said coefficient when its polarity is zero or negative. This treatment reverses the parity and increases the magnitude of the discrete cosine transform coefficient whose parity is reversed, and makes the parity of the sum of the discrete cosine transform coefficients odd.

The parity inverters 28 represented in Figures 11, 13, 15 and 17 and the operation described in accordance with the flow diagrams illustrated in Figures 9, 12, 14 and 16, can be modified to make the sum parity odd. of the discrete cosine transform coefficients by changing the parity of a discrete cosine transform coefficient different from the last non-zero coefficient read in the zigzag scan order. For example, in an 8 x 8 two-dimensional discrete cosine transform, the parity of one of the discrete cosine transform coefficients can be changed, either the one corresponding to the direct component, the discrete cosine transform coefficient of the component ( 7.7), that is, the one corresponding to the highest frequency component, the coefficient of the component (7.0) in the upper right corner, or the coefficient of the component (0.7) in the lower left corner. Since, in particular, the discrete cosine transform coefficient of the component (7,7), which is the highest frequency component, has a small influence on the image quality, this component is particularly suitable to be the which corresponds to the coefficient whose parity can be reversed.

ES 2 389 797 T3

In the parity inverters shown in Figures 11, 13, 15 and 17, alternative discrete cosine transform coefficients can be selected as the discrete cosine transform coefficient whose parity can be inverted, substituting the address EOB_adrs applied to address comparator 62 for the direction of the discrete cosine transform coefficient. Alternatively, if the parity of the discrete cosine transform coefficient of the highest frequency component is to be changed, the read counter 61 and address comparator 62 may be omitted, and the memory full signal FULL may be used to identify the coefficient. Discrete cosine transform of the highest frequency component as a coefficient whose parity can be changed.

In a further alternative version, the summation odd conversion circuits 14 shown in Figures 6, 8 and 10 may determine the sum of specific discrete cosine transform coefficients, for example the coefficients of the component (0,0) , the component (4,0), the component (0,4) and the component (4,4). The sum parity odd conversion circuit would then perform a parity invert operation to convert the sum of the specific discrete cosine transform coefficients to an odd number. Figure 18 shows a variant of the odd-sum conversion circuit 14 represented in Figure 8. In this variant, the sum of the specific discrete cosine transform coefficients is determined to determine whether parity inversion is necessary. The elements of the circuit shown in figure 18 that correspond to those of the circuit shown in figure 8 are indicated by the same reference figures, and will not be described again in this case.

In the circuit for converting the sum value to odd shown in FIG. 18, the selector 51 breaks the line between the inverse quantizer 13 and the accumulator 23A. Selector 51 also receives from counter 20 the count coeff_adrs value, which indicates the number of block discrete cosine transform coefficients that have been received from inverse quantizer 13.

In response to the computation coeff_adrs value received from counter 20, selector 51 determines whether or not each discrete cosine transform coefficient received from inverse quantizer 13 is one of the specific coefficients, and is therefore to be included in the determined sum by accumulator 23A. Thus, for example, selector 51 determines whether the computation coeff_adrs value is a value corresponding to the component (0,0), to the component (4,0), to the component (0,4) or to the component (4.4). When selector 51 determines that the discrete cosine transform coefficient is one of the specific coefficients, it transfers said coefficient to accumulator 23A. Accordingly, the summation value odd conversion circuit depicted in Fig. 18 determines the sum of specific discrete cosine transform coefficients in the block and, if the sum's parity is even, changes the parity of at least one of the discrete cosine transform coefficients to make the odd sum. The sum odd conversion circuit depicted in FIG. 18 then transfers the set parity discrete cosine transform coefficient block to inverse discrete cosine transform circuit 15.

The circuit depicted in FIG. 18 can be modified in a manner similar to that illustrated in FIG. 10A to enable the circuit to determine the exclusive logical sum of the least significant bits of the specific discrete cosine transform coefficients. The circuit of FIG. 18 is modified by substituting adder 23 for the least significant bit detector 29 and for the exclusive OR gate 30 shown in FIG. 10A.

Turning now to FIG. 6, the discrete cosine transform coefficients in the coefficient block are transferred from summation odd-value conversion circuit 14 to inverse discrete cosine transform circuit 15, described above. The sum of the discrete cosine transform coefficients generated by the odd-value conversion circuit of the sum is an odd number. If the sum of the discrete cosine transform coefficients provided by the inverse quantizer was an even number, the odd sum conversion circuit 14 changed the parity of at least one of the discrete cosine transform coefficients to make the sum of the discrete cosine transform coefficients transferred to the inverse discrete cosine transform circuit 15. The inverse discrete cosine transform circuit 15 applies inverse discrete cosine transform treatment to the discrete cosine transform coefficients of the block to obtain the recovered difference block S4. The recovered difference block is transferred to adder 16.

The adder 16 performs a pixel by pixel addition between the recovered difference block S4 and the adaptation block S2 received from the second picture memory group 4. The resulting reconstructed image block S5 is provided to the second image memory group 4, where it constitutes a block of the reconstructed image stored in one of the image memories specified by the memory controller 3.

Variable-length encoder 17 applies variable-length encoding, such as Huffman encoding, etc., to each block SC of quantized transform coefficients from difference block encoder 9, along with its motion vector MV ("motion vector ”), The motion compensation signal MM, quantization table data, and so on. The variable-length encoder 17 also assembles the encoded data

ES 2 389 797 T3 with variable length with the start codes and header information of the respective layers of the MPEG standard to form the compressed motion picture signal.

The matrix lines / macroblock counter 5 counts the block matrix line initiation signals SS and the macroblock initiation signals BS generated by the memory controller 3 in synchronism with the beginning of each block matrix line and each macroblock of the blocks. images read from the first group 2 of image memories for treatment. When its count value reaches a predetermined value, the matrix line / macroblock counter 5 generates the start signal S0, which is applied to the variable length encoder 17.

In response to the start signal S0, the variable-length encoder 17 transfers the compressed motion picture signal to the output buffer 19, where it is temporarily stored. Next, the compressed motion picture signal is read from the output buffer 19 as a bit string with a predetermined bit rate. The bit stream of the compressed motion picture signal is transferred to a complementary expander via a transmission path, or the bit stream of the compressed motion picture signal is recorded on a suitable recording medium, such as like an optical disc.

The recording medium is a recording medium on which the compressed motion picture signal obtained from the motion picture signal is recorded by predictive coding and discrete cosine transform processing. Each block of each reconstructed image used as a reference image in predictive coding is reconstructed by inversely quantizing a block of the quantized discrete cosine transform coefficients included in the compressed moving image signal, converting the sum of the coefficients to an odd value. Discrete cosine transform of the resulting block of coefficients, and subjecting to inverse orthogonal transformation the block of discrete cosine transform coefficients with the modified sum.

A transmission apparatus in accordance with the invention may include a compressor in accordance with the invention, as described above.

It may be thought that it would be better to perform the odd conversion operation of the sum value in the difference block encoder 9 of the compressor. The sum value odd conversion operation would make the sum of the discrete cosine transform coefficients in each block of quantized coefficients included in the compressed motion picture signal an odd number. It might be thought that processing the motion picture signal compressed in this way would make the odd conversion of the sum of the discrete cosine transform coefficients in the expander unnecessary. However, with such an arrangement, after the discrete cosine transform coefficients have been quantized in the compressor and inversely quantized in the expander, the sum of the discrete cosine transform coefficients that is input to the Inverse discrete cosine in the expander may no longer be an odd number. Therefore, the sum odd conversion operation must be performed before the inverse discrete cosine transform processing in the expander to ensure that a mismatch error does not occur.

A compressed motion image signal expander to which this invention is applied, as defined in the appended claims, will now be described with reference to Fig. 19. In Figure 19, the compressed motion picture signal is received as a string of bits via a transmission line from the compressor, or by reproducing the compressed motion picture signal from a suitable recording medium, such as an optic disc. The bit string is transferred to input buffer 31, where it is temporarily stored, and from which it is read, image by image, in the variable-length reverse encoder 32. The variable-length reverse encoder 32 extracts the header information of respective layers of the MPEG encoding from the compressed motion picture signal, and extracts the picture decoding control PH information from said header information, which it transfers to the controller 33 from memory.

Variable length reverse encoder 32 applies variable length reverse encoding to variable length encoded discrete cosine transform coefficient blocks to provide quantized coefficient blocks, including the current block Cb of quantized discrete cosine transform coefficients. The current block Cb of quantized discrete cosine transform coefficients is supplied to the difference block decoder 34. Difference block decoder 34 decodes block Cb of quantized discrete cosine transform coefficients to provide restored difference block BS, and supplies this last block to adder 39.

The variable-length inverse encoder 32 extracts the motion vector MV and the motion compensation mode signal MM for the quantized discrete cosine transform coefficient block Cb from the compressed motion picture signal, and transfers this information to the compensator. 37 movement. The motion compensator 37 causes an adaptation block to be read from the image memory group 38 for

ES 2 389 797 T3 the restored difference block BS.

The image memory block includes several image memories, each of which stores an already reconstructed image. The adaptation block BS is a block of the reconstructed image stored in one of the image memories in a direction specified by the motion vector MV. The image memory of the image memory group 38 that stores the reconstructed image from which the adaptation block is read, is specified by the memory controller 33.

As mentioned above, an image can be encoded by prediction from a previous reconstructed image, by prediction from a next reconstructed image, and by prediction from a block obtained by performing a pixel-by-pixel linear operation. over the reconstructed image, and from a next reconstructed image. Finally, an image can be encoded without using any prediction techniques. In this case, the adaptation block provided by the picture memory group 38 is a null block, ie a block in which all the pixel values ​​are set to zero. The motion compensated matching blocks provided by the image memory group 38 are adaptively modified, and the optimal combination is selected for each block. This process is done using a block that has a block size of 16 x 16 pixel.

Each adaptation block provided by the picture memory group 38 is transferred to adder 39. Adder 39 performs a pixel-by-pixel addition between the restored difference block BS received from the difference block decoder 34 and the block adaptation provided by image memory group 38. The result of this sum is a reconstructed image block, which is stored in one of the image memories of the image memory group 38 specified by the memory controller 33. The reconstructed image blocks generated by the adder 39 are stored one by one in the selected image memory by overwriting on the reconstructed image previously stored in the image memory, to form a new reconstructed image.

The reconstructed images stored in the image memory group 38 are read in a sequence controlled by an output image indication signal generated by the memory controller 33. The read images are transferred, as a reproduced motion picture signal, to a suitable image display device, for example a video monitor. The display device displays a moving image in response to the reproduced moving image signal.

The difference block decoder 34 will now be described with reference to FIG. 19. Difference block decoder 34 comprises inverse quantizer 40, odd-sum conversion circuit 35, and inverse discrete cosine transform circuit 36. The inverse quantizer 40 uses a quantization table to inverse quantize the block Cb of quantized discrete cosine transform coefficients received from the variable-length inverse encoder 32. The odd-sum conversion circuit 35 receives the resulting block of discrete cosine transform coefficients from the inverse quantizer 40, and prevents mismatch errors in the inverse discrete cosine transform processing performed by the inverse quantizer circuit 36. inverse discrete cosine transform. The inverse discrete cosine transform circuit 36 ​​applies inverse discrete cosine transform treatment to the block of discrete cosine transform coefficients with the modified sum generated by the sum conversion circuit 35 to an odd value.

Figure 20 shows an example of the construction of the inverse quantizer 40. The main components of the inverse quantizer 40 are the coverage / level decoder 41, the address counter 47, the address converter 48, the first block memory 42, the second block memory 43, and inverse quantization circuit 46.

The coverage / level decoder 41 receives block Cb of quantized discrete cosine transform coefficients from the variable-length inverse encoder 32. The coverage / level decoder 41 decodes the coverage / level coding that was applied to the quantized discrete cosine transform coefficients in the variable length encoder of the compressor. The resulting block of quantized discrete cosine transform coefficients is transferred to first block memory 42 or second block memory 43 in zigzag scan order. The first block memory 42 and the second block memory 43 each store a block of quantized discrete cosine transform coefficients.

The address counter 47 and the address converter 48 generate, respectively, write addresses and read addresses for the first block memory 42 and the second block memory 43. Quantized discrete cosine transform coefficient blocks are written and read alternately from the first block memory 42 and the second block memory 43. Each block of quantized discrete cosine transform coefficients is written to one of the block memories in zigzag scan order in response to the address provided by address counter 47, and read from block memory in scan order in response to the addresses provided by the frame converter 48.

ES 2 389 797 T3 addresses. The different order of directions between writing and reading converts the order of the quantized discrete cosine transform coefficients of the block from a zigzag scan order to a raster scan order.

The address counter 47 generates the enrollment addresses in zigzag scan order. Address converter 48 receives addresses in zigzag scan order from address counter 47 and uses an address translation table to convert addresses to addresses in frame scan order. The addresses generated by address counter 47 and address converter 48 are selected by selector 49 for application to first block memory 42 and second block memory 43 as addresses adrs1 and adrs2. When a block of quantized discrete cosine transform coefficients from the coverage / level decoder 41 is written to the first block memory 42 or the second block memory 43, the respective addresses adrs1 and adrs2 are provided by the counter 47 of directions through selector 49 in zigzag scan order. When the block of quantized discrete cosine transform coefficients is read from the first block memory 42 or from the second block memory 43 for the inverse quantization circuit 46, the respective addresses adrs1 and adrs2 are provided by the address converter 48 through selector 49 in frame scan order.

When all quantized discrete cosine transform coefficients have been stored in first block memory 42 or second block memory 43, the block of discrete cosine transform coefficients is read in frame scan order for circuit 46 inverse quantization. The inverse quantization circuit 46 inverse quantizes the quantized discrete cosine transform coefficients of the block, and transfers the resulting block of discrete cosine transform coefficients to the sum conversion circuit 35 to an odd value. The inverse quantization performed by the inverse quantization circuit 46 is identical to the inverse quantization performed by the inverse quantizer 13 in the local decoder of the motion picture signal compressor shown in FIG. 6.

When the odd-sum conversion circuit 35 determines that the parity of the sum of the discrete cosine transform coefficients in the block of discrete cosine transform coefficients from the inverse quantizer 40 is even, it operates on at least one of the block's discrete cosine transform coefficients to convert the sum of the block's discrete cosine transform coefficients to an odd number. The odd sum conversion circuit 35 supplies the discrete cosine transform coefficient block with the modified sum to the inverse discrete cosine transform circuit 36. The operation of converting the sum value to odd performed by the sum conversion circuit 35 to an odd value is identical to the operation of converting the sum value to odd performed by the summation odd-value conversion circuit 14. in the local decoder of the moving image signal compressor shown in FIG. 6.

The inverse discrete cosine transform circuit 36 ​​performs inverse discrete cosine transform processing on the discrete cosine transform coefficient block with the sum converted to an odd value, to provide the restored difference block BS, which is supplied to the adder 39.

The practical operation of the inverse quantizer 40 shown in FIG. 20 is illustrated by the timing diagram shown in FIGS. 21A through 21I. Variable-length inverse encoder 32 extracts block Cb of quantized discrete cosine transform coefficients from the compressed motion picture signal. The variable length reverse encoder 32 generates an event enable signal EV_EN, illustrated in FIG. 21A, which instructs the coverage / level decoder 41 to read the block of discrete cosine transform coefficients. The quantized discrete cosine transform coefficients contained in block Cb of quantized discrete cosine transform coefficients are coverage / level encoded.

The variable length reverse encoder 32 also provides the event number signal EVENT_NO to the coverage / level decoder 41, as shown in FIG. 21B. The event number signal EVENT_NO indicates the number of coverage / level pairs in block Cb of quantized discrete cosine transform coefficients, that is, the number of data pairs indicating coverage and level.

When the coverage / level decoder 41 receives the event number signal EVENT_NO, it applies a read request signal RE_REQ for each coverage / level data pair to the variable-length reverse encoder 32, as shown in FIG. 21C. Each time it receives the read request signal RE_REQ, the variable-length reverse encoder 32 transfers a coverage / level data pair to the coverage / level decoder 41, as shown in Figures 21D and 21E. Thus, the variable-length reverse encoder 32 applies to the coverage / level decoder 41 the number of coverage / level data pairs corresponding to the number of read request signals it receives.

The coverage / level decoder 41 decodes the coverage / level encoding of the quantized and coverage / level-encoded discrete cosine transform coefficients, to supply a block of coeffi29.

ES 2 389 797 T3 discrete cosine transform clients quantized in zigzag scan order as WDATA to first block memory 42, as shown in FIG. 21G. At the same time, as shown in Fig. 21F, the address counter 47 counts the quantized discrete cosine transform coefficients from the coverage / level decoder 41 and transfers the address signal adrs1 in zigzag scan order, indicating the writing address of each quantized discrete cosine transform coefficient, to the first block memory 42 through selector 49.

When the coverage / level decoder 41 receives the EOB code from the variable-length inverse encoder 32, indicating that it has received the last non-zero discrete cosine transform coefficient, the coverage / level decoder 41 adjusts the discrete cosine transform coefficient quantized to the EOB code, and all of the following discrete cosine transform coefficients quantized to zero, and transfers these zeroed coefficients to the first block memory 42.

Also, when receiving the EOB code, the coverage / level decoder 41 transfers the EOB_EN signal to the position registers 44 and 45, as shown in FIG. 21H. The EOB_EN signal indicates to the position registers that the EOB code has been received. The position registers also receive, from the address counter 47 through the address converter 48, the address of each quantized discrete cosine transform coefficient input into the first and second block memories 42 and 43. When the coverage / level decoder 41 receives the EOB code, the address generated by the address counter 47 is the address of the last non-zero coefficient. The EOB_EN signal causes the EOB_POS address of the last non-zero coefficient, converted to a scan address per frame by the address converter 48, to be written to the position register of the block memory in which the memory block is being written. quantized discrete cosine transform coefficients. One of the position registers 44 and 45 thus stores the address of the last non-zero coefficient of the block of quantized discrete cosine transform coefficients.

When the coverage / level decoder 41 has transferred the entire block of quantized discrete cosine transform coefficients to the first block memory 42 or the second block memory 43, the address counter 47 applies the bank switching signal BANK. memory to the first block memory 42 and to the second block memory 43. The memory bank switching signal BANK switches the mode of the block memories, so that the first block memory 42, which was initially in the write mode, is switched to the read mode, and the second memory 43 of blocks is switched to enrollment mode. Thus, when the coverage / level decoder 41 decodes the next block of quantized discrete cosine transform coefficients, the resulting coefficients will be written to the second block memory 43. The BANK signal also toggles selector 49, so that the addresses applied to the block memory in enroll mode are the addresses in zigzag scan order generated by the address counter 47, and the addresses applied to the block memory. blocks in the read mode are the addresses corresponding to the frame scan order generated by the address converter 48.

Also, when the coverage / level decoder 41 has transferred the entire block of quantized discrete cosine transform coefficients to the first block memory 42, the first block memory 42 applies the memory full signal FULL1 to the inverse quantization circuit 46. . The memory full signal FULL1 indicates that all quantized discrete cosine transform coefficients in the block have been stored. When the inverse quantization circuit 46 receives the memory full signal FULL1, it sends the read request signal RD_EN to the first block memory 42. The read request signal causes the first block memory to read the quantized discrete cosine transform coefficients stored therein in response to addresses adrs1 provided in frame scan order by address converter 48 through selector 49. Consequently, the quantized discrete cosine transform coefficients of the block are read from the first block memory 42. The discrete cosine transform coefficients read in response to each direction are transferred to the inverse quantization circuit 46.

At the same time that the quantized discrete cosine transform coefficients of the block are read from the first block memory 42, the quantized discrete cosine transform coefficients of the next block are written in zigzag scan order to the second block memory 43. in response to addresses from address counter 47.

The inverse quantization circuit 46 inverse quantizes the quantized discrete cosine transform coefficients of the block of coefficients, in a manner similar to the inverse quantizer 13 included in the motion picture signal compressor described above with reference to FIG. 6. The block resulting from discrete cosine transform coefficients is transferred to the sum conversion circuit 35 to an odd value.

When the parity of the sum of the block's discrete cosine transform coefficients corresponds to an even number, the odd-sum conversion circuit 35 operates on at least one of the block's discrete cosine transform coefficients to make odd the sum of the discrete cosine transform coefficients of the block, similarly to summation odd conversion circuit 14 included in the motion picture signal compressor described above. The resulting block of coefficients of

ES 2 389 797 T3 discrete cosine transform whose sum has been converted to an odd number is transferred to inverse discrete cosine transform circuit 36.

For example, odd-sum conversion circuit 35 may reference position registers 44 and 45 to determine whether or not the current discrete cosine transform coefficient is the last non-zero coefficient in scan order in zigzag, so that the odd sum conversion circuit 35 can change the parity of the last non-zero coefficient to make the sum of the block's discrete cosine transform coefficients odd. Alternatively, the odd sum conversion circuits 35 may operate on the discrete cosine transform coefficient of the highest frequency component to make the sum of the discrete cosine transform coefficients odd. It may be preferable to invert the parity of the discrete cosine transform coefficient of the higher frequency component, because the higher frequency component has little influence on the image quality and it is not necessary to determine which of the transform coefficients of Discrete cosine is the last nonzero coefficient. This is true also in the case where the scan order is different from the zigzag scan order.

It should be emphasized that, to avoid mismatch errors, the odd-sum conversion operations performed in the motion picture signal compressor and the compressed motion picture signal expander must be identical to each other. .

2. Second embodiment

Figure 22 shows the configuration of a second embodiment of a moving image signal compressor. The second embodiment is the preferred embodiment of the invention. Figure 23 shows the configuration of the odd-number sum converter circuit 50 of the motion picture signal compressor shown in Figure 22. The elements of the second embodiment of the moving image signal compressor corresponding to those of the first embodiment of the moving image signal compressor illustrated in Figure 6 are indicated by the same reference numerals, and will not be described again here. case. The second embodiment differs from the first embodiment in the configuration of the odd-sum converter circuit 50.

In the odd-sum conversion circuit 50 shown in detail in FIG. 23, the counter 20 counts the number of discrete cosine transform coefficients received from the inverse quantizer 13, and transfers the resulting computation coeff_adrs value to circuit 21 of parity determination.

Accumulator 23A comprises adder 23 and register 24. Adder 23 sums each discrete cosine transform coefficient in a block of coefficients received from inverse quantizer 13, with the sum of the discrete cosine transform coefficients already received in the block. stored in register 24. Register 24 is reset after the sum for each block of discrete cosine transform coefficients has been determined. The resulting sum of the transform coefficients is transferred from adder 23 to register 24 and to parity determination circuit 21. The accumulator 23A only needs to add the least significant bits of the block's discrete cosine transform coefficients to provide a suitable result for the parity determination circuit 21 to judge whether the parity of the sum of the discrete cosine transform coefficients is odd or even.

The parity determining circuit 21 operates in response to the count coeff_adrs value received from the counter 20, as follows. When the count value indicates that all the discrete cosine transform coefficients of the block have been added by the accumulator 23A, the parity determination circuit 21 determines whether the parity of the sum of the cosine transform coefficients is odd or even. discrete received from accumulator 23A. For example, in the case of an 8 x 8 two-dimensional discrete cosine transform, when the count value indicates that the sum of the 64 discrete cosine transform coefficients has been determined, the parity determination circuit 21 determines whether it is odd or even the parity of the sum of the discrete cosine transform coefficients received from accumulator 23A.

In practice, when the discrete cosine transform coefficients are represented by binary numbers, the parity determination circuit 21 examines the least significant bit of the sum of the discrete cosine transform coefficients received from accumulator 23A. A least significant bit equal to zero indicates that the sum's parity is even. In this case, the parity determining circuit 21 applies the treatment request signal REQ1 to the parity inverter 53 to cause said inverter to perform a parity invert operation. In response to the treatment request signal REQ1, the parity inverter 53 changes the polarity of at least one (ie, an odd number) of the block's discrete cosine transform coefficients to make the sum of those coefficients odd. On the other hand, a least significant bit equal to 1 indicates that the parity of the sum is odd. In this case, the parity inverter 53 does not generate the treatment request signal REQ1, and the parity inverter 53 does not modify the parity of all the discrete cosine transform coefficients of the block, because the parity of the sum of the coefficients Discrete cosine transform is already odd.

ES 2 389 797 T3

The block of discrete cosine transform coefficients is transferred from inverse quantizer 13 not only to accumulator 23A, but also to parity inverter 53 through delay circuit 52. The delay circuit 52 delays the discrete cosine transform coefficients of the block by a time corresponding to the processing times of the accumulator 23A and the parity determination circuit 21, such that the last discrete cosine transform coefficient, i.e. the coefficient of the highest frequency component (for example, the discrete cosine transform coefficient of the component (7,7) into an 8 x 8 discrete cosine transform), arrives at the parity inverter 53 at the same time as the treatment request signal REQ1.

Thus, the parity inverter 53 transfers to the inverse discrete cosine transform circuit 15 without modifying all the discrete cosine transform coefficients except the coefficient corresponding to the highest frequency component. When the parity determining circuit 21 has not generated the treatment request signal REQ1, the parity inverter 53 also transfers the discrete cosine transform coefficient of the highest frequency component to the inverse discrete cosine transform circuit without modification. . Only when the parity determining circuit 21 has generated the treatment request signal REQ1, the parity inverter 53 inverts the least significant bit of the transform coefficient of the highest frequency component, and transfers to the cosine transform circuit 15 Inverse discrete the inverted parity coefficient of the highest frequency component.

Thus, when the parity determining circuit 21 indicates that the parity of the sum of the discrete cosine transform coefficients of the block is even, the parity inverter 53 operates on the highest frequency coefficient (for example, the Discrete cosine transform coefficient of component (7,7) into a discrete 8 x 8 cosine transform) in the block. The parity inverter reverses the parity of the highest frequency discrete cosine transform component, and thus renders the sum of the discrete cosine transform coefficients of the block of coefficients transferred to the inverse discrete cosine transform circuit odd. Thus, the parity of the sum of the discrete cosine transform coefficients of the block of coefficients is always odd. The discrete cosine transform coefficient of component (7,7) is the coefficient that has the least influence on the output values ​​of the inverse discrete cosine transform.

Additional practical examples of the odd-sum conversion circuit 50 of the preferred embodiment of the invention will now be described.

Figure 24 illustrates an example in which the adder 23 of Figure 23 has been replaced by the least significant bit detector 29 and exclusive-OR gate 30. The elements of the circuit shown in figure 24 corresponding to those of the circuit illustrated in figure 23 are indicated by the same reference figures, and will not be described again in this case. The least significant bit detector 29 detects the least significant bit of each discrete cosine transform coefficient in the block, and the exclusive-OR gate 30 and register 24 together determine the exclusive logical sum of the least significant bits of the transform coefficients of the block. discrete cosine of the block. The parity of the exclusive logical sum is determined by the parity determining circuit 21, as described above with reference to Figures 10A and 23.

Alternatively, AND gate 88 and counter 89 of FIG. 10B may be used to replace exclusive OR gate 30 and register 24 depicted in FIG. 24.

Another example is shown in Figure 25. In this case, the selector 51 between the inverse quantizer 13 and the accumulator 23A is inserted in the circuit 50 for converting sum to an odd value illustrated in FIG. 23. The elements of the circuit represented in FIG. 25 corresponding to those of the circuit illustrated in Fig. 23 are indicated by the same reference figures, and will not be described again in this case. The circuit represented in figure 25 determines only the sum of specific coefficients, for example those corresponding to the component (0,0), the component (4,0), the component (0,4) and the component (4,4 ), to determine if conversion to odd of the sum value is required. Selector 51 receives the computation coeff_adrs value from counter 20 to determine whether or not each discrete cosine transform coefficient received from inverse quantizer 13 is one of the specific coefficients, and is to be summed accordingly. When selector 51 determines that the discrete cosine transform coefficient is one of the specific coefficients and has to be added, that is, the computation coeff_adrs value has a value corresponding, for example, to the component (0,0), the component (4.0), component (0.4) or component (4.4), selector 51 supplies the discrete cosine transform coefficient to accumulator 23A. Selector 51 causes the summation odd conversion circuit shown in FIG. 25 to determine the sum of specific coefficients. The parity inverter 53 then operates on at least one of the specific discrete cosine transform coefficients to convert the sum of the specific coefficients to an odd number. The summation odd parity discrete cosine transform coefficient block is then transferred to the inverse discrete cosine transform circuit 15.

In another alternative solution, the selector 51 shown in Figure 25 may be inserted in the connection line between the inverse quantizer 13 and the least significant bit detector 29 in the circuit illustrated in Figure 24. The

ES 2 389 797 T3 circuit depicted in Figure 24, modified in this way, would determine the exclusive logical sum of the least significant bits of the specific discrete cosine transform coefficients selected by selector 51.

In a further alternative embodiment of the odd-sum conversion circuit 50, when the last discrete cosine transform coefficient received from the inverse quantizer 13 is the coefficient of the continuous component, that is when the order of the frame scan is opposite to that of the embodiments described above, the discrete cosine transform coefficient to which the parity inversion operation was applied is not the one corresponding to the highest frequency component, but the coefficient of the continuous component.

An example of the practical circuit configuration of the parity inverter 53 will now be described with reference to FIG. 26. The parity inverter 53 is a simplified version of the parity inverter 28 described above and illustrated in Figure 11. The parity inverter 53 includes the least significant bit inverter 63, the third and fourth AND gates 64 and 65, the OR gate 66 and reversing gate 71.

In the parity inverter 53, the least significant bit inverter 63 inverts the least significant bit of each discrete cosine transform coefficient in the block of coefficients received from the inverse quantizer 13. This parity inverter inverts the parity of each transform coefficient discrete cosine. Normally, the treatment request signal REQ1 is absent, so the parity inverter transfers each received discrete cosine transform coefficient to the inverse discrete cosine transform circuit 15 (Fig. 23) through the third AND gate 64 and the OR gate 69.

When the discrete cosine transform coefficient of the highest frequency component is received by the sum conversion circuit 50 to an odd value (FIG. 23), the computation coeff_adrs value generated by the counter 20 indicates to the determination circuit 21 of parity that the value received by the parity determining circuit 21 is the sum of all the discrete cosine transform coefficients included in the block. In response, the parity determining circuit 21 determines whether the parity of the sum of the discrete cosine transform coefficients is odd or even.

When the parity determining circuit 21 determines that the parity of the sum of the discrete cosine transform coefficients of the block is even, it transfers the treatment request signal REQ1 to the parity inverter 53. The treatment request signal REQ1 arrives at the parity inverter 53 through the delay circuit 52 at the same time as the discrete cosine transform coefficient of the highest frequency component. The treatment request signal REQ1 changes the states of the third and fourth AND gates 64 and 65. This causes the highest frequency discrete cosine transform coefficient with the least significant bit inverted from the minus bit inverter 63 to be transferred. significant to the inverse discrete cosine transform circuit 15, through the fourth AND gate 65 and the OR gate 69. The discrete cosine transform coefficient of the highest frequency with the least significant bit inverted is transferred to the inverse discrete cosine transform circuit, instead of the normal coefficient of the highest frequency component, to make the parity odd.

On the other hand, when the parity determining circuit 21 determines that the parity of the sum of the discrete cosine transform coefficients of the block is odd, it does not generate the treatment request signal REQ1. The parity inverter 53 transfers the normal discrete cosine transform coefficient of the highest frequency to the inverse discrete cosine transform circuit 15 through the third AND gate 64 and OR gate 69, since it is not required to make odd the parity of the sum of the block of discrete cosine transform coefficients.

Figures 27 to 29 show modifications to the practical example of the parity inverter 53 represented in figure 26.

Figure 27 shows the one-unit adder 73, similar to the one-unit adder shown in Figure 13, arranged to replace the least significant bit inverter 63 in the parity inverter illustrated in Figure 26. The circuit is otherwise identical. The modified parity inverter as shown in Figure 27 inverts the parity of each of the discrete cosine transform coefficients in the block by adding one unit to them. Thus, when the parity determining circuit 21 transfers the treatment request signal REQ1 to the parity inverter, the parity inverter transfers to the inverse discrete cosine transform circuit 15 the coefficient of the highest frequency component with a summed unit, rather than the normal discrete cosine transform coefficient of the highest frequency. This substitution makes the parity of the sum of the block's discrete cosine transform coefficients odd.

As shown in FIG. 28, the magnitude reduction circuit 80 shown in FIG. 15 may be used as a substitute for the least significant bit inverter 63 in the circuit shown in FIG. 26. The circuit shown in FIG. 26 remains for the most part. other unaltered. The parity inverter represented in the

ES 2 389 797 T3 Figure 26, modified as shown in Figure 28, makes the sum of the discrete cosine transform coefficients odd according to equation (15) described above. When the parity determining circuit 21 generates the treatment request signal REQ1, the parity of the sum of the discrete cosine transform coefficients of the block is made odd by transferring the coefficient of the highest frequency with its inverted parity to circuit 15 inverse discrete cosine transform. The parity of the discrete cosine transform coefficient of the highest frequency component is inverted in one of two ways: one unit is subtracted from said coefficient by the unit subtractor 82 when the discrete cosine transform coefficient of the highest frequency high is positive, or one unit is added to said coefficient by the one unit adder 83 when it is zero or negative.

As shown in FIG. 29, the magnitude increase circuit 90 shown in FIG. 17 may be used as a substitute for the least significant bit inverter 63 of the circuit shown in FIG. 26. The circuit shown in FIG. 26 remains otherwise. unaltered. The parity inverter shown in FIG. 26, modified as shown in FIG. 29, makes the parity of the sum of the discrete cosine transform coefficients odd according to equation (16) described above. When the parity determining circuit 21 generates the treatment request signal REQ1, the parity of the sum of the discrete cosine transform coefficients of the block is made odd by transferring the discrete cosine transform coefficient of the highest frequency component. , with its parity reversed, to the inverse discrete cosine transform circuit 15. The parity of the discrete cosine transform coefficient of the highest frequency component is inverted in one of two ways: a unit is subtracted from the highest frequency discrete cosine transform coefficient by the subtractor 93 from one unit when the highest frequency discrete cosine transform coefficient is zero or negative, or one unit is added to the coefficient of higher frequency discrete cosine transform by one unit adder 92 when the higher frequency discrete cosine transform coefficient is positive.

A second embodiment of the compressed motion picture signal decompressor will now be described.

In the second embodiment of the compressed motion picture signal decompressor, the odd-sum converter circuit 50 is used in replacement of the odd-sum converter circuit 35 of the first embodiment of the compressed motion picture signal decoder, illustrated and described above with reference to Figure 19. The circuit depicted in Figure 19 is otherwise used without modification. In the second embodiment of the compressed motion picture signal decompressor, the processing to convert the sum of the discrete cosine transform coefficients to an odd number is performed in a similar way to the processing performed by the odd-sum converter circuit. in the second embodiment of the moving image signal compressor, illustrated and described with reference to FIG. 22. Thus, in the second compressed motion picture signal decompressor, it is unnecessary to transfer the address EOB_adrs from the variable-length reverse encoder 32 to the odd-sum converter circuit 50.

The invention described above makes it possible to apply an inverse discrete cosine transform method and realize a discrete cosine transform apparatus, a moving image signal compressor, a compressed motion image signal expander, and a transmitting apparatus for a compressed motion picture signal in which the probability of a mismatch error occurring in the course of inverse discrete cosine transform processing is reduced to a point where errors do not occur in practice. of maladjustment. Additionally, the invention makes it possible to realize a recording medium in which no mismatch error occurs when a compressed motion picture signal is reproduced from the medium and expanded by a processing that includes an inverse orthogonal transformation.

When a discrete cosine transform is used in the compression of the moving picture signal and an inverse discrete cosine transform in the expansion of the compressed moving picture signal, the invention makes it possible to prevent mismatch errors from occurring in the motion picture signal. inverse discrete cosine transform. This prevents deterioration of image quality. Accordingly, in a moving image signal compressor and in a compressed moving image signal expander to which this invention is applied, there is no possibility that the images decoded locally in the compressor and the images reconstructed by the expander are Different from each other. Thus a high image quality can be provided.