Event qualified test architecture

[Name of invention]

Event-specific inspection methods and circuits

[Brief Description of Drawings]

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an integrated circuit implementing the IEEE 1149.1 boundary scanning architecture.

2 is a block diagram of the inspection architecture of the present invention;

3 is a block diagram of an event-limited cell;

4 is a block diagram of another embodiment of an event confinement cell;

5 is a block diagram of an event-limiting module;

6 is a block diagram of an event-limiting module controller;

Fig. 7 is a flowchart showing how the state machine of the event confinement module controller selects an inspection protocol;

8 to 17 are state diagrams of a test protocol.

18 is a block diagram of a circuit board including a plurality of sub-circuits having the test architecture of the present invention;

Fig. 19 is a block diagram of a digital signal monitor employing the present invention;

Fig. 20 is a block diagram of an analog signal monitor employing the present invention;

* Explanation of symbols for main parts of the drawing

12 : TAP 14 : TCR 1

16 : TCR 2 18 : Functional Logic Circuit

22 : EQM 24 : EQC

28 : TMEM 30 : XNOR gate

32, 36: scanning memory cell 33: multiplexer

34 : OR gate 38 : EQM controller

40 : Command register 42 : Loop counter

44 : event counter 46 : event count memory

[Detailed Description of the Invention]

This application is filed on June 30, 1989 in U.S. Patent Application No. 308,272, titled Digital Bus Monitor Integrated Circuits, filed on February 8, 1989, entitled Event QualICied Testing Architecture for Integrated Circuits, which is incorporated herein by reference. U.S. Patent Application No. 374,896, filed August 9, 1989, for System Scan Path Architecture, U.S. Patent Application No. 391,571, filed August 9, 1989, for System Scan Path Protocols U.S. Patent Application No. 391,801.

FIELD OF THE INVENTION The present invention relates generally to electronic circuits, and more particularly, to event qualICied test architectures.

As semiconductor technology continues to increase the speed at which ICs operate, at-speed functional testing at both the IC and circuit board level becomes more difficult. Typically, circuit boards are tested at normal speed using functional testing equipment.

The functional checker measures the response from the board's primary output by inputting a test pattern to the board's primary input. If the primary output does not match the expected response, the functional check fails. The purchase or design unit cost of a high-speed functional tester suitable for the level of board design technology is rising rapidly.

According to the recently published boundary scan standard of IEEE 1149.1, a boundary scan method is included as a method for improving board level inspection capability in more IC designs. The 1149.1 standard describes an inspection architecture that can be designed within an IC to facilitate inspection of interconnect wiring between ICs within a circuit.

The 1149.1 architecture includes a test access port (TAP) and a series of scannable boundary test cells with one cell per input and output signal. The input check cells are coupled to the input check cell register TCR1, and the output check cells are coupled to the output check cell register TCR2.

The 1149.1 standard provides an instruction called an external probe (Extent), which places the IC in an off-line nonfunctional test mode and causes the output pin of the IC to be controlled by TCR2, while the input pin is set to TCR1. make it observable through This command allows wiring interconnects as well as coupling logic between ICs in the board design to be easily checked by repeated scan access operations to TCR1 and TCR2.

The 1149.1 standard also provides a command called Sample that allows the IC boundary scan path to be accessed when the IC is in on-line functional mode. In response to the control input to the TAP, the sample command captures the data coming into and out of the IC in TCR1 and TCR2 and then shifts for inspection. This check does not affect the operation of the IC.

However, the sample instruction has several limitations. One problem lies in synchronizing the control inputs so that the data is sampled at the steady state rather than the transition state. Another problem with the sample instruction is to limit when the boundary data is sampled. In order to obtain meaningful data, the sample action must be bounded by the occurrence of expected events. However, simultaneous random sampling of data is limited in practical application in system testing.

Another problem with the sample command is that the same control signals are routed globally to each IC on the board design to shift data through all ICs during the scan operation. Since each IC receives the same control signals, the data sampling operation must be applied globally across all IC boundaries. Since not all ICs operate at the same system clock in a typical board design, it is impossible to obtain valid data from all IC boundaries with one sample operation.

Therefore, a need has arisen for a circuit design that allows board-level functional testing to be performed by a test logic circuit within the IC itself rather than by external test equipment. In addition, the test circuitry must sample data at steady state, respond to event constraints, and operate according to a separate system clock.

According to the present invention, an inspection method and apparatus are provided which substantially eliminate the problems associated with the conventional inspection method and apparatus.

In the present invention, occurrences of specific events are detected and counted. In response to a predetermined number of occurrences, a check is performed. The test can be repeated a predetermined number of times by counting the events and executing the test after receiving a predetermined number of event signals.

In one embodiment of the present invention, a second specific event may be detected and counted. In response to counting the predetermined number of the second specified event, the test may be stopped.

In another embodiment of the invention, occurrences of certain events are detected and counted. A check is executed during the occurrence of a specific, selected event.

The present invention provides several technical advantages over the prior art. SUMMARY OF THE INVENTION The present invention overcomes the problems described in the 1149.1 sample instruction and provides a method for performing inspection functions beyond simple sampling of data patterns. Tests can be started and stopped in response to selected event occurrences. The start or end of the test may be delayed from a predetermined occurrence by a predetermined number of clock cycles, and the test may be run for a predetermined number of cycles. When the present invention is capable of controlling the test operation, it operates independently from the circuit TAP, allowing different circuits to perform different test operations at different times.

Since the local inspection control circuit is used instead of the global inspection control method that is input to all circuits, the concentration of inspection at the circuit board level can be reduced.

Additionally, the present invention may enable boundary check logic circuitry during normal operation of the host circuitry, allowing for normal rate data transfer checks between circuits. The present invention provides the ability to check for problems with normal speed when physical probing of the board design is not possible or when probing affects the operation of the board.

In order to more fully understand the present invention and its advantages, the present invention will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the present invention can best be understood by reference to FIGS.

Figure 1 shows an integrated circuit (IC) implementing the IEEE 1149.1 boundary scan architecture. IC 10 includes a test access port (TAP) and a series of scannable boundary test cells, one cell per input and output signal. The input check cells are coupled into an input check cell register (TCR1) 14 and the output check cells into an output check cell register (TCR2) 16 . A functional logic circuit 18 of IC 10 is coupled between TCR1 and TCR2.

TAP 12 provides a serial interface to the test logic circuit of IC 10 .

TAP 12 receives two control inputs to regulate operation, a check clock (TCK) and a check mode select (TMS). The TAP 12 also has a test data input (TDI) and a test data output (TDO) to allow serial data to be input to and output from the test architecture. Inside the TAP 12 is a command register for loading test commands, which can be accessed serially through the TDI and TDO pins.

The Extest command places the IC 10 in an off-line, non-functional test mode so that the output pins of the IC are controlled by TCR2, the input pins being observable through TCR1 14. During this command, TAP 12 receives external control signals from TMS and TCK to control the input and output pins of IC 10 via TCR1 and TCR2. During an external test command, the output pins of the IC can cause the input pins to output test data when they receive test data. This command allows the functional logic circuit 18 as well as the wiring interconnections between the ICs on the board to be easily checked by repeated scan access operations to TCR1 (14) and TCR2 (16).

Also, when the IC 10 is in the on-line functional mode, the sample instruction causes the boundary scan path of the IC 10 to be accessed. In response to the control input to the TAP 12, the sample command captures data into and out of the IC at TCR1 14 and TCR2 16 and then shifts the captured data for inspection. The sample inspection does not affect the operation of the integrated circuit 10 .

However, in operation, the sample command has several problems that limit its use. One problem involves synchronizing the TCK and TMS control inputs to system data that traverses the boundary of the target IC so that the data is sampled when it is in a steady state rather than a transition state. Another problem with the sample instruction relates to limiting the time at which boundary data is sampled. In order to obtain meaningful data, the sample action must be bounded by the occurrence of expected events. However, simultaneous random sampling of data is limited in practical application in system testing.

Another problem with the sample command is that the TCK and TMS control signals are routed globally to each IC in the board design to shift data through all ICs during the scan operation. Since each IC receives the same control signals, the data sample operation must be applied globally across all IC boundaries. In a typical board design, since different system clocks are used for multiple ICs, it is impossible to obtain valid data from all IC boundaries with one sample operation. Therefore, in order to use a sample command, the command is repeated with different selected control signals. Therefore, one TCK and TMS pair can be selected to perform the sample operation of one IC in the circuit, and then another TCK and TMS pair can be selected to repeat the sample operation of another IC in the circuit.

The present invention implements a normal speed system check of a circuit comprising multiple ICs. Although the present invention has been described with respect to a plurality of ICs mounted on a board, the circuits include a plurality of sub-circuits in an IC design, a plurality of ICs (wafer density) mounted on a common substrate, or a plurality of circuits installed in one system. It can be used with the circuit board of

2 is a block diagram of the present invention. IC 20 embodying the present invention includes TAP 12, TCR1 14, TCR2 16 and functional logic circuit 18 as described with respect to FIG. The TAP 12 is connected to an Event Qualification Module (EQM) 22 . The EQM 22 receives an event defined input (EQI) signal and outputs an event defined output (EQO) signal. EQM 22 also outputs control signals to event defined cell 24 ab (generally indicated by reference numeral 24 ), TCR1 14 , TCR2 16 , and test memory (TMEM) 28 . EQM receives outputs from EQCs 24a-b. EQC 24a-b receives inputs from the input signal (also connected to TCR1) and from the output of TCR2 16, respectively. The output of TCR1 14 is connected to the input of TMEM 28 , and the output of TMEM 28 is connected to the input of TCR2 16 . TAP, TCR, EQM, and TMEM refer to U.S. Patent Application Serial No. 308,272, filed February 8, 1989, entitled Event Qualified Testing Architecture for Integrated Circuits by Whitsel, all of which are incorporated herein by reference; U.S. Patent Application No. 374,896, filed on June 30, 1989, entitled Digital Bus Monitor Integrated Circuits; U.S. Patent Application No. 391,571, filed on August 9, 1989, entitled System Scan Path Architecture; and System Scan Path It is described in connection with U.S. Patent Application No. 391,801, filed August 9, 1989, entitled Protocols.

When using boundary check logic to perform a normal speed function check, there is a need for a way to limit when control to enable the check logic occurs. The event confinement architecture of the present invention provides a method of eliminating the need for external test control by placing the confinement and control logic required to enable the test logic into the IC design itself. When constrained, the architecture controls the boundary (or other) test logic of the host IC to operate synchronously with the IC during test.

An event confinement cell (EQC) is coupled to each IC input and output signal, which on its own or in combination with other signals can act as a test limiter. In addition, a logic controller, referred to as an event qualification module (EQM) 22, is included within the IC 20 to provide local limiting and control over the test logic of the IC.

EQCs 24a-b and EQM 22 are both selectable by TAP 12 for serial access to the architecture. The architecture does not prohibit the IEEE 1149.1 check operation. The architecture provides a built-in function that allows TCR1 (14) and TCR2 (16) to be synchronously enabled with the IC's I/O data at a finite time to perform on-line testing at the boundaries of the ICs.

TCRs 14 and 16 may be configured to operate as observable or controllable logic circuits. When the TCRs are in observable mode, they are set to either take a snapshot sample of a single data pattern entering and exiting the IC 20, or multiple data patterns to be compressed into symbols using a symbol analysis technique. The data sample observation mode examines a single input and/or output data pattern, whereas the symbol analysis observation mode examines an exact sequence of multiple input and/or output data patterns. If the symbol matches the expected symbol, then the data pattern sequence is correct; if it does not, one or more data patterns in the sequence are in error.

When the TCRs 14 and 16 are in controllable mode, they can be set to insert a single check data pattern, or a pseudo-random counting pattern of a generated sequence, instead of the normal system data entering and leaving the IC. In certain inspection situations, one TCR may be configured to perform a control function and another TCR to perform an observation function.

In addition to the TCR1 (14) and TCR2 (16) check logic blocks, the IC 20 stores input data coming into the IC instead of the system data normally output from the IC and can be set to insert the stored test data. memory (TMEM) 28 . The advantage of memory over TCR is that it can store and/or output multiple test data patterns. Memory can be accessed serially through TAP 12, similar to TCRs 14 and 16, to load or unload test data.

During on-line system testing, TCRs 14 and 16 and TMEM 28 receive control signals from EQM 22 rather than TAP 12 to execute set observable and/or controllable test functions, respectively. . Using the TCRs 14 and 16 and the TMEM 28, it is possible to set up the inspection architecture to execute the predetermined inspections described above individually or in combination. A list of test operations and combinations thereof is shown in Table 1.

<tables id="1"><title>inspection action</title><img file="KR100217536B1_D0001.tif" /></tables>

<tables id="1a"><img file="KR100217536B1_D0002.tif" /></tables>

<tables id="1b"><img file="KR100217536B1_D0003.tif" /></tables>

[Event Qualified Cell (EQC)]

The basic task of the EQCs 24a-b is to compare the received signal with the memorized signal and output a signal indicating when the two signals match. EQCs 24a-b herein have been described for use at the input and output boundaries of IC designs, but it should be understood that they may be used at the boundary of any desired logic block having input and/or output stages for signal data.

3 is a block diagram of the EQC 24 . An I/O signal, such as the signal fed to EQC 24a by an input (INPUT) signal or the output of TCR2 16 fed to EQC 24b, is coupled to one input of an XNOR gate 30 . The other input of the XNOR gate 30 is received from the output of the scan memory cell 32 . The input of the scan memory cell 32 is coupled to a multiplexer 33 and control is input from the EQM 22 . The multiplexer 33 inputs the TDI signal and the output of the scan memory 32 . The output of XNOR gate 30 is connected to the input of OR gate 34 , and the other input to OR gate 34 is supplied by the output of second scan memory cell 36 . The input of the scan memory cell 36 is connected to a multiplexer 37 and control is inputted from the EQM 22 . The multiplexer 37 inputs the output of the scan memory 32 and the output of the scan memory 36 . The output of the scan memory cell 36 is coupled to the TDO output signal. The output of OR gate 34 contains the CMPOUT signal and is connected to EQM 22 .

EQC 24a of FIG. 3 includes comparison circuitry (XNOR gate) 30 and scannable memories 32 and 36 for storing a plurality of comparison data (CMPDAT) and comparison mask (CMPMSK) bits. EQC 24 has an input for receiving the boundary I/O signal to be compared and for receiving a control signal from EQM 22 . EQC 24 has a compare output CMPOUT for sending the result of the comparison operation to EQM 22 . When the I/O signal output from the memory 32 matches the CMPDAT bit, the CMPOUT output sends a match signal to the EQM 22 to indicate a match. EQC's comparison circuit is disabled by the CMPMSK bit output from memory 36 so that EQC can output a match signal on CMPOUT regardless of whether the I/O signal and the CMPDAT bit match. The memories simultaneously output the CMPDAT and CMPMSK bits to the comparison logic circuitry to perform three operations: comparing the I/O signal to a logic 1, comparing the I/O signal to a logic 0, or a mask Enables comparison operations and operations that force a true comparison output. Comparative masking specifies a don't care state for one or more I/O signals that are not required in the definition of a particular inspection operation.

Memories 32 and 36 are simple shift registers of generally equal length. When accessed by the TAP 12 (via EQM), the memories are linked together via the MUX 37 to shift data into and out of the memories via the TDI and TDO pins. During scan access, all EQCs in the IC are linked together to form one serial shift register. The EQC shift register is coupled to the TDI input and TDO output pins of the IC during a scan operation to input and output data to and from the EQC shift register. When the memories are not accessed by the TAP 12 for a shift operation, the memories will be controlled by the EQM 22 to output the CMPDAT and CMPMSK data bits to the comparison circuit during execution of one of the EQM's protocols. can

During operation, TAP 12 loads into memory the CMPDAT and CMPMSK data bits used in the EQM protocol. After the memories are loaded, the TAP 12 accesses the EQM 22 to load the protocol command and enables the EQM 22 to control the memories. The serial output of each memory 32 and 36 after the shift operation is the first CMPDAT and CMPMSK data bits used in the first compare operation of the EQM. After the first compare operation is complete, the EQM controls the memories 32 and 36 to shift out the second pair of CMPDAT and CMPMSK data bits used in the second compare operation. When the memories 32 and 36 output the next pair of CMPDAT and CMPMSK bits, the previous pair of bits is fed back to the respective memories through the MUXs 33 and 37 and stored in the memory. By cycling the bit pairs back through the memories, the comparison output sequence can be repeated indefinitely.

Although EQM 22 has a protocol that operates on storage of one CMPDAT and CMPMSK bit, other protocols may require storage of multiple CMPDAT and CMPMSK data bits. The CMPDAT and CMPMSK memories must be capable of storing at least two bits each to output two pairs of CMPDAT and CMPMSK data bits. The two pairs of CMPDAT and CMPMSK bits cause the EQM to initiate a test operation in response to the condition detected by the first pair and stop the test operation in response to the condition detected by the second pair. Certain test protocols implemented by EQM 22 may require storage of additional CMPDAT and CMPMSK data bits to enable multiple start/stop and/or other comparison operations necessary for testing.

For more efficient storage of CMPDAT and CMPMSK data, a single remote memory may be used instead of having local memories within each EQC. EQC in Figure 5 shows the design of a cell without local memory 32 and 36. The function of EQC 24 is the same, the only difference is that the CMPDAT and CMPMSK bit signals are stored in remote memory instead of in its own cell. will be.

[Event Limited Module (EQM)]

FIG. 5 shows a block diagram of an EQM having a finite state machine controller 38 and a scan path comprising a command register 40, a loop counter 42 and an event counter 44. The controller includes a CMPOUT signal from EQC 24 (CMPOUT 1-n), a system clock (SYSCLK), an external event-qualified input (EQI) signal, a command from the command register 40, and a loop count from the loop counter 42. It has an input for receiving a minimum (LPCMIN) signal and an event count minimum (EVCMIN) signal from an event counter 44 coupled to an event count memory 46 . The controller 39 has an output for controlling the check logic and EQCs and outputting an external event limited output (EQO) signal. Although not shown in Figure 1, the controller also receives the system clock from the functional logic circuit of the IC or from an external system clock input. The system clock driving the EQM's controller is synchronized with the I/O boundary data. By synchronizing the system clock and the controller as well as the test logic circuit, it can be controlled to operate synchronously with the system logic circuit to be tested. The scan path of the EQM receives the scan control path (TAP CONTROL) from the TAP to cause data to be shifted in and out of the scan path via TDI and TDO signals. The scan path's command register 40 contains a series of scan cells (flip-flops or latches) that can be loaded through a scan operation to output commands to the EQM controller 38 . The loop counter section includes a series of scan cells from which count values can be loaded through scan operations.

When data is not shifted through loop counter 42, loop counter 42 may receive control from controller 38 to act as a count down counter. The loop counter 42 outputs a loop count minimum signal LPCMIN to the controller to indicate when it counts down to the minimum count value.

The event counter 44 includes a series of scan cells that can be loaded through a scan operation with a count value. The count value loaded into the event counter 44 may be written to an event count memory 46 attached to the parallel output of the counter to cause multiple count values to be memorized. When data is not shifted through event counter 44, event counter 44 may receive control from controller 38 to act as a count down counter. The event counter 44 outputs an event counter minimum signal EVCMIN to the controller to indicate when to count down to the minimum count value. Because event counter 44 has memory for storing multiple count values, it can receive control from the controller to load a new count value when the current count reaches a minimum value.

The ability to load new count values from memory allows the EQM controller to execute sophisticated check protocols, as described below.

[EQM controller]

6 is a diagram showing a block diagram of the EQM controller 38. As shown in FIG. EQM controller 38 includes a finite state machine 48, an AND gate 40 used to combine the CMPOUT signals with a single item comparison signal CTERM, and a controller for selecting the EVENT signal input to state machine 48. a first multiplexer (MUX1) 52, and a second multiplexer (MUX2) 54 for selecting a signal output to the EQO output. State machine 48 includes the EVENT signal from MUX1 52, COMMAND input from command register 40, LPCMIN input from loop counter 42, EVCMIN input from event counter 44, and functional logic of the IC. Receive SYSCLK from circuit 18 or input pin. The state machine 48 outputs a control signal to the boundary check logic circuit and the EQCs 24a-b, and also outputs a check state that can be selectively output to the EQO output via the MUX2 54 .

The COMMAND input instructs state machine 48 to execute the selected test protocol and controls the select inputs of MUX1 52 and MUX2 54 . During execution of the protocol, state machine 48 monitors the EVENT output from MUX1 52 . When MUX1 52 is set to output CTERM as the EYENT signal, state machine 48 monitors the CTERM signal to determine when to issue control to initiate and stop test operations. The CTERM signal is selected by MUX1 52 when the definition of the check operation is only based on local boundary conditions occurring at the host IC (see Board Level Local Event Qualifications below).

Alternatively, when MUX1 52 is set to output an EQI input as an EVENT signal, state machine 48 monitors the EQI signal to determine when to generate control to initiate and stop test operations. The EQI signal is selected when the definition of the test operation is not based solely on the local boundary conditions of the host IC, but rather based on the range of IC boundary conditions and/or other external conditions generated or input during board design (board level global events described below). See the Qualifications section).

The command input also selects which of the CTERM signal, end of test (EOT) status signal from state machine 48, and EQO disable (EQODIS) signal is output to the EQO pin via MUX2 54 . The CTERM signal is selected and output to the EQO pin when the EQM is operating in global limited mode (see the following board level global event qualification section). The EOT status signal is selected when the EQM is operating in Local Qualified mode and output on the EQO pin (see the following Board Level Local Event Qualification section). The EOT signal operates at the end of each protocol and indicates that the protocol-controlled inspection operation is complete. When the EQODIS signal is selected and output to the EQO pin, the IC's EQO pin is disabled, so that it does not affect other circuits to which it can be input.

[EQM controller check protocol]

The state machine 48 of the EQM controller 38 includes commands for selecting and executing one of the test protocols shown in the state diagram of FIG. 7 described below. A No Operation (NOP) command is input to EQM controller 38 when there is no test protocol to be executed. Figure 7 shows how state machine 48 decodes the COMMAND input to select one of the probe protocol or NOP commands. When a protocol command is entered, state machine 48 leaves Idle state 56 and enters one of protocols 58-76 that is translated by command translator 78 . During the execution of the protocol, the EQM outputs a control that can be used to enable the test logic of the IC of FIG. 2 to perform certain test operations described in Table 1. If no protocol is to be executed, state machine 48 returns to idle state 56 via NOP command 79 .

After the protocol is executed, the test end state 80 is entered before returning to the idle state 56 . The controller 38 maintains the test end state until the next command is input as shown in the decision block 82 . During the test end state, the EOT state signal shown in FIG. 6 may be set and output from the EQO pin through MUX2. The reason for selecting the EOT signal to be output to the EQO pin is explained in the Board Level Local Event Qualifications section of this document.

All protocols 58-76 use event and loop counters 44 and 42 shown in relation to the state machine of FIG. Event counter 44 is a countdown counter used to count the number of events or system clocks input to state machine 48 . Using event counter 44 to count events allows state machine 48 to respond to an Nth event, where N equals the count value loaded into event counter 44 instead of the first event . The ability to initiate and stop inspection operations in response to a first, second, or nth programmable event enhances the ability of the event confinement architecture to execute inspections or other actions in response to event input. The loop counter 42 is a countdown counter mainly used to count the number of times a protocol is repeated. When the loop counter 42 is loaded with a count M, the protocol is repeated exactly M times.

[Protocol 1]

Protocol 1 causes a check or other procedure to occur once in response to the Nth event, and repeat M times, as shown in the pseudocode to be described below and the state diagram of FIG. 8 . In this specification, a state is a logical location in a state diagram. States in the state diagram are shown as transitioning from one state to another either automatically or in response to a condition input. The way states are indicated determines the function of the state diagram. A state can exist in one of two forms: a temporary state and a fixed state. Transient states are entered on one clock and exited on the next subsequent clock, ie, they cannot loop back on their own. A fixed state can be entered with one clock and exited or looped back on the next subsequent clock.

An action is a predefined action that is executed when the state diagram transitions from one state to another. The state machine outputs control to external logic circuitry to accomplish the operation. Actions are shown by dotted lines in the figure.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an action until N occurrences of the event are detected (state 84). Whenever state machine 48 detects an expected event (EVENT=1), it examines the EVCMIN signal of the event counter to know if the counter is at its minimum count (EVCMIN=1). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for event input (state 88), then decrements event counter 44 once (action 90), and Start monitoring the next occurrence. When an event is detected and the event counter 44 is the minimum count, state machine 48 issues control to execute a single check operation (state 92) and then waits for the event to end (state 95).

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 checks the loop counter's LPCMIN signal to see if loop counter 42 is at the minimum count (state 95), if loop counter 42 is not at the minimum count (state 95). LPCMIN=0), state machine 48 decrements loop counter 42 once (action 98), generates control to load a new N count into event counter 44 (action 100), and memory of EQCs Output a new pair of CMPDAT and CMPMSK signals (action 102) and repeat the protocol sequence described above. When the loop counter 42 is at the minimum count (LPCMIN=1), the state machine 48 transitions to the check end state 104 to end the protocol.

The pseudo code for protocol 1 is as follows.

For M times do:

Begin

On Nth event do test

End

End of Test

[Protocol 2]

Protocol 2 operation causes a check or other procedure to occur while the Nth event is provided M iterations as shown in the pseudocode described below and the state diagram of FIG. 9 .

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an action until N occurrences of the event are detected. Whenever state machine 48 detects an expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 106). If an event is detected and event counter 44 is not at the minimum count in state 106, state machine 48 waits for event input (state 110) and then decrements event counter 44 once (action 112), start monitoring the next occurrence of the same event. When an event is detected and event counter 44 is at the minimum count, state machine 48 generates control to execute a check action when an event input is provided (state 114). When the event input disappears, state machine 48 ends the check operation.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 examines the LPCMIN signal of the loop counter to see if the counter is at its minimum count (state 114). If loop counter 42 is not at the minimum count, state machine 48 decrements loop counter 42 once (action 118) and generates control to load a new N count into event counter 44; (Action 120), cause the memory in the EQC to output a new pair of CMPDAT and CMPMSK signals (Action 122), and repeat the protocol sequence described above. When loop counter 42 is at the minimum count, state machine 48 transitions into check end state 124 to end the protocol.

The pseudocode for protocol 2 is as follows:

For M times do

Begin

During Nth event do test

End

End of test

[Protocol 3]

The operation of protocol 3 is as shown in the pseudocode described below and the state diagram of FIG. 10, where a test or other procedure is initiated in response to a first Nth event, and stops in response to a second Nth event, which is repeated M times. make it

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects a first expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 126). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 130), then decrements event counter 44 once (action 132), the same Start monitoring the next occurrence of an event. When an event is detected and event counter 44 is at the minimum count, state machine 48 generates control to initiate a check operation (state 134). When the detected event that initiates the check operation disappears, state machine 48 generates control to load event counter 44 with a new count of N (action 136) and memories within EQC cause a new pair of CMPDAT and CMPMSK signals. is output (action 138) to be used for comparison (state 140) for the second Nth event that stops the inspection operation.

When state machine 48 monitors a second Nth event that halts the check operation (state 140), it continues to generate control to maintain the check operation. Whenever state machine 48 detects a second event, it examines the EVCMIN signal of the event counter to see if the counter is at its minimum count. When an event is detected and the event counter 44 is not at the minimum count, the state machine 48 waits for the event input to disappear (state 144), then decrements the event counter 44 once, and the next occurrence of the same event occurs. start monitoring (Action 146). When an event is detected and the event counter 44 is at the minimum count, state machine 48 generates control to stop the check operation (state 148).

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass of the protocol, state machine 48 examines the LPCMIN signal of the loop counter to see if the counter is at the minimum count (state 148). If loop counter 42 is not at the minimum count, state machine 48 decrements loop counter 42 once (action 152) and generates control to load a new N count into event counter 44; (Action 154), cause the memory in the EQC to output a new pair of CMPDAT and CMPMSK signals (Action 156), and repeat the protocol sequence described above. When loop counter 42 is at the minimum count, state machine 48 transitions to check end state 158 to end the protocol.

The pseudocode for protocol 3 is as follows:

For M times do

Begin

On Nth event start test

On Nth event stop test

End

End of test

[Photocall 4]

The operation of protocol 4, as shown in the pseudocode described below and the state diagram of FIG. 11, is that a check or other procedure is initiated at N clocks after detection of the first Nth event, and is stopped in response to the second Nth event, which Repeat M times.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects a first expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 160). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 164), then decrements event counter 44 once (action 166), and 1 Start monitoring the next occurrence of an event. When an event is detected and event counter 44 is at the minimum count, state machine 48 loads a new N count into event counter 44 (action 168), and for each system clock input, event counter 44 ) decrement once (state 170 and action 174).

When event counter 44 reaches the minimum count indicated by the EVCMIN signal, state machine 48 generates control to initiate a check operation, loads a new N count into event counter 44 (action 176), cause the memories within the EQCs to output a new pair of CMPDAT and CMPMSK signals that are used to compare against the second Nth event stopping the test operation (action 178). The ability to delay the initiation of the check operation for a predetermined number of clocks allows the start of the check operation at some point after the event initiation occurs (state 179).

After the check is initiated, the state machine 48 uses the event counter 44 to delay stopping the check operation until N occurrences of a second event are detected. Whenever state machine 48 detects a second expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 170). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 181), then decrements event counter 44 once, and the next occurrence of the second event. Initiate monitoring of (Action 182). When an event is detected and the event counter 44 is at the minimum count, the state machine 48 issues control to stop the check operation.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 examines the LPCMIN signal of the loop counter to see if the counter is at its minimum count. When loop counter 42 is not at the minimum count, state machine 48 decrements loop counter 42 once (action 184). Control occurs to load a new N count into event counter 44 (action 186). After the event has progressed (state 189), the state machine outputs a control that causes the memory in the EQC to output a new pair of CMPDAT and CMPMSK signals (action 188), and repeats the protocol sequence described above. When the loop counter 42 is at the minimum count, the state machine 48 transitions to the Check End state to end the protocol (state 190).

The pseudocode for protocol 4 is:

For M times do

Begin

On Nth event start test after N clocks

On Nth event stop test

End

End of test

[Protocol 5]

The operation of protocol 5 is initiated in response to the first Nth event, and stopped N clocks after detection of the second Nth event, as shown in the pseudocode described below and in the state diagram of FIG. Repeat M times.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects a first expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 192). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 196), then decrements event counter 44 once (action 198), and 1 Start monitoring the next occurrence of an event. When an event is detected and event counter 44 is at the minimum count, state machine 48 issues control to initiate a check operation (state 200), and loads a new N count into event counter 44 (action 202), cause the memory inside the EQC to output a new pair of CMPDAT and CMPMSK signals that are used to compare against the second Nth event that initiates the stop sequence of the check operation (action 204).

After the check is initiated, the state machine 48 uses the event counter 44 to delay stopping the check operation until N occurrences of the second event are detected. Whenever state machine 48 detects a second expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 206). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 210), then decrements event counter 44 once (action 212), and a second Initiates monitoring of the next occurrence of an event. When an event is detected and event counter 44 is at its minimum count, state machine 48 loads a new N count into event counter 44 (action 214), and for each system clock input, event counter 44 ) decrement once (states 216 and 219 and action 220). When the event counter 44 reaches the minimum count indicated by the EVCMIN signal, the state machine 48 generates control to stop the check operation. The ability to delay the stop of the check operation for a predetermined number of clocks allows the check operation to stop at a certain point after the event stop occurs.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 examines the LPCMIN signal of the loop counter to see if the counter is at its minimum count (state 216). When the loop counter 42 is not at the minimum count, the state machine 48 decrements the loop counter 42 once (action 221), and generates control to load a new N count into the event counter 44 ( Action 222), cause the memory in the EQC to output a new pair of CMPDAT and CMPMSK signals (action 224), and repeat the protocol sequence described above. When the loop counter 42 is at the minimum count, the state machine 48 transitions to the Check End state (state 226) to end the protocol.

The pseudocode for protocol 5 is as follows:

For M times do

Begin

On Nth event start test

On Nth event stop test after N clocks

End

End of test

[Protocol 6]

The operation of protocol 6 starts N clocks after detection of the first N-th event, and stops N clocks after detection of the second N-th event, as shown in the pseudo code described below and the state diagram of FIG. , this is repeated M times.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects a first expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 228). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 232), then decrements event counter 44 once (action 234), and 1 Start monitoring the next occurrence of an event. When an event is detected and event counter 44 is at the minimum count, state machine 48 loads a new N count into event counter 44 (action 236), and for each system clock input, event counter 44 ) is decremented once (state 238 and action 242).

When event counter 44 reaches the minimum count indicated by the EVCMM signal, state machine 48 loads a new N count into event counter 44 (action 244), and the memories inside the EQCs are checked by a check operation. output a new pair of CMPDAT and CMPMSK signals used for comparison for a second Nth event that initiates a stop sequence of n (action 246), and generate control to initiate a check operation (state 248). The ability to delay the initiation of the check operation for a predetermined number of clocks allows the start of the check operation at some point after the event initiation occurs.

After the check is initiated, state machine 48 uses event counter 44 to delay stopping the check operation until N occurrences of the second event are detected (state 248).

Whenever state machine 48 detects a second expected event, it checks whether the counter is at the minimum count.

Examine the EVCMIN signal of the event counter to find out. If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 252), then decrements event counter 44 once (action 254), and a second Initiates monitoring of the next occurrence of an event. When an event is detected and event counter 44 is at its minimum count, state machine 48 loads a new N count into event counter 44 (action 256), and for each system clock input, event counter 44 ) is reduced once. When event counter 44 reaches the minimum count indicated by the EVCMIN signal (state 258 and action 262), state machine 48 generates control to stop the check operation. The ability to delay the stop of the check operation for a predetermined number of clocks allows the check operation to stop at a certain point after the event stop occurs.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass of the protocol, state machine 48 examines the LPCMIN signal of the loop counter to see if the counter is at the minimum count (state 258). When the loop counter 42 is not at the minimum count, the state machine 48 decrements the loop counter 42 once (action 264), and generates control to load a new N count into the event counter 44 ( action 266), cause the memory in the EQC to output a control that causes the output of a new pair of CMPDAT and CMPMSK signals (action 268), and repeat the protocol sequence described above. When the loop counter 42 is at the minimum count, the state machine 48 transitions to the Checked state (state 270) to end the protocol.

The pseudocode for protocol 6 is:

For M times do

Begin

On Nth event start test after N clocks

On Nth event stop test after N clocks

End

End of test

[Protocol 7]

Protocol 7 causes a check or other procedure to be initiated in response to the first Nth event as shown in the pseudocode described below and in the state diagram of FIG. 14, stopped after N system clocks, and repeated M times.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects a first expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 272). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 276), then decrements event counter 44 once (action 278). , initiates monitoring of the next occurrence of the same event. If an event is detected and event counter 44 is at the minimum count, state machine 48 loads into event counter 44 a new count of N equal to the number of system clocks on which the check is executed (action 280), and the check Control occurs to initiate an action (state 282). During the check, event counter 44 is decremented once during each system clock input (state 282 and action 286). When the event counter 44 reaches the minimum count, the state machine 48 stops the check operation.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 checks the loop counter's LPCMIN signal to see if the counter is at the minimum count (state 282), when the loop counter 42 is not at the minimum count, the state machine ( 48) decrements loop counter 42 once (action 288), generates control to load a new N count into event counter 44 (action 290), and memory in EQC causes a new pair of CMPDAT and CMPMSK signals. (Action 292), and repeat the protocol sequence described above. When the loop counter 42 is at the minimum count, the state machine 48 transitions to the Check End state (state 294) to end the protocol.

The pseudocode for protocol 7 is:

For M times do

Begin

On Nth event do test for N clocks

End

End of test

[Protocol 8]

Protocol 8 allows a check or other procedure to be initiated after N system clocks after detection of the Nth event, stopped after N system clocks, and repeated M times, as shown in the pseudocode described below and the state diagram of FIG.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an action until N occurrences of the event are detected. Whenever state machine 48 detects an expected event, it checks the EVCMIN signal of the event counter to see if counter 44 is at the minimum count (state 296). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 300), then decrements event counter 44 once (action 302), and the expected Initiates monitoring of the next occurrence of an event. When an event is detected and event counter 44 is at the minimum count, state machine 48 loads a new N count into event counter 44 (action 304). The N count is equal to the number of system clock cycles that must occur before the check operation can be initiated.

After the new count is loaded, state machine 48 decrements event counter 44 once while receiving each system clock input (state 306 and action 310). When event counter 44 reaches the minimum count indicated by the EVCMIN signal, state machine 48 reloads into event counter 44 a new N count equal to the number of system clock cycles in which the check operation is executed ( Action 312) Generate control to initiate an inspection operation (state 314). After the new count is loaded, state machine 48 decrements event counter 44 once while receiving each system clock input (state 314 and action 318). When the event counter 44 reaches the minimum count, the state machine 48 generates control to stop the check operation.

The loop counter 42 is used to cause the protocol described above to be repeated M times. After each pass through the protocol, state machine 48 examines the loop counter's LPCMIN signal to see if counter 42 is at its minimum count. When loop counter 42 is not at the minimum count, state machine 48 decrements loop counter 42 once (action 320), generates control to load a new N count into event counter 44 ( Action 322), cause the memory in the EQC to output a new pair of CMPDAT and CMPMSK signals (action 292), and repeat the protocol sequence described above. When the loop counter 42 is at the minimum count, the state machine 48 transitions to the Check End state (state 326) to end the protocol.

The pseudocode for protocol 8 is:

For M times do

Begin

On Nth event;

Pause of N clocks

Do test for N clocks

End

End of test

[Protocol 9]

Protocol 9, as shown in the pseudocode described below and in the state diagram of Figure 16, is that a check or other procedure is initiated in response to the Nth event, executed for N system clocks, and then the loop counter 42 is not at its minimum count. If not, let it pause for N system clocks before resuming the test.

During this protocol, the event counter 44 of Figure 5 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects an expected event, it checks the EVCMIN signal of the event counter to see if the counter is at the minimum count (state 328). If an event is detected and event counter 44 is not at the minimum count, state machine 48 waits for the event input to disappear (state 332), then decrements event counter 44 once (action 334), Initiate monitoring of the next occurrence of the same event. If an event is detected and event counter 44 is at the minimum count, state machine 48 loads into event counter 44 a new count of N equal to the number of system clocks on which the check is executed (action 336), and the check Control is generated to initiate an action (state 338). During the check, event counter 44 is decremented once during each system clock input (state 338 and action 342).

When the event counter 44 reaches the minimum count, the state machine 48 stops the check operation and checks to see if the loop counter 42 is at the minimum count. Depending on whether the loop counter 42 is at the minimum count or not, the state machine takes one of two possible actions. In a first operation in which the loop counter 42 is not at the minimum count, as determined by examining the LPCMIN signal, the state machine 48 decrements the loop counter 42 once (action 344), and then the check operation is A new N count equal to the number of paused system clocks is loaded into event counter 44 (action 346). Event counter 44 is decremented once during each system clock input (state 348 and action 352).

When the event counter 44 reaches the minimum count, a new N count is loaded into the event counter 44 (action 354), and the event counter 44 once again reaches the minimum count, at which time the loop counter 42 . The check operation is resumed until is checked again for the above-mentioned minimum count. In a second operation where the loop counter 42 is at the minimum count, the protocol ends and the state machine 48 transitions to the check end state 356 .

The pseudocode for protocol 9 is as follows:

On Nth event do;

Do test for N clocks

Then For (M-1) tlmes do

Begin

Pause for N clocks

Do test for N clocks

End

End of test

[Protocol 10]

Protocol 10 allows a check or other procedure to be initiated in response to the Nth event. Once initialized as shown in the pseudocode described below and the state diagram of Figure 18, the protocol pauses for N system clocks, runs for N system clocks, and executes the pause and run sequence M times.

During this protocol, the event counter 44 of Figure 6 is used to delay the initiation of an operation until N occurrences of the first event are detected. Whenever state machine 48 detects an expected event, it checks the EVCMIN signal of the event counter to see if counter 44 is at the minimum count (state 358), an event is detected, and event counter 44 If not at the minimum count, state machine 48 waits for the event input to disappear (state 362), then decrements event counter 44 once (action 364), and begins monitoring the same event and the next occurrence. When an event is detected and event counter 44 is at the minimum count, state machine 48 loads into event counter 44 a new N count equal to the number of system clocks at which the actual start of the check is delayed or paused. control is generated for During pause operation, event counter 44 is decremented once during each system clock input (state 368 and action 372).

When event counter 44 reaches the minimum count, state machine 48 initiates a check and generates control to load a new N count into event counter 44 (action 374). During the check operation, the event counter 44 is decremented once during each system clock input (state 376 and action 380). When the event counter 44 reaches the minimum counter, as determined by monitoring the EVCMIN signal, the state machine 48 examines the loop counter's LPCMIN signal to see if the loop counter 42 is at the minimum count. Stop the inspection operation. If loop counter 42 is not at the minimum count, state machine 48 decrements loop counter 42 (action 382) and loads a new N count into event counter 44 (action 384), as described above. Repeat one sequence (pause for N, then check for N). When loop counter 42 is at the minimum count, state machine 48 ends the protocol and transitions to check end state 386 .

The pseudocode for protocol 10 is as follows.

On Nth event;

For M times do

Begin

Pause for N clocks

Do Test for N clocks

End

End of test

[Board level event only]

The event confinement architecture is described herein as being applied locally to the boundary of one IC. Here, we describe how multiple ICs participate in the event confinement process. FIG. 18 shows a board design with a plurality of ICs 20 including the event confinement architecture shown in FIG. 2 along with a voting circuit 388 . The select circuit is required for board level confinement and is used to combine all EQO signals from each IC into a single signal that is fed back to each IC through the EQI input.

The board has inputs and outputs for system data, a 4-wire 1149.1 check bus interface (TCK TMS TDI and TDO signals), and an interrupt (INT) to output event signals. The four wire test bus and INT signal are coupled to a test bus controller 390 . The test bus controller 390 serially accesses the IC 20 on the board design via the 1149.1 test bus to establish and execute test operations and extract test data obtained from the test.

[Board Level - Local Event Only]

The IC 20 of FIG. 18 may be configured to perform local limit and check operations with scan access from the 1149.1 check bus controller. When IC 20 operates in a locally confined mode, each IC performance check is limited only by conditions that occur locally at the boundary of the IC. In this mode, all of the ICs 20 of FIG. 18 may be configured to execute respective test operations concurrently, each test operation being controlled by a different type of event confinement protocol. For example, some ICs can be configured to compress input and output data to the TCRs 14 and 16 using event confinement protocol 3, while others use event confinement protocol 2 to compress the internal TMEM 28 It can be set to memorize input data in

During localization, EQM state machine 48 selects the CTERM shown in Figure 6 to be the source of the events it monitors to start and stop the test protocol. CTERM indicates the status of local comparison operations occurring at the boundary of the host IC. Therefore, in localized mode, a protocol can be started and stopped only in response to an operational comparison that occurs at the boundary of host ICs.

Also, during localization, the EQO output from each IC 20 is set to output the EOT status signal from the EQM state machine 48 of FIG. The selection circuit 388 receives the EQO signals and outputs an EQI signal that is fed back to the EQI input of each IC. The EQI output from the select circuit 388 is also fed off-board via the INT signal. The selection circuit does not output the EQI signal until all the ICs 20 have completed the local check operation (protocol) and output the EOT status signal from the EQO output. By monitoring the INT output, test bus controller 390 can determine when all test operations performed by each IC 20 are complete. When the INT signal is detected, the test bus controller 390 executes a scan operation to extract the test data collected within each IC for testing.

[Board level-Global event limited]

Local qualification is used when multiple tests are required, but there are times when the limit of tests needs to extend outside the boundaries of the target IC. Increasing the number of boundary signals participating in the confinement process improves the resolution as to when the inspection operation is enabled. For example, a signal at one IC boundary may not provide sufficient confinement for a particular test operation. However, by combining the boundary signal of the target IC with the boundary signals of neighboring ICs, a global confined mode that can be used to more accurately enable the inspection operation is obtained.

During global confinement, the EQO signal from each IC 20 is set to output the result of the IC's local boundary comparison operation. EQO signals from all ICs 20 may be input to a selection circuit 388 and combined into one composite global comparison signal. A non-participating IC sets its EQO output to a state that does not interface with the operation of the select circuit (see EQODIS input to MUX2 54 in FIG. 6). The output of the select circuit 388 is fed back to the EQI input of each IC so that the EQM inside each IC 20 can monitor the generation of the global comparison signal.

Whenever a match occurs at all IC boundaries, the EQO outputs of IC 20 are all enabled, and the selection circuit 388 outputs a global comparison signal back to the EQI inputs of each IC. EQM 22 of each IC 20 executes a protocol that controls a predetermined test operation in response to the EQI input. By monitoring the INT output, test bus controller 390 can determine when the global test operation is complete so that the obtained test data can be scanned out of the ICs for retrieval.

[Only use EQM when designing IC]

Although this specification has described an event limited architecture as including both EQC 24 and EQM 22, it is possible to use only EQM 22 when there is not enough logic circuitry in the IC to implement EQC 24. When only EQM 22 is used, the EQI input acts as a single event input to start and stop the EQM's protocol. The EQM operation remains the same, the only difference is that the definition of the check operation must always be input to the IC via the EQI pin instead of being selectively generated inside the IC. Since no internal limiting occurs when the IC does not contain an EQC, or similar comparison circuit, the EQO pin is used to output only the EOT status signal from the EQM controller 38 or the EQODIS signal through MUX2 54 (the first see also 6).

[Using architecture in different IC architectures]

Although this specification has described the event-only architecture as being included within the typical IC architecture of FIG. 2, other types of IC architectures may readily be used. 19 and 20 show two IC architectures implementing the above architecture. These IC architectures differ from the architecture shown in FIG. 2 in that they have only input signals, check logic for receiving the input signals, and an event limited architecture.

[Digital Signal Monitor]

The digital signal monitor IC 392 of FIG. 19 includes a TCR 14 , a TMEM 28 , an EQC 24 , an EQM 22 and a TAP interface 12 . The TAP provides serial access to the IC 392 to establish test operations and extract test results. Digital signals are input to TCR 14 and TMEM 28 for monitoring and EQC 24 for comparison against expected data. In operation, EQM 22 receives an event input from EQC 2B or from an EQI input to initiate execution of a predetermined protocol. When an event is received, the protocol is initiated and EQM 22 outputs control to TCR 14 and TMEM 28 to initiate data monitoring. The TCR 14 may be configured to sample a single data input pattern or to compress a stream of data input patterns. The TMEM 28 can be configured to store multiple data input patterns. When the protocol is complete, EQM 22 outputs control to TCR 14 and TMEM 28 to stop monitoring data. After the test is complete, the data stored in the TCR 14 and TMEM 28 can be scanned out through the TAP interface for testing.

[Analog Signal Monitor]

The analog signal monitor IC 394 of FIG. 20 includes a TCR 14, a TMEM 28, an EQC 24, an EQM 22, a TAP 12, an analog multiplexer 396 and an analog/digital converter (ADC) ( 398). The analog signal monitor 394 receives a plurality of analog signals input to the analog multiplexer 396 . The multiplexer selects one of the analog signal inputs to the ADC 398 . ADC 398 converts the analog signal input into a digital pattern representing the voltage of the analog signal. After one transformation is completed, the transformation is repeated. Therefore, when the voltage of the analog signal changes, the digital output of ADC 398 changes to reflect the new voltage of the analog signal.

After the analog signal is converted to digital form, the analog monitor operates exactly like the digital signal monitor of FIG.

The digital pattern output from ADC 398 is input to TCR 14 and TMEM 28 for monitoring and EQC 24 for comparison against expected data.

EQM 22 receives event inputs from EQC 24 or from EQI to initiate execution of a predetermined protocol. When an event is received, the protocol is initiated and the EQM outputs control to cause the TCR 14 and TMEM 24 to initiate monitoring of the digital pattern output from the ADC. The TCR can be set to sample a single digital pattern or to compress a stream of digital patterns. The TMEM 24 can be configured to store multiple digital patterns. When the protocol is complete, EQM 22 outputs control to TCR 14 and TMEM 24 to stop monitoring data. After the test is complete, the data stored in the TCR 14 and TMEM 24 can be scanned out through the TAP interface for testing.

The present invention overcomes the problems described in the 1149.1 sample instruction and provides a method for performing another functional check immediately after sampling of a single data pattern. Because the present invention can be implemented in the IC itself, no external circuitry must be added to the circuit board to provide synchronization and confinement of external control inputs to perform on-line test operations.

Also, when the present invention is enabled to control the test operation, it operates independently from the IC's TAP, allowing different ICs to do different tests at different times. Having local test control within each IC instead of a global test control input for all ICs can reduce centralization of testing at the circuit board level.

Importantly, the ability of the present invention to enable boundary check logic circuitry when the host IC is operating normally allows checking of normal rate data transfers between ICs in the board design. Using this method, timing sensitivity and/or intermittent data transfer failures that may occur between multiple ICs within a functional circuit can be detected. These types of failures are either impossible or very difficult to detect without physically probing the board design.

At the level of board design technology using surface mount technology, physical access to probe functional boards is very limited and in some cases not possible at all. Also, in circuits designed using very high speed techniques, electrical loads associated with the probing instrument may affect the behavior of the signal being probed, which may cause the circuit to malfunction.

The present invention provides an alternative method of checking for normal speed related issues when physical probing of the board design is not possible or when probing affects the operation of the board. Because the present invention can be designed into an IC, it remains in the product after leaving the factory inspection room. Therefore, it can be reused during the product lifecycle for system integration, environmental inspection, field service and repair.

Although the preferred embodiment of the present invention has been described in detail, it should be understood that various changes, substitutions and changes may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.