Hierarchical connection method and apparatus

This invention relates generally to the use of buses to communicate between devices comprising circuits, systems, boards and networks, and more particularly to serial backplane buses. The invention can be applied to any environment in which a serial communication bus is or may be used, including circuit boards, backplanes, integrated circuits and systems.

BACKGROUND OF THE INVENTION

When manufacturing integrated circuits or circuit boards for systems, using a serial communication bus for testing and debugging quickly becomes standard practice. The use of the serial bus enables the system, circuit board or integrated circuits to be tested and the connections to be confirmed without the need for interventional hardware or probes. This is particularly important because the packaging of the devices achieves higher densities, as well as for multiple integrated circuits housed on a single module, or for systems in which the circuit is otherwise unavailable for physical access.

The industry has developed and continues to develop standards protocols for such serial buses. The standards are necessary and desirable to ensure that components and boards purchased from different vendors can communicate with each other on a common bus. The concepts of this invention are generally applied to any type of serial bus. However, in order to clarify the description of the invention, it is described as a feature added to the well understood and documented IEEE / ANSI standard serial bus developed for board level IC testing and as IEEE / ANSI Standard 1149.1 or more generally referred to as the JTAG edge scanning standard.

The IEEE / ANSI-1149.1 standard describes a 4-wire serial bus that can be used to transmit serial data to and receive serial data from multiple ICs on a board. Although the 1149.1 serial bus was originally developed to serially access ICs at the board level, it can also be used at the backplane level to serially access ICs on multiple boards.

The 1149.1 standard describes a 4-wire serial bus that can be used to transfer serial data between a serial bus master and a slave device. Although the 1149.1 bus is designed to serially access ICs on a board, it can be used on the backplane level to serially access boards in a backplane. The 1149.1 has two serial access configurations labeled "Ring" and "Star" that can be used on the backplane level.

In a backplane 1149.1 ring configuration, all boards in the backplane directly receive the control output signals from the primary serial bus master (PSBM) and are linearly chained between the data output and the data input of the PSBM. During a scan operation, the PSBM outputs control scan data through all boards in the backplane via its test data output (TDO) and test data input (TDI) bus connections. The problem associated with the ring configuration is that the scan operation only works if all boards are contained in the backplane and can be operated to sample data from their TDI input to TDO output signals. If one of the boards is removed or has a fault, the PSBM cannot scan the data from the backplane. Because the ring configuration does not allow access to the remaining boards when one is removed or locked, it does not fully meet the requirements of a serial bus for the backplane and large system applications.

In a backplane 1149.1 star configuration, all boards in the backplane directly receive the test clock (TCK) and TDI signals from the PSBM and output a TDO signal to the PSBM. Each board also receives a unique test mode selection (TMS) signal from the PSBM. In the star configuration, only one board is released at a time for serial access by the PSBM. If a board is released, the TMS signal assigned to this board is active, while all other TMS signals are inactive. The problem with the star configuration is that each board needs its own TMS signal. In a backplane with 100 boards, the PSBM must have 100 individually controllable TMS signals, the backplane must have lines for each of the 100 TMS signals. Because of these requirements, star configurations are typically not considered for backplane applications.

IRE Wescom Conference Record, November 1989, Vol. 33, pp. 294-299 describes the use of the 1149.1 standard bus in both ring and star configurations.

Two serial IEEE bus standards P1149.5 and P1394 are in development for use in system rear panels. Because these standards are specifically designed for backplane applications, they appear to address the problems associated with using the 1149.1 standard bus as the backplane bus. However, the protocols of these announced standards differ from the 1149.1 protocol, which is why procedures must be defined to translate between them and 1149.1.

The IEEE P1149.5 standard working group is currently defining a module test and maintenance bus that can be used in backplane environments. P1149.5 is a single master / multislave bus that is defined by a 5-wire interface. The P1149.5 bus master initiates a data transfer operation by sending a data packet to all slave devices. The data packet includes an address and command section. The slave device that has an appropriate address is enabled to respond to the command section of the data packet as described in the P1149.5 standard proposal.

Integrating a P1149.5 bus into an 1149.1 bus environment requires new additional system hardware and software as well as developers with a detailed understanding of both bus types. When P1149.5 is integrated into an 1149.1 environment, an unnecessary complication is added to an otherwise simple serial access approach. Another problem is that the bandwidth of the 1149.1 serial data transfer is adversely affected by the process and hardware for protocol conversion from 1149.5 to 1149.1.

The IEEE P1394 standard working group is currently defining a high speed 2-wire serial bus that can be used in either a cable environment or a system backplane environment. In contrast to P1149.5, the P1394 standard is not a single master / multislave bus type. In P1394 all devices (nodes) connected to the bus are considered to have the same master rank. The fact that the P1394 can operate with a 2-wire interface makes this bus attractive in newer 32-bit backplane standards, in which only two wires are reserved for serial communication. However, there are problems using P1394 as a backplane test bus to access 1149.1 board environments.

First, P1394 is significantly more complex to operate than P1149.1, so the devices used to translate between P1394 and 1149.1 can be costly. Second, P1394 is not a full-time test bus, but a universal serial communication bus, its main purpose in a backplane environment is to serve as a spare interface in the event that the parallel interface between the boards is disabled. While an 1149.1 test access can be achieved via P1394, it is only available during the time slices during which the bus does not handle any functional operations. Such on-line 1149.1 test bus access is limited and must be coordinated with other transactions that occur on the P1394 bus. This requires additional hardware and software complexity.

Another method of achieving a backplane-to-board level interface is to expand the protocol defined in standard 1149.1. Such an approach was described in a paper presented at the 1991 International Test Conference by D. Bhavsar under the title "An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes". The Bhavsar paper describes a method of extending the 1149.1 protocol so that it can be used to access an interface circuit located between the backplane and board level 1149.1 buses. The interface circuit responds to the 1149.1 protocol sent over the backplane bus to load an address. If the address matches the address of the interface circuit, the interface circuit is connected to the rear wall. After the interface circuitry is connected to the backplane, the additional 1149.1 protocol is entered into the interface circuitry to connect the backplane and board level 1149.1 buses. After this connection procedure, the board level 1149.1 bus can be controlled by the backplane 1149.1 bus. Bhavsar's approach also has problems that limit its effectiveness as a universal 1149.1 bus interface from the backplane to the board.

Bhavsar's approach does not allow one board to be selected and then another board to be selected without first resetting the backplane and board level 1149.1 buses by placing them in their test logic reset (TLRST) states. Setting the TLRST state causes the test state setting in the ICs of a preselected board to be lost due to the test reset effect of the 1149.1 bus on the test access ports (TAPs) of the ICs.

Furthermore, it is often desirable to select and initiate self-tests in a selected group of backplanes. However, since the Bhavsar approach requires the 1149.1 bus to be reset each time a new board is selected, it is impossible to have more than one board self-test at a time since the bus reset cancels any previously initiated self-test ,

There is therefore a need for a simple, efficient, and effective facility to support the use of a standard 1149.1 serial bus in a multi-board backplane environment.

The invention provides a system having a master device and a plurality of slave devices connected by a communication bus;

each slave device including an addressable port circuit that is operable to connect the communication bus to, or the communication bus from, the slave bus using the same bus protocol as the communication bus -Device separates;

each addressable port circuit includes: a primary port to which the communication bus is connected; a secondary port to which the slave device bus is connected; a connection device connected to the primary port and the secondary port and operable to connect or disconnect the communication bus from the slave device bus in response to a control signal; and control circuitry for generating the control signal in response to a dialing sequence (selection sequence) output by the master device;

wherein when the communication bus is not used for normal communication according to the bus protocol, the master device can send a dialing sequence to the communication bus using a protocol different from the normal communication protocol to send the logical address to a slave device to be selected next specify; and

the control circuitry in each slave device is arranged to check whether an address output by the master device corresponds to the logical address of this slave device; wherein the control circuitry is arranged to, if this address does not correspond to the logical address, send a message to the connection device in order to separate the bus of this slave device from the communication bus; and wherein the circuitry is arranged such that, if this address corresponds to the logical address, it sends a message to the connecting device in order to connect the bus of this slave device to the communication bus in such a way that it is separated from the system by one Communication bus are perceived.

Generally, and in one embodiment of the invention, a backplane access approach is disclosed that provides a method of using the 1149.1 bus on the backplane level without the problems described above. Using this approach, it becomes clear that a homogeneous serial bus can be used across a system design, rather than translating between multiple serial bus types. Using a common serial bus in system designs can simplify software and hardware development efforts, since only an understanding of one bus type is required.

In a first embodiment of the invention, a circuit, referred to as an addressable shadow port (ASP), and a protocol, referred to as a shadow protocol, are described which provide a simple and efficient method of directly connecting the 1149.1 backplane and board buses. When the 1149.1 backplane bus is either in its Run Test / Idle (RT / IDLE) state or in its Test Logic Reset (TLRST) state, the ASP circuitry can be enabled via the shadow protocol of the invention to provide a serial 1149.1- Connect the bus of a target board to the serial backplane 1149.1 bus. After the shadow protocol described here has been used to interconnect the target board and backplane buses, the protocol of the invention becomes inactive and transparent to the operation of the 1149.1 bus protocol.

The use of the invention results in several improvements over the use of the 1149.1 standard in a system or backplane environment or the prior art expansion approaches in terms of data transfer efficiency, the ability to remove boards, or to support backplanes, in which not all Slots are occupied, the possibility of holding the 1149.1 bus in an idle state when boards are selected and deselected, and the advantageous use of the well understood 1149.1 serial bus without the need for additional bus development or a translator circuit to achieve these improvements.

Another embodiment is disclosed in which a single board contains multiple 1149.1 scan paths, each of which can be connected to the serial backplane bus using an individually addressable shadow port, for additional flexibility in scan path and testability design. Other preferred embodiments and improvements are also disclosed.

Other embodiments extend the ASP circuit and protocol to enable the serial local bus to be controlled either by a remote serial bus master circuit or alternatively by a primary serial bus master located on the serial backplane bus. The ASP capabilities are expanded to allow the input and output of parallel data to memory via the ASP and the primary serial bus master. The ASP circuit and protocol are further expanded to allow interrupt, status and command information to be transmitted between a remote serial bus master and a primary serial bus master to support higher level commands and remote functions that are autonomous from the remote serial bus master be carried out.

The invention is then applied to hierarchically organized systems in which several backplane systems are linked via networks which are coupled in a multi-level environment. The ASP capabilities are expanded to allow the primary serial bus master to directly select any board within the hierarchy and to send and receive data and commands from it.

An additional embodiment is disclosed in which the circuitry and protocol of the invention are adapted for use with the proposed 2-wire serial backplane buses, which are considered by some in the industry. Modifications and improvements are described to make the invention compatible with such a bus.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings show:

1 shows a typical backplane-to-board connection using the 1149.1 bus standard;

2 shows a state diagram of the states of the 1149.1 bus transitions during operation;

3 shows a typical prior art ring configuration of a standard 1149.1 bus used in a backplane environment;

Figure 4 shows a typical prior art star configuration of an 1149.1 bus in a backplane environment;

5 shows an embodiment of a connection between a serial bus master and a single board in a backplane environment using the 1149.1 standard bus and inserting the addressable shadow connector of the connection;

FIG. 6 shows a system backplane with multiple boards connected to a serial bus master via an 1149.1 serial bus using the protocol and hardware of the invention;

Figure 7 is a block diagram of the circuitry required to implement the addressable shadow pad circuit of the invention;

Fig. 8 shows the timing of transmission of an IDLE bit pair of the protocol of the invention;

Figure 9 shows the timing of transmission of a SELECT bit pair of the protocol of the invention;

Figure 10 shows the timing of a logical 1 data bit pair transmission of the protocol of the invention;

Fig. 11 shows the timing of a logical 0 data bit pair transmission of the protocol of the invention;

Figure 12 illustrates the transactions that take place between the serial bus master and the addressable shadow port of the invention during the shadow protocol selection and confirmation transactions;

Figure 13 shows the signal transitions on the serial bus lines that take place during the selection and confirmation transactions between the addressable shadow port and the serial bus master using the protocol of the invention;

Figure 14 is a state diagram showing the states of the transmitter circuitry present in the serial bus master and the transitions of the addressable shadow port of the invention during the transactions of the protocol;

15 is a state diagram showing the states of the receiver circuit included in the serial bus master and the transitions of the addressable shadow port of the invention during the transactions of the protocol;

Fig. 16 is a state diagram showing the states of the master control circuit of the serial bus master circuit transitions during the transactions of the protocol of the invention;

Fig. 17 is a state diagram showing the states of the slave control circuit of the transitions of the addressable shadow port circuit during the transactions of the protocol of the invention;

18 shows the subcircuits required in a preferred embodiment of the addressable shadow pad circuit of the invention;

Fig. 19 shows an alternative embodiment in which an integrated circuit with a plurality of secondary connections includes a plurality of independently addressable shadow connection circuits, each connected to a single primary connection which is coupled to the serial bus;

Figure 20 shows an integrated circuit incorporating the invention and provided with the addressable shadow port of the invention, a primary port connected to the serial backplane bus, and an internal serial bus connected to a plurality of application specific logic circuit blocks.

Corresponding reference numerals and symbols in the different figures refer to corresponding parts, unless stated otherwise.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following abbreviations are used in this description:

SBM designates the serial bus master of the invention, a circuit that can address and access other boards connected to the serial bus;

PSBM denotes the primary serial bus master;

ASP designates the addressable shadow port hardware of the invention;

TAP denotes a test access port, the standard hardware interface of the devices connected to the 1149.1 bus;

TMS denotes the test mode selection line, the control line of the 1149.1 bus;

TDO denotes the test data output line, one of the lines on which the 1149.1 bus carries serial data;

TDI denotes the test data input line, one of the lines on which the 1149.1 bus transmits data;

TCK denotes the test clock line, the common clock line that is used by all devices connected to the 1149.1 serial bus to synchronize transfers between devices.

A serial bus slave is a circuit or device that can be enabled and can communicate with a serial bus master over the serial bus network. A serial bus slave, as used in this specification, refers to any well-defined logic block or circuit with an input and output circuit that can be operated to enable communication on a serial bus. For convenience, this application treats serial busslaves as if they were printed circuit boards that span multiple ICs and are plugged into a system backplane. However, it is clear that the inventions can be used in applications that define serial bus slaves as: (1) subcircuits in an IC, (2) ICs on a common substrate (e.g. Multi-chip modules), (3) ICs on a printed circuit board, (3) boards plugged into a system backplane, (4) backplanes in a subsystem, (5) subsystems in a system or (6) systems that work with other systems are connected.

A serial bus master is a circuit or device that can output the necessary control signals to enable communication connections to a serial bus slave via the serial bus network. Throughout the rest of this description, the serial bus master is referred to as SBM.

1 shows an SBM 1, which is connected via a connector 2 to an example circuit board 3, which is connected to the 1149.1 standard 4-wire bus as is provided by the prior art. Within the board 3, the 4-wire serial bus is connected to various integrated circuits (ICs) IC1, IC2, ICn through a standard IC level serial interface circuit called a test access port (TAP). The TAP includes a control circuit that is responsive to the 4-wire serial bus to enable and disable serial access to the IC. The TAP pins used to connect to the serial bus include a serial test data input pin (TDI), a serial test data output pin (TDO), a test clock pin (TCK) and a test mode selection pin (TMS). The TAP's TDI pin is a unidirectional data input signal used to push serial data bit streams into the IC. The TAP's TDO pin is a unidirectional data out signal used to push serial data bit streams out of the IC. The TAP's TCK pin is a unidirectional clock input signal that is used to clock the serial data bit streams into and out of the IC via the TDI and TDO pins. The TMS TMS pin is a unidirectional control input that is used to enable the pushing of serial data bit streams into and out of the IC.

In operation, the circuit board 3 is plugged into a rear wall, the TAP of each IC IC1, IC2 etc. being connected in parallel to the TMS and TCK signals of the serial backplane bus from the SBM. Furthermore, each TAP of the ICs is serially linked or concatenated via their TDI and TDO pin connections to form a single serial data path between the TDI input signals and TDO output signals of the backplane. From the backplane, the SBM can input TMS and TCK signals into the board to cause the TAPs of the ICs to push data from the SBM's TDO output signal serially into the board via an IC on the board and back from the board into the TDI input signal of the SBM.

To understand the relationship between the invention and the 1149.1 standard serial bus, an overview of the 1149.1 serial bus operation is required. 2, a simplified diagram of the operation of the 1149.1 serial bus is shown. As shown in FIG. 1, in operation of the SBM, TMS and TCK control signals are output to the TAP control devices of each IC on the board to cause the ICs to keep up with the serial bus states of FIG. 2. The TAP of each IC operates in synchronism with the SBM's TCK clock output and responds to the SBM's TMS control output to be placed in and out of the serial bus states of Figure 2. The serial bus states include: RESET, IDLE, Select Data Scan (SELDS), Data Scan Sequence (DSS), Select Command Scan (SELCS) and Command Scan Sequence (CSS).

As shown in the board example shown in Fig. 1, a description of each 1149.1 bus state is given in the following paragraphs. 1 comprises the ICs 5, each IC having a TAP interface 7 and a connection to the 1149.1 bus via the backplane connector 2. The TAP interfaces of each IC on board 3 are designed to receive and respond to the serial bus states of FIG. 2 to control serial access to the ICs. The SBM 1 connected to the backplane is designed to generate and transmit the serial bus states of FIG. 2 to serially access the ICs on the board.

RESET state - in response to a TMS input, the TAP of each IC on the board can be caused to transition from any state to the RESET state, as shown in FIG. 2. In the RESET state, the TAP forces the test logic in the IC into a blocking state so that the test logic cannot interfere with the normal operation of the IC. The serial bus forces the TAP of each IC to hold the RESET state while the TMS signal is high.

IDLE state - in response to a TMS input, the TAP can put any IC from any state to the IDLE state. In the IDLE state, the TAP responds to TMS control inputs to: (1) remain idle, (2) enter the data scan sequence, (3) enter the command scan sequence, or (4) transition to the RESET state.

Data Scan Sequence - in response to the TMS input, the TAP can transition any IC from the IDLE state through the data select scan state (SELDS) to a data scan sequence (DSS). While the TAP is in the DSS state, an additional TMS control signal is input to cause data to be shifted from the TDI to the TDO via the IC's test data register. After the shift operation is completed, an additional TMS control signal is input to cause the TAP to exit the DSS and enter the IDLE state.

Command scan sequence - in response to a TMS signal input, the TAP of each IC changes from the IDLE state via the SELDS and Select Command Scan (SELCS) states to a command scanning sequence (CSS). While the TAP is in the CSS, an additional CMS control signal is input to cause data to be shifted from the TDI to the TDO via the IC's test command register. After the shift operation is completed, an additional TMS control signal is input to cause the TAP to exit the CSS and enter the IDLE state.

In summary, the ICs on the board, when connected to the 1149.1 serial bus signals of the backplane, keep pace with the serial bus when it transitions to or operates in any defined states. The TMS signal output by the SBM is used to control the operation of the TAP of each IC on the board.

Fig. 3 shows a back wall with the boards PLATINE1, PLATINE2 to PLATINEN, which are connected to the bus of the 1149.1 standard or the JTAG bus in the "ring" configuration of the prior art, which are also connected to the serial bus master SBM connected is. In the prior art backplane ring configuration, any number N of boards are connected to the 4-wire serial 1149.1 bus in the backplane wiring. All boards receive the TCK and TMS control output signals from an SBM connected to the backplane. As shown in Fig. 3, the TDM output of the SBM is connected to the TDI input of the first board, goes through the ICs of the board (as shown in Fig. 1) and is connected to the backplane via the board's TDO connector output. The TDO output of the first board is input to the TDI input of the second board, runs through the ICs of the board and is output to the rear panel via the TDO output of the board, etc. The TDO of the last board (N) is via the The TDO output of the board is output to the rear wall and entered into the TDI input of the SBM.

The SBM's TCK output clocks the data and command shift operations. The TMS output of the SBM runs the control signal to enable the shifting operations through all boards in the backplane ring configuration. The shift operation only works when all of the boards are contained in the ring and can be operated to shift data from its TDI input to the TDO output in response to the TMS and TCK control input signals from the SBM. If one of the boards on the backplane is removed, or if a board is unable to move data due to a fault in one of its ICs or in the connections between one of its ICs, the SBM cannot pass data and command information through the boards in the backplane slide.

The main problem with using the 1149.1 ring configuration as a serial backplane bus, as shown in Fig. 3, is that the scan operations only work as long as each board is electrically connected to the serial backplane bus and can be operated as In response to the TCK clock and TMS control signals the backplane pushes data from your TDI input to your TDO output. In most applications, the SBM requires serial access to backplane boards when one or more boards are removed for repair and / or replacement. Because the backplane ring configuration does not allow serial access to the remaining boards when one or more boards are removed, it does not meet the requirements of a serial backplane bus.

Although this description of the ring configuration has been made with respect to in-ring interconnected boards in a backplane, the same problems arise with multiple ring-connected circuits in an IC, with multiple ring-connected ICs on a common substrate, with multiple ring-connected boards in a backplane, with multiple ring-connected subsystems in one system and in several ring-connected systems.

Fig. 4 shows a backplane star configuration of the prior art, in which up to N boards, BOARD 1, BOARD 2, BOARD N, with a 4-wire serial 1149.1 bus located in the backplane wiring and also with the SBM serial bus master connected, connected. All boards receive the TCK and TDI bus signals from the SBM and output a TDO bus signal to the SBM. Each board also receives a unique TMS signal (1, 2 ... n) from the SBM. In the star configuration, only one board can be released by the SBM in order to transfer data from the TDO output of the SBM via the board level ICs (see FIG. 1) to the TDI input of the board and via the TDO output of the board To push the TDI input of the SBM. Because the boards all share a common TDO output wiring connection, only one board can be enabled at a time to output serial data on the TDO to be received by the SBM.

If a board is released for sales access, the TMS signal assigned to this board is active, while all other TMS signals of the other boards are inactive. When the scan access to the enabled board is complete, another board can be enabled via its TMS signal to enable the SBM to scan data and command information to and from this selected board.

The star configuration of the prior art disadvantageously requires that each board have its own TMS signal and backplane wire connection. In a back wall with 100 boards z. B. the SBM would have to have 100 individually controllable TMS signals to allow access to each of the 100 boards. In addition, the backplane would need to have wiring channels to support 100 TMS signals, one TMS signal wire for each board in the backplane. Due to a limited number of wiring channels in today's backplane bus standards, the star configuration cannot be used in most applications because it requires a TMS signal for each board in the backplane.

Although this description again refers to star-connected boards in a rear wall, the same problem occurs with: several star-connected circuits in an IC, several star-connected ICs on a common substrate, several star-connected boards in a back wall and several star-connected subsystems in one system.

Serial backplane buses are in development that eliminates some or all of the problems described using the 1149.1 serial backplane bus. For example, there is a military backplane bus called the Test and Maintenance Bus (TMBus) that can be used to access a board that contains 1149.1 compatible ICs. Two serial IEEE bus backplane standards (P1149.5 and P1394) are also under development and can also be used to access a board that contains 1149.1-compatible ICs. However, all known serial backplane buses work differently from the 1149.1 serial bus and are therefore not directly compatible, and all require translation hardware and software that contain at least two different bus standards.

In order to connect one of the suggested serial backplane buses mentioned to the 1149.1 standard board level bus, special interface circuits must be developed to translate between each of the various backplane serial bus protocols and the 1149.1 board level serial bus protocol. These serial bus interfaces are unique to each serial backplane bus because each serial backplane bus uses a different protocol. Thus, several interfaces have to be developed, one for each serial backplane bus protocol type. Furthermore, each interface disadvantageously requires that a complex IC be placed on the board to translate between one of the serial backplane buses and the 1149.1 serial board level bus. In addition, inserting the interface circuit between a backplane and the 1149.1 serial board level bus significantly reduces the bandwidth of serial data to and from an 1149.1 board environment. Furthermore, the above-mentioned serial backplane bus types are complex compared to the 1149.1 serial bus and require experienced engineers to develop the sophisticated and expensive interfaces and software. Although certain military and high quality commercial applications are capable of taking advantage of this sophisticated and expensive approach, these solutions are unsuitable and unusable for most commercial applications and systems.

Part 1

Addressable shadow connection and protocols

A first embodiment of a circuit board example using the invention is shown in FIG. 5. The circuit board 11 comprises a plurality of ICs IC1, IC2, ICN and an addressable shadow connection ASP which is connected to a system backplane bus using the 1149.1 standard bus and is also connected to a serial bus master SBM. When connected to the 1149.1 serial bus via the ASP, the ICs operate exactly as for the circuit board of FIG. 1 has been described. The ASP has a backplane interface for the connection with the serial backplane level 1149.1 bus signals, a board interface for the connection with the serial board level 1149.1 bus signals as well as an address input. The 1149.1 serial backplane bus signals are labeled: primary TDI (PTDI), primary TDO (PTDO), primary TCK (PTCK), and primary TMS (PTMS). The 1149.1 serial board bus signals are labeled: secondary TDI (STDI), secondary TDO (STDO), secondary TCK (STCK) and secondary TMS (STMS). The address input in the ASP is used to identify the board on which the ASP is mounted.

The invention defines a serial bus protocol and circuit that provides an addressable method of connecting the SBM to one of many boards in a backplane via an 1149.1 serial bus network. The circuit and the associated protocol are referred to below as an addressable shadow connection (ASP). The term "shadow" indicates the peculiarity of the protocol and circuitry that it is in the background of the serial bus to which it is associated. When the 1149.1 serial bus is operating, the ASP is inactive and does not interfere with the operation of the bus. The ASP can be enabled if the serial 1149.1 backplane bus is in one of the IDLE or RESET states (Fig. 2). The ASP is released when it is necessary to connect the SBM to one of the boards in the rear panel. After the ASP has been used to connect a board to the SBM, it is locked and is transparent to the normal operation of the 1149.1 serial bus or any bus to which it is associated.

Because the invention works with its own unique protocol that is not part of the 1149.1 protocol, it offers a solution for extending the 1149.1 standard of the backplane environment without modification of the 1149.1 standard or the need for additional hardware translation circuitry.

The ASP protocol can select or deselect boards while the 1149.1 serial backplane bus is in IDLE or RESET states. This is an important advantage over other proposed and existing approaches because, by allowing the 1149.1 bus to remain in the IDLE state when a new board is selected, the invention enables the self-test or other plateau functions to be performed on each board simultaneously supported. If it were necessary to go back to the 1149.1 standard RESET state to select the next board, the ASP protocol could not support these higher level test functions to run on multiple boards at the same time. Furthermore, desirable tests could not be performed between boards either, because when the boards 'ICs detect the RESET state on the bus, the test mode is canceled and the boards' ICs switch to functional mode. This situation could arise if e.g. B. board-to-board operations are to be tested.

5, the board address is entered externally into the ASP, it may also be hard-wired within the ASP circuit or be electrically programmable. The protocol of the invention provides the ability to select a particular board by the SBM issuing the address of the board to be selected using a unique serial protocol that does not interfere with the existing standard protocol developed for the 1149.1 serial bus.

FIG. 6 shows a number of circuit boards PLATINE1, PLATINE2, PLATINEN, which are each similar to those in FIG. 5 and are connected to the SBM via ASPs. If one of the boards has to be accessed during operation, the SBM sends a selection protocol that addresses and enables the ASP of the selected board. An address is embedded in the ASP selection protocol, which is used to compare with the address assigned to each ASP. All ASPs receive the selection protocol from the SBM, however only the one with the appropriate address is selected. In response to the SBM selection protocol, the selected ASP sends a confirmation protocol, including its address, back to the SBM to check the connection. After sending the confirmation protocol, the selected ASP establishes a connection between the backplane and board 1149.1 signals so that the PTDI backplane signal is connected to the STDO board signal and similarly PTMS to STMS, PTCK to STCK and PTDO be connected to STD1. In response to the ASP confirmation protocol, the SBM also exchanges commands and data with the selected board via the now transparent ASP using the serial 1149.1 standard bus protocol.

After the SBM has terminated its 1149.1 serial access to the currently selected board, it can select another board by sending a new selection protocol that addresses and releases another ASP on a board. The new selection protocol can be sent by the SBM while the serial bus is in the IDLE or RESET state (or in any other 1149.1 state in which the TDO and TDI signals are disabled). In response to the new selection protocol, the newly selected ASP sends a confirmation protocol back to the SBM and then creates a connection between the backplane and board level 1149.1 buses. When a new ASP is selected, the previously selected ASP is disconnected from the 1149.1 backplane bus. The disconnecting ASP remains in the state in which the backplane bus was when the disconnection took place, ie in IDLE or RESET. In response to the new ASP confirmation protocol, the SBM can issue the 1149.1 standard protocol to transfer serial data to and from the ICs of the newly selected board. This process is repeated every time a new board is selected.

The confirmation protocol section of the ASP protocol scheme also allows the SBM to verify that it has successfully selected a board. If e.g. For example, if the SBM issues a selection log to address a board in the backplane, and that board address does not exist, or the addressed board is locked or has been removed from the backplane, the SBM does not receive a confirmation log. If the SBM does not receive an acknowledgment protocol, it does not attempt to communicate with the board using the 1149.1 serial bus protocol. The SBM can also identify the problem and issue an error message that the connection to that particular backplane address has failed.

A key feature of the invention is the ability to electronically connect a serial backplane bus to a serial board plane bus in response to a unique protocol developed. The ASP protocol has two sections; a selection protocol sent from the SBM to the ASP of each board in the backplane and a confirmation protocol that is transmitted from the ASP of the selected board to the SBM.

This protocol is transmitted between the SBM and the ASP of each board in the backplane using the existing 4-wire serial bus signals defined by the 1149.1 serial bus. No additional backplane signals are required to use the invention. The protocol is also sent so that it does not interfere with the existing 1149.1 serial bus protocol.

This result is achieved by using the dead time of the 1149.1 serial bus to send the ASP selection and confirmation signals. In the 1149.1 serial bus configuration of FIG. 6, the SBM's TDO and TDI signals are only active to transfer serial data between the SBM and the selected board when the 1149.1 serial bus is in its DSS or CSS states of FIG . 2 is active. If the 1149.1 serial bus is in RESET or IDLE states, the TDO and TDI signals of the 1149.1 serial bus are blocked. Therefore, while the 1149.1 serial bus is in the RESET or IDLE state, the SBM can output the selection protocol of the invention at the TDO output of the SBM to the PTDI inputs of the ASPs and the confirmation protocol of the invention from the PTDO output of the selected ASP at the TDI -Received input of the SBM. Because the 1149.1 serial bus does not require the use of the TDO and TDI signals while they are used to transmit the selection and confirmation protocols of the invention, these transactions do not interfere with the operation of the 1149.1 serial bus.

The ASP and protocol extend the functionality of the SBM's TDO output and TDI input 1149.1 signals so that when not in use by the 1149.1 serial bus they can be used to implement the protocol of the invention transmitted to address and select one of the boards that are connected to the serial backplane bus via the ASP circuit. When comparing the star configuration of the prior art in FIG. 4 with the ASP configuration in FIG. 6 The benefits of the ASP circuitry and protocol arise from the fact that the ASP approach eliminates the need for additional TMS signals required in the 1149.1 star configuration. The ASP provides a method of eliminating the problems associated with the 1149.1 star configuration shown in FIG. 4 and effectively uses the 1149.1 serial bus on the backplane to access boards serially.

Furthermore, when the use of different backplane buses for connection in 1149.1 board environments is compared to the use of the ASP to achieve the same result, the invention advantageously does not require the use of high quality, expensive and inefficient translation circuits, and the protocol of the invention advantageously to the SBM allows to select several boards, to access them and to deselect them, without the need to reset the serial bus and its interfaces.

7 shows a block diagram of the ASP circuit. The circuitry of the addressable switch connector includes a primary connector for connection to the serial backplane level 1149.1 bus signals (PTDI, PTMS, PTCK, PTDO), a secondary connector for connection to the serial board level 1149.1 bus signals (STDO, STMS, STCK, STD1) and a control logic section. The control logic section interfaces the primary and secondary ports and also receives board address input.

During a selection protocol, the control logic receives a PTDI input sequence from the SBM. If the address received during the selection protocol transmission matches the board address entered in the control logic, the control logic establishes a connection between the primary and secondary connections and sends a confirmation protocol containing the board address back to the SBM via the PTDO output. In response to receiving the confirmation protocol, the SBM outputs the 1149.1 serial bus protocol on the backplane to serially input and output data to the selected board via the connection established by the control logic between the primary and secondary ports of the ASP to spend this.

If the address received during the selection protocol transfer does not match the board address entered, the control logic does not establish a connection between the primary and secondary connections and does not send an acknowledgment protocol to the SBM. In response to the acknowledgment protocol not being received, the SBM detects that the board address does not exist or is unable to respond and does not attempt to transfer serial data to the board using the 1149.1 serial bus protocol.

As shown in Fig. 1, the 1149.1 serial bus has four bus signals, two signals for data transmission (TDI and TDO), a signal that provides a clock (TCK), and a signal that controls the operation of the bus (TMS ). The TMS signal controls the state of the bus, as shown in the diagram in FIG. 2. The TMS signal determines whether the serial bus shifts data on the TDO and TDI signal paths or is placed in an IDLE or RESET state. Thus, the 1149.1 serial bus uses separate signal paths to control the operation of the bus (TMS) and the transmission of serial data on the bus (TDO and TDI). Since the aim of the invention is not to disrupt the normal operation of the bus with which it is used, the invention cannot reuse the TMS signal to control its selection and confirmation protocols.

To enable the SBM and ASP to exchange the selection and confirmation protocols of the invention without using the 1149.1 TMS control signal, an encoding scheme has been developed which allows control and data information to be transmitted together on a single wiring channel. As shown in Fig. 6, the coding scheme allows the SBM to transmit the selection protocol from its TDO output to the PTDI inputs of the ASPs. Similarly, the coding scheme allows the selected ASP to transmit the acknowledgment protocol from its PTDO output to the SBM's TDI input. In both transactions, the protocols are transmitted over a single backplane channel. The selection protocol runs through the wiring channel between the TDO output of the SBM and the PTDI inputs of the ASPs. The confirmation protocol runs through the wiring channel between the PTDO output of the selected ASP and the TDI input of the SBM.

Although this description describes the selection and confirmation protocols as being sent on separate individual wiring channels, they can also be transmitted on a common single wiring channel since the protocols are never transmitted simultaneously. The reason that the preferred embodiment shown here uses separate individual wiring channels for the selection and confirmation protocols is to maintain compatibility with the 1149.1 serial bus standard, which uses two separate wiring channels, so that serial data input and data output transmissions simultaneously can take place.

Both the selection and confirmation protocols of the invention require a method of sending a control signal to indicate: (1) an idle state, (2) a start data transfer state, and (3) a stop data transfer state. In addition, both protocols require a method of transferring data during the interval between the start and stop data transfer states.

A unique bit-pair coding scheme is used to accomplish the transmission of both control signals and data on a single wire. The coded bit pairs are transmitted between the SBM and the ASP during the selection and confirmation protocols in synchronism with the backplane TCK signal. Two TCKs are required to transmit each coded bit pair. The Fig. 8-11 show the bit pair encodings of the invention for: (8) an idle bit pair, (9) a select bit pair, (10) a logic 1 bit pair, and (11) a logic 0 bit pair, respectively.

In Fig. 8 is a coded control signal, designated idle (I), identified by the transmission of two consecutive logical 1 bits from a transmitter to a receiver. During the selection protocol, the SBM (transmitter) outputs the idle bit pair at its TDO output to the PTDI inputs of the ASPs (receiver). During the confirmation protocol, the selected ASP (transmitter) outputs the idle bit pair at its PTDO output to the TDI input of the SBM (receiver). In the timing diagram of Fig. 8, it is clear that idle bit pairs are output by the transmitter with the falling edge of TCK and are input to the receiver with the rising edge of TCK.

In Fig. 9 is a coded control signal, designated with selection (S), identified by the transmission of two successive logical 0 bits from a transmitter to a receiver. During the selection protocol, the SBM (transmitter) outputs the selection bit pair at its TDO output to the PTDI inputs of the ASPs (receiver). During the confirmation protocol, the selected ASP (transmitter) outputs the selection bit pair at its PTDO output to the TDI input of the SBM (receiver). In the timing diagram of FIG. 9, it is clear that selection bit pairs are output by the transmitter with the falling edge of TCK and are input to the receiver with the rising edge of TCK.

In Fig. 10 is a coded control signal, designated data (D), identified by the transmission of a logic 0 bit followed by a logic 1 bit from a transmitter to a receiver. During the selection protocol, the SBM (transmitter) outputs the logical 1 data bit pair at its TDO output to the PTDI inputs of the ASPs (receiver). During the confirmation protocol, the selected ASP (transmitter) outputs the logical 1 data bit pair at its PTDO output to the TDI input of the SBM (receiver). In the timing diagram of Fig. 10, it is clear that logic 1 data bit pairs are output by the transmitter with the falling edge of TCK and are input to the receiver with the rising edge of TCK.

In Fig. 11 is a coded control signal, designated data (D), identified by the transmission of a logic 1 bit followed by a logic 0 bit from a transmitter to a receiver. During the selection protocol, the SBM (transmitter) outputs the logical 0 data bit pair at its TDO output to the PTDI inputs of the ASPs (receiver). During the confirmation protocol, the selected ASP (transmitter) outputs the logical 0 data bit pair at its PTDO output to the TDI input of the SBM (receiver). In the timing diagram of FIG. 11, it is clear that logic 0 data bit pairs are output by the transmitter with the falling edge of TCK and are input to the receiver with the rising edge of TCK.

It should be noted that the definitions of a logic 1 data bit pair are represented by a 0-1 bit sequence and a logic 0 data bit pair is represented by a 1-0 bit sequence, which can be reversed without to deviate from the property of the invention. It should also be noted that the timing property with the rising edge and the falling edge of the bit pairs can be redefined in an application if necessary without departing from the property of the invention.

The definitions of the idle bit pair represented by two consecutive ones and the select bit pair represented by two consecutive zeros can be interchanged without departing from the scope of the invention. In the 1149.1 serial bus application of the invention, however, the definitions of the idle and select bit pairs as shown in Figures 1 and 2 are very important. When the 1149.1 serial bus is in the RESET or IDLE state, the TDO output of the SBM and slave devices is locked to a logic high level. While the 1149.1 serial bus is in the RESET or IDLE states, the protocol of the invention can be output on the bus. Since both the selection and confirmation protocols begin and end with the output of IDLE bit pairs, it makes sense that the idle bit pairs have the same logic level in which the blocked TDO outputs are located, e.g. B. a logic high. The definition shown for the idle bit pair, two consecutive logical ones, thus enables a clean transition between the 1149.1 protocol and the protocol of the invention. An unintentional change to the ASP protocol of the invention is also avoided by using this definition of the idle bit pair.

An example of the ASP selection and confirmation protocols is shown in the diagram of FIG. In the diagram, the sequence that is framed between the first and second idle (I) bit pair signals followed by the indication "TDO to PTDI" is the selection protocol that goes from the TDM output of the SBM to the PTDI inputs of the ASPs is issued. The sequence framed between the first and second idle bit pair signals (I) followed by the indication "PTDO to TDI" is the confirmation protocol that is output from the PTDO output of the selected ASP to the TDI input of the SBM , The selection protocol always precedes the confirmation protocol, as shown in the diagram.

Within the selection and confirmation protocols, the first and second selection bit pair signals (S) frame a sequence of data (D) bit pair symbols. The sequence of "2's" following the TCK display represents the number of test clocks required for each bit pair signal that is transmitted during the respective protocol. For the sake of clarity, a timeline reference is shown to indicate the chronological order in which the bit pair signals are transmitted. As in Fig. 12 As shown, the ASP protocol can be executed during the periods during which the 1149.1 serial bus is idle in the RESET or IDLE states to select a board for serial access.

The "T" signals in the protocol sequences in FIG. 12 show three-state conditions at the TDO output from the SBM and at the PTDO output of the ASP. The tri-state conditions are set up on the TDO and PTDO outputs whenever the 1149.1 serial bus is idle in the RESET or IDLE states. When a T signal is shown in the protocol sequence, the logic level on the wiring channel is a logical 1 due to the pull-up resistance at the TDI and PTDI inputs connected to the PTDO and TDO outputs.

The ASP protocol of the invention takes advantage of this 1149.1 pull-up requirement by defining the idle bit pair as two logical ones so that when the protocol of the invention is idle, ie when no selection or confirmation protocols are transmitted , the logic level that it outputs on the bus cannot be distinguished from the T-signal logic level. Thus, the idle bit pair encoding is required to make the invention transparent to the normal operation of the 1149.1 serial bus. In an alternative serial bus, in which the inactive state of the bus drives the data wiring channels to a logic low level, it would be necessary to encode the idle bit pair as two logic zeros and to encode the selection bit pairs as two logic ones that the invention works transparently with this serial bus protocol.

The I signals in the protocol sequences show the transmission of an idle bit pair (two logical ones). The I signals are transmitted at the beginning and end of both the selection and confirmation protocols to frame the protocols. The I signal transmission at the beginning of the selection and confirmation protocols cannot be distinguished from the existing logic state of the wiring channel, since the T signals indicate that the wiring signal has been pulled to a logic high level. However, the I-signal transmission at the end of the selection and confirmation protocols can be distinguished from the other preceding selection and data bit pairs (S and D), since the I-signal is the only bit pair that can be identified by a 2-bit Sequence of logical ones is defined.

The S signals in the protocol sequences indicate the transmission of a selection bit pair (two logical zeros). The S signals are transmitted at the beginning and end of a sequence of data bit pair (D) transfers to frame the data transfer operation. It is possible to frame the data bit pair transmission since the S signals can be distinguished from the I and D signals at the beginning and at the end of the data transmission, since the S signals are the only bit pair that are Bit sequence of logical zeros is defined.

The D signals in the protocol sequences indicate the transmission of a data bit pair. A logical 0 data bit pair is a logical 1 bit followed by a logical 0 bit. A logical 1 data bit pair is a logical 0 bit followed by a logical 1 bit. The D signals are transmitted after the S signal has been transmitted and continue until the second S signal is transmitted. The logic 0-D signal can be differentiated from the I, S and logic 1-D signals. The logical 1-D signal can be differentiated from the I, S and logical 0-D signals. A series of D-signal transmissions between the first and second S-signals in the selection and confirmation protocols will hereinafter be referred to as an address or an "A" signal. The number of D signals that are transmitted within an address frame can be chosen so that it is either a fixed or a variable number. If a fixed address framing is selected, all addresses framed between the first and second S signals receive the same number of D signals. If a variable address framing is selected, the number of D signals transmitted within an address is determined by the occurrence of the first and second S signals. The advantage of fixed address framing over variable address framing is that address lengths can be predicted during fixed framing, which allows short or long addresses to be detected as errors, which improves the fault tolerance of the selection and confirmation protocols of the invention.

Figure 13 shows an example of selection and confirmation protocol signals (I, p. A) as they are transmitted between an SBM and a board resident ASP to enable scan access to board ICs BD1 via the 1149.1 serial bus. In FIG. 13, the SBM is connected to only one board, but in reality several boards are connected to the SBM, as shown in FIG. 6.

The SBM has a transmitter circuit XMT for outputting the selection protocol to the ASP from the TDO to the PTDI, a receiver circuit RCR for receiving the confirmation protocol from the ASP from the PTDO to the TDI and a master control circuit MCC for regulating the operation of the transmitter and receiver circuits. When the SBM's transmitter circuitry is not used to output the selection protocol, it can be used to output serial data to the selected board via the ASP during the 1149.1 scan operations. Similarly, when the SBM is not used to receive the acknowledgment protocol, the receiver circuitry can be used to receive serial data from the selected board via the ASP during the 1149.1 scan operations. The SBM's transmitter and receiver circuits are controlled by the master control circuit to either send and receive the 1149.1 serial bus protocol or the protocol of the invention.

The ASP has a receiver circuit RCR for receiving the selection protocol from the SBM, a transmitter circuit XMT for outputting the confirmation protocol to the SBM and a slave control circuit SCC for regulating the operation of the transmitter and receiver circuits. The receiver, transmitter and slave control circuits are part of the control logic section of the ASP block diagram of FIG. 7. When the ASP's receiver and transmitter circuits are not used to exchange the selection and confirmation protocols, and when the ASP is selected, the receiver and transmitter circuits can allow serial data through the ASP from PTDI to STDO and from STD1 to PTDO can flow during the 1149.1 scan operations. Furthermore, when the ASP is selected, the TCK and TMS outputs from the SBM pass through the ASP through the PTCK to STCK and PTMS to STMS signal paths to control the board ICs during the 1149.1 scan operations ,

When scan access to the BD1 board is required, the SBM master control circuitry causes the transmitter to output the ISASI selection protocol signal sequence to the ASP receiver while the 1149.1 bus is idle. The "A" signal framed between the first and second S signals is a series of D signals corresponding to the address of the circuit board 1. At the end of the selection protocol transmission from the SBM, the slave control circuit of the ASP checks the address entered in the receiver circuit to determine whether it matches the board address. If a match occurs, the ASP's slave control circuit enables the ASP's transmitter circuitry to output the ISASI acknowledge protocol signal sequence to the SBM's receiver, and then electronically connects the backplane and board level serial bus signals. At the end of the ASP confirmation protocol transmission, the SBM master control circuit checks the address entered into the receiver circuit to determine if the expected board address has been returned. When the expected address has been returned, the SBM master control circuit enables the transmitter and receiver circuits to perform 1149.1 scan operations and serially access board 1 ICs. During the scan operation, the SBM outputs serial data and control signals through the ASP, from its TDO and TMS outputs, and receives serial data from the board through the ASP at its TDI input. The TCK output of the SBM runs free, so that it always delivers a clock which is entered into the ASP and the board.

A state diagram of the operation of the SBM and ASP transmitter circuits is shown in FIG. 14. The SBM transmitter circuit is a master transmitter, while the ASP transmitter is a slave transmitter. The SBM uses its transmitter circuit to transmit the selection protocol sequence, while the ASP uses its transmitter circuit to transmit the confirmation protocol sequence. The SBM issues a signal to its transmitter whenever it is necessary to send a selection protocol, but the ASP can only issue the confirmation protocol to its transmitter in response to a selection protocol transmission from the SBM. Because the selection and confirmation protocol sequences are identical, a common transmitter circuit design can be used in both the SBM and ASP devices, which simplifies the implementation of the circuit of the invention.

In the state diagram, the transmitter circuit is placed in the transmitter locked state while the 1149.1 bus is active. This condition ensures that the transmitter cannot be inadvertently released while the 1149.1 bus is operating to issue selection or confirmation logs. When the 1149.1 bus is idle, the transmitter circuit goes into the transmitter idle state. If it is not necessary to issue a selection or confirmation protocol, the transmitter circuit remains in the transmitter idle state until the 1149.1 bus becomes active again, in which case the transmitter circuit returns to the transmitter locked state.

If it is necessary to issue a selection or confirmation log while the transmitter circuit is in the transmitter idle state, the transmitter circuit goes into the transmit idle signal state to output the first I signal, then goes into the transmit select signal. State to output the first S signal then goes to the send address state to output a series of D signals indicating the address, then goes into the transmit select signal state to output the second S signal, then goes into the transmit idle signal state to output the second I signal, and finally returns to the transmitter idle state. After the protocol has been sent, the transmitter will return to the transmitter locked state whenever the 1149.1 bus becomes active.

A state diagram of the operation of the SBM and ASP receiver circuits is shown in FIG. The ASP uses its receiver circuit to receive the selection protocol sequence, while the SBM uses its receiver circuit to receive the confirmation protocol sequence. Since the received selection and confirmation protocol sequences are identical, a common receiver circuit design can be used in both SBM and ASP devices, which simplifies the implementation of the invention.

In the state diagram, the receiver circuit is placed in the receiver locked state when the 1149.1 bus is active. This state ensures that the receiver cannot be unintentionally released while the 1149.1 bus is operating to receive an incorrect input state. When the 1149.1 bus is idle, the receiver circuit changes to the receiver idle state. When the 1149.1 bus becomes active again, the receiver circuit returns to the receiver locked state. During the receiver idle state, the receiver circuit waits for an I or S signal to occur. In response to an I signal, the receiver remains in the receiver idle state. In response to an S signal, the receiver signals the occurrence of a first S signal to the associated master or slave control circuits MCC or SCC and changes to the start address input state in order to start the address input operation.

When a change to the start address input state takes place, the receiver circuit waits for the appearance of an I, S or D signal. In response to the input of an I or S signal, the receiver circuit goes from the start address input state back to the receiver idle state and signals the master or slave control circuit that an incorrect first S signal has been received. This transition path provides: (1) a method of returning the receiver circuit to the receiver idle state in the event that the receiver has changed to the start address input state in response to an incorrect input, and (2) a method of signaling to the associated master or slave control circuit that a selection or confirmation protocol has not currently been started and for resetting and waiting for the next occurrence of a first S signal display. In response to a D signal input, the receiver circuit goes from the start address input state to the address input state and begins receiving the transmitted address. The receiver remains in the address input state and continues to receive the address while D signals are input. In response to an S signal, the receiver circuit stops entering the address, signals the occurrence of a second S signal of the associated master or slave control circuit and changes from the address input state to the stop address input state. When the receiver of the ASP changes to the stop address input state, the slave control circuit compares the address input to the ASP with the board address to determine if the board has been selected. The ASP receiver transitions from the stop address input state to the receiver idle state in response to an I signal input from the SBM. If the entered address matches the board address, the slave control circuit of the ASP instructs the transmitter circuit of the ASP to send an acknowledgment protocol to the receiver of the SBM and then connects the serial backplane bus to the serial board bus.

When the receiver of the SBM goes into the stop address input state, the master control circuit compares the address entered into the SBM with the expected board address to determine whether the correct board has been selected. The SBM receiver transitions from the stop address input state to the receiver idle state in response to an I signal input from the ASP. If the entered address matches the expected board address, the SBM's master control circuit can serially access the board using the 1149.1 serial bus protocol. If the address entered does not match the expected board address, the SBM's master control circuitry does not attempt to access the board serially and reports the error.

16, a state diagram of the operation of the SBM master control circuit is shown. The master control circuit regulates the operation of the transmitter and receiver circuits of the SBM. The master control circuitry can enable the SBM's transmitter and receiver circuits to communicate with the ASPs using either the 1149.1 serial bus protocol or the selection and confirmation protocols of the invention. Initially, the master control circuit communicates with the ASPs using the selection and confirmation protocols of the invention to select a serial access board. After a board is selected, the master control circuit serially accesses the board using the 1149.1 serial bus protocol.

The state diagram of Fig. 16 shows that when no board is being accessed, the master control circuit is in the master control circuit idle state. If access is required to a board whose ASP has been previously selected, the master control circuit can transition from the master control circuit idle state to the scan board state and access the board serially using the 1149.1 protocol. However, if the board's ASP has not been previously selected or if a new board is to be accessed, the master control circuit must select the board's ASP before going into the scan board state. To select the ASP of a board, the master control circuit goes from the master control circuit idle state to the transmit selection protocol state. In the transmit selection protocol state, the master control circuit loads the transmitter circuit of the SBM with the address of the board to be selected and then enables the transmitter circuit to transmit a selection protocol sequence for selecting the ASP of the board.

After the transmitter circuit has been enabled to transmit the selection protocol, the master control circuit changes from the transmission selection protocol state to the reception confirmation protocol state. In the receive acknowledgment protocol state, the master control circuit enables the receiver circuit of the SBM to receive the confirmation protocol from the selected ASP. After the confirmation protocol is received, the master control circuit changes from the receive confirmation protocol state to the expected address received? State to check whether the address of the selected ASP has been received. If an incorrect address is received, the master control circuit aborts the board select operation and transitions from the expected address received? State to the message address error state. In the report address error state, the master control circuit reports the address error and sets the transmitter and receiver circuits of the SBM to their idle states.

When the correct address has been received, the master control circuit can either transition from the expected address receive? State to the master control circuit idle state and access the selected board at a later time, or transition to the board scan state to use immediately of the 1149.1 serial bus protocol to access the board. In any event, when the master control circuit goes into the board scan state, it configures the SBM's transmitter and receiver circuits so that they can be used to communicate with the board using the 1149.1 serial bus protocol. After the board has been serially accessed in the board scan state, the master control circuit transitions from the board scan state to the master control circuit idle state, where it locks and holds the SBM's transmitter and receiver circuits until it is necessary to access the same or another board in series ,

17, a state diagram of the operation of the slave control circuit of the ASP is shown. The slave control circuit regulates the operation of the transmitter and receiver circuits of the ASP. The slave control circuit enables the transmitter and receiver circuits of the ASP to communicate with the SBM using the selection and confirmation protocols of the invention. After the ASP is selected by the SBM, the slave control circuit enables the transmitter and receiver circuits to pass on the serial data that is input and output via the ASP during the 1149.1 scan operations.

The state diagram shows that if no selection protocols are sent from the SBM to the ASP, the slave control circuit is in the slave control circuit idle state. When the start of a selection protocol is received by the receiver circuit of the ASP, the slave control circuit changes from the slave control circuit idle state to the receive selection protocol state. After the selection protocol is received, the slave control circuit goes from the receive selection protocol state to the address match? State. In the address-fits? State, the slave control circuit reads the address received by the receiver circuit of the ASP and compares the address with the board address. If the address does not match the ASP's board address, the slave control circuit goes from the address match? State to the disconnect bus state to separate any previously established board to backplane bus signals within the ASP. From the disconnect bus state, the slave control circuit goes into the slave control circuit idle state, and waits for another selection protocol sequence to start.

If the address matches the board address of the ASP, does the slave control circuit go from the address match? -State over in the send confirmation protocol state. In the transmit select protocol state, the slave control circuit loads the board address into the transmitter circuit of the ASP and then enables the transmitter circuit of the ASP to send the confirmation protocol sequence to the receiver circuit of the SBM to confirm that the ASP is selected and the board-to- Backplane connections are set up. After the acknowledgment protocol is sent, the slave control circuit blocks the transmitter of the ASP and transitions from the transmit acknowledgment protocol state to the connect bus state. In the connect bus state, the slave control circuit outputs a control signal to connect the board and backplane bus signals within the ASP, allowing the SBM to serially access the board ICs using the 1149.1 serial bus protocol. After the buses have been connected, the slave control circuit changes from the connect bus state to the slave control circuit idle state to wait for another selection protocol entered by the SBM to start.

18 shows a possible circuit implementation of hardware of the addressable shadow connection.

The receiver circuit RCR comprises a control device for regulating the log input from the SBM and a serial input / parallel output SIPO register for receiving the serial address from the SBM and for outputting the address in parallel to the slave control circuit. The PTDI signal is input to the SIPO register to provide the serial address during the selection protocols and is input to the controller to control the operation of the receiver during the selection protocols. The parallel address output by the SIPO register is input to the slave control circuit via the address input in order to indicate when a selection protocol has started, when the address is ready for reading and when the selection protocol has ended.

The RCR controller of the receiver determines when a first "I then S then D" signal sequence occurs at the PTDI that indicates the start of the selection protocol and the beginning of the address entry. In response to this input, the controller enables SIPO to receive the serial address entered at the PTDI. The RCR controller next determines when a first "D then S then I" sequence occurs on the PTDI signal which indicates the end of the address entry and selection protocol. In response to this input sequence, the RCR controller sends the status to the slave controller to enable the address in the SIPO register so that it is input to the slave control circuit in parallel via the AI ​​bus, and ends the selection protocol input operation.

The transmitter circuit XMT comprises a control device for regulating the confirmation protocol output from the ASP and a parallel input / serial output or PISO register for receiving the parallel ASP address from the slave control circuit and for outputting the serial address to the PSBM. The PISO register receives the parallel data from the slave control circuit via the address output bus AO and outputs the address serially to the multiplexer MX1 ​​via the confirmation protocol output signal APO. The XMT control device receives the control signal input from the slave control device via the control bus and outputs a status to the slave control circuit via the status bus. The control signal input on the XMT control bus regulates the parallel-to-serial conversion process that takes place during the confirmation protocol. The status output by the transmitter XMT informs the slave control circuit of the status of the transmitter during the confirmation protocol, ie whether the confirmation protocol is in progress or completed.

At the start of an acknowledgment protocol, the slave control circuit releases the multiplexer MX1 ​​and the three-state buffer 3SB in order to forward the APO signal from the transmitter to the PTDO output. The slave control circuit then enters the ASP address via the AO bus in the transmitter XMT, whereupon it is pushed out to PTDO. In response to the address input, the transmitter XMT outputs an I and an S signal at the PTDO output to start the confirmation protocol, whereupon it sends the address serially to the PTDO. After the address is pushed out, the transmitter circuit XMT outputs an S and I signal sequence to stop the confirmation protocol.

The slave control circuit is a controller that controls the operation of the ASP transmitter circuit, the receiver circuit RCR and the multiplexers MX1 and MX2 in response to a matching address input during a selection protocol. The slave control circuit receives the signals PTMS and PTCK from the primary connection of the ASP, the address input AI and the status buses from the receiver RCR, the status bus from the transmitter XMT, the external ASP board address signals, a reset signal from the power-on reset circuit PRST and the reset address signals from the reset address circuit. The slave control circuit outputs a control signal to the receiver circuit RCR, the transmitter circuit XMT, the three-state buffers 3SB and the multiplexers MX1 and MX2.

The slave control circuit is clocked with the PTCK input from the primary connection. The PTMS input from the primary port indicates to the slave control circuit when the 1149.1 bus is busy, idle, or reset. The status entered by the receiver and transmitter circuits informs the slave control circuit of the status of the receiver and transmitter circuits. The AI ​​bus from the receiver is used to enter the address received during a selection protocol into the slave control circuit. The reset input from the PRST circuit resets the slave control circuit upon power up. The reset address input from the RSTA circuit allows the slave control circuit to be reset via a reset address entered via a select protocol operation.

The control signal output from the slave control circuit controls the operation of the receiver, the transmitter, and the MX1 and MX2. The AO bus output from the slave control circuit is used to enter the parallel address of the ASP into the transmitter during the confirmation protocol.

During the selection protocols, the slave control circuit receives the parallel address entered by the RCR receiver over the AI ​​bus. The status bus entered by the receiver informs the slave control circuit when a selection protocol has been started, when the address entry has been completed and when the selection protocol has ended. Based on the address input AI, the slave control circuit determines whether a match has occurred and whether it has been selected. If the received address matches the board address, the ASP responds by issuing an acknowledgment protocol, after which it connects the primary and secondary ports of the ASP.

During the acknowledgment protocols, the slave control circuit issues a control signal to the transmitter XMT to start an acknowledgment protocol and also to enter the ASP address over the AO bus into the transmitter XMT for output during the acknowledgment protocol. The status bus input from the XMT transmitter informs the slave control device when the confirmation protocol begins and ends. After the confirmation protocol is completed, the slave control circuit outputs a control signal to enable the STDO and PTDO tri-state buffers 3SB and connects PTMS to STMS via the multiplexer MX2 and STD1 to PTDO via the multiplexer MX1.

The multiplexer MX1 ​​receives the selection control signal, which is input from the slave control circuit, and the APO signal from the transmitter XMT and the STD1 signal from the secondary connection of the ASP. MX1 outputs the selected input (STD1 or APO) to the PTDO output signal via the 3-state output buffer 3SB. The output buffer 3SB is released or blocked (set in a high-resistance state) by means of a control signal which is input from the slave control circuit.

The multiplexer MX2 also receives the selection control signal from the slave control circuit, the PTMS signal from the primary connection and the input of a logical 0 and 1. In response to the control signal input, the MX2 sends the selected data input PTMS, logic 0 or logic 1, to the STMS - output signal off.

When power is initially applied to the ASP hardware, the slave control circuit is reset by input of the power-on reset circuit PRST, thereby deselecting the ASP from the backplane. When reset, the slave control circuit issues a control signal to: reset the transmitter and receiver circuits to their idle states, lock the STDO outputs through their 3SB tri-state buffers, to cause the STMS signal from the multiplexer MX2 output a logical 1 and cause the STCK signal to output the PTCK clock. The logic 1 output on the STMS signal and the free running clock on the STCK ensure that the serial board level bus is blocked and the TAPs of the ICs on the board go into their RESET state, as shown in FIG. 2. Although an internal power-on reset circuit PRST is shown, the reset can also be accomplished by other means such as e.g. B. inputting a reset signal into the slave control circuit using an external reset input signal.

The ASP can also be reset by entering a selection protocol with an address that matches the reset address RSTA, as shown in FIG. The reset address is a fixed address that is input to the slave control circuit and is compared to the address input by the receiver circuit after a selection protocol is received. If the address entered matches the reset address, the ASP is reset to the same state as that described for the power-on reset. The fixed reset address is the same for all ASPs, so that a global reset of all ASPs can be achieved by sending a single selection protocol that contains the reset address. Since the reset address is used to reset the ASP, it must be unique and must not be used again as the board address. A preferred value for the ASP reset address is 0, since board address numbering usually begins with address 1 and extends to address N, as shown in FIG. 6. If the SBM of Fig. 6 If a selection protocol is entered that contains the reset address 0, the ASPs respond by resetting themselves and deselecting from the serial backplane bus. Furthermore, no confirmation log is sent from the ASPs to the SBM when a reset address is entered via a selection log. Elimination of the acknowledgment protocol is required to avoid the logic state collision that would occur between the PTDO outputs of the multiple ASPs during an acknowledgment protocol transmission.

When the SBM puts the 1149.1 serial backplane bus in the RESET state (as shown in FIG. 2), the PTMS signal is in a logic 1 state while the PTCK signal is active and the PTDI and PDTO Signals are locked to a logic high level (T state of FIG. 12). If the SBM enters a selection protocol into the ASP during the RESET state and the address matches the ASP's board address, the ASP is selected and replies to the SBM with a confirmation protocol. During the confirmation protocol, the slave control circuit releases the PTDO tri-state buffer 3SB and selects the confirmation protocol output APO as a data output using the multiplexer MX1, so that the transmitter circuit XMT can output the confirmation protocol.

After sending the confirmation protocol, the slave control circuit connects the serial board and backplane buses together. During the connection process, the STDO tri-state buffer 3SB is released to output the PTDI backplane signal, and the multiplexer MX1 ​​is switched from outputting the APO input to the PTDO to output the STD1 board signal input to the PTDO, with the PTDO tri-state buffer 3SB remains enabled and the multiplexer MX2 is switched from outputting the logical 1 or 0 entered at the STMS to output the entered PTMS backplane signal. The following three scenarios describe what happens at the STMS output when an ASP that has previously (1) reset, (2) deselected and left in the RESET state, or (3) deselected and left in the IDLE state has been selected while the backplane 1149.1 bus is in the RESET state.

(1) If the ASP is selected (while the backplane bus is in the RESET state) after it has been reset, the multiplexer MX2 switches from outputting the logical 1 input at the STMS to outputting the PTMS backlight signal present at the STMS. Since the PTMS signal is a logic 1 when the backplane bus is in the RESET state, the STMS output signal remains at a logic 1 during the connection process.

(2) If the ASP is selected (while the backplane bus is in the RESET state after being previously unselected while the backplane bus is in the RESET state (PTMS is a logic 1 level in the RESET state), the multiplexer MX2 switches from outputting the previous PTMS state (logical 1 input) on the STMS to outputting the present PTMS backplane signal on the STMS. Since the PTMS signal is a logic 1 when the backplane bus is in the RESET state, the STMS signal output remains at a logic 1 during the connection process.

(3) If the ASP is selected (while the backplane bus is in the RESET state) after it has been previously unselected while the backplane bus was in the IDLE state (PTMS is a logic 0 level in the IDLE state), Multiplexer MX2 switches from outputting the previous PTMS state (logical 0 input) on the STMS to outputting the pending PTMS backplane signal on the STMS. Since the PTMS is a logic 1 when the backplane is in the RESET state, the STMS output changes from outputting a logic 0 to outputting a logic 1 during the connection process.

When the SBM puts the 1149.1 serial backplane bus in a RESET state (Fig. 2), the PTMS signal is in a logic 1 state, while the PTCK signal is active and the PTDI and PTDO signals are in a logic state High level state are locked (T state of Fig. 12). If the SBM enters a selection protocol during the RESET state in order to select a new ASP, the currently selected ASP is deselected and separated from the backplane bus by a control signal which is output by the slave control circuit of the ASP. During the disconnection process, the STDO and PTDO outputs are locked to a logic 1 state via their 3-state buffers 3SB, the multiplexer MX1 ​​continues to select the STD1 signal and inputs it into the input of the PTDO 3SB, while the multiplexer M2 switches from outputting a logic high level from the PTMS backplane signal (PTMS is at a high level when the backplane bus is in the RESET state) on the STMS to output the logic 1 that is input at the STMS. By forcing the MX2 to select and output the logical 1 entered at the STMS output, the serial board level 1149.1 bus remains in the RESET state after the ASP is unselected. The invention thus allows the ASP to keep the serial board level 1149.1 bus in the RESET state after it has been deselected.

When the SBM places the 1149.1 serial backplane bus in the IDLE state (FIG. 2), the PTMS signal is in a logic 0 state, while the PTCK signal is active and the PTDI and PTDO signals are in a logic state High level state are locked (T state of Fig. 12). If the SBM enters a selection protocol into the ASP during the IDLE state and the address matches the board address of the ASP, the ASP is selected and replies to the SBM with a confirmation protocol. During the acknowledge protocol, the slave control circuit enables the 3DB PTDO tri-state buffer and selects the acknowledge protocol output signal APO for the multiplexer MX1 ​​so that the transmitter circuit can issue the acknowledge protocol.

After sending the confirmation protocol, the slave control circuit connects the serial board and backplane buses together. During the connection process, the STDO tri-state buffer 3SB is released to output the PTDI backplane signal, while the multiplexer MX1 ​​is switched from outputting the APO input at the PTDO to outputting the STD1 board signal input at the PTDO, and wherein the PTDO tri-state buffer 3SB remains released and the multiplexer MX2 is switched from outputting the logical 1 or 0 entered on the STMS signal to outputting the PTMS backplane signal entered on the STMS signal. The following three scenarios describe what happens at the STMS output when an ASPI that was previously: (1) reset, (2) deselected and then set to the RESET state, or (3) deselected and left in the IDLE state , is selected while the backplane 1149.1 bus is in the IDLE state.

(1) If the ASP is selected (while the backplane bus is in the IDLE state) after it has been reset, the multiplexer MX2 switches from outputting the logical 1 input at the STMS to outputting the PTMS backplane signal present at the STMS. Since the PTMS signal is a logic 0 when the backplane bus is in the IDLE state, the STMS output changes from outputting a logic 1 to outputting a logic 0 during the connection process.

(2) If the ASP is selected (while the backplane bus is in the IDLE state) after it has been previously unselected while the backplane bus was in the RESET state (PTMS is a logic 1 level in the RESET state) , the multiplexer MX2 switches from outputting the previous PTMS state (logic 1 input) on the STMS to outputting the existing PTMS backplane signal on the STMS. Since the PTMS signal is a logic 0 when the backplane bus is in the IDLE state, the STMS output changes from outputting a logic 1 to outputting a logic 0 during the connection process.

(3) If the ASP is selected (while the backplane bus is in the IDLE state) after it has been previously unselected while the backplane bus is in the IDLE state (PTMS is a logic 0 level in the IDLE state), the multiplexer MX2 switches from outputting the previous PTMS state (logic 0 input) on the STMS to outputting the pending PTMS backplane signal on the STMS. Since the PTMS is a logic 0 when the backplane is in the IDLE state, the STMS output remains at a logic 0 during the connection process.

When the SBM places the 1149.1 serial backplane bus in the IDLE state (Fig. 2), the PTMS signal is in a logic 0 state, while the PTCK signal is active and the signals PTDI and PTDO are in a logic state High level state are locked (T state of Fig. 12). If the SBM enters a selection protocol during the IDLE state in order to select a new ASP, the currently selected ASP is deselected and separated from the backplane bus by a control signal which is output by the slave control circuit of the ASP. During the disconnection process, the STDO and PTDO outputs are locked to a logic 1 state via their 3-state buffers 3SB, while the MUX continues to select the STD1 signal and inputs it into the input of the PTDO 3SB, while the multiplexer M2 stops outputting a logic low level from the PTMS backplane signal (PTMS is low when the backplane bus is in the IDLE state) on the STMS to output the logic 0 that is entered on the STMS. By forcing the MX2 to select and output the logical 0s input at the STMS output, the serial board level 1149.1 bus remains in the IDLE state after the ASP is unselected. The invention thus allows the ASP to keep the serial board level 1149.1 bus in the IDLE state after it has been unselected.

Although this application has described the ASP protocol with respect to the 1149.1 standard bus, the ASP protocol described here can be used with any other serial bus and protocol, as will be appreciated by those skilled in the art. The invention can be used with other pre-existing or newly defined serial buses to provide a method for serially connecting a slave device (IC, board, etc.) to an SBM. For example, a typical serial bus includes the following types of signals. A control signal (like TMS) that regulates the normal operation of the serial bus. A clock signal (such as TCK) that times the flow of serial data through the devices on the serial bus. A serial data input signal (such as TDI) for inputting data into a slave device. A serial data output signal (such as TDO) for outputting data from a slave device. Since the normal operation of the serial bus is regulated by a control signal (such as TMS), this avoids that developed for the ASP. Log the use of this signal to select or deselect the slave devices. By designing the ASP protocol to be independent of a particular serial bus control signal, inserting the invention into existing serial buses does not require modifying the normal operating mode of the serial bus.

The ASP circuit can exist as a packaged IC for insertion on a printed circuit board, as an unpackaged component for insertion on a multi-chip module substrate, as a subcircuit within an integrated circuit, or as an embedded circuit in a multi chip module semiconductor substrate. Other alternative implementations are possible and are considered to be within the scope of this application and its claims.

Although the description of the invention here illustrates the ASP circuit as a board-mounted device that can be operated to selectively convert 1149.1 serial backplane bus signals to 1149.1 serial board serial signals, the ASP Circuitry at any level of the electronic device can be used to provide a serial addressable interface between an SBM and the slave devices on a serial bus. For example, in Fig. 6 the ASP circuit can be considered as a circuit that creates an interface between the SBM and: (1) a plurality of subcircuits (1-n) which are connected to a common serial bus within an IC, (2) a plurality of ICs (1-n) which are connected to a common serial bus on a multi-chip module, (3) a plurality of ICs (1-n) connected to a common serial bus on a board, (4) a plurality of boards (1-n) connected to a common serial bus on a backplane, (S) a plurality rear walls, which are connected to a common serial bus in a subsystem, (6) a plurality of subsystems (1-n) which are connected to a common serial bus in a system, or (7) a plurality of systems (1-n) which are connected to a common serial bus network are connected. These and other applications are also considered to be within the scope of this application.

19 shows an alternative preferred embodiment of the invention in a circuit 13 with three separate secondary connections, each of which is connected to the primary connections by means of separately addressable ASP circuits ASP-1, ASP-2 and ASP-3. In some board designs, the 1149.1 serial bus can be divided into separate scan paths. Separate ASPs are required to select each scan path individually and to access it from the 1149.1 backplane bus via the primary connection. However, to reduce the number of ASP circuits on a board, multiple ASP circuits can be packaged in one IC, as shown in FIG. 19. Each ASP circuit ASP-1, ASP-2, ASP-3 has its own unique address (01, 10, 11) and a common connection to the primary connection, so that exactly it can be selected and released to the 1149.1 backplane bus enable access to the desired board level scan path through the corresponding secondary port (SP1-SP3 in the figure). To reduce the IC package size, the individual ASP addresses within the IC can be hard-wired, or can be programmed using fuse links, RAM, ROM, or other programmable logic in the device, thereby eliminating the need for IC package pins for the ASP Addresses is eliminated.

20 shows a custom IC or ASIC 35 that has a built-in ASP, an address input, and an internal serial test bus connected to various large application logic blocks 37, each with a separate TAP test port 39. This figure demonstrates that for high density VLSI ICs or multi-chip modules the ASP of the invention can be used to provide efficient access to these internal scan paths as well.