Semiconductor device, display device including semiconductor device, electronic device including semiconductor device, and method for manufacturing semiconductor device

The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device, and also to a display device and an electronic device each having the semiconductor device.

A technology for constructing a transistor (also called a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

For example, a technique for manufacturing a transistor using a Zn-O-based oxide or an In-Ga-Zn-O-based oxide as an oxide semiconductor has been disclosed (see Patent Documents 1 and 2).

Furthermore, there is a trend for display devices using transistors (such as liquid crystal panels and organic EL panels) to have larger screen sizes. In the case of display devices using active elements such as transistors, the increase in screen size has been accompanied by problems such as degradation of display quality, such as uneven display and poor gradation, because the voltage applied to the element varies depending on the position of the connected wiring due to wiring resistance.

Furthermore, there is a trend for display device screen resolutions to become higher, such as high definition (HD, 1366 x 768) and full high definition (FHD, 1920 x 1080), and the development of display devices for so-called 4K digital cinema, with resolutions of 3840 x 2048 or 4096 x 2180, is also being rushed.

2. Description of the Related Art As the resolution of the screen of a display device improves, the driving frequencies used in the driving circuits of the display device tend to increase, and it is desirable to use low-resistance materials with little signal delay for wiring or signal lines.

Conventionally, aluminum films have been widely used as materials for wiring or signal lines, but research and development into copper films has been actively conducted to further reduce resistance. However, copper films have drawbacks such as poor adhesion to the underlayer and the copper elements in the copper film tend to diffuse into the semiconductor layer of the transistor, deteriorating the transistor characteristics. Therefore, in order to improve adhesion to the underlayer and prevent the diffusion of copper elements, a technology has been disclosed for fabricating a transistor using a silicon nitride film, a copper alloy layer formed on the silicon nitride film, and a pure copper layer formed on the copper alloy layer. (See Patent Document 3).

<p><patcit num="1"><text>JP 2007-123861 A</text></patcit><patcit num="2"><text>JP 2007-96055 A</text></patcit><patcit num="3"><text>JP 2010-230965 A</text></patcit></p>

<p>In Patent Document 1, a silicon-based semiconductor material is assumed to be used as a semiconductor thin film applicable to a transistor. Therefore, there is a problem that a manufacturing method or a structure is not optimal for applying the oxide semiconductor film to a transistor using the oxide semiconductor film in a channel formation region.</p><p>In view of the above problems, an object of one embodiment of the present invention is to provide a method for manufacturing a transistor which has stable electrical characteristics and little signal delay caused by wiring resistance in a semiconductor device including an oxide semiconductor film, to provide a semiconductor device including the transistor, and to provide a high-performance display device including the transistor.</p>

<p>In a method for manufacturing a semiconductor device including a bottom-gate transistor in which an oxide semiconductor film is used for a channel formation region, a source electrode and a drain electrode are formed in contact with the oxide semiconductor film. The source electrode and the drain electrode are formed using first to third metal films, and a material containing a copper element is used for the second metal film.</p><p>In a method for manufacturing a source electrode and a drain electrode in contact with an oxide semiconductor film, a first metal film and a second metal film are formed, a first photolithography process is performed on the second metal film, and a part of the second metal film is removed by a first etching process. Then, a third metal film is formed on the first metal film and the second metal film, a second photolithography process is performed on the third metal film, and a part of the first metal film and the third metal film are removed by a second etching process. In addition, the second etching process removes the first metal film and the third metal film on the outside of the end of the second metal film removed by the first etching process. By using such a manufacturing method, the second metal film is covered (more preferably, wrapped) by the first metal film and the third metal film, and therefore, the material containing the copper element used for the second metal film can be suppressed from diffusing into the oxide semiconductor film. More details are as follows.</p><p>One embodiment of the present invention is a method for manufacturing a semiconductor device including a step of forming a gate electrode, a step of forming a gate insulating film over the gate electrode, a step of forming an oxide semiconductor film in contact with the gate insulating film and overlapping with the gate electrode, and a step of forming a source electrode and a drain electrode over the oxide semiconductor film. The source electrode and the drain electrode include a step of forming a first metal film and a second metal film, a step of performing a first photolithography step on the second metal film and removing a part of the second metal film by first etching, a step of forming a third metal film over the first metal film and the second metal film, and a step of performing a second photolithography step on the third metal film and removing a part of the first metal film and the third metal film by second etching, in which the second etching removes the first metal film and the third metal film outside end portions of the second metal film removed by the first etching.</p><p>The above manufacturing method may further include a step of forming a first insulating film over the source electrode and the drain electrode, a step of introducing oxygen onto the first insulating film, a step of forming a second insulating film over the first insulating film, a step of forming an aluminum film over the second insulating film, a step of introducing oxygen onto the aluminum film to form an aluminum oxide film, and a step of forming a planarizing insulating film on the aluminum oxide film.</p><p>In the above-described manufacturing methods, the first metal film and the third metal film may be metal films containing one or more elements selected from the group consisting of tungsten, tantalum, titanium, and molybdenum, or metal nitride films, and the second metal film may contain copper.</p><p>In each of the above manufacturing methods, the first etching may be performed by a wet etching method, and the second etching may be performed by a dry etching method.</p><p>Another embodiment of the present invention is a semiconductor device including a gate electrode, a gate insulating film formed over the gate electrode, an oxide semiconductor film formed in contact with the gate insulating film and overlapping with the gate electrode, and a source electrode and a drain electrode formed over the oxide semiconductor film, in which the source electrode and the drain electrode are formed using a first metal film, a second metal film, and a third metal film, and the second metal film is formed in a region inside end portions of the first metal film and the third metal film.</p><p>Another embodiment of the present invention is a semiconductor device including a gate electrode, a gate insulating film formed over the gate electrode, an oxide semiconductor film in contact with the gate insulating film and formed to overlap with the gate electrode, a source electrode and a drain electrode formed over the oxide semiconductor film, and a signal line electrically connected to the source electrode, the signal line including a first metal film, a second metal film, and a third metal film, the second metal film being formed in a region inside end portions of the first metal film and the third metal film, and the source electrode and the drain electrode including the first metal film and the third metal film.</p><p>The above-mentioned structure may further include an oxygen-excess first insulating film over the source electrode and the drain electrode, a second insulating film formed on the first insulating film, an aluminum oxide film formed on the second insulating film, and a planarizing insulating film formed on the aluminum oxide film.</p><p>In each of the above structures, the first metal film and the third metal film may be a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, or a metal nitride film, and the second metal film may contain copper.</p><p>In each of the above structures, the gate electrode preferably contains one or more elements selected from the group consisting of tungsten, tantalum, titanium, molybdenum, and copper.</p><p>Further, display devices and electronic devices having the above-described semiconductor device are also included in the scope of the present invention.</p>

<p>In a semiconductor device including an oxide semiconductor film, a method for manufacturing a transistor which has stable electrical characteristics and little signal delay caused by wiring resistance can be provided. A semiconductor device including the transistor can also be provided. Furthermore, a high-performance display device including the transistor can also be provided.</p>

<figref num="1">1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device.</figref><figref num="2">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="3">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="4">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="5">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="6">1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device.</figref><figref num="7">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="8">1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.</figref><figref num="9">FIG. 1 is a plan view illustrating one embodiment of a display device.</figref><figref num="10">FIG. 1 is a cross-sectional view showing one embodiment of a display device.</figref><figref num="11">FIG. 1 is a cross-sectional view showing one embodiment of a display device.</figref><figref num="12">1A to 1C are diagrams illustrating examples of electronic devices including a semiconductor device.</figref><figref num="13">1A and 1B are diagrams illustrating an example of a tablet terminal including a semiconductor device.</figref>

Hereinafter, the embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

It should be noted that the ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion of components and do not imply numerical limitations.

In this specification and the like, the terms "above" and "below" do not limit the positional relationship of components to "directly above" or "directly below." For example, the expression "a gate electrode on a gate insulating film" does not exclude other components between the gate insulating film and the gate electrode.

In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

In addition, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms "source" and "drain" may be used interchangeably.

In this specification, "electrically connected" includes a case where the connection is made via "something having some electrical action". Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

In this specification and the like, the patterning is performed using a photolithography process. However, the patterning is not limited to the photolithography process, and a process other than the photolithography process can be used. In addition, the mask formed in the photolithography process is removed after the etching process.

Embodiment 1 In this embodiment, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1 to 5. In this embodiment, a transistor including an oxide semiconductor film will be described as an example of a semiconductor device.

&lt;Configuration Example 1 of Semiconductor Device&gt; Fig. 1 shows a configuration example of a transistor 150. Fig. 1(A) is a plan view of the transistor 150, Fig. 1(B) is a cross-sectional view taken along X1-Y1 in Fig. 1(A), and Fig. 1(C) is a cross-sectional view taken along V1-W1 in Fig. 1(A). Note that in Fig. 1(A), some of the components of the transistor 150 (e.g., the gate insulating film 106, etc.) are omitted in order to avoid complication.

The transistor 150 shown in FIG. 1 includes a gate electrode 104 formed over a substrate 102, a gate insulating film 106 formed over the gate electrode 104, an oxide semiconductor film 108 formed in contact with the gate insulating film 106 at a position overlapping with the gate electrode 104, and a source electrode 110 and a drain electrode 112 formed over the oxide semiconductor film 108.

The gate electrode 104 is composed of a first gate electrode 104a and a second gate electrode 104b. The first gate electrode 104a is preferably a metal film or a metal nitride film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum. The second gate electrode 104b is preferably a copper film. For example, in this embodiment, a tungsten film is used as the first gate electrode 104a, and a copper film is used as the second gate electrode 104b. By forming the gate electrode 104 with such a stacked structure, the gate electrode 104 can have a low resistance. By providing the first gate electrode 104a, the adhesion between the substrate 102 and the copper film used as the second gate electrode 104b can be improved, and/or the diffusion of the copper element in the copper film used as the second gate electrode 104b can be suppressed.

The gate insulating film 106 is composed of a first gate insulating film 106a and a second gate insulating film 106b. The first gate insulating film 106a may have a function of suppressing diffusion of copper elements in a copper film used as the second gate electrode 104b, and may be a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride oxide film, or the like. The second gate insulating film 106b may have a function of supplying oxygen to an oxide semiconductor film 108 to be formed later, and may be a silicon oxide film, a silicon oxynitride film, or the like. For example, in this embodiment, a silicon nitride film is used as the first gate insulating film 106a, and a silicon oxynitride film is used as the second gate insulating film 106b. By using the gate insulating film 106 having such a stacked structure, diffusion of copper elements in a copper film used as the gate electrode 104 can be suppressed, and oxygen can be supplied to an oxide semiconductor film 108 to be formed later.

The source electrode 110 is composed of a first metal film 110a, a second metal film 110b, and a third metal film 110c, and the drain electrode 112 is composed of a first metal film 112a, a second metal film 112b, and a third metal film 112c. The second metal film 110b and the second metal film 112b are formed in regions inside the ends of the first metal film 110a, the first metal film 112a, the third metal film 110c, and the third metal film 112c.

The first metal film 110a, the first metal film 112a, the third metal film 110c, and the third metal film 112c are preferably made of a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, or a metal nitride film. The second metal film 110b and the second metal film 112b are preferably made of a copper element.

For example, in this embodiment, a tungsten film is used as the first metal film 110a and the first metal film 112a, a copper film is used as the second metal film 110b and the second metal film 112b, and a tantalum nitride film is used as the third metal film 110c and the third metal film 112c. The second metal film 110b and the second metal film 112b are formed on the first metal film 110a and the first metal film 112a, and are covered with the third metal film 110c and the third metal film 112c.

That is, the copper film used as the second metal film 110b and the second metal film 112b has a lower surface covered with a tungsten film used as the first metal film 110a and the first metal film 112a, and an upper surface and a side surface covered with a tantalum nitride film used as the third metal film 110c and the third metal film 112c. The first metal film 110a and the first metal film 112a, and the third metal film 110c and the third metal film 112c function as a barrier metal that suppresses the diffusion of copper elements in the copper film.

By configuring the source electrode 110 and the drain electrode 112 in this manner, the source electrode 110 and the drain electrode 112 can be made to have low resistance, and the diffusion of copper elements in the copper film used in the source electrode 110 and the drain electrode 112 to the outside can be suppressed.

The source electrode 110 and the drain electrode 112 are formed, for example, by forming a first metal film and a second metal film on the oxide semiconductor film 108, performing a first photolithography process on the second metal film, removing a part of the second metal film by a first etching process, and forming a second metal film 110b and a second metal film 112b. Then, a third metal film is formed on the first metal film and the second metal film (the second metal film 110b and the second metal film 112b) so as to cover the second metal film. Then, a second photolithography process is performed on the third metal film, and removing a part of the first metal film and the third metal film by a second etching process, and forming the first metal film 110a, the first metal film 112a, the third metal film 110c, and the third metal film 112c. With such a formation method, the copper film used as the second metal film is not in direct contact with the oxide semiconductor film 108; therefore, diffusion of impurities (especially copper elements) that may be mixed into a back channel portion of the oxide semiconductor film 108 can be suppressed.

In addition, a structure may be provided on the source electrode 110 and the drain electrode 112, further including an oxygen-excess first insulating film 114a, a second insulating film 114b formed on the first insulating film 114a, an aluminum oxide film 116 formed on the second insulating film 114b, and a planarizing insulating film 118 formed on the aluminum oxide film 116.

Note that details of the other components will be described later with reference to FIGS. 2 to 5 in a manufacturing method of the transistor 150 illustrated in FIGS.

&lt;Method 1 for Manufacturing a Semiconductor Device&gt; First, a gate electrode 104 including a first gate electrode 104a and a second gate electrode 104b is formed over a substrate 102 (see FIG. 2A).

There are no significant limitations on the substrate that can be used for the substrate 102, but it is necessary that the substrate has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, various glass substrates used in the electronics industry, such as barium borosilicate glass and aluminoborosilicate glass, can be used. The substrate should have a thermal expansion coefficient of 25×10^-7/°C above 50×10^-7/°C or less (preferably 30×10^-7/°C above 40×10^-7/°C or less) and a strain point of 650°C or more and 750°C or less (preferably 700°C or more and 740°C or less) is preferably used.

In addition, when using large-sized glass substrates such as the fifth generation (1000mm x 1200mm or 1300mm x 1500mm), sixth generation (1500mm x 1800mm), seventh generation (1870mm x 2200mm), eighth generation (2200mm x 2500mm), ninth generation (2400mm x 2800mm), and tenth generation (2880mm x 3130mm), fine processing may be difficult due to shrinkage of the substrate caused by heat treatment in the manufacturing process of the semiconductor device. Therefore, when using a large-sized glass substrate as described above as a substrate, it is preferable to use one with little shrinkage. For example, a large-sized glass substrate may be used as the substrate, which has a shrinkage of 20ppm or less, preferably 10ppm or less, and more preferably 5ppm or less after heat treatment at a temperature of preferably 450°C, more preferably 500°C for 1 hour.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 102. To manufacture a flexible semiconductor device, the transistor 150 including the oxide semiconductor film 108 may be directly manufactured over a flexible substrate, or the transistor 150 including the oxide semiconductor film 108 may be manufactured over another manufacturing substrate and then peeled off and transferred to the flexible substrate. Note that in order to peel off and transfer the transistor 150 from the manufacturing substrate to the flexible substrate, a peeling layer may be provided between the manufacturing substrate and the transistor 150 including the oxide semiconductor film.

A base insulating film may be provided over the substrate 102. The base insulating film can be formed by a plasma CVD method, a sputtering method, or the like using an oxide insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or gallium oxide, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material of these.

Alternatively, the substrate 102 may be subjected to a heat treatment. For example, the heat treatment may be performed at 650° C. for 1 to 5 minutes using a GRTA (Gas Rapid Thermal Anneal) device that performs heat treatment using high-temperature gas. Note that the high-temperature gas used in the GRTA is an inert gas that does not react with the object to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Alternatively, the heat treatment may be performed in an electric furnace at 500° C. for 30 minutes to 1 hour.

The gate electrode 104 can be formed using a material containing one or more elements selected from tungsten, tantalum, titanium, molybdenum, and copper. In this embodiment, a copper film having a thickness of 100 nm to 400 nm is formed as the second gate electrode 104b by sputtering. In addition, the first gate electrode 104a is formed as a lower layer of the second gate electrode 104b, functioning as a barrier metal for suppressing the diffusion of copper elements in the copper film.

In this embodiment, as the first gate electrode 104a, a tantalum nitride film having a thickness of 20 nm to 100 nm is formed by sputtering.

In this embodiment, a stacked structure of the first gate electrode 104a and the second gate electrode 104b will be described, but the present invention is not limited to this structure. For example, a third gate electrode may be further provided on the second gate electrode 104b. The third gate electrode may be made of the same material as the first gate electrode 104a.

Next, the gate insulating film 106 including a first gate insulating film 106a and a second gate insulating film 106b is formed over the substrate 102 and the gate electrode 104 (see FIG. 2B).

The first gate insulating film 106a is preferably a nitride insulating film having a thickness of 10 nm to 100 nm, more preferably 20 nm to 50 nm, formed by a plasma CVD method, a sputtering method, or the like. Examples of the nitride insulating film include a silicon nitride film and a silicon nitride oxide film. By using a nitride insulating film as the first gate insulating film 106a in contact with the substrate 102 and the gate electrode 104, it is possible to suppress the diffusion of impurities from the substrate 102 or the gate electrode 104. In particular, when a metal material containing copper is used for the gate electrode 104 (more specifically, the second gate electrode 104b), the first gate insulating film 106a can suppress the diffusion of copper into the oxide semiconductor film 108.

In this embodiment, the first gate insulating film 106a is a silicon nitride film having a thickness of 50 nm formed by plasma CVD. The deposition gas for the silicon nitride film is, for example, silane (SiH₄) and nitrogen gas mixture, or silane, nitrogen and ammonia (NH₃) mixed gas, etc. can be used.

The second gate insulating film 106b is preferably an oxide insulating film having a thickness of 100 nm to 350 nm, more preferably 100 nm to 200 nm, formed by a plasma CVD method, a sputtering method, or the like. Examples of the oxide insulating film include a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon oxynitride film, and an aluminum oxynitride film.

The second gate insulating film 106b is made of hafnium oxide, yttrium oxide, hafnium silicate (HfSi_xO_y(x&gt;0, y&gt;0)), nitrogen-doped hafnium silicate (HfSiO_xN_y(x&gt;0, y&gt;0)), hafnium aluminate (HfAl_xO_y(x&gt;0, y&gt;0)) and high-k materials such as lanthanum oxide can be used to reduce gate leakage current.

In this embodiment, a silicon oxynitride film having a thickness of 200 nm is formed as the second gate insulating film 106b by a plasma CVD method. The plasma CVD method can reduce the film formation time compared to the sputtering method. Furthermore, the plasma CVD method has smaller in-plane film thickness variations than the sputtering method, and is less susceptible to particle contamination.

Note that the second gate insulating film 106b is an insulating film in contact with the oxide semiconductor film 108, and therefore preferably contains oxygen and preferably contains as little impurities as possible, such as water and hydrogen. However, it is more difficult to reduce the hydrogen concentration in the film by the plasma CVD method than by the sputtering method. Therefore, the formed second gate insulating film 106b may be subjected to heat treatment (dehydration or dehydrogenation treatment) for reducing, more preferably removing, hydrogen atoms.

The temperature of the heat treatment is 250° C. to 650° C., preferably 450° C. to 600° C., or lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the gate insulating film 106 is heat-treated at 650° C. for 1 hour in a vacuum (reduced pressure) atmosphere.

The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus may be used. The LRTA apparatus is an apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. The high-temperature gas is an inert gas such as a rare gas such as argon or nitrogen that does not react with the workpiece during heat treatment. When a GRTA apparatus is used as the heat treatment apparatus, the substrate may be heated in an inert gas heated to a high temperature of 650°C to 700°C because the treatment time is short.

The heat treatment may be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less), or a rare gas (argon, helium, etc.), but it is preferable that the atmosphere of the nitrogen, oxygen, ultra-dry air, or rare gas does not contain water, hydrogen, etc. In addition, it is preferable that the purity of the nitrogen, oxygen, or rare gas introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

The gate insulating film 106 can be dehydrated or dehydrogenated by the heat treatment, and the gate insulating film 106 from which impurities such as hydrogen or water that cause fluctuations in transistor characteristics are removed can be formed.

The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with another heat treatment.

Next, the oxide semiconductor film 108 is formed in contact with the gate insulating film 106 and overlaps with the gate electrode 104 (see FIG. 2C).

The oxide semiconductor film 108 may have a single-layer structure or a stacked-layer structure. The oxide semiconductor film 108 may have an amorphous structure or a crystalline structure. When the oxide semiconductor film 108 has an amorphous structure, the oxide semiconductor film 108 may be subjected to heat treatment in a later manufacturing process to become a crystalline oxide semiconductor film. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor film is 250° C. or higher and 700° C. or lower, preferably 400° C. or higher, more preferably 500° C. or higher, and further preferably 550° C. or higher. Note that the heat treatment can serve as another heat treatment in the manufacturing process.

The oxide semiconductor film 108 can be formed by a sputtering method, a molecular beam epitaxy (MBE) method, a plasma CVD method, a pulsed laser deposition method, an atomic layer deposition (ALD) method, or the like as appropriate.

When the oxide semiconductor film 108 is formed, it is preferable to reduce the hydrogen concentration in the oxide semiconductor film 108 as much as possible. In order to reduce the hydrogen concentration, for example, when the film is formed by a sputtering method, a high-purity rare gas (typically, argon) from which impurities such as hydrogen, water, a hydroxyl group, or a hydride have been removed, oxygen, or a mixed gas of a rare gas and oxygen is appropriately used as an atmospheric gas supplied to a treatment chamber of a sputtering apparatus.

Furthermore, by performing the deposition by introducing a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the treatment chamber, the hydrogen concentration in the deposited oxide semiconductor film 108 can be reduced. In order to remove residual moisture in the treatment chamber, an adsorption-type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump, is preferably used.

Alternatively, a turbomolecular pump with a cold trap may be used. A cryopump is a pump that pumps, for example, hydrogen molecules, water (H₂Since the pumping capability of the cryopump is high for pumping compounds containing hydrogen atoms (preferably compounds containing carbon atoms), the concentration of impurities in the oxide semiconductor film 108 formed in a treatment chamber evacuated using a cryopump can be reduced.

In this embodiment, the oxide semiconductor film 108 is formed by a sputtering method using a metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 or a metal oxide target with an atomic ratio of In:Ga=2:1. However, the target material and composition that can be used for the oxide semiconductor film 108 are not limited to these target materials and compositions. The oxide semiconductor film 108 can be formed by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. A target having crystallinity, such as single crystal or polycrystal, is preferable as a target that can be used for the oxide semiconductor film 108. By using a crystalline target, the formed thin film also has crystallinity, and in particular, the formed thin film is likely to have crystals oriented along the c-axis.

In addition, the oxide semiconductor film 108 is preferably in a supersaturated state in which the oxygen content is higher than the stoichiometric composition immediately after the film formation. For example, when the oxide semiconductor film 108 is formed by a sputtering method, the film is preferably formed under conditions in which the proportion of oxygen in the film formation gas is high, and particularly, it is preferably formed in an oxygen atmosphere (100% oxygen gas). For example, when the oxide semiconductor film 108 is formed using an In-Ga-Zn oxide (IGZO) under conditions in which the proportion of oxygen in the film formation gas is high (particularly, an atmosphere of 100% oxygen gas), release of Zn from the film is suppressed even when the film formation temperature is 300° C. or higher.

Furthermore, when the oxide semiconductor film 108 is formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1, the composition of the target may differ from the composition of the thin film formed on the substrate. For example, when a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1 is used, the composition of the oxide semiconductor film 108, which is a thin film, may have an atomic ratio of In:Ga:Zn=1:1:0.6 to 0.8, depending on the film formation conditions. This is believed to be because Zn sublimes during the formation of the oxide semiconductor film 108, or the sputtering rates of the components In, Ga, and Zn are different.

Therefore, in order to form a thin film having a desired composition, it is necessary to adjust the composition of the metal oxide target in advance. For example, in order to set the composition of the oxide semiconductor film 108, which is a thin film, to In:Ga:Zn=1:1:1 in atomic ratio, the composition of the metal oxide target may be set to In:Ga:Zn=1:1:1.5 in atomic ratio. That is, the Zn content of the metal oxide target may be increased in advance. However, the composition of the target is not limited to the above values and may be appropriately adjusted depending on the film formation conditions and the composition of the thin film to be formed. In addition, it is preferable to increase the Zn content of the metal oxide target because the crystallinity of the obtained thin film is improved.

When the oxide semiconductor film 108 is formed by a sputtering method, the relative density of a metal oxide target used for the film formation is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target with a high relative density, the oxide semiconductor film 108 can be formed as a dense film.

Forming the oxide semiconductor film 108 while keeping the substrate 102 at high temperature is also effective in reducing the concentration of impurities that may be contained in the oxide semiconductor film 108. The temperature to which the substrate 102 is heated may be greater than or equal to 150° C. and less than or equal to 450° C., preferably greater than or equal to 170° C. and less than or equal to 350° C. By heating the substrate at a high temperature during film formation, the oxide semiconductor film 108 can be formed as a crystalline film.

The oxide semiconductor used for the oxide semiconductor film 108 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that the oxide semiconductor contains both In and Zn. Furthermore, it is preferable that the oxide semiconductor film 108 contains gallium (Ga) in addition to the above elements as a stabilizer for reducing variations in electrical characteristics of a transistor using the oxide semiconductor. Furthermore, it is preferable that the oxide semiconductor film 108 contains tin (Sn) as a stabilizer. Furthermore, it is preferable that the oxide semiconductor film 108 contains hafnium (Hf) as a stabilizer. Furthermore, it is preferable that the oxide semiconductor film 108 contains aluminum (Al) as a stabilizer. Furthermore, it is preferable that the oxide semiconductor film 108 contains zirconium (Zr) as a stabilizer.

As another stabilizer, one or more of the lanthanides lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be used.

Examples of oxide semiconductors include indium oxide, tin oxide, zinc oxide, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides (also referred to as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In In-Nd-Zn based oxides, In-Sm-Zn based oxides, In-Eu-Zn based oxides, In-Gd-Zn based oxides, In-Tb-Zn based oxides, In-Dy-Zn based oxides, In-Ho-Zn based oxides, In-Er-Zn based oxides, In-Tm-Zn based oxides, In-Yb-Zn based oxides, In-Lu-Zn based oxides, In-Sn-Ga-Zn based oxides, In-Hf-Ga-Zn based oxides, In-Al-Ga-Zn based oxides, In-Sn-Al-Zn based oxides, In-Sn-Hf-Zn based oxides, and In-Hf-Al-Zn based oxides can be used.

In this case, for example, In-Ga-Zn oxide means an oxide having In, Ga, and Zn as main components, regardless of the ratio of In, Ga, and Zn. Also, metal elements other than In, Ga, and Zn may be included.

In addition, InMO₃(ZnO)_m(m&gt;0 and m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co. In addition, as the oxide semiconductor, In₂SnO₅(ZnO)_nA material expressed as (n&gt;0, and n is an integer) may be used.

For example, an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3), In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or In:Ga:Zn=3:1:2 (=1/2:1/6:1/3), or an oxide having a similar composition, may be used. Alternatively, an In-Sn-Zn oxide having an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide having a similar composition, may be used.

However, the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold value, variation, etc.) In order to obtain the required semiconductor characteristics, it is preferable to appropriately select the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc.

For example, high mobility can be obtained relatively easily in In-Sn-Zn oxides. However, mobility can also be increased in In-Ga-Zn oxides by lowering the bulk defect density.

For example, the composition of an oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide having an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1) if a, b, and c are such that (aA)²+(bB)²+(cC)²r²The above condition is satisfied. For example, r may be set to 0.05. The same is true for other oxides.

The oxide semiconductor film 108 is preferably a C-axis aligned crystalline oxide semiconductor (CAAC-OS) film.

The CAAC-OS film is neither completely single crystalline nor completely amorphous. The CAAC-OS film is an oxide semiconductor layer having a crystalline-amorphous mixed phase structure in which a crystalline part is included in an amorphous phase. Note that the crystalline part is often within a cube having a side of less than 100 nm. In addition, in an image observed with a transmission electron microscope (TEM), the boundary between the amorphous part and the crystalline part in the CAAC-OS film is not clear. In addition, grain boundaries cannot be confirmed in the CAAC-OS film by TEM. Therefore, the CAAC-OS film is suppressed from decreasing electron mobility due to grain boundaries.

The crystal parts included in the CAAC-OS film have c-axes aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface, and have a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane, with metal atoms arranged in layers or metal atoms and oxygen atoms arranged in layers when viewed from a direction perpendicular to the c-axis. The directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, when it is simply described as "perpendicular," it also includes a range of 85° to 95°. When it is simply described as "parallel," it also includes a range of -5° to 5°.

Note that the distribution of crystal parts in the CAAC-OS film may not be uniform. For example, when crystals are grown from the surface side of the oxide semiconductor film during the formation of the CAAC-OS film, the proportion of crystal parts near the surface may be higher than that near the surface where the CAAC-OS film is formed. In addition, by adding impurities to the CAAC-OS film, the crystal parts may become amorphous in the regions where the impurities are added.

The c-axes of the crystal parts contained in the CAAC-OS film are aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface, and therefore may be oriented in different directions depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface on which the CAAC-OS film is formed or the cross-sectional shape of the surface).

The direction of the c-axis of the crystal part is parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by forming the film or by carrying out a crystallization treatment such as a heat treatment after the film formation.

A transistor including a CAAC-OS film has small changes in electrical characteristics due to irradiation with visible light or ultraviolet light, and therefore has high reliability.

When a CAAC-OS film is used as the oxide semiconductor film 108, there are three methods for obtaining the CAAC-OS film. The first method is to form an oxide semiconductor layer at a film formation temperature of 100° C. to 450° C., more preferably 150° C. to 400° C., and to orient the c-axis approximately perpendicular to the surface. The second method is to form an oxide semiconductor layer with a thin thickness, and then perform a heat treatment at 200° C. to 700° C., and to orient the c-axis approximately perpendicular to the surface. The third method is to form a thin first layer, and then perform a heat treatment at 200° C. to 700° C., and then form a second layer, and to orient the c-axis approximately perpendicular to the surface.

Note that in the case of depositing an oxide semiconductor film having crystallinity (single crystal or microcrystalline) other than a CAAC-OS film as the oxide semiconductor film 108, the deposition temperature is not particularly limited.

The oxide semiconductor film 108 has an energy gap of 2.8 eV to 3.2 eV, which is larger than the energy gap of silicon, which is 1.1 eV.^-9cm^-3is 10 times the intrinsic carrier density of silicon¹¹cm^-3is extremely small compared to

Majority carriers (electrons) in the oxide semiconductor film 108 flow only from the source of the transistor. In addition, since the channel formation region can be completely depleted, the off-state current of the transistor can be made extremely small. The off-state current of the transistor using the oxide semiconductor film 108 is extremely small, being 10 yA/μm or less at room temperature and 1 zA/μm or less even at 85° C. to 95° C.

The oxide semiconductor film 108 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor film 108 may be a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and the first oxide semiconductor layer and the second oxide semiconductor layer may be made of metal oxides having different compositions. For example, the first oxide semiconductor layer may be made of a ternary metal oxide, and the second oxide semiconductor layer may be made of a binary metal oxide. Both the first oxide semiconductor layer and the second oxide semiconductor layer may be made of a ternary metal oxide.

The first oxide semiconductor layer and the second oxide semiconductor layer may have the same constituent elements but different compositions. For example, the atomic ratio of the first oxide semiconductor layer may be In:Ga:Zn=1:1:1, and the atomic ratio of the second oxide semiconductor layer may be In:Ga:Zn=3:1:2. The atomic ratio of the first oxide semiconductor layer may be In:Ga:Zn=1:3:2, and the atomic ratio of the second oxide semiconductor layer may be In:Ga:Zn=2:1:3.

In this case, the In and Ga contents of the oxide semiconductor layer closer to the gate electrode (channel side) of the first oxide semiconductor layer and the second oxide semiconductor layer are preferably In&gt;Ga. The In and Ga contents of the oxide semiconductor layer farther from the gate electrode (back channel side) are preferably InGa. In an oxide semiconductor, the s orbitals of heavy metals mainly contribute to carrier conduction, and an increase in the In content tends to increase the overlap of the s orbitals. Therefore, an oxide having a composition of In&gt;Ga has higher mobility than an oxide having a composition of InGa. In addition, since Ga has a larger energy for forming oxygen vacancies than In and is less likely to cause oxygen vacancies, an oxide having a composition of InGa has more stable characteristics than an oxide having a composition of In&gt;Ga. Therefore, by applying an oxide semiconductor layer having a composition of In&gt;Ga to the channel side and an oxide semiconductor layer having a composition of InGa to the back channel side, it is possible to further increase the mobility and reliability of a transistor.

When the oxide semiconductor film 108 is stacked, oxide semiconductors having different crystallinity may be used for the first oxide semiconductor layer and the second oxide semiconductor layer. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or an oxide semiconductor having crystallinity (for example, CAAC-OS) may be appropriately combined. When an amorphous oxide semiconductor is used for at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, internal stress or external stress of the oxide semiconductor can be alleviated, and the variation in characteristics of the transistor can be reduced, thereby further improving the reliability of the transistor. On the other hand, an amorphous oxide semiconductor easily absorbs impurities that serve as donors such as hydrogen and easily generates oxygen vacancies, and is therefore easily made n-type. For this reason, it is preferable to use an oxide semiconductor having crystallinity (for example, CAAC-OS) for the oxide semiconductor layer on the channel side.

Examples of the combination of composition and crystallinity when the oxide semiconductor film 108 is stacked include a stacked structure of an amorphous oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=1:1:1 and a crystalline oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=3:1:2, or a stacked structure of a crystalline oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=1:1:1 and a crystalline oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=3:1:2, in that order from the gate insulating film 106. Another stacked structure may be a stacked structure of a crystalline oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=3:1:2 and a crystalline oxide semiconductor layer having an atomic ratio of about In:Ga:Zn=1:1:1. As another example of a stacked structure, a stacked structure of an amorphous oxide semiconductor layer having an atomic ratio of approximately In:Ga:Zn=1:1:1 and an amorphous oxide semiconductor layer having an atomic ratio of approximately In:Ga:Zn=3:1:2, or a stacked structure of an amorphous oxide semiconductor layer having an atomic ratio of approximately In:Ga:Zn=3:1:2 and an amorphous oxide semiconductor layer having an atomic ratio of approximately In:Ga:Zn=1:1:1 may be used.

Further, before the oxide semiconductor film 108 is formed, planarization treatment may be performed on a surface on which the oxide semiconductor film 108 is to be formed. The planarization treatment is not particularly limited, but may be polishing treatment (for example, chemical mechanical polishing (CMP)), dry etching treatment, or plasma treatment.

As the plasma treatment, for example, reverse sputtering can be performed in which argon gas is introduced to generate plasma. The reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere to form plasma in the vicinity of the substrate, thereby modifying the surface. Note that nitrogen, helium, oxygen, or the like may be used instead of argon. By performing reverse sputtering, powdery substances (also referred to as particles or dust) attached to the deposition surface of the oxide semiconductor film 108 can be removed.

As the planarization treatment, a polishing treatment, a dry etching treatment, or a plasma treatment may be performed multiple times or a combination of these treatments may be performed. In the case where a combination of these treatments is performed, the order of the steps is not particularly limited and may be appropriately set depending on the unevenness of the surface on which the oxide semiconductor film 108 is to be formed.

After the oxide semiconductor film 108 is formed, heat treatment is preferably performed to reduce or remove (dehydrate or dehydrogenate) excess hydrogen (including water or a hydroxyl group) contained in the oxide semiconductor film 108. The heat treatment can be performed under conditions similar to those of the heat treatment performed on the second gate insulating film 106b.

This heat treatment can reduce, or more preferably remove, hydrogen, which is an impurity that imparts n-type conductivity, from the oxide semiconductor film 108. When an insulating film containing oxygen is used as the second gate insulating film 106b, this heat treatment supplies oxygen contained in the second gate insulating film 106b to the oxide semiconductor film 108. When the oxide semiconductor film 108 is desorbed by dehydration or dehydrogenation treatment, oxygen is supplied from the second gate insulating film 106b to the oxide semiconductor film 108, and oxygen vacancies in the oxide semiconductor film 108 can be filled by the oxygen.

After the oxide semiconductor film 108 is heated by heat treatment, high-purity oxygen gas, high-purity nitrous oxide gas, or ultra-dry air (air having a moisture content of 20 ppm (55° C. in terms of dew point) or less, preferably 1 ppm or less, and more preferably 10 ppb or less, as measured by a CRDS (cavity ring-down laser spectroscopy) dew point meter) may be introduced into the same furnace while maintaining the heating temperature or slowly cooling from the heating temperature. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, or the like. Alternatively, it is preferable that the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is 6 N or more, preferably 7 N or more (i.e., the impurity concentration in the oxygen gas or nitrous oxide gas is 1 ppm or less, preferably 0.1 ppm or less). The action of oxygen gas or nitrous oxide gas supplies oxygen, which is a main component material of the oxide semiconductor film 108 and has been reduced simultaneously in the impurity removal process by the dehydration or dehydrogenation treatment, to the oxide semiconductor film 108, so that the oxide semiconductor film 108 can be highly purified and made to be i-type (intrinsic).

The heat treatment for dehydration or dehydrogenation may be performed together with other heat treatments in the manufacturing process of the transistor 150.

Next, a first metal film 109a and a second metal film 109b which are to be a source electrode and a drain electrode (including wirings formed in the same layer as the source electrode and the drain electrode) are formed over the gate insulating film 106 and the oxide semiconductor film 108 (see FIG. 2D).

The first metal film 109a is preferably a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, or a metal nitride film. In this embodiment, a tungsten film having a thickness of 50 nm formed by sputtering is used as the first metal film 109a.

The first metal film 109a may have a laminated structure, for example, a first layer of the first metal film 109a may be a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, and a second layer of the first metal film 109a may be a laminated structure of a metal nitride film containing one or more elements selected from tungsten nitride, tantalum nitride, titanium nitride, and molybdenum nitride.

The first metal film 109a is in contact with the oxide semiconductor film 108 and is therefore made of a material that does not extract oxygen from the oxide semiconductor film 108 to cause it to become n-type or a material that does not diffuse into the oxide semiconductor film 108 to cause it to become n-type. In addition, the first metal film 109a is desirably made of a material that suppresses diffusion of copper elements from a copper film used for the second metal film 109b to the oxide semiconductor film 108 (a so-called barrier metal material).

The second metal film 109b is preferably a film containing elemental copper. Alternatively, a copper alloy containing a few weight percent of aluminum, gold, silver, zinc, tin, nickel, or the like may be used.

In this embodiment, as the second metal film 109b, a copper film having a thickness of 200 nm and formed by sputtering is used.

Next, a resist is applied onto the second metal film 109b, and a first patterning is performed to form a resist mask 141 (see FIG. 2(E)).

The resist mask 141 can be formed by applying a photosensitive resin, exposing the photosensitive resin to light, and developing the resin. Note that the photosensitive resin may be either a positive type or a negative type. The resist mask 141 may be formed by an inkjet method. When the resist mask 141 is formed by an inkjet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

Next, a part of the second metal film 109b is removed by a first etching to form a second metal film 110b and a second metal film 112b (see FIG. 3(A)).

As a method for removing the second metal film 109b, a wet etching method is preferably used. In addition, as a chemical solution used in the wet etching method, a chemical solution that can etch the second metal film 109b and does not remove the first metal film 109a may be used. For example, when a tungsten film is used as the first metal film 109a and a copper film is used as the second metal film 109b, a mixture of water, hydrogen peroxide, and carboxylic acid, or a mixture of water, phosphoric acid, nitric acid, sulfuric acid, and potassium sulfate may be used as the chemical solution.

Alternatively, the time for wet etching may be adjusted to perform isotropic etching, so that the side surfaces of the second metal film 110b and the second metal film 112b are recessed inward from the side surfaces of the resist mask 141.

Next, the resist mask 141 is removed (see FIG. 3B).

The resist mask 141 can be removed by a wet method using a stripping liquid, a dry method such as plasma treatment, or a combination of these methods.

Next, a third metal film 109c is formed on the first metal film 109a, the second metal film 110b, and the second metal film 112b (see FIG. 3(C)).

The third metal film 109c can be formed by the same method and material as the first metal film 109a. In the present embodiment, the third metal film 109c is a tantalum nitride film having a thickness of 100 nm formed by sputtering.

Next, a resist is applied onto the third metal film 109c, and a second patterning is performed to form a resist mask 142 (see FIG. 3(D)).

The resist mask 142 can be formed using a material and method similar to that of the resist mask 141.

Next, the first metal film 109a and a portion of the third metal film 109c are removed by a second etching to form the first metal film 110a, the first metal film 112a, the third metal film 110c, and the third metal film 112c (see FIG. 4(A)).

The second etching removes the first metal film 109a and the third metal film 109c on the outer side of the ends of the second metal film 110b and the second metal film 112b removed by the first etching.

Dry etching is preferably used as a method for removing the first metal film 109a and the third metal film 109c. For example, when a tungsten film is used as the first metal film 109a and a tantalum nitride film is used as the third metal film 109c, SF₆and O₂Mixture of gases, or SF₆and BCl₃A mixed gas of the above may be used.

Note that it is desirable to optimize the etching conditions so that the oxide semiconductor film 108 is not etched and divided when the first metal film 109a and the third metal film 109c are etched. However, it is difficult to obtain conditions under which only the first metal film 109a and the third metal film 109c are etched and the oxide semiconductor film 108 is not etched at all. When the first metal film 109a and the third metal film 109c are etched, the oxide semiconductor film 108 may be partially etched and have a groove (depression).

Next, the resist mask 142 is removed, and a source electrode 110 consisting of a first metal film 110a, a second metal film 110b, and a third metal film 110c, and a drain electrode 112 consisting of a first metal film 112a, a second metal film 112b, and a third metal film 112c are formed (see Figure 4(B)).

By using such a method for forming the source electrode 110 and the drain electrode 112, the oxide semiconductor film 108 (more specifically, the back channel side) does not come into contact with the copper film used for the second metal film 110b and the second metal film 112b, so that copper elements that may adhere to or diffuse into the oxide semiconductor film 108 can be suppressed.

The resist mask 142 can be removed by a method similar to that for removing the resist mask 141 .

After the source electrode 110 and the drain electrode 112 are formed, the oxide semiconductor film 108 (more specifically, the back channel side) is preferably cleaned. For example, oxygen plasma treatment or cleaning treatment using dilute hydrofluoric acid is effective for cleaning the oxide semiconductor film 108. By performing such cleaning, an etching gas component used in forming the source electrode 110 and the drain electrode 112, a residue of the resist mask 142, or the like can be removed from the oxide semiconductor film 108, and the oxide semiconductor film 108 can be further purified.

After the source electrode 110 and the drain electrode 112 are formed, a heat treatment may be performed.

The temperature of the heat treatment is from 250° C. to 650° C., preferably from 450° C. to 600° C., or below the distortion point of the substrate.

Through the above steps, the transistor 150 described in this embodiment is formed.

Next, a first insulating film 114a is formed over the transistor 150, more specifically, over the oxide semiconductor film 108, the source electrode 110, and the drain electrode 112. Then, oxygen 145 is introduced into the first insulating film 114a and the oxide semiconductor film 108 (see FIG. 4C).

The first insulating film 114a can be formed by a plasma CVD method or a sputtering method, and an oxide insulating film such as a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon oxynitride film, or an aluminum oxynitride film can be used. The thickness of the first insulating film 114a is preferably 50 nm to 100 nm.

The first insulating film 114a is preferably an oxygen-excess oxide insulating film, which allows oxygen to be suitably supplied to the oxide semiconductor film 108.

In this embodiment, a silicon oxynitride film having a thickness of 30 nm is formed as the first insulating film 114a by plasma CVD. The film forming conditions for the first insulating film 114a are, for example, SiH₄and N₂The gas flow rate ratio of O to SiH₄:N₂The oxygen concentration may be set to 20 sccm:3000 sccm, the pressure to 200 Pa, the RF power supply power (power supply output) to 100 W, and the substrate temperature to 350° C.±15° C. Note that the first insulating film 114a is an insulating film in contact with the oxide semiconductor film 108, and therefore preferably contains as little impurities as possible, such as water and hydrogen, similar to the gate insulating film 106.

The oxygen 145 includes at least any of oxygen radicals, ozone, oxygen atoms, and oxygen ions (including molecular ions and cluster ions).

The oxygen 145 can be introduced into the first insulating film 114a by, for example, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. Note that a gas cluster ion beam may be used as the ion implantation method.

The oxygen 145 may be introduced to the entire surface of the first insulating film 114a at once, or may be introduced using, for example, a linear ion beam. When a linear ion beam is used, the substrate or the ion beam is moved (scanned) relatively to introduce the oxygen 145 to the entire surface of the first insulating film 114a.

As the supply gas of oxygen 145, a gas containing O may be used. For example, O₂Gas, N₂O gas, CO₂Gas, CO gas, NO₂Gases such as argon (Ar) may be used as the oxygen supply gas.

For example, when oxygen is introduced by ion implantation, the dose of oxygen 145 is 1×10¹³ions/cm²5×10 or more¹⁶ions/cm²or less, and the oxygen content in the first insulating film 114a after the oxygen introduction treatment is preferably set to a level exceeding the stoichiometric composition of the first insulating film 114a. Note that the oxygen implantation depth may be appropriately controlled by the implantation conditions.

Note that when an oxide insulating film (for example, a silicon oxide film or a silicon oxynitride film) is used as the first insulating film 114a, oxygen is one of the main components of the oxide insulating film. For this reason, it is difficult to accurately estimate the oxygen concentration in the oxide insulating film by using a method such as secondary ion mass spectrometry (SIMS). That is, it is difficult to determine whether oxygen is intentionally added to the oxide insulating film. The same can be said when excess oxygen contained in the first insulating film 114a is supplied to the oxide semiconductor film 108 in a later step.

By the way, oxygen has¹⁷O and¹⁸It is known that oxygen isotopes such as O exist and their abundance ratios in nature are approximately 0.038% and 0.2% of all oxygen atoms, respectively. That is, the concentrations of these isotopes in an insulating film in contact with the oxide semiconductor film (the first insulating film 114a in this embodiment) or in the oxide semiconductor film can be estimated by a method such as SIMS. Therefore, by measuring these concentrations, it may be possible to more accurately estimate the oxygen concentration in the insulating film in contact with the oxide semiconductor film or in the oxide semiconductor film. Therefore, by measuring these concentrations, it may be possible to determine whether oxygen has been added to the insulating film in contact with the oxide semiconductor film.

In this manner, the oxygen 145 is introduced into the oxide semiconductor film 108 through the first insulating film 114a. The oxygen-excess first insulating film 114a can supply oxygen to the oxide semiconductor film 108 by solid-phase diffusion caused by heat treatment in a transistor manufacturing process. Furthermore, oxygen may be introduced into the oxide semiconductor film 108 through the first insulating film 114a through the introduction of the oxygen 145.

Next, the second insulating film 114b is formed on the first insulating film 114a (see FIG. 4(D)).

The second insulating film 114b can be formed by a plasma CVD method or a sputtering method, and can be a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film. The thickness of the second insulating film 114b is preferably 50 nm to 500 nm.

In this embodiment, a silicon oxynitride film having a thickness of 370 nm is formed as the second insulating film 114b by the plasma CVD method. The film forming conditions for the second insulating film 114b are, for example, SiH₄and N₂The gas flow rate ratio of O to SiH₄:N₂The flow rate may be set to O = 30sccm:4000sccm, the pressure to 200Pa, the RF power supply power (power supply output) to 150W, and the substrate temperature to 220°C±15°C.

When the first insulating film 114a and the second insulating film 114b are formed from the same material, the interface between the first insulating film 114a and the second insulating film 114b may not be clearly visible. Therefore, in this embodiment, the interface between the first insulating film 114a and the second insulating film 114b is shown by a dashed line.

Note that, like the first insulating film 114a, the second insulating film 114b preferably contains as little impurities as possible, such as water and hydrogen. Therefore, in this embodiment, the second insulating film 114b after deposition is subjected to a heat treatment (dehydration or dehydrogenation treatment) for the purpose of removing hydrogen atoms.

The temperature of the heat treatment can be, for example, 250° C. to 600° C., and preferably 300° C. to 600° C. In this embodiment, the heat treatment is performed at 350° C. for 1 hour.

Next, an aluminum film 115 is formed on the second insulating film 114b (see FIG. 5(A)).

The aluminum film 115 is preferably formed by a sputtering method, a vapor deposition method, a CVD method, or the like. The thickness of the aluminum film 115 is preferably 3 nm or more and 10 nm or less. In this embodiment, a 5 nm-thick aluminum film is formed by a sputtering method.

The aluminum film 115 formed on the second insulating film 114b is turned into an aluminum oxide film by performing oxygen introduction treatment later, and functions as a barrier film for the transistor. The aluminum oxide film has a high blocking effect (blocking effect) that does not allow impurities such as hydrogen and water, and oxygen to pass through the film, that is, has a barrier property.

Next, oxygen 147 is introduced into the aluminum film 115. As a result, the aluminum film 115 becomes an aluminum oxide film 116 (see FIG. 5(B)).

Oxygen 147 can be introduced in the same manner as oxygen 145.

Furthermore, oxygen 147 may be introduced into a part of the second insulating film 114b through the aluminum film 115. This allows the second insulating film 114b to compensate for oxygen that may be desorbed by the previous heat treatment, and also allows a region containing more oxygen than the stoichiometric composition to be formed. Note that such a region containing more oxygen than the stoichiometric composition may be present in a part of the second insulating film 114b. Note that the oxygen implantation depth may be appropriately controlled by the implantation conditions.

In addition, a region containing oxygen exceeding the stoichiometric composition may be formed in the aluminum oxide film 116. However, the aluminum oxide film 116 formed by the oxygen introduction process does not need to contain oxygen that matches the stoichiometric composition, and may have some electrical conductivity. For example, when the composition is Al₂O_xIn the case of the aluminum oxide film represented by the formula (1), x is preferably set to 1 or more and 3.5 or less. In addition, when the aluminum oxide film 116 has conductivity, its resistivity ρ is set to 10¹⁰Ωm or more 10¹⁹Ω·m or less, preferably 10¹⁰Ωm or more 10¹⁸Ω·m or less, more preferably 10¹¹Ωm or more 10¹⁵It is preferable that the resistivity be Ω·m or less. When the aluminum oxide film 116 has a resistivity in the above range, electrostatic damage to the transistor 150 can be prevented.

The aluminum oxide film 116 is a film formed by oxidizing the aluminum film 115. By forming the aluminum oxide film 116 by oxidizing the aluminum film 115, productivity can be improved compared to the case of forming an aluminum oxide film by a sputtering method.

Note that heat treatment may be performed after the oxygen 147 is introduced into the aluminum film 115. By the heat treatment, oxygen contained in the first insulating film 114a or the second insulating film 114b may be supplied to the oxide semiconductor film 108 so that oxygen vacancies in the oxide semiconductor film 108 are filled.

The temperature of the heat treatment can be, for example, 250° C. to 600° C., and preferably 300° C. to 600° C. In this embodiment, the heat treatment is performed at 300° C. for 1 hour.

Next, a planarization insulating film 118 is formed over the aluminum oxide film 116 (see FIG. 5C).

The planarization insulating film 118 may be made of any heat-resistant organic material capable of planarizing the unevenness of the transistor 150, such as polyimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, polyamide resin, or epoxy resin. In addition to the above organic materials, low-dielectric constant materials (low-k materials), siloxane resin, or the like may be used. Note that the planarization insulating film 118 may be formed by stacking a plurality of insulating films made of these materials. In this embodiment, an acrylic resin having a thickness of 1.5 μm is used as the planarization insulating film 118.

As described above, the transistor 150 described in this embodiment uses an oxide semiconductor film for a channel formation region and copper, which is a low-resistance material, for the gate electrode, the source electrode, and the drain electrode. In addition, the back channel side of the oxide semiconductor film is not in contact with the copper film when the source electrode and the drain electrode are formed, so that copper elements that may adhere to or diffuse into the oxide semiconductor film can be suppressed. In addition, the gate electrode, the source electrode, and the drain electrode each use a copper film and have a barrier metal that can suppress the diffusion of the copper element. Therefore, a transistor with stable electrical characteristics and reduced signal delay due to wiring resistance can be provided.

The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

(Embodiment 2) In this embodiment, a modified example of the semiconductor device shown in Embodiment 1 and a manufacturing method thereof different from the manufacturing method of the semiconductor device shown in Embodiment 1 will be described with reference to Figures 6 to 8. Note that the same reference symbols are used for the reference symbols shown in Figures 1 to 5, and repeated description thereof will be omitted.

&lt;Configuration Example 2 of Semiconductor Device&gt; Fig. 6 shows a configuration example of a transistor 250 and a signal line region 260. Fig. 6(A) is a plan view of the transistor 250 and the signal line region 260, and Fig. 6(B) is a cross-sectional view taken along X2-Y2 in Fig. 6(A). Note that in Fig. 6(A), in order to avoid complication, some of the components of the transistor 250 and the signal line region 260 (e.g., the gate insulating film 206, the second metal film 210b, etc.) are omitted.

The semiconductor device shown in FIG. 6 includes a gate electrode 204 formed on a substrate 102, a gate insulating film 206 formed on the gate electrode 204, an oxide semiconductor film 108 formed in contact with the gate insulating film 206 and at a position overlapping the gate electrode 204, a source electrode 210 and a drain electrode 212 formed on the oxide semiconductor film 108, and a signal line 232 electrically connected to the source electrode 210, the signal line 232 being made of a first metal film 210a, a second metal film 210b, and a third metal film 210c, the second metal film 210b being formed in a region inside the ends of the first metal film 210a and the third metal film 210c, and the source electrode 210 and the drain electrode 212 being made of the first metal film 210a, the first metal film 212a, the third metal film 210c, and the third metal film 212c.

The gate electrode 204 is composed of a first gate electrode 204a and a second gate electrode 204b. The first gate electrode 204a is preferably a metal film or a metal nitride film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum. The second gate electrode 204b is preferably a copper film. For example, in this embodiment, a tungsten film is used as the first gate electrode 204a, and a copper film is used as the second gate electrode 204b. By forming the gate electrode 204 with such a stacked structure, the gate electrode 204 can have a low resistance. By providing the first gate electrode 204a, the adhesion between the substrate 102 and the copper film used as the second gate electrode 204b can be improved, and/or the diffusion of the copper element in the copper film used as the second gate electrode 204b can be suppressed.

The gate insulating film 206 is composed of a first gate insulating film 206a and a second gate insulating film 206b. The first gate insulating film 206a may have a function of suppressing diffusion of copper elements in a copper film used as the second gate electrode 204b, and may be a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride oxide film, or the like. The second gate insulating film 206b may have a function of supplying oxygen to the oxide semiconductor film 108 to be formed later, and may be a silicon oxide film, a silicon oxynitride film, or the like. For example, in this embodiment, a silicon nitride film is used as the first gate insulating film 206a, and a silicon oxynitride film is used as the second gate insulating film 206b. By using the gate insulating film 206 having such a stacked structure, diffusion of copper elements in the copper film used as the gate electrode 204 can be suppressed, and oxygen can be supplied to the oxide semiconductor film 108 to be formed later.

Furthermore, it is preferable to use a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, or a metal nitride film as the first metal film 210a, the first metal film 212a, the third metal film 210c, and the third metal film 212c.

For example, in this embodiment, the first metal film 210a and the first metal film 212a are made of tungsten films, and the third metal film 210c and the third metal film 212c are made of tantalum nitride films.

In addition, it is preferable that the second metal film 210b contains copper element In the present embodiment, a copper film is used as the second metal film 210b.

In this manner, the configurations of the source electrode 210 and the drain electrode 212 used in the transistor 250 are different from the configuration of the signal line 232. By electrically connecting the signal line 232 using a copper film to the source electrode 210 and the drain electrode 212, signal delays and the like caused by wiring resistance can be suppressed. Furthermore, by using a material containing copper for the source electrode 210 and the drain electrode 212 used in the transistor 250, copper elements that may diffuse into the oxide semiconductor film 108 can be effectively disposed at a position away from the source electrode 210 and the drain electrode 212. Furthermore, since the signal line 232, the source electrode 210, and the drain electrode 212 can be manufactured in the same semiconductor manufacturing process, an excellent effect of reducing manufacturing costs can be achieved.

Next, a manufacturing method of the transistor 250 and the signal line region 260 shown in FIG. 6 will be described with reference to FIGS.

&lt;Method 2 for manufacturing a semiconductor device&gt; First, a gate electrode 204, a gate insulating film 206, and an oxide semiconductor film 108 are formed over a substrate 102. Note that the gate electrode 204, the gate insulating film 206, and the oxide semiconductor film 108 can be formed by referring to the steps shown in FIGS. 2A to 2D in Embodiment 1. After that, a first metal film 209a and a second metal film 209b which serve as a source electrode, a drain electrode, and a signal line are formed over the gate insulating film 206 and the oxide semiconductor film 108 (see FIG. 7A).

The first metal film 209a is preferably a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, or a metal nitride film. In this embodiment, a tungsten film having a thickness of 50 nm formed by sputtering is used as the first metal film 209a.

The first metal film 209a may have a laminated structure, for example, a first layer of the first metal film 209a may be a metal film containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, and a second layer of the first metal film 209a may be a laminated structure of a metal nitride film containing one or more elements selected from tungsten nitride, tantalum nitride, titanium nitride, and molybdenum nitride.

The first metal film 209a is in contact with the oxide semiconductor film 108 and is therefore made of a material that does not extract oxygen from the oxide semiconductor film 108 to cause it to become n-type or a material that does not diffuse into the oxide semiconductor film 108 to cause it to become n-type. In addition, the first metal film 209a is desirably made of a material that suppresses diffusion of copper elements from the copper film used for the second metal film 209b to the oxide semiconductor film 108.

The second metal film 209b is preferably a film containing copper. Alternatively, a copper alloy containing a few weight percent of aluminum, gold, silver, zinc, tin, nickel, or the like may be used.

In this embodiment, as the second metal film 209b, a copper film having a thickness of 200 nm formed by sputtering is used.

Next, a resist is applied onto the second metal film 209b, and a first patterning is performed to form a resist mask 241 (see FIG. 7(B)).

The resist mask 241 can be formed using a material and method similar to those of the resist mask 141 described in Embodiment 1.

Next, a part of the second metal film 209b is removed by a first etching process to form a second metal film 210b (see FIG. 7(C)).

As a method for removing the second metal film 209b, a wet etching method is preferably used. In addition, as a chemical solution used in the wet etching method, a chemical solution that can etch the second metal film 209b and does not remove the first metal film 209a may be used. For example, when a tungsten film is used as the first metal film 209a and a copper film is used as the second metal film 209b, a mixture of water, hydrogen peroxide, and carboxylic acid, or a mixture of water, phosphoric acid, nitric acid, sulfuric acid, and potassium sulfate may be used as the chemical solution.

Alternatively, the time for wet etching may be adjusted to perform isotropic etching, so that the side surfaces of the second metal film 210b are recessed inward from the side surfaces of the resist mask 241.

In this manner, during the first etching, the second metal film 209b is left in the signal line region 260, and the second metal film 209b is removed in the region where the oxide semiconductor film 108 is formed.

Next, the resist mask 241 is removed, and a third metal film 209c is formed on the first metal film 209a and the second metal film 210b (see FIG. 7(D)).

The resist mask 241 can be removed by a method similar to that of removing the resist mask 141 described in Embodiment 1.

The third metal film 209c can be formed by the same method and material as the first metal film 209a. In the present embodiment, the third metal film 209c is a tantalum nitride film having a thickness of 100 nm formed by sputtering.

Next, a resist is applied onto the third metal film 209c, and a second patterning is performed to form a resist mask 242 (see FIG. 8(A)).

The resist mask 242 can be formed using a material and method similar to those of the resist mask 241.

Next, the first metal film 209a and a portion of the third metal film 209c are removed by a second etching to form the first metal film 210a, the first metal film 212a, the third metal film 210c, and the third metal film 212c (see FIG. 8(B)).

The second etching removes the first metal film 209a and the third metal film 209c outside the end of the second metal film 210b removed by the first etching.

Dry etching is preferably used as a method for removing the first metal film 209a and the third metal film 209c. For example, when a tungsten film is used as the first metal film 209a and a tantalum nitride film is used as the third metal film 209c, SF₆and O₂Mixture of gases, or SF₆and BCl₃A mixed gas of the above may be used.

Note that it is desirable to optimize the etching conditions so that the oxide semiconductor film 108 is not etched and divided when the first metal film 209a and the third metal film 209c are etched. However, it is difficult to obtain conditions under which only the first metal film 209a and the third metal film 209c are etched and the oxide semiconductor film 108 is not etched at all. When the first metal film 209a and the third metal film 209c are etched, the oxide semiconductor film 108 may be partially etched and have a groove (depression).

Next, the resist mask 242 is removed, and a source electrode 210 made of the first metal film 210a and the third metal film 210c and a drain electrode 212 made of the first metal film 212a and the third metal film 212c are formed. In addition, in the signal line region 260, a signal line 232 made of the first metal film 210a, the second metal film 210b, and the third metal film 210c is formed (see FIG. 8(C)).

In this manner, the signal line 232 using the copper film as the second metal film 210b and the source electrode 210 and the drain electrode 212 not using the second metal film 210b can be manufactured in the same process.

The resist mask 242 can be removed by the same method as the resist mask 241 .

After the signal line 232, the source electrode 210, and the drain electrode 212 are formed, the oxide semiconductor film 108 (more specifically, the back channel side) is preferably cleaned. For example, oxygen plasma treatment or cleaning treatment using dilute hydrofluoric acid is effective for cleaning the oxide semiconductor film 108. By performing such cleaning, an etching gas component used in forming the source electrode 210 and the drain electrode 212 or a residue of the resist mask 242 can be removed from the oxide semiconductor film 108, and the oxide semiconductor film 108 can be further purified.

Heat treatment may be performed after forming the signal line 232, the source electrode 210, and the drain electrode 212. The temperature of the heat treatment is set to 250° C. or higher and 650° C. or lower, preferably 450° C. or higher and 600° C. or lower, or lower than the distortion point of the substrate.

Through the above steps, the transistor 250 and the signal line region 260 described in this embodiment are formed.

Next, the first insulating film 114a, the second insulating film 114b, the aluminum oxide film 116, and the planarizing insulating film 118 are formed over the transistor 250 and the signal line region 260 (see FIG. 8D).

The first insulating film 114a, the second insulating film 114b, the aluminum oxide film 116, and the planarization insulating film 118 can be formed according to the steps described in Embodiment 1.

In this manner, the configurations of the source electrode 210 and the drain electrode 212 of the transistor 250 are different from the configuration of the signal line 232 of the signal line region 260. By electrically connecting the signal line 232 using a copper film to the source electrode 210 and the drain electrode 212, it is possible to suppress signal delays and the like caused by wiring resistance. Furthermore, by using a structure in which a material containing copper is not used for the source electrode 210 and the drain electrode 212 used in the transistor 250, it is possible to effectively dispose the copper element, which may diffuse into the oxide semiconductor film 108, at a position away from the source electrode 210 and the drain electrode 212.

In addition, since the signal line 232, the source electrode 210, and the drain electrode 212 can be manufactured in the same semiconductor manufacturing process, there is an excellent effect of reducing manufacturing costs.

The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

(Embodiment 3) A display device having a display function can be manufactured using the transistors or signal lines described in Embodiments 1 and 2. In addition, a part or the whole of a driver circuit including a transistor can be integrally formed over the same substrate as a pixel portion to form a system-on-panel. An example of the display device will be described with reference to FIG. 9.

9, a sealant 312 is provided so as to surround a pixel portion 302, a source driver circuit portion 304, and a gate driver circuit portion 306 which are provided over a first substrate 300. A second substrate 301 is provided over the pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306. Thus, the pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306 are sealed together with a display element by the first substrate 300, the sealant 312, and the second substrate 301.

In addition, in FIG. 9, an FPC terminal portion 308 (FPC: Flexible printed circuit) electrically connected to the pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306 is provided in an area other than the area surrounded by the sealing material 312 on the first substrate 300, and an FPC 316 is connected to the FPC terminal portion 308, and various signals and potentials given to the pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306 are supplied by the FPC 316.

9, a signal line 310 is connected to each of the pixel portion 302, the source driver circuit portion 304, the gate driver circuit portion 306, and the FPC terminal portion 308. Various signals and potentials supplied by the FPC 316 are given to the pixel portion 302, the source driver circuit portion 304, the gate driver circuit portion 306, and the FPC terminal portion 308 through the signal line 310.

9 shows an example in which the source driver circuit portion 304 and the gate driver circuit portion 306 are formed on the same first substrate 300 as the pixel portion 302, but the present invention is not limited to this configuration. For example, only the gate driver circuit portion 306 may be formed on the first substrate 300, or only the source driver circuit portion 304 may be formed on the first substrate 300. In this case, a substrate on which a separately prepared source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 300.

The method for connecting the separately formed drive circuit board is not particularly limited, and may be a chip on glass (COG) method, a wire bonding method, a tape automated bonding (TAB) method, or the like.

The display device includes a panel in which a display element is sealed, and a module in which an IC including a controller and the like are mounted on the panel.

In this specification, the term "display device" refers to an image display device, a display device, or a light source (including a lighting device).The term "display device" also includes a module to which a connector, such as an FPC, TAB tape, or TCP (Tape Carrier Package), is attached, a module to which a printed wiring board is provided at the end of the TAB tape or TCP, or a module in which a drive circuit board or an IC is directly mounted on a display element by the COG method.

The pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306 provided over the first substrate 300 each include a plurality of transistors, and the transistors exemplified in Embodiments 1 and 2 can be applied to the pixel portion 302, the source driver circuit portion 304, and the gate driver circuit portion 306 can include any of the transistors exemplified in Embodiments 1 and 2. In this embodiment, a case in which the transistors exemplified in Embodiment 2 are applied will be described.

In addition, liquid crystal elements (also called liquid crystal display elements) and light-emitting elements (also called light-emitting display elements) can be used as display elements provided in the display device. The light-emitting elements include elements whose luminance is controlled by current or voltage, and specifically include inorganic EL (Electro Luminescence), organic EL, etc. In addition, display media whose contrast changes due to electrical action, such as electronic ink, can also be used.

One mode of a display element provided in a display device will be described with reference to Fig. 10 and Fig. 11. The display device shown in Fig. 10 and Fig. 11 corresponds to a cross-sectional view taken along dashed line QR in Fig. 9.

The display device shown in FIG. 10 has a terminal electrode 360 consisting of a first metal film 360a, a second metal film 360b, and a third metal film 360c on an FPC terminal portion 308 provided on a first substrate 300, and the terminal electrode 360 is electrically connected to a terminal of the FPC 316 via an anisotropic conductive film 380.

The terminal electrode 360 is formed in the same process as the source electrodes and drain electrodes of the transistor 350 and the transistor 352, and in the same process as the signal line 310.

In addition, the pixel portion 302 and the source driver circuit portion 304 provided on the first substrate 300 each have a plurality of transistors. In FIGS. 10 and 11, a transistor 350 included in the pixel portion 302 and a transistor 352 included in the source driver circuit portion 304 are illustrated as examples.

In this embodiment, the transistor 350 included in the pixel portion 302 and the transistor 352 included in the source driver circuit portion 304 have the same size, but this is not limited to this. The transistors used in the pixel portion 302 and the source driver circuit portion 304 can be used with appropriately changed sizes (L/W) or the number of transistors used. Although not shown in Figures 10 and 11, the gate driver circuit portion 306 can have the same structure as the source driver circuit portion 304, although the connection destination or connection method is different.

10 and 11, the transistor 350, the transistor 352, and the signal line 310 can have structures similar to those of the transistor 250 and the signal line 232 described in the above embodiment 2.

That is, the transistor 350 and the transistor 352 have a source electrode and a drain electrode made of a first metal film and a third metal film, and the signal line 310 has wiring made of a first metal film, a second metal film, and a third metal film. The first metal film and the third metal film are metal films or metal nitride films containing one or more elements selected from tungsten, tantalum, titanium, and molybdenum, and the second metal film is formed of a material containing a copper element.

Moreover, the terminal electrode 360 has the same configuration as the signal line 310, and is made up of a first metal film, a second metal film, and a third metal film.

In this manner, in the transistors 350 and 352, the source and drain electrodes are formed without using a copper film, and the signal line 310 and the terminal electrode 360 are formed with a copper film. By using the transistors 350 and 352, the signal line 310, and the terminal electrode 360, a display device having stable electrical characteristics and low-resistance electrodes or wirings can be provided.

10 and 11, an insulating film 364, a protective insulating film 366, and a planarizing insulating film 368 are provided over the transistor 350 and the transistor 352.

In this embodiment, a silicon oxynitride film is used as the insulating film 364, and an aluminum oxide film is used as the protective insulating film 366. Note that the insulating film 364 and the protective insulating film 366 can be formed by a sputtering method or a plasma CVD method.

The silicon oxynitride film provided as the insulating film 364 is provided in contact with the oxide semiconductor film and can supply oxygen to the oxide semiconductor film.

The aluminum oxide film provided as the protective insulating film 366 has a high blocking effect that prevents impurities such as hydrogen and water, and oxygen from permeating the film. Therefore, the aluminum oxide film functions as a protective film that prevents impurities such as hydrogen and water, which are factors of fluctuation, from entering the oxide semiconductor film and prevents oxygen, which is a main component material of the oxide semiconductor film, from being released from the oxide semiconductor film during and after the manufacturing process.

In addition, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used as the planarization insulating film 368. Note that the planarization insulating film 368 may be formed by stacking a plurality of insulating films made of these materials.

In the display device described in this embodiment, a planarization insulating film 368 is provided over the transistor 352 formed in the source driver circuit portion 304, and a conductive film 370a is provided over the planarization insulating film 368 at a position overlapping with a channel formation region of the oxide semiconductor film. However, the present invention is not limited to this structure, and a structure in which the conductive film 370a is not provided may be used. By providing the conductive film 370a at a position overlapping with the channel formation region of the oxide semiconductor film, a change in the threshold voltage of the transistor 352 before and after a BT test can be reduced. The conductive film 370a may have the same potential as or different from that of the gate electrode of the transistor 352 and can function as a second gate electrode. The conductive film 370a may have a potential of GND, 0 V, or be in a floating state.

Note that the conductive film 370a also has a function of shielding an external electric field, that is, a function of preventing an external electric field from acting on the inside (a circuit portion including the transistor 352) (particularly, an electrostatic shielding function against static electricity). The shielding function of the conductive film 370a can prevent the electrical characteristics of the transistor 352 from being changed due to the influence of an external electric field such as static electricity. Note that the conductive film 370a may be provided over a wide area so as to overlap with the transistor 352. This is expected to further improve the electrostatic shielding function.

In addition, in the display device described in this embodiment, a planarization insulating film 368 is provided over the transistor 350 formed in the pixel portion 302, and a conductive film 370b connected to a source electrode or a drain electrode is provided over the planarization insulating film 368. The conductive film 370b functions as a pixel electrode in the pixel portion 302.

The transistor 350 provided in the pixel portion 302 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

The display device shown in FIG. 10 is an example of a liquid crystal display device using liquid crystal elements as display elements.

10, a liquid crystal element 402 which is a display element includes a conductive film 370b, a counter electrode 404, and a liquid crystal layer 406. Note that an insulating film 410 functioning as an alignment film and an insulating film 412 are provided so as to sandwich the liquid crystal layer 406. The counter electrode 404 is provided on the second substrate 301 side, and the conductive film 370b and the counter electrode 404 are stacked with the liquid crystal layer 406 interposed therebetween.

The spacers 435 are columnar spacers obtained by selectively etching an insulating film, and are provided to control the film thickness (cell gap) of the liquid crystal layer 406. Note that spherical spacers may also be used.

When a liquid crystal element is used as a display element, it is possible to use thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersion type liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on the conditions.

In addition, when the in-plane switching mode is adopted, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to an isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral agent is mixed in an amount of several weight percent or more is used in the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that an alignment treatment is not required, and the viewing angle dependency is small. In addition, since an alignment film is not required, a rubbing treatment is also not required, so that electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and damage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. In a transistor using an oxide semiconductor film, the electrical characteristics of the transistor may significantly change due to the influence of static electricity, and may deviate from the design range. Therefore, it is more effective to use a liquid crystal material of a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor film.

The specific resistance of the liquid crystal material is 1×10⁹Ω cm or more, preferably 1×10¹¹Ω cm or more, and more preferably 1×10¹²The specific resistance value in this specification is a value measured at 20°C.

The size of a storage capacitor provided in a liquid crystal display device is set so that charge can be stored for a predetermined period, taking into consideration the leakage current of a transistor arranged in a pixel portion, etc. The size of the storage capacitor may be set in consideration of the off-current of the transistor, etc. By using a transistor including an oxide semiconductor film that is highly pure and in which the formation of oxygen vacancies is suppressed, it is sufficient to provide a storage capacitor having a capacitance that is or less, preferably or less, of the liquid crystal capacitance in each pixel.

The transistor including the oxide semiconductor film used in this embodiment, which is highly purified and in which the formation of oxygen vacancies is suppressed, can reduce the current value in an off state (off-state current value). Therefore, the retention time of an electric signal such as an image signal can be extended, and the writing interval can be set to be long in a power-on state. Therefore, the frequency of a refresh operation can be reduced, which has the effect of reducing power consumption.

In addition, the transistor having the oxide semiconductor film which is highly purified and in which the formation of oxygen vacancies is suppressed, which is used in this embodiment, can achieve relatively high field-effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. In other words, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driver circuit, the number of components of the semiconductor device can be reduced. Furthermore, by using a transistor capable of high speed driving in the pixel portion, a high-quality image can be provided.

In addition, wiring containing copper is used as a signal line connected to a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion, so that signal delays caused by wiring resistance are small and the display device can be used in a large screen.

Liquid crystal display devices can use TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc.

Also, the liquid crystal display device may be a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device adopting a vertical alignment (VA) mode. There are several types of vertical alignment modes, for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, etc. can be used. The present invention can also be applied to a VA type liquid crystal display device. A VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. A VA type liquid crystal display device is a type in which liquid crystal molecules are oriented vertically to the panel surface when no voltage is applied. Also, a method called multi-domain or multi-domain design can be used, in which a pixel is divided into several regions (subpixels) and the molecules are tilted in different directions in each region.

In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, a backlight, a sidelight, or the like may be used as a light source.

In addition, the display method in the pixel section may be a progressive method, an interlace method, or the like. The color elements controlled by the pixels when displaying colors are not limited to the three colors of RGB (R stands for red, G for green, and B for blue). For example, there are RGBW (W stands for white), or RGB plus one or more colors such as yellow, cyan, and magenta. The size of the display area may differ for each dot of the color elements. However, the disclosed invention is not limited to a display device for color display, and may also be applied to a display device for monochrome display.

In addition, a light-emitting element utilizing electroluminescence can be applied as a display element included in the display device. Light-emitting elements utilizing electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound, and the former are generally called organic EL elements and the latter inorganic EL elements.

In an organic EL element, when a voltage is applied to a light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, causing a current to flow. Then, the carriers (electrons and holes) recombine, causing the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements.

Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film inorganic EL elements according to the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination-type light emission that utilizes donor and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Note that the following description will be given using an organic EL element as the light-emitting element.

In order to extract light emitted from the light emitting element, at least one of a pair of electrodes needs to be light-transmitting.

Then, a transistor and a light-emitting element are formed on a substrate, and there are light-emitting elements with a top emission structure in which light is extracted from the surface opposite the substrate, a bottom emission structure in which light is extracted from the surface on the substrate side, and a double-sided emission structure in which light is extracted from the substrate side and the surface opposite the substrate, and light-emitting elements with any emission structure can be used.

11 shows an example of a display device using a light-emitting element as a display element. A light-emitting element 450 which is a display element is electrically connected to a transistor 350 provided in a pixel portion 302. Note that the configuration of the light-emitting element 450 is a stacked structure of a conductive film 370b, an electroluminescent layer 452, and an upper electrode 454, but is not limited to the illustrated configuration. The configuration of the light-emitting element 450 can be changed as appropriate according to the direction of light extracted from the light-emitting element 450, etc.

The partition 456 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material for the partition 456. For example, when the partition 456 is formed using the photosensitive resin material, the photosensitive resin material is applied over the planarization insulating film 368 and the conductive film 370b, and a desired region is irradiated with light to form an opening in a part of the conductive film 370b, and the sidewall of the opening can be formed as an inclined surface having a continuous curvature.

The electroluminescent layer 452 may be formed of either a single layer or a laminate of a plurality of layers.

A protective film may be formed on the upper electrode 454 and the partition wall 456 to prevent oxygen, hydrogen, water, carbon dioxide, and the like from entering the light-emitting element 450. As the protective film, a silicon nitride film, a silicon nitride oxide film, and the like can be formed. A filler 458 is provided in the space sealed by the first substrate 300, the second substrate 301, and the sealant 312 to seal the space. It is preferable to package (enclose) the light-emitting element 450 with a protective film (lamination film, ultraviolet curing resin film, and the like) or a cover material that is highly airtight and has little degassing so as not to be exposed to the outside air.

In addition to an inert gas such as nitrogen or argon, an ultraviolet-curable resin or a thermosetting resin can be used as the filler 458. PVC (polyvinyl chloride), acrylic resin, polyimide resin, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler 458.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ/4 plate, λ/2 plate), or a color filter may be appropriately provided on the emission surface of the light-emitting element. An anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment can be applied to the surface to diffuse reflected light by using unevenness to reduce glare.

10 and 11, the first substrate 300 and the second substrate 301 may be a flexible substrate other than a glass substrate, for example, a plastic substrate having light transmission. As the plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film may be used. Also, a sheet having a structure in which aluminum foil is sandwiched between PVF films or polyester films may be used.

As described above, by using the transistors or signal lines described in Embodiments 1 and 2, a display device having various functions can be provided.

This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

(Embodiment 4) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). Examples of electronic devices include television devices (also called televisions or television receivers), monitors for computers, electronic paper, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, personal digital assistants (PDAs), mobile terminals (including smartphones, tablet PCs, etc.), sound players, and large game machines such as pachinko machines. Examples of electronic devices including the semiconductor devices described in the above embodiments will be described with reference to FIGS. 12 and 13.

12A shows a notebook personal computer including a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, etc. By applying the semiconductor device described in any of the above embodiments to the display portion 3003, a notebook personal computer having stable electrical characteristics and reduced signal delay due to wiring resistance can be provided.

12B shows a personal digital assistant (PDA), which includes a main body 3021 provided with a display portion 3023, an external interface 3025, operation buttons 3024, and the like. A stylus 3022 is also provided as an accessory for operation. By applying the semiconductor device described in any of the above embodiments to the display portion 3023, a personal digital assistant (PDA) having more stable electrical characteristics and less signal delay due to wiring resistance can be obtained.

12C shows an example of an electronic book. For example, an electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housings 2701 and 2703 are integrated with an axis 2711, and can be opened and closed around the axis 2711. With this configuration, the electronic book can be operated like a paper book.

A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portions 2705 and 2707 may be configured to display a continuous screen or different screens. By using a configuration to display different screens, for example, text can be displayed on the right display portion (the display portion 2705 in FIG. 12C) and an image can be displayed on the left display portion (the display portion 2707 in FIG. 12C). By using the semiconductor device described in any of the above embodiments for the display portions 2705 and 2707, an e-book reader having stable electrical characteristics and reduced signal delay due to wiring resistance can be obtained. When a semi-transmissive or reflective liquid crystal display device is used as the display portion 2705, it is expected that the display portion 2705 will be used in a relatively bright environment. Therefore, a solar cell may be provided so that power can be generated by the solar cell and the battery can be used for charging the display portion 2705. Note that a lithium ion battery is used as the battery, which has an advantage of being compact.

12C shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2701 is provided with a power source 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned using the operation keys 2723. Note that a keyboard, a pointing device, and the like may be provided on the same surface as the display unit of the housing. In addition, a terminal for external connection (such as an earphone terminal or a USB terminal), a recording medium insertion portion, and the like may be provided on the back or side of the housing. Furthermore, the electronic book 2700 may be provided with a function as an electronic dictionary.

The electronic book 2700 may be configured to transmit and receive information wirelessly. It is also possible to wirelessly purchase and download desired book data from an electronic book server.

12D shows a mobile phone which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like. The housing 2800 also includes a solar cell 2810 for charging the mobile phone, an external memory slot 2811, and the like. An antenna is built into the housing 2801. By applying the semiconductor device described in any of the above embodiments to the display panel 2802, a mobile phone having stable electrical characteristics and little signal delay due to wiring resistance can be obtained.

The display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 on which images are displayed are indicated by dotted lines in Fig. 12(D). Note that a boost circuit for boosting the voltage output from the solar cell 2810 to a voltage required for each circuit is also mounted.

The display direction of the display panel 2802 changes appropriately depending on the usage mode. In addition, a camera lens 2807 is provided on the same surface as the display panel 2802, so that videophone is possible. The speaker 2803 and the microphone 2804 are capable of videophone, recording, playback, and the like, in addition to voice calls. Furthermore, the housing 2800 and the housing 2801 can be slid from the unfolded state as shown in FIG. 12(D) to an overlapping state, so that the size can be made small enough to be portable.

The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, and allows charging and data communication with a personal computer, etc. Also, a recording medium can be inserted into the external memory slot 2811 to accommodate the storage and movement of larger amounts of data.

In addition to the above functions, the device may also be equipped with an infrared communication function, a television receiving function, and the like.

12E shows a digital video camera including a main body 3051, a display portion (A) 3057, an eyepiece 3053, an operation switch 3054, a display portion (B) 3055, a battery 3056, and the like. By applying the semiconductor device described in any of the above embodiments to the display portion (A) 3057 and the display portion (B) 3055, a digital video camera having stable electrical characteristics and reduced signal delay due to wiring resistance can be provided.

12F shows an example of a television set. In a television set 9600, a display portion 9603 is incorporated in a housing 9601. Images can be displayed by the display portion 9603. Here, the housing 9601 is supported by a stand 9605. By applying the semiconductor device described in any of the above embodiments to the display portion 9603, the television set can have stable electrical characteristics and little signal delay due to wiring resistance.

The television set 9600 can be operated using an operation switch provided in the housing 9601 or a separate remote control. The remote control may be provided with a display unit that displays information output from the remote control.

The television device 9600 includes a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

FIG. 13 shows an example of a tablet terminal, where FIG. 13(A) to FIG. 13(C) show a tablet terminal 5000, and FIG.

In the tablet terminal 5000 shown in Fig. 13(A) to Fig. 13(C), Fig. 13(A) shows a front view, Fig. 13(B) shows a side view, and Fig. 13(C) shows a rear view. Also, in the tablet terminal 6000 shown in Fig. 13(D), a front view is shown.

The tablet terminal 5000 is composed of a housing 5001, a display unit 5003, a power button 5005, a front camera 5007, a rear camera 5009, a first external connection terminal 5011, and a second external connection terminal 5013, etc.

The display unit 5003 is incorporated in the housing 5001 and can be used as a touch panel. For example, an icon 5015 or the like can be displayed on the display unit 5003 to perform tasks such as email and schedule management. A front camera 5007 is incorporated in the front side of the housing 5001, and can capture an image of the user's side. A rear camera 5009 is incorporated in the rear side of the housing 5001, and can capture an image of the opposite side to the user. The housing 5001 is also provided with a first external connection terminal 5011 and a second external connection terminal 5013. For example, the first external connection terminal 5011 can output sound to earphones or the like, and the second external connection terminal 5013 can transfer data or the like.

Next, a tablet terminal 6000 shown in Figure 13 (D) is composed of a first housing 6001, a second housing 6003, a hinge portion 6005, a first display portion 6007, a second display portion 6009, a power button 6011, a first camera 6013, a second camera 6015, etc.

The first display unit 6007 is incorporated in the first housing 6001, and the second display unit 6009 is incorporated in the second housing 6003. For example, the first display unit 6007 is used as a display panel and the second display unit 6009 is a touch panel. A text icon 6017 displayed on the first display unit 6007 can be checked, and an icon 6019 displayed on the second display unit 6009 or a keyboard 6021 (actually, a keyboard image displayed on the second display unit 6009) can be used to select an image or input characters. Of course, the first display unit 6007 may be a touch panel and the second display unit 6009 may be a display panel, or both the first display unit 6007 and the second display unit 6009 may be touch panels.

Moreover, the first housing 6001 and the second housing 6003 are connected by a hinge portion 6005, and the first housing 6001 and the second housing 6003 can be opened and closed. With such a configuration, when carrying the tablet terminal 6000, the first display portion 6007 incorporated in the first housing 6001 and the second display portion 6009 incorporated in the second housing 6003 are brought together, so that the surfaces (for example, a plastic substrate or the like) of the first display portion 6007 and the second display portion 6009 can be protected, which is preferable.

The first housing 6001 and the second housing 6003 may be configured to be separable by a hinge portion 6005 (so-called convertible type). Such a configuration is preferable because it broadens the range of use, for example, by placing the first housing 6001 vertically and the second housing 6003 horizontally.

In addition, the first camera 6013 and the second camera 6015 can also capture 3D images.

The tablet terminal 5000 and the tablet terminal 6000 may be configured to be able to transmit and receive information wirelessly. For example, the tablet terminal 5000 and the tablet terminal 6000 may be configured to be able to connect wirelessly to the Internet, etc., purchase desired information, and download it.

Furthermore, the tablet terminal 5000 and the tablet terminal 6000 can have a function of displaying various information (still images, videos, text images, etc.), a function of displaying a calendar, date, time, etc. on the display unit, a touch input function of touch inputting or editing information displayed on the display unit, a function of controlling processing by various software (programs), etc. Also, a detection device such as a light sensor that can optimize the brightness of the display according to the amount of external light, or a sensor that detects tilt such as a gyro or acceleration sensor may be built in.

By applying the semiconductor device described in the above embodiment to the display portion 5003 of the tablet terminal 5000, the first display portion 6007, and/or the second display portion 6009 of the tablet terminal 6000, a tablet terminal having stable electrical characteristics and little signal delay due to wiring resistance can be obtained.

This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

102 substrate

104 Gate electrode

104a first gate electrode

104b Second gate electrode

106 Gate insulating film

106a first gate insulating film

106b Second gate insulating film

108 Oxide semiconductor film

109a First metal film

109b Second metal film

109c Third metal film

110 Source electrode

110a first metal film

110b Second metal film

110c Third metal film

112 Drain electrode

112a First metal film

112b Second metal film

112c Third metal film

114a first insulating film

114b Second insulating film

115 Aluminum Film

116 Aluminum Oxide Film

118 Planarizing Insulating Film

141 Resist Mask

142 Resist Mask

145 oxygen

147 oxygen

150 Transistor

204 Gate electrode

204a First gate electrode

204b Second gate electrode

206 Gate insulating film

206a First gate insulating film

206b Second gate insulating film

209a First metal film

209b Second metal film

209c Third metal film

210 Source electrode

210a First metal film

210b Second metal film

210c Third metal film

212 Drain electrode

212a First metal film

212c Third metal film

232 Signal Line

241 Resist Mask

242 Resist Mask

250 Transistor

260 Signal Line Area

300 substrate

301 substrate

302 Pixel section

304 Source driver circuit section

306 Gate driver circuit section

308 FPC terminal

310 Signal Line

312 Sealing materials

316 FPC

350 Transistor

352 Transistor

360 Terminal Electrode

360a First metal film

360b Second metal film

360c Third Metal Film

364 Insulating film

366 Protective insulating film

368 Planarizing Insulating Film

370a Conductive film

370b Conductive film

380 Anisotropic Conductive Film

402 Liquid crystal element

404 Counter electrode

406 Liquid crystal layer

410 Insulating film

412 Insulating film

435 Spacer

450 Light emitting element

452 Electroluminescent Layer

454 Upper electrode

456 Partition wall

458 Filler

2700 E-books

2701 Chassis

2703 Chassis

2705 Display

2707 Display

2711 Shaft

2721 power supply

2723 Operation Keys

2725 speaker

2800 Chassis

2801 Chassis

2802 Display Panel

2803 speaker

2804 microphone

2805 Operation Keys

2806 Pointing Device

2807 Camera Lenses

2808 External connection terminal

2810 Solar Cell

2811 External memory slot

3001 Main unit

3002 Chassis

3003 Display

3004 keyboard

3021 Main unit

3022 stylus

3023 Display

3024 Operation buttons

3025 External Interfaces

3051 Main unit

3053 Eyepiece

3054 Operation switch

3056 battery

5000 Tablet devices

5001 Chassis

5003 Display

5005 Power button

5007 Front camera

5009 Rear camera

5011 External connection terminal

5013 External connection terminal

5015 icon

6000 Tablet devices

6001 Chassis

6003 Chassis

6005 Hinge part

6007 Display

6009 Display

6011 Power button

6013 camera

6015 camera

6017 Text Icon

6019 icon

6021 keyboard

9600 Television equipment

9601 Chassis

9603 Display

9605 stand