Wiring structure, method of forming the same thin film transistor, method of forming the same and display device

The present invention relates to a wiring structure used in a display device typified by a liquid crystal display device, a semiconductor device typified by ULSI, a method for forming a wiring structure, a thin film transistor, a method for forming a thin film transistor, a liquid crystal display device, and the like. With respect to such display devices.

In the field of display devices represented by liquid crystal display devices, the wiring length tends to increase in recent years due to the expansion of the display area. In addition, the development of monolithic peripheral circuit parts by incorporating additional functions such as a drive driver circuit and an in-pixel memory is also in progress. On the other hand, in the field of semiconductors represented by LSI and ULSI, studies are underway for further miniaturization to improve the degree of integration. There is also a demand for further improvement in operating speed. Against this background, in the fields of display devices and semiconductors, there is increasing interest in wiring having low resistivity and high electromigration resistance and stress migration resistance.

By the way, it is known that copper (Cu) has a lower specific resistance and higher electromigration resistance and stress migration resistance than aluminum (Al), which is generally used as a wiring material in the past. Therefore, copper is expected as a next-generation wiring material.

The copper wiring formed on the electronic device includes a main body made of copper and a copper alloy seed layer sandwiched between the main body and the electric device to improve the electromigration resistance between them. The ones that have been prepared are known. Copper alloy seed layers include copper, tin (Su), indium (In), zirconium (Zr), titanium (Ti), carbon (C), nitrogen (N), oxygen (O), chlorine (Cl), and It contains at least one element selected from the group consisting of sulfur (S) (see, eg, Patent Document 1).

Further, for copper that easily diffuses into silicon oxide, studies are being conducted to improve the diffusion of copper into silicon oxide by using a copper alloy containing magnesium (Mg) or aluminum (Al). .. That is, when a copper alloy film containing Mg or Al is formed on the silicon oxide layer and heat treatment is performed, magnesium oxide or aluminum oxide is produced at the interface between the copper alloy film and the silicon oxide layer. Magnesium oxide or aluminum oxide is said to have the effect of suppressing the diffusion of copper. Therefore, the copper alloy film as described above is considered to have a self-diffusion stopping ability (see, for example, Non-Patent Document 1).

In addition, silicon oxide (SiO)₂As a method of forming a copper wiring layer on a layer or a titanium nitride (TiN) layer, a method of forming a copper alloy film containing Mg on a silicon oxide layer or a titanium nitride layer and performing an annealing treatment is known. There is. As a result, MgO / Cu / MgO / SiO₂, And a composite layer such as MgO / Cu / MgO / TiN is formed (see, for example, Non-Patent Document 2).

Further, by forming a copper alloy containing titanium (Ti) on silicon oxide and annealing it, titanium oxide (TiO) is formed at the interface between the copper alloy and silicon oxide._X), And attempts have been made to suppress the diffusion of copper by this titanium oxide (see, for example, Non-Patent Document 3).<patcit num="1"><text>Japanese Unexamined Patent Publication No. 11-340229 (paragraphs 0010 to 0029, FIGS. 1 to 10)</text></patcit><nplcit num="1"><text>T.Suwwan de Felipe and 3 others Thin Solid Films 335 (1998) 49-53</text></nplcit><nplcit num="2"><text>WHLee and 12 others Applied Physics Letters Volume77, Number14 (2 October 2000) p.2192 ~ p2194</text></nplcit><nplcit num="3"><text>CJLiu, JSChen Applied Physics Letters Volume80, Number15 (15 April 2002) p.2678 ~ p.2680</text></nplcit>

<p> However, the technique described in Patent Document 1 has a problem that copper is easily diffused from the main body or the copper alloy seed layer to the electric device.</p><p> On the other hand, when the techniques described in Non-Patent Documents 1 to 3 are applied to wiring structures such as wirings and electrodes, there are the following problems. That is, the copper alloy has a higher resistivity than the copper alone. Therefore, forming the wiring structure from a copper alloy containing Mg, Ti, etc. has little merit in terms of reducing the resistance of the wiring structure. Moreover, since the difficulty of dry etching of RIE or the like in a copper alloy is the same as that of copper alone, it is difficult to form fine wiring.</p><p> In the present invention, although the main body of the wiring structure is mainly composed of copper, fine wiring can be formed, the specific resistance is low, copper is difficult to diffuse to the surroundings, and the wiring is attached to the substrate. It is an object of the present invention to provide a wiring structure having high adhesion strength, a method for forming a wiring structure, a thin film transistor, a method for forming a thin film transistor, and a display device having the wiring structure or the thin film transistor.</p>

<p> The wiring structure according to one embodiment of the present invention is a wiring structure provided on the surface to be processed of the substrate, and is a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component. It was formed by oxidizing a seed layer formed on the surface to be treated of the substrate and a metal for forming a metal oxide contained in the metal material, and was provided between the substrate and the seed layer. It includes a barrier layer and a wiring structure layer provided on the seed layer.</p><p> The wiring structure according to another embodiment of the present invention is a wiring structure provided on the surface to be processed of the substrate, and is a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component. A seed layer formed on the surface to be treated of the substrate, a copper-based wiring structure layer provided on the seed layer, and a metal for forming a metal oxide contained in the metal material. A barrier layer, which is formed by oxidizing the metal and is provided between the substrate and the seed layer to suppress the diffusion of copper from the wiring structure layer, and a wiring structure provided on the wiring structure layer. It includes a capping layer that suppresses the diffusion of copper from the body layer.</p><p> The wiring structure includes wiring, terminals, electrodes, and the like. As the substrate, it is preferable to use a substrate containing oxygen at least on or near the surface to be treated. As the substrate containing oxygen at least on or near the surface to be treated, for example, a substrate in which the entire substrate is formed of a compound containing oxygen can be used. Further, a substrate formed by forming a layer made of an oxygen-containing compound on an oxygen-free substrate may be used as the substrate. In this case, if the exposed surface of the layer made of the oxygen-containing compound is the surface to be treated, the condition that oxygen is contained at least in or near the surface to be treated is satisfied.</p><p> As the substrate, for example, glass, quartz glass, ceramics, a silicon wafer, or the like can be used alone. Further, as the substrate, for example, a substrate made of glass, quartz glass, ceramics, a silicon wafer, a resin, or the like on which an insulating film or a semiconductor layer is formed may be used. Further, as the substrate, for example, a substrate obtained by laminating a plurality of insulating layers or semiconductor layers on the substrate may be used. Further, as the substrate, a circuit element or a substrate formed by forming a part of the circuit element on the substrate can also be used. The circuit element includes, for example, a thin film transistor and the like.</p><p> A metal material containing copper as a main component refers to a metal material in which approximately 80 at% or more of the total metal material is copper. The ratio of the metal for forming a metal oxide is preferably 0.5 at% to 20 at%, more preferably 2 at% to 10 at% with respect to the entire metal material. The metal oxide-forming metal preferably contains at least one of magnesium, titanium, aluminum, and chromium.</p><p> The wiring structure layer containing copper as a main component refers to a metal material in which approximately 90 at% or more of copper is used as a whole. Preferably, the wiring structure layer is formed of copper alone.</p><p> According to the wiring structure of the present invention, since the seed layer is provided and the wiring structure layer is provided on the seed layer, the main body portion (seed layer and wiring structure layer) of the wiring structure is formed. Although it is mainly composed of copper, it is possible to form fine wiring. Moreover, since the main body portion contains copper as a main component, the specific resistance is low. Further, since a barrier layer formed by oxidizing the metal for forming a metal oxide contained in the metal material is provided between the substrate and the seed layer, it is difficult for copper to diffuse from the main body portion to the surroundings, and It is possible to increase the adhesion strength of the main body portion to the substrate.</p><p> Further, by providing the capping layer on the wiring structure layer as in the wiring structure according to the other embodiment of the present invention, the diffusion of copper from the main body portion can be further suppressed.</p><p> The method for forming the wiring structure according to one embodiment of the present invention includes a step of forming a copper alloy seed layer on a substrate with a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component. Using the copper alloy seed layer as a seed, a step of forming a wiring structure layer containing copper as a main component on the copper alloy seed layer in a predetermined pattern, and oxidizing the metal for forming a metal oxide to form the substrate. Includes a step of forming a barrier layer on top.</p><p> A method for forming a wiring structure according to another embodiment of the present invention includes a step of forming a barrier metal layer capable of suppressing the diffusion of copper on a substrate, and a metal on copper as a main component on the barrier metal layer. A step of forming a copper alloy seed layer from a metal material mixed with a metal for forming an oxide, and a wiring structure layer containing copper as a main component on the copper alloy seed layer using the copper alloy seed layer as a seed. It includes a step of forming a predetermined pattern and a step of oxidizing the metal for forming a metal oxide to form a barrier layer on the barrier metal layer.</p><p> According to the method for forming a wiring structure of the present invention, since the wiring structure layer is formed on the copper alloy seed layer using the copper alloy seed layer as a seed, fine wiring can be formed. Moreover, the remaining layer after the barrier layer is formed from the copper alloy seed layer has a lower concentration of the metal for metal oxide formation than the initial copper alloy seed layer. Therefore, the remaining layer after forming the barrier layer from the copper alloy seed layer has a lower resistivity than the initial copper alloy seed layer. Since the remaining layer after forming the barrier layer from the copper alloy seed layer forms the main body portion of the wiring structure together with the wiring structure layer, according to the method for forming the wiring structure of the present invention, the main body portion of the main body portion. A wiring structure having a low specific resistance can be obtained. Further, a barrier layer formed by oxidizing the metal for forming a metal oxide contained in the metal material is formed on the substrate. Therefore, in the wiring structure formed by the present invention, copper is unlikely to diffuse from the main body portion to the surroundings, and the adhesion strength of the main body portion to the substrate is high.</p><p> Further, by providing the barrier metal layer on the substrate as in the method for forming the wiring structure according to another embodiment of the present invention, the diffusion of copper from the main body portion can be further suppressed.</p><p> The thin film of the present invention has a source region, a conductive semiconductor layer having a drain region provided apart from the source region, a source electrode electrically connected to the source region, and electricity with the drain region. A thin film comprising a drain electrode to be specifically connected, a gate insulating film, and a gate electrode provided above a region between the source region and the drain region via the gate insulating film. At least one of the source region and the drain region has a surface to be treated, and a barrier metal layer provided so as to be in contact with at least one of the source region and the drain region, and a metal in copper as a main component. A seed layer formed of a metal material mixed with a metal for forming an oxide and provided on the surface to be treated, a wiring structure layer containing copper as a main component provided on the seed layer, and the metal. A barrier layer formed by oxidizing a metal for forming a metal oxide contained in a material and provided between the barrier metal layer and the seed layer, and a wiring structure provided on the wiring structure layer. It includes a capping layer that suppresses the diffusion of copper from the layer.</p><p> According to the thin film transistor of the present invention, it is possible to form a source electrode and a drain electrode by providing a wiring structure layer on the seed layer. Therefore, it is possible to obtain a thin film transistor provided with a fine source electrode and a fine drain electrode. Moreover, since the seed layer and the wiring structure layer are mainly composed of copper, it is possible to reduce the specific resistances of the source electrode and the drain electrode. Further, since a barrier layer formed by oxidizing the metal for forming a metal oxide contained in the metal material is provided between the substrate and the seed layer, copper does not easily diffuse to the surroundings and adheres to the substrate. A source electrode and a drain electrode having high strength can be obtained. Moreover, since the barrier metal layer is provided on the semiconductor layer and the capping layer is provided on the wiring structure layer, the diffusion of copper from the source electrode and the drain electrode can be further suppressed. Further, the source region and the source electrode can be electrically contacted with each other, or the drain region and the drain electrode can be electrically contacted with each other via the barrier metal layer.</p><p> The method for forming a thin film transistor according to the present invention includes a step of forming a semiconductor layer, a step of forming a gate insulating film on the semiconductor layer, and a step of forming a metal oxide on copper as a main component on the gate insulating film. The process of forming a copper alloy seed layer with a metal material mixed with metal, A step of forming a resin layer having a groove on the copper alloy seed layer to expose a part of the copper alloy seed layer in a predetermined pattern, and a region exposed by the groove on the copper alloy seed layer. A step of forming a wiring structure layer having a peripheral portion and containing copper as a main component, a step of forming an etching protective layer on the wiring structure layer, and a step of forming the etching protective layer and then the resin layer. The step of removing the copper alloy seed layer, the step of etching the copper alloy seed layer along the peripheral portion of the wiring structure layer, and the step of injecting the first impurity into the semiconductor layer using the etching protection layer as a mask. A step of removing the etching protective layer, and a step of injecting a second impurity having a concentration lower than that of the first impurity into the semiconductor layer using the wiring structure layer as a mask after removing the etching protective layer. A step of forming a capping layer capable of suppressing the diffusion of copper from the wiring structure layer on the wiring structure layer, and a barrier layer on the gate insulating film by oxidizing the metal for forming a metal oxide. Includes a step of producing.</p><p> According to the method for forming a thin film transistor of the present invention, the gate electrode can be finely formed because the wiring structure layer is formed on the copper alloy seed layer using the copper alloy seed layer as a seed. Moreover, since the concentration of the metal for metal oxide formation is lower in the remaining layer after the barrier layer is formed from the copper alloy seed layer than in the initial copper alloy seed layer, the specific resistance is also lowered accordingly. .. The remaining layer after the barrier layer is formed from the copper alloy seed layer forms the main body portion of the gate electrode together with the wiring structure layer. Therefore, according to the present invention, it is possible to obtain a thin film transistor provided with a gate electrode having a low resistivity. Further, since a barrier layer formed by oxidizing the metal for forming a metal oxide contained in the metal material is generated on the substrate, it is difficult for copper to diffuse from the main body portion to the surroundings, and to the substrate of the main body portion. A gate electrode having high adhesion strength can be obtained. Moreover, the first impurity can be injected into the semiconductor layer using the etching protection layer as a mask, and the second impurity can be injected into the semiconductor layer using the wiring structure layer as a mask. Therefore, it is not necessary to form a mask when injecting the first and second impurities into the semiconductor. Therefore, the step of forming the mask can be omitted.</p>

Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 5. In the present embodiment, a mode in which the display device of the present invention is applied to a liquid crystal display device, a mode in which the wiring structure of the present invention is applied to a scanning line included in the display device, and a method for forming the wiring structure of the present invention. One form will be described.

1 to 3 disclose a liquid crystal display device 1 as a display device. Note that FIG. 1 shows an example of an equivalent circuit of the active matrix type liquid crystal display device 1. The liquid crystal display device 1 includes a pair of transparent substrates 2, 3, a liquid crystal layer 4, a base insulating film 5, a pixel electrode 6, a scanning line 7 as a wiring structure, a signal line 8, a counter electrode 9, and a thin film transistor (Thin Film Transistor). (Hereinafter referred to as TFT) 10, scanning line drive circuit 11, signal line drive circuit 12, liquid crystal controller 13 and the like are provided.

As the pair of transparent substrates 2 and 3, for example, a pair of glass plates can be used. These transparent substrates 2 and 3 are joined via a frame-shaped sealing material (not shown). The liquid crystal layer 4 is provided in a region between the pair of transparent substrates 2 and 3 surrounded by the sealing material.

One of the pair of transparent substrates 2 and 3, for example, the inner surface of the transparent substrate 3 on the rear side (lower side in FIGS. 2 and 3) has an underlying insulating film 5, a plurality of pixel electrodes 6, and a plurality of scanning lines 7. , A plurality of signal lines 8, a plurality of TFTs 10, and the like are provided.

As the underlying insulating film 5, for example, silicon oxide, silicon nitride, or the like can be used. The pixel electrode 6 is made of, for example, ITO or the like. As shown in FIG. 2, the TFT 10 is provided on the underlying insulating film 5. The TFT 10 includes a gate electrode 20, a gate insulating film 21, a semiconductor layer 22, a source electrode 23, and a drain electrode 24 as a wiring structure. Each TFT 10 is provided so as to have a one-to-one correspondence with each pixel electrode 6.

The plurality of scanning lines 7 are aligned along the row direction of the pixel electrodes 6 provided in a matrix in the row direction and the column direction (the horizontal direction in FIG. 1 and the direction extending from the front side of the paper surface to the back side of the paper surface in FIG. 3). , It is provided on the underlying insulating film 5. These scanning lines 7 are electrically connected to the gate electrode 20 included in the TFT 10. Further, each end of each of these scanning lines 7 is electrically connected to the scanning line driving circuit 11.

The plurality of signal lines 8 are provided on the gate insulating film 21 so as to be along the column direction (vertical direction in FIG. 1) of the pixel electrodes 6 provided in a matrix in the row direction and the column direction. These signal lines 8 are electrically connected to one of the source electrode 23 or the drain electrode 24 included in the corresponding TFT 10. Each end of each of these signal lines 8 is electrically connected to the signal line drive circuit 12.

As the TFT10, for example, a bottom gate type amorphous silicon TFT can be adopted. The gate electrode 20 is provided on the underlying insulating film 5. The gate insulating film 21 is provided so as to cover the gate electrode 20, the scanning line 7, and the underlying insulating film 5. As the gate insulating film 21, for example, silicon oxide, silicon nitride, or a laminated film of silicon oxide and silicon nitride can be used. The semiconductor layer 22 includes a non-doped amorphous silicon layer (non-doped a-Si layer) 22a forming a channel region 26a and n as a contact layer.⁺Type amorphous silicon layer (n⁺It has a type a-Si layer) 22b. The non-doped a-Si layer 22a is located above the gate electrode 20 and is provided on the gate insulating film 21. n⁺The mold a-Si layer 22b is provided on the non-doped a-Si layer 22a. This n⁺The mold a-Si layer 22b has a groove 25 that partially exposes the non-doped a-Si layer 22a. This n⁺Of the mold a-Si layer 22b, one side divided by the groove 25 is the source region 26b, and the other side is the drain region 26c.

The source electrode 23 and the drain electrode 24 are n⁺N so as to contact the source region 26b and drain region 26c of the type a-Si layer 22b, respectively.⁺It is provided on the mold a-Si layer 22b. One of the source electrode 23 and the drain electrode 24, for example, the drain electrode 24, is electrically connected to the corresponding signal line 8.

The pixel electrode 6 is provided on the gate insulating film 21 so as to be electrically connected to the source electrode 23, which is the other of the source electrode 23 and the drain electrode 24. The passivation layer 27 having an opening 27a for exposing the pixel electrode 6 is provided so as to cover the source electrode 23, the drain electrode 24, the signal line 8, and the gate insulating film 21.

As shown in FIG. 3, the scanning line 7 as a wiring structure includes a seed layer 30, a barrier layer 32, a copper wiring layer 33 as a wiring structure layer, and a capping layer 35. The seed layer 30 is made of a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component, and is provided on the upper surface of the underlying insulating film 5 (the surface to be treated 70a of the substrate 70 to be described later). The barrier layer 32 is formed by oxidizing the metal for forming a metal oxide contained in the metal material, and is between the underlying insulating film 5 and the seed layer 30 (the interface between the substrate 70 and the seed layer 30 described later). It is provided in. The barrier layer 32 also acts to improve the adhesion between the copper wiring layer 33 and the underlying insulating film 5. The copper wiring layer 33 made of a simple substance of copper is provided on the seed layer 30. That is, these are laminated in the order of the barrier layer 32, the seed layer 30, and the copper wiring layer 33 on the underlying insulating film 5 (on the substrate 70 described later). On the copper wiring layer 33, a capping layer 35 that suppresses the diffusion of copper from the copper wiring layer 33 is provided.

The scanning line driving circuit 11 and the signal line driving circuit 12 are connected to the liquid crystal controller 13, respectively. The liquid crystal controller 13 receives, for example, an image signal and a synchronization signal supplied from the outside, and receives a pixel video signal Vpix and a vertical scanning control signal Y._CT, And horizontal scan control signal X_CTOccurs.

On the inner surface of the transparent substrate 2 on the front side (upper side in FIGS. 2 and 3), a single film-like transparent counter electrode 9 facing the plurality of pixel electrodes 6 is provided. The counter electrode 9 is made of, for example, ITO or the like. A color filter is provided on the inner surface of the transparent substrates 2 and 3 on the front side so as to correspond to a plurality of pixel regions in which the plurality of pixel electrodes 6 and the counter electrodes 9 face each other, and in the region between the pixel regions. A light-shielding film may be provided correspondingly.

A polarizing plate (not shown) is provided on the outer surfaces of the pair of transparent substrates 2 and 3. Further, when the liquid crystal display device 1 is a transmissive type, a surface light source (not shown) is provided behind the transparent substrate 3 on the rear side. The liquid crystal display device 1 may be a reflective type or a semi-transmissive reflective type.

Hereinafter, the process of forming a film on the inner surface of the transparent substrate 3 on the rear side will be described.

First, the substrate 70 on which the scanning line 7 is formed is prepared as follows. The step of preparing the substrate 70 on which the scanning line 7 is formed is also a part of the step of forming a film on the inner surface of the transparent substrate 3 on the rear side.

First, a glass plate having a thickness of 0.7 mm is prepared as the transparent substrate 3 on the rear side. A silicon oxide layer as the underlying insulating film 5 is formed on the transparent substrate 3. In the present embodiment, the layer thickness of the underlying insulating film 5 is 400 nm. This can be achieved by depositing silicon oxide on the transparent substrate 3 so as to have a thickness of 400 nm by using a CVD method (for example, PE-CVD method (Plasma Enhanced Chemical Vapor Deposition)). The gate electrode 20 is formed on the underlying insulating film 5. This can be formed by forming a metal layer to be the gate electrode 20 and etching the metal layer into a predetermined pattern.

The scanning line 7 and the gate electrode 20 are formed on the underlying insulating film 5 so as to be electrically connected to each other. The substrate 70 on which the underlying insulating film 5 is formed on the transparent substrate 3 is the substrate 70 on which the scanning line 7 and the gate electrode 20 are formed. That is, the substrate 70 forming the scanning line 7 and the gate electrode 20 includes the transparent substrate 3 and the underlying insulating film 5, and the upper surface of the underlying insulating film 5 is the surface to be processed 70a of the substrate 70. In the present embodiment, the underlying insulating film 5 is formed of silicon oxide. Therefore, the substrate 70 contains oxygen in the surface to be processed 70a and its vicinity (in the underlying insulating film 5).

Next, the scanning line 7 is formed on the substrate 70. First, a metal material prepared by mixing a metal for forming a metal oxide with copper as a main component is prepared. In the present embodiment, as the metal material, a copper alloy metal material containing 2 at% of titanium as a metal for forming a metal oxide in copper is used.

As shown in FIG. 4A, a copper alloy seed layer 31 made of the metal material is formed on the surface to be treated 70a of the substrate 70, that is, on the underlying insulating film 5. The copper alloy seed layer 31 can be formed by forming a film of the metal material by a sputtering method. In this embodiment, the layer thickness of the copper alloy seed layer 31 is 30 nm. Of course, the formation of the copper alloy seed layer 31 is not limited to the sputtering method, and a vapor deposition method or the like may be used.

Next, as shown in FIG. 4 (B), a photosensitive resin mask (hereinafter referred to as a photoresist mask) 34 as a resin layer is formed on the copper alloy seed layer 31 by using PEP. The photoresist mask 34 has a groove 34a that exposes a part of the copper alloy seed layer 31 to a predetermined pattern. The pattern of the groove 34a is the wiring pattern of the scanning line 7.

The oxide film (natural oxide film, etc.) formed in the region exposed by the groove 34a of the photoresist mask 34 in the upper portion 31b of the copper alloy seed layer 31 is removed.

After that, as shown in FIG. 4 (C), in the region exposed by the groove 34a of the photoresist mask 34 in the upper portion 31b of the copper alloy seed layer 31, the copper alloy seed layer 31 is used as the core and the copper alone is used. The copper wiring layer 33 is formed. In the present embodiment, the layer thickness of the copper wiring layer 33 is 400 nm. The simple substance of copper is substantially pure copper, and a small amount of impurities can be mixed in. By doing so, the copper wiring layer 33, which is the main body portion of the scanning line 7, can be selectively formed on the copper alloy seed layer 31.

The copper wiring layer 33 can be formed by electroless plating copper on the copper alloy seed layer 31, for example, so as to fill the groove 34a of the photoresist mask 34. In the electroless plating method , copper is selectively deposited on the copper alloy seed layer 31, so that there is an advantage that no catalytic treatment is required. Further, in the electroless plating method, even if the thickness of the copper wiring layer 33 is thin, it is possible to suppress the non-uniformity of the film thickness distribution, which is a problem when applied to a large area substrate such as the liquid crystal display device 1. Moreover, the adhesion of the scanning line 7 to the substrate 70 can be improved. The copper wiring layer 33 may be formed by using an electrolytic plating method instead of the electroless plating method.

As shown in FIG. 4 (D), the photoresist mask 34 is removed using a stripping solution or the like. When removing the photoresist mask 34, an ashing process, which is a dry process, may be used in combination. When this ashing treatment is performed, the exposed portion of the copper wiring layer 33 and the exposed portion of the copper alloy seed layer 31 may be oxidized. In such a case, it is desirable to add a step of removing the oxide film formed on the exposed portion after the ashing treatment.

As shown in FIG. 5 (E), a region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31 is etched and removed along the peripheral portion 33a of the copper wiring layer 33. Wet etching is used as the etching method. As the wet etching solution, for example, a solution of cupric chloride-hydrochloric acid system, ferric chloride system, sulfuric acid-hydrogen peroxide solution system, percaoso-sulfuric acid-potassium hydrogen hydrogen system or the like can be used.

By the way, when a wiring made of copper is formed by wet etching a copper layer using a resist mask, side etching occurs due to isotropic etching, and it is difficult to form fine wiring. On the other hand, in the present embodiment, the region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31 is removed by etching. As described above, the seed layer 30 is sufficiently thinner than the copper wiring layer 33, and is etched along the peripheral portion 33a of the copper wiring layer 33, so that etching is easy. Therefore, in this embodiment, fine wiring can be formed.

When the copper alloy seed layer 31 is etched, the peripheral portion 33a and the upper portion 33b of the copper wiring layer 33 are also partially etched at the same time. Therefore, it is preferable that the copper wiring layer 33 is formed to be one size larger and thicker in consideration of the amount of etching of the copper alloy seed layer 31 at the same time in the process of FIG. 4D. Further, in order to reduce the difference in etching rate between the copper alloy seed layer 31 and the copper wiring layer 33, it is preferable to perform an annealing treatment before etching.

Further, as shown in FIG. 5 (F), a capping layer 35 that suppresses the diffusion of copper from the copper wiring layer 33 and the copper alloy seed layer 31 is formed on the copper wiring layer 33 and the copper alloy seed layer 31. .. In the present embodiment, for example, Co is covered so as to cover the exposed surfaces of the copper wiring layer 33 and the copper alloy seed layer 31 (the upper portion 33b and the peripheral portion 33a of the copper wiring layer 33, and the peripheral portion 31a of the copper alloy seed layer 31). -A capping layer 35 composed of WB, Co-B, Ni-B, etc. is formed. In the present embodiment, the layer thickness of the capping layer 35 is 50 nm. The capping layer 35 can be formed, for example, by using an electroless plating method. At this time, the capping layer 35 is selectively formed only on the exposed surfaces of the copper wiring layer 33 and the seed layer 30, and is not formed on the gate insulating film 21.

The capping layer 35 can be plated without Pd catalyst treatment by using dimethylamine boron as a reducing agent, such as Co-WB, Co-B, Co-P, Ni-B, Ni-P, Ni-WP, etc. It is desirable, but not limited to, to form a metal material such as the above by an electroless plating method. For the capping layer 35, a metal material suitable for plating for forming on the copper wiring layer 33 by a plating method may be selected, or catalyst treatment such as Pd may be performed.

Next, for example, heat treatment (annealing treatment) at about 350 ° C. is performed. As a result, the titanium contained in the copper alloy seed layer 31 is diffused and oxidized by, for example, oxygen contained in the underlying insulating film 5 or oxygen gas in the air, and as shown in FIG. 5 (G), the substrate is oxidized. A barrier layer 32 made of titanium oxide (TiOx) is formed at the interface with the insulating film 5. Further, as a result, the copper alloy seed layer 31 is substantially made of copper, and at the interface between the seed layer 30 which is the main body portion of the scanning line 7 together with the copper wiring layer 33 and the seed layer 30 and the base insulating film 5. It is formed into two layers, a barrier layer 32 that suppresses the diffusion of copper from the seed layer 30 and the copper wiring layer 33 into the underlying insulating film 5. As a result, the scanning line 7 is formed.

Subsequently, the gate insulating film 21 is formed so as to cover the gate electrode 20 and the scanning line 7. The semiconductor layer 22 is formed on the gate insulating film 21. Specifically, a non-doped a-Si layer 22a is formed on the gate insulating film 21, and n is formed on the non-doped a-Si layer 22a.⁺A mold a-Si layer 22b is formed. Non-doped a-Si layer 22a and n⁺After patterning the mold a-Si layer 22b, n⁺The source electrode 23 and the drain electrode 24 are formed on the mold a-Si layer 22b. This can be achieved by forming an aluminum layer to be the source electrode 23 and the drain electrode 24 and etching the aluminum layer into a predetermined pattern. After that, the source electrode 23 and the drain electrode 24 are masked, and n between these electrodes 23 and 24.⁺Etch the mold a-Si layer 22b. From the above, TFT10 is formed.

A signal line 8 is formed on the gate insulating film 21 so as to be electrically connected to one of the source electrode 23 and the drain electrode 24, for example, the drain electrode 24. The pixel electrode 6 is formed so as to be electrically connected to the source electrode 23 of each TFT 10. A passivation layer 27 is formed so as to cover the TFT 10, the gate insulating film 21, and the pixel electrode 6. Subsequently, an opening 27a for exposing the pixel electrode 6 is formed in the passivation layer 27. As described above, the film forming step on the transparent substrate 3 on the rear side is completed.

As described above, the scanning line 7 of the present embodiment is a wiring structure provided on the surface to be processed 70a (on the underlying insulating film 5) of the substrate 70. The scanning line of the present embodiment is formed of a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component, and is provided with a seed layer 30 provided on the surface to be treated 70a of the substrate 70, and the seed layer 30. The copper wiring layer 33 provided on the seed layer 30 is formed by oxidizing the metal for forming a metal oxide contained in the metal material, and is provided between the substrate 70 and the seed layer 30 to form the copper wiring layer 33. It is provided with a barrier layer 32 that suppresses the diffusion of copper from the metal.

Further, the method of forming the scanning line 7 of the present embodiment includes a step of forming a copper alloy seed layer 31 on the substrate 70 with a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component. A step of forming a copper wiring layer 33 in a predetermined pattern on the copper alloy seed layer 31 using the copper alloy seed layer 31 as a seed, and a barrier layer 32 at the interface with the substrate 70 by oxidizing the metal for forming a metal oxide. It is provided with a process of generating.

Therefore, according to the present embodiment, even though the copper wiring layer 33 and the seed layer 30, which are the main body portions of the scanning line 7, are mainly composed of copper, fine wiring is possible and the specific resistance is low. It is possible to obtain a scanning line 7 in which copper is difficult to diffuse to the surroundings and a high adhesion strength to the substrate, and a method for forming the scanning line 7.

That is, in the present embodiment, the copper wiring layer 33 is selectively formed on the copper alloy seed layer 31, and the region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31 is removed by etching. , The scanning line 7 is formed in a desired shape. Since the copper alloy seed layer 31 is sufficiently thinner than the copper wiring layer 33 and may be etched along the peripheral portion 33a of the copper wiring layer 33, etching is easy. Therefore, in the present embodiment, it is possible to realize fine wiring of 1 μm or less, which is difficult to form by wet etching a copper layer having a thickness of about 33 copper wiring layers.

Furthermore, when the damascene method including the CMP process is applied to the wiring structure of the display device, the throughput of the process is not good. Further, when the method of wet-etching a copper layer having a thickness of about 33 copper wiring layers is applied to the wiring structure of the display device, similarly, a step of removing unnecessary parts after forming the copper layer on the entire surface of the substrate. Therefore, it is difficult to form fine wiring. In addition, since the area of the copper alloy layer used as wiring and the area required to form the copper layer is very small compared to the area of the entire substrate, most of the formed copper alloy layer and copper layer are removed. It will be discarded. As a result, the utilization efficiency of copper as a raw material becomes extremely poor, and the product price also rises due to the effect of high cost.

On the other hand, in the present embodiment, since the copper wiring layer 33 having a predetermined pattern can be selectively formed on the copper alloy seed layer 31, the CMP step is unnecessary. Therefore, compared with the conventional technique and the method of wet-etching a copper layer having a thickness of about 33 copper wiring layers, the utilization efficiency of copper is high and the throughput is good. Moreover, since the manufacturing cost can be suppressed, the product price can be reduced.

Further, conventionally, a CMP device corresponding to a large-diameter wafer size of about 12 inches in diameter has been developed, but a display device using a glass plate having a larger area than the above wafer and not having good accuracy such as flatness is manufactured. The CMP device corresponding to the above has not been put into practical use. Therefore, in the conventional technique, it is difficult to apply full polishing by a CMP device to a large-area glass substrate to form copper wiring.

On the other hand, in the present embodiment, since the CMP step is not required, a wiring structure such as a scanning line 7 can be formed on the substrate regardless of the area of the substrate. That is, the present embodiment can also be applied to a display device using a glass substrate having a large area.

Further, in the present embodiment, the copper alloy seed layer 31 having a higher specific resistance than the copper alone and the copper wiring layer 33 substantially made of the copper alone are formed separately. Therefore, by increasing the layer thickness ratio of the copper wiring layer 33 to the copper alloy seed layer 31, the resistivity of the scanning line 7 can be reduced to substantially the same as that of copper alone. Therefore, the scanning line 7 having a low specific resistance can be obtained. Moreover, the copper alloy seed layer 31 after the barrier layer 32 is deposited becomes a seed layer 30 substantially made of copper. Therefore, since the seed layer 30 functions as a part of the wiring (the main body portion), the contribution of the use of the copper alloy seed layer 31 to the increase in the specific resistance of the scanning line 7 can be small.

Further, since the copper alloy seed layer 31 is a layer made of an alloy containing copper, no catalytic treatment is required when the copper wiring layer 33 is formed by electroless plating. Moreover, by performing the heat treatment, a barrier layer 32, which is a metal oxide layer having a barrier property that suppresses the diffusion of copper, can be formed at the interface with the substrate 70. Therefore, the barrier layer 32 can suppress the diffusion of copper from the seed layer 30 and the copper wiring layer 33 to the substrate 70.

Further, it is generally known that a layer made of copper has a low adhesion to an insulator layer or a semiconductor layer. Therefore, when the copper layer is provided on the insulator layer or the semiconductor layer, the adhesion layer is usually formed of a metal having relatively good adhesion to the insulator or semiconductor such as nickel, chromium, titanium, tantalum, molybdenum, etc. However, the copper layer is fixed on the insulator layer and the semiconductor layer through the adhesive layer.

On the other hand, in the present embodiment, metal oxidation having relatively good adhesion to a metal, an insulator, or a semiconductor between the main body portion (seed layer 30 and copper wiring layer 33) of the scanning line 7 and the substrate 70. A physical layer, that is, a barrier layer 32 is interposed. Therefore, even if the adhesion layer as described above is omitted, the main body portion (seed layer 30 and copper wiring layer 33) of the scanning line 7 can be satisfactorily fixed on the substrate 70. As described above, according to the present embodiment, the scanning line 7 having high adhesion strength to the substrate 70 can be obtained.

Moreover, since titanium is used as the metal for forming the metal oxide, TiO which becomes the barrier layer 32 at the interface between the substrate 70 and the seed layer 30._XLayers can be created. TiO_XThe layer has copper diffusion suppression, and has good adhesion to the underlying insulating film 5 and copper (the main body portion of the scanning line 7).

Further, the method for forming the scanning line 7 of the present embodiment further includes a step of forming the capping layer 35 that suppresses the diffusion of copper from the copper wiring layer 33 on the copper wiring layer 33. Therefore, it is possible to suppress the diffusion of copper from the copper wiring layer 33 to the gate insulating film 21 and the a-Si layer 22a side. Further, as a result, the copper wiring layer 33 is surrounded by the barrier layer 32 that functions as the copper diffusion prevention layer and the capping layer 35, so that a more reliable scanning line 7 can be obtained.

Further, in the method for forming the scanning line 7 of the present embodiment, a substrate 70 is prepared as the substrate 70, which contains oxygen in or near the region corresponding to at least the region forming the copper alloy seed layer 31 on the surface thereof. It has more processes. Therefore, the oxygen contained in the substrate 70 can be used to oxidize the metal for forming a metal oxide contained in the copper alloy seed layer 31. Therefore, the barrier layer 32 can be satisfactorily formed on the substrate 70 without supplying oxygen from the outside.

Further, in the method for forming the scanning line 7 of the present embodiment, since the step of forming the barrier layer 32 includes a step of performing an annealing treatment, the barrier layer 32 can be satisfactorily formed on the substrate 70.

Further, in the method for forming the scanning line 7 of the present embodiment, after the step of forming the copper wiring layer 33 on the copper alloy seed layer 31 in a predetermined pattern, the copper wiring layer 33 is joined to the copper wiring layer 33 of the copper alloy seed layer 31. It includes a step of etching a region other than the region. As described above, the seed layer 30 is sufficiently thinner than the copper wiring layer 33, and may be etched along the peripheral portion 33a of the copper wiring layer 33. Therefore, the etching of the seed layer 30 is easier than the etching of the copper wiring layer 33. In this way, after forming the copper wiring layer 33 on the copper alloy seed layer 31 in a predetermined pattern, the scanning line is etched by etching a region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31. 7 can be selectively and easily formed.

In addition, in the method for forming the scanning line 7 of the present embodiment, the photoresist mask 34 as a resin layer having a groove 34a on the copper alloy seed layer 31 that exposes a part of the copper alloy seed layer in a predetermined pattern. The step of forming the copper wiring layer 33 having the peripheral portion 33a is further provided in the region exposed by the groove 34a on the copper alloy seed layer 31. Thereby, the copper wiring layer 33 can be formed on the copper alloy seed layer 31 in a desired pattern.

Further, a method of forming the copper wiring layer 33 on the copper alloy seed layer 31 in a predetermined pattern using the photoresist mask 34 (in the present embodiment, the copper wiring layer 33 is selected on the copper alloy seed layer 31 by the plating method). In the method of forming the wiring structure by combining the method of forming the wiring structure and the etching of the copper alloy seed layer 31 by wet etching), the pattern of the scanning line 7 is determined by the photoresist mask 34. Therefore, in the present embodiment, the pattern of the scanning line 7 can be drawn by the region not masked by the photoresist mask 34. By using this method, the scanning lines 7 can be selectively formed by a relatively simple process.

Moreover, in the method for forming the scanning line 7 of the present embodiment, the CMP step required by the so-called damascene method, the copper diffusion prevention layer forming step required between the substrate and the seed layer, and the metal layer are embedded. There is no need for an etching process or the like to form a groove for this purpose. Further, in the CMP process in the damascene method, since an abrasive (slurry) is used, it is necessary to clean the abrasive and the object to be polished (including metal ions), but in this embodiment, which does not require the CMP process. , This cleaning step is also unnecessary. Moreover, there is no foreign matter mixed in when polishing the CPM. Further, in the method for forming the scanning line 7 of the present embodiment, the number of steps can be reduced as compared with the damascene method, so that the manufacturing cost can be reduced.

Although the present embodiment has been described by taking the scanning line 7 as an example of the wiring structure, the wiring structure and the method of forming the wiring structure of the present invention are not limited to the scanning line 7, and the signal line or the like. It can be widely applied to various other wirings, electrodes, terminals and the like.

In the first embodiment described above, a wiring structure having a capping layer 35 is used, but the gate insulating layer is composed of a layer having diffusion suppression performance against copper such as silicon nitride, or is one of the layers. Therefore, it is also possible to apply a wiring structure that does not have the capping layer 35.

Hereinafter, the second embodiment of the present invention will be described with reference to FIGS. 6 to 8.

In the present embodiment, in the present embodiment, one embodiment in which the display device of the present invention is applied to a liquid crystal display device, one embodiment in which the wiring structure of the present invention is applied to a TFT gate electrode included in the display device, and the wiring of the present invention. One form of the structure forming method and one form of the TFT forming method of the present invention will be described.

The TFT 10 is a top-gate polysilicon TFT (n-type TFT having an LDD structure), and includes a gate electrode 60, a gate insulating film 61, a semiconductor layer 62, a source electrode 63, and a drain electrode 64. As shown in FIG. 6, the semiconductor layer 62 is provided on the underlying insulating film 5. The semiconductor layer 62 has a channel region 66a made of polysilicon, a source region 66b and a drain region 66c, which are made by doping polysilicon with impurities and have lower resistance than the channel region 66a. The gate insulating film 61 is provided so as to cover the semiconductor layer 62 and the underlying insulating film 5. As the gate insulating film 61, for example, silicon oxide (SiO)₂) Etc. can be used. The gate electrode 60 is provided on the gate insulating film 61. The scanning line 7 is formed integrally with the gate electrode 60.

The interlayer insulating layer 67 is provided so as to cover the gate electrode 60, the scanning line 7, and the gate insulating film 61. The interlayer insulating layer 67 is, for example, silicon oxide (SiO).₂), Silicon nitride (SiNx) and the like can be used. The gate insulating film 61 and the interlayer insulating layer 67 have contact holes 61a and 67a that expose a part of the source region 66b and the drain region 66c of the semiconductor layer 62.

The source electrode 63 is provided on the interlayer insulating layer 67 so as to be electrically connected to the source region 66b via the contact holes 61a and 67a. The drain electrode 64 is provided on the interlayer insulating layer 67 so as to be electrically connected to the drain region 66c via the contact holes 61a and 67a. One of the source electrode 63 and the drain electrode 64, for example, the drain electrode 64, is electrically connected to the corresponding signal line 8. That is, although not shown in FIG. 6, the signal line 8 is provided on the interlayer insulating layer 67 so as to be electrically connected to the corresponding drain electrode 64.

The passivation layer 68 is provided so as to cover the source electrode 63, the drain electrode 64, the signal line 8, and the interlayer insulating layer 67. A flattening layer 69 is provided on the passivation layer 68. The passivation layer 68 and the flattening layer 69 each have contact holes 68a and 69a for electrically connecting the pixel electrode 6 to the source electrode 63, which is the other of the source electrode 63 and the drain electrode 64. .. The pixel electrode 6 is provided on the flattening layer 69 so as to come into contact with the source electrode 63 via the contact holes 68a and 69a.

The gate electrode 60 as a wiring structure includes a seed layer 30, a barrier layer 32, a copper wiring layer 33 as a wiring structure layer, and a capping layer 35. The seed layer 30 is made of a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component, and is provided on the upper surface of the gate insulating film 61. The barrier layer 32 is formed by oxidizing a metal for forming a metal oxide contained in the metal material, and is provided between the gate insulating film 61 and the seed layer 30. The copper wiring layer 33 made of a simple substance of copper is provided on the seed layer 30. That is, on the gate insulating film 61, the barrier layer 32, the seed layer 30, and the copper wiring layer 33 are laminated in this order. Since the other configurations are the same as those of the first embodiment described above including the parts not shown, the duplicated description will be omitted by adding the same reference numerals to the drawings.

Hereinafter, the process of forming a film on the inner surface of the transparent substrate 3 on the rear side will be described.

The underlying insulating film 5 is formed on the transparent substrate 3 in the same manner as in the first embodiment. An a-Si layer (not shown) to be an active layer is formed on the underlying insulating film 5 by, for example, a PE-CVD method or the like. Then, the a-Si layer is annealed in an atmosphere at a temperature of 500 ° C. to desorb hydrogen in the a-Si layer. Further, by crystallization by the ELA (Excimer Laser Anneal) method, a polysilicon layer as the semiconductor layer 62 is formed. After forming a resist mask on the semiconductor layer 62 by PEP, the semiconductor layer 62 is processed into a predetermined island shape by using a CDE (Chemical Dry Etching) method. Then, by the PE-CVD method, a gate insulating film 61 made of silicon oxide is formed on the semiconductor layer 62 and the underlying insulating film 5 so as to cover the semiconductor layer 62 (see FIG. 7 (A)).

The substrate 90 on which the underlying insulating film 5, the semiconductor layer 62, and the gate insulating film 61 are formed on the transparent substrate 3 is the substrate 90 on which the gate electrode 60 is formed. That is, the substrate 90 forming the gate electrode 60 includes a transparent substrate 3, an underlying insulating film 5, a semiconductor layer 62, and a gate insulating film 61. The gate electrode 60 is formed on the gate insulating film 61 so as to be disposed above the semiconductor layer 62. That is, the upper surface of the gate insulating film 61 is the surface to be processed 90a of the substrate 90. In this embodiment, the gate insulating film 61 is formed of silicon oxide. Therefore, the substrate 90 contains oxygen in the surface to be processed 90a and its vicinity (in the gate insulating film 61).

Next, the gate electrode 60 and the scanning line 7 are formed on the substrate 90. 7 and 8 schematically show a process for forming the gate electrode 60 and the scanning line 7. First, a metal material prepared by mixing a metal for forming a metal oxide with copper as a main component is prepared. In the present embodiment, as the metal material, a copper alloy metal material containing 2 at% of magnesium as a metal for forming a metal oxide in copper is used.

As shown in FIG. 7A, a copper alloy seed layer 31 made of the metal material is formed on the surface to be treated 90a of the substrate 90, that is, on the gate insulating film 61. The step of forming the copper alloy seed layer 31 is the same as the step shown in FIG. 4 (A) of the first embodiment.

A photosensitive resin mask (hereinafter referred to as a photoresist mask) 34 as a resin layer is formed on the copper alloy seed layer 31 by using PEP. The photoresist mask 34 has a groove 34a that exposes a part of the copper alloy seed layer 31 to a predetermined pattern (wiring pattern). The step of forming the photoresist mask 34 is the same as the step shown in FIG. 4 (B) of the first embodiment.

As shown in FIG. 7 (B), after removing the oxide film formed in the region exposed by the groove 34a of the photoresist mask 34 in the upper portion 31b of the copper alloy seed layer 31, the copper wiring layer is formed in this region. Form 33. This step is the same as the step shown in FIG. 4 (C) of the first embodiment.

As shown in FIG. 7C, an etching protection layer 37 for protecting the copper wiring layer 33 from etching is formed on the copper wiring layer 33 (upper 33b of the copper wiring layer 33). The etching protection layer 37 can be formed by electroless plating, for example, a metal containing nickel (Ni) as a main component so as to fill the groove 34a of the photoresist mask 34. The etching protection layer 37 is not limited to nickel as long as it can protect the upper portion 33b of the copper wiring layer 33 from the etching process.

As shown in FIG. 7 (D), the photoresist mask 34 is removed using a stripping solution or the like. This step is the same as the step shown in FIG. 4 (D) of the first embodiment.

As shown in FIG. 8 (E), a region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31 is etched and removed along the peripheral portion 33a of the copper wiring layer 33. At this time, a part of the peripheral portion 33a of the copper wiring layer 33 is side-etched together with a region other than the region joined to the copper wiring layer 33 of the copper alloy seed layer 31, but the upper portion 33b of the copper wiring layer 33 is etched. Since it is protected by the protective layer 37, the upper portion 33b of the copper wiring layer 33 is not etched. That is, the copper wiring layer 33 is not etched in the thickness direction. The etching protection layer 37 can prevent a decrease in the layer thickness of the copper wiring layer 33 and suppress an increase in surface unevenness caused by a high intergranular etching rate during wet etching of the copper alloy seed layer 31. ..

Using the etching protection layer 37 as a mask, phosphorus (P) as a first impurity is ion-doped into the region of the semiconductor layer 62 that becomes the source region 66b and the drain region 66c. As a result, a source region 66b and a drain region 66c are formed as high-concentration impurity regions.

Next, as shown in FIG. 8 (F), only the etching protection layer 37 is etched and removed. Then, using the copper wiring layer 33 as a mask, phosphorus as a second impurity is ion-doped into the regions corresponding to both sides of the copper wiring layer 33 of the semiconductor layer 62. The second impurity has a lower concentration than the first impurity. As a result, low-concentration impurity regions 66d and 66e and channel regions 66a sandwiched between these low-concentration impurity regions 66d and 66e are formed. These low-concentration impurity regions 66d and 66e are formed in regions substantially corresponding to the side-etched portions of the copper wiring layer 33 formed under the etching protection layer 37.

When the etching protection layer 37 is formed of a metal containing Ni as a main component and the copper wiring layer 33 is not used as a mask when injecting a second impurity into the semiconductor layer 62, the etching protection layer 37 Does not have to be removed. In this case, the etching protection layer 37 becomes a part of the wiring structure.

After that, as shown in FIG. 8 (G), the exposed surfaces of the copper wiring layer 33 and the copper alloy seed layer 31 (the upper 33b and the peripheral portion 33a of the copper wiring layer 33, and the peripheral portion 31a of the copper alloy seed layer 31, That is, the outer surface of the copper wiring layer 33 and the outer surface of the copper alloy seed layer 31 except for the joint surface between the substrate 90 and the copper alloy seed layer 31 and the joint surface between the copper alloy seed layer 31 and the copper wiring layer 33. ) Is covered, for example, a capping layer 35 made of Co-WB, Co-B, Ni-B, etc. is formed. This step is the same as the step shown in FIG. 5 (F) of the first embodiment.

Next, for example, by performing a heat treatment (annealing treatment) at about 350 ° C., the magnesium contained in the copper alloy seed layer 31 is oxidized using the oxygen contained in the underlying insulating film 5 (silicon oxide film). As a result, as shown in FIG. 8 (H), a barrier layer 32 made of magnesium oxide (MgO) is formed on the underlying insulating film 5. This step is the same as the step shown in FIG. 5 (G) of the first embodiment. Further, as described above, the gate electrode 60 and the scanning line 7 are formed. The step of forming the barrier layer 32 may be performed in a subsequent step.

Further, an interlayer insulating layer 67 is formed on the gate electrode 60, the scanning line 7, and the gate insulating film 61 so as to cover the gate electrode 60 and the scanning line 7. After forming a resist mask with PEP on the interlayer insulating layer 67, the gate insulating film 61 and the interlayer insulating layer 67 are etched to form contact holes 61a and 67a that open to the surfaces of the source region 66b and the drain region 66c. .. A metal layer to be a source electrode 63 and a drain electrode 64 is formed on the interlayer insulating layer 67 so as to fill the contact holes 61a and 67a. The source electrode 63 and the drain electrode 64 are formed by etching this metal layer into a predetermined pattern. A signal line 8 is formed in a predetermined pattern on the interlayer insulating layer 67 so as to be electrically connected to the corresponding drain electrode 64.

A passivation layer 68 is formed on the source electrode 63, the drain electrode 64, the signal line 8, and the interlayer insulating layer 67 so as to cover the source electrode 63, the drain electrode 64, and the signal line 8. Subsequently, a flattening layer 69 is formed on the passivation layer 68. Contact holes 68a and 69a that expose the surface of the source electrode 63 are formed in the passage layer 68 and the flattening layer 69. A transparent electrode layer or a reflective metal layer to be the pixel electrodes 6 is formed on the flattening layer 69 so as to fill the contact holes 68a and 69a. Then, the pixel electrode 6 is formed by etching the transparent electrode layer or the reflective metal layer into a predetermined pattern. As described above, the film forming step on the transparent substrate 3 on the rear side is completed.

According to this embodiment, although the copper wiring layer 33 and the seed layer 30 which are the main body portions of the gate electrode 20 contain copper as a main component, fine wiring can be formed and the specific resistance is low. It is possible to obtain a gate electrode 20 in which copper is difficult to diffuse to the surroundings and a high adhesion strength to the substrate, and a method for forming the gate electrode 20.

Further, since the metal material forming the copper alloy seed layer 31 contains magnesium as a metal for forming a metal oxide, a barrier layer 32 made of magnesium oxide (MgO) can be obtained. MgO layer is TiO_XLike the layer, it has copper diffusion suppression, and has good adhesion to the gate insulating film 61 and copper (the main body of the gate electrode 60). Therefore, the barrier layer 32 made of magnesium oxide can satisfactorily suppress the diffusion of copper from the copper wiring layer 33, and the main body portion (seed layer 30 and copper wiring layer 33) of the gate electrode 60 is made of the substrate 90. Can be well fixed on top.

Further, in the method for forming the gate electrode 60 of the present embodiment, the step of etching the region other than the region joined with the copper wiring layer 33 of the copper alloy seed layer 31 is performed before etching the copper alloy seed layer 31. The step of forming the etching protection layer 37 on the wiring layer 33 is included. Therefore, it is possible to prevent a decrease in the layer thickness of the copper wiring layer 33 and suppress an increase in surface unevenness caused by a high intergranular etching rate during wet etching of the copper alloy seed layer 31.

Moreover, in the method of forming the gate electrode 60 of the present embodiment, the step of etching the region other than the region joined with the copper wiring layer 33 of the copper alloy seed layer 31 is etching protection after etching the copper alloy seed layer 31. It includes a step of removing layer 37. Therefore, even if this etching protection layer 37 is used, there is almost no effect on the physical properties of the scanning line 7. Moreover, since the etching protection layer 37 is removed, nickel, cobalt, or the like can be applied as the etching protection layer 37.

Further, according to the method for forming the TFT 10 of the present embodiment, the step of forming the semiconductor layer 62, the step of forming the gate insulating film 61 on the semiconductor layer 62, and the step of forming the gate insulating film 61 on the gate insulating film 61 as the main component. A step of forming a copper alloy seed layer 31 from a metal material obtained by mixing a metal for forming a metal oxide in copper, and exposing a part of the copper alloy seed layer 31 in a predetermined pattern on the copper alloy seed layer 31. A step of forming a photoresist mask 34 having a groove 34a to be made to be allowed, a step of forming a copper wiring layer 33 having a peripheral portion 33a in a region exposed by the groove 34a on the copper alloy seed layer 31, and a copper wiring. A step of forming an etching protection layer 37 that protects the copper wiring layer 33 from etching on the layer 33, a step of removing the photoresist mask 34 after forming the etching protection layer 37, and a copper wiring layer of the copper alloy seed layer 31. A step of etching along the peripheral portion 33a of 33, a step of injecting the first impurity into the semiconductor layer 62 using the etching protective layer 37 as a mask, a step of removing the etching protective layer 37, and a step of removing the etching protective layer 37. Later, using the copper wiring layer as a mask, a step of injecting a second impurity having a concentration lower than that of the first impurity into the semiconductor layer 62, and diffusion of copper from the copper wiring layer 33 onto the copper wiring layer 33. A step of forming a capping layer 35 capable of suppressing the above, and a step of oxidizing the metal for metal oxide formation using oxygen contained in the gate insulating film 61 to form a barrier layer 32 on the gate insulating film 61. It has.

According to the method for forming the TFT 10 of the present embodiment, the etching protection layer 37 formed to protect the copper wiring layer 33 from etching is also applied as a mask in the step of injecting the first impurity into the semiconductor layer 62. Can be done. Therefore, even though the main body of the wiring structure is mainly composed of copper, fine wiring can be formed, the specific resistance is low, copper is difficult to diffuse to the surroundings, and the adhesion strength to the substrate is strong. A top-gate polysilicon TFT having a high gate electrode 60 can be formed with good quality while suppressing the number of steps.

Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. 9 to 11. In the present embodiment, the display device of the present invention is applied to a liquid crystal display device, the TFT of the present invention is applied to a top-gate polysilicon TFT, and the wiring structure of the present invention is the source electrode of the TFT. And one form applied to the drain electrode, and one form of the method for forming the wiring structure of the present invention will be described.

The source electrode 63 and the drain electrode 64 as the wiring structure each include a barrier metal layer 38, a seed layer 30, a barrier layer 32, a copper wiring layer 33 as a wiring structure layer, and a capping layer 35, respectively. There is.

The barrier metal layer 38 is a metal layer capable of suppressing the diffusion of copper, and is formed by the upper surface of the interlayer insulating layer 67, the wall surface defining the contact hole 67a, the wall surface defining the contact hole 61a, and the contact holes 61a and 67a. It is provided on the upper surface of the exposed conductive semiconductor layer 62 (on the first surface to be processed 100a of the substrate 100, which will be described later). The seed layer 30 is made of a metal material obtained by mixing a metal for forming a metal oxide with copper as a main component, and is provided on the upper surface of the barrier metal layer 38 as a second surface to be treated 38a. The barrier layer 32 is formed by oxidizing a metal for forming a metal oxide contained in the metal material, and is provided between the barrier metal layer 38 and the seed layer 30. The copper wiring layer 33 is provided on the seed layer 30. On the copper wiring layer 33, a capping layer 35 that suppresses the diffusion of copper from the copper wiring layer 33 is provided.

As shown in FIG. 9, in the present embodiment, the gate electrode 60 is an electrode composed of a single metal layer, but it may be a wiring structure as described in the second embodiment. Since the other configurations are the same as those of the third embodiment described above including the parts not shown, the duplicated description will be omitted by adding the same reference numerals to the drawings.

Hereinafter, the process of forming a film on the inner surface of the transparent substrate 3 on the rear side will be described.

The underlying insulating film 5 is formed on the transparent substrate 3 in the same manner as in the first embodiment. The semiconductor layer 62 is formed on the underlying insulating film 5 in the same manner as in the third embodiment. A gate insulating film 61 made of silicon oxide is formed on the semiconductor layer 62 and the underlying insulating film 5. The gate electrode 60 and the scanning line 7 are formed on the gate insulating film 61. An interlayer insulating layer 67 is formed on the gate electrode 60, the scanning line 7, and the gate insulating film 61. Contact holes 61a and 67a are formed in the gate insulating film 61 and the interlayer insulating layer 67. In this way, the underlying insulating film 5, the semiconductor layer 62, the gate insulating film 61 having the contact hole 61a, the gate electrode 60, the scanning line 7, and the interlayer insulating layer 67 having the contact hole 67a are formed on the transparent substrate 3. Is the substrate 100 that forms the source electrode 63 and the drain electrode 64. Further, the upper surface of the interlayer insulating layer 67, the wall surface defining the contact hole 67a, the wall surface defining the contact hole 61a, and the upper surface of the semiconductor layer 62 exposed by the contact holes 61a, 67a are the first of the substrate 100. The surface to be processed is 100a. Therefore, the substrate 100 contains oxygen in the surface to be treated 100a and its vicinity (in the interlayer insulating layer 67 and in the semiconductor layer 62).

The source electrode 23 and the drain electrode 64 are formed on the substrate 100. 10 and 11 schematically show a process for forming the source electrode 63 and the drain electrode 64.

As shown in FIG. 10A, a barrier metal layer 38 capable of suppressing the diffusion of copper is formed on the first surface to be treated 100a of the substrate 100. The barrier metal layer 38 can form, for example, TiN, Ti, TaN, Ta, Ni alloy, Co alloy and the like. In the present embodiment, the layer thickness of the barrier metal layer 38 is set to 50 nm.

Next, a metal material prepared by mixing a metal for forming a metal oxide with copper as a main component is prepared. In the present embodiment, as the metal material, a copper alloy metal material containing 2 at% of aluminum as a metal for forming a metal oxide is used. A copper alloy seed layer 31 made of the metal material is formed on the second surface to be treated 38a of the barrier metal layer 38, that is, on the upper surface. The copper alloy seed layer 31 can be formed by forming the metal material into a film by a sputtering method, a vapor deposition method, or the like.

As shown in FIG. 10B, a photoresist mask 34 as a resin layer is formed on the interlayer insulating layer 67 by using PEP. The photoresist mask 34 has a groove 34a corresponding to the contact hole 67a. The step of forming the photoresist mask 34 is the same as the step shown in FIG. 4 (B) of the first embodiment.

Further, the copper wiring layer 33 is formed in the region exposed by the groove 34a of the photoresist mask 34 on the copper alloy seed layer 31. This step is the same as the step shown in FIG. 4 (C) of the first embodiment.

As shown in FIG. 10 (C), the photoresist mask 34 is removed using a stripping solution or the like. This step is the same as the step shown in FIG. 4 (D) of the first embodiment.

As shown in FIG. 11 (D), the copper alloy seed layer 31 is etched along the peripheral portion 33a of the copper wiring layer 33. This step is the same as the step shown in FIG. 5 (E) of the first embodiment.

As shown in FIG. 11 (E), the barrier metal layer 38 is etched using the copper wiring layer 33 as a mask.

As shown in FIG. 11 (F), it covers the exposed surfaces of the copper wiring layer 33 and the copper alloy seed layer 31 (the upper 33b and the peripheral portion 33a of the copper wiring layer 33, and the peripheral portion 31a of the copper alloy seed layer 31). As described above, the capping layer 35 made of, for example, Co-WB, Co-B, NiB, etc. is formed. This step is the same as the step shown in FIG. 5 (F) of the first embodiment. As described above, the source electrode 63 and the drain electrode 64 are formed.

Next, for example, by performing a heat treatment (annealing treatment) at about 350 ° C., the aluminum contained in the copper alloy seed layer 31 is oxidized using the oxygen contained in the underlying insulating film 5 (silicon oxide film). Aluminum oxide (Al) on the underlying insulating film 5₂O₃) Is formed. This step is the same as the step shown in FIG. 5 (G) of the first embodiment.

By the way, the source electrode 63 and the drain electrode 64 need to be electrically connected to the source region 66b and the drain region 66c of the semiconductor layer 62, respectively. In the present embodiment, the source electrode 63 and the drain electrode 64 have a barrier metal layer 38 having conductivity at the interface with the semiconductor layer 62. That is, the seed layer 30 and the copper wiring layer 33 are surrounded by the conductive barrier metal layer 38 and the capping layer 35, respectively. Therefore, the copper wiring layer 33 and the semiconductor layer 62 of the source electrode 63 and the copper wiring layer 33 and the semiconductor layer 62 of the drain electrode 64 are electrically connected to each other.

As described above, the source electrode 63 and the drain electrode 64 of the present embodiment have a conductive semiconductor layer 62 having a source region 66b and a drain region 66c provided apart from the source region 66b, and a source region. A source electrode 63 electrically connected to 66b, a drain electrode 64 electrically connected to a drain region 66c, a gate insulating film 61, and a gate insulating film above the region between the source region 66b and the drain region 66c. It is a TFT 10 including a gate electrode 60 provided via 61. Further, the source region 66b and the drain region 66c have a first surface to be processed 100a. The source electrode 63 and the drain electrode 64 have a second surface to be treated 38a, a barrier metal layer 38 provided on the first surface to be treated 100a, and a metal oxide formed on copper as a main component. A seed layer 30 formed of a metal material mixed with a metal for processing and provided on the second surface to be processed 38b, and a copper wiring layer 33 containing copper as a main component provided on the seed layer 30. This copper is formed by oxidizing a metal for forming a metal oxide contained in the metal material, and is provided on a barrier layer 32 provided between the barrier metal layer 38 and the seed layer 30 and a copper wiring layer 33. It has a capping layer 35 that suppresses the diffusion of copper from the wiring layer 33.

That is, in the source electrode 63 and the drain electrode 64 of the present embodiment, the barrier layer 32 and the barrier metal layer 38 are provided between the seed layer 30 and the substrate 100. Since the barrier layer 32 and the barrier metal layer 38 each function as a copper diffusion prevention layer, the diffusion of copper from the seed layer 30 and the copper wiring layer 33 to the substrate 100 is performed more than the wiring structure of the first embodiment. It can be suppressed even better. Moreover, since the source electrode 63 and the drain electrode 64 of the present embodiment have a barrier metal layer 38 having conductivity at the interface with the semiconductor layer 62, the semiconductor layer 62 and the copper wiring layer 33 are separated into a barrier metal layer. It can be electrically connected via 38.

Further, since the metal material forming the copper alloy seed layer 31 contains aluminum as a metal for forming a metal oxide, aluminum oxide (Al).₂O₃) Is obtained. Al₂O₃The layer is TiO_XLike the layer and MgO layer, it has copper diffusion suppression and has good adhesion to the substrate 100. Therefore, the barrier layer 32 made of aluminum oxide can satisfactorily suppress the diffusion of copper from the copper wiring layer 33, and the main body portions of the source electrode 63 and the drain electrode 64 (seed layer 30 and copper wiring layer 33). ) Can be satisfactorily fixed on the substrate 100.

In the method for forming the source electrode 63 and the drain electrode 64 of the present embodiment, a step of forming a barrier metal layer 38 capable of suppressing the diffusion of copper on the substrate 100 and a copper as a main component on the barrier metal layer 38. A step of forming a copper alloy seed layer 31 with a metal material obtained by mixing a metal for forming a metal oxide with a metal, and a predetermined pattern of a copper wiring layer 33 on the copper alloy seed layer 31 with the copper alloy seed layer 31 as a seed. It is provided with a step of forming the barrier layer 32 on the barrier metal layer 38 by oxidizing the metal for forming the metal oxide. Therefore, the specific resistances of the source electrode 63 and the drain electrode 64 can be suppressed low. Moreover, the source electrode 63 and the drain electrode 64, which are hard to diffuse to the surroundings and have high reliability, can be selectively formed on the substrate 100. Further, since the laminate having the barrier layer 32 and the barrier metal layer 38 functions as a copper diffusion prevention layer, the seed layer 30 and the copper wiring layer 33 to the substrate 100 are more likely to be used than the wiring structure of the first embodiment. A source electrode 63 and a drain electrode 64 that can further suppress copper diffusion can be obtained.

As described above, according to the present embodiment, although the main body portion of the wiring structure contains copper as the main component, fine wiring can be formed, the specific resistance is low, and copper diffuses to the surroundings. A TFT 10 having a source electrode 63 and a drain electrode 64, which are difficult and have high adhesion to the substrate, can be obtained, and a display device 1 having such a TFT 10 can be obtained.

The wiring structure having the barrier metal layer 38 is not limited to the application to the source electrode 63 and the drain electrode 64. The wiring structure having the barrier metal layer 38 may be applied to wiring structures such as gate electrodes 20, 60, scanning lines 7, and signal lines 8.

Further, in the present embodiment, the copper alloy seed layer 31 is etched without forming the etching protective layer 37, but after the etching protective layer 37 is formed as described in the second embodiment, the copper alloy is formed. The seed layer 31 may be etched.

In the first to third embodiments, as a method of forming the copper wiring layer 33 on the copper alloy seed layer 31 in a predetermined pattern, a photoresist mask 34 as a resin layer is used and a metal is formed by a plating method. A method of selectively forming the layer and a method of forming the metal layer by etching such as wet etching are given as an example, but the copper wiring layer 33 is formed on the copper alloy seed layer 31 in a predetermined pattern. The method is not limited to this.

Further, the resin layer material is not limited to the photosensitive resin, but is a material that can be removed and has substantially no electrical and chemical effect on the surface to be treated of the substrate and the wiring structure to be formed. All you need is.

Further, the metal for forming a metal oxide may be oxidized by using oxygen contained in the treatment atmosphere.

Further, in the first embodiment, titanium is adopted as the metal for forming the metal oxide, in the second embodiment, magnesium is adopted as the metal for forming the metal oxide, and in the third embodiment, the metal oxide is adopted. Although aluminum is used as the forming metal, the metal oxide forming metal can be arbitrarily selected to include one of magnesium, titanium, aluminum, and chromium. By selecting titanium, a barrier layer 32 made of titanium oxide can be obtained. By selecting magnesium, a barrier layer 32 made of magnesium oxide can be obtained. By selecting aluminum, a barrier layer 32 made of aluminum oxide can be obtained. By selecting chromium, a barrier layer 32 made of chromium oxide can be obtained. By including two or more of titanium, magnesium, aluminum, and chromium, a barrier layer 32 composed of a mixture of a plurality of metal oxides can be obtained. Whichever is selected, the diffusion of copper from the copper alloy seed layer 31 and the copper wiring layer 33 can be suppressed.

The present invention is not limited to liquid crystal display devices, and can be applied to display devices such as inorganic ELD devices and organic ELD devices.

<figref num="1">The plan view which shows the display device which concerns on 1st Embodiment of this invention.</figref><figref num="2">FIG. 1 is a cross-sectional view taken along the line II-II in Fig. 1.</figref><figref num="3">Sectional view shown along the line III-III in FIG.</figref><figref num="4">(A) to (D) are process diagrams for explaining the first half of the method of forming the scanning line provided in the display device of FIG. 1 and the gate electrode provided in the TFT.</figref><figref num="5">(E) to (G) are process diagrams for explaining the latter half of the method of forming the scanning line provided in the display device of FIG. 1 and the gate electrode provided in the TFT, following FIG.</figref><figref num="6">The cross-sectional view which shows a part of the display device which concerns on 2nd Embodiment of this invention.</figref><figref num="7">(A) to (D) are process diagrams for explaining the first half of the method of forming the TFT included in the display device of FIG.</figref><figref num="8">(D) to (H) are process diagrams for explaining the latter half of the method of forming the TFT included in the display device of FIG. 6, following FIG. 7.</figref><figref num="9">The cross-sectional view which shows a part of the display device which concerns on 3rd Embodiment of this invention.</figref><figref num="10">(A) to (C) are process diagrams for explaining the first half of the method of forming the source electrode and drain electrode of the TFT included in the display device of FIG.</figref><figref num="11">(D) to (F) are process diagrams for explaining the latter half of the method of forming the source electrode and the drain electrode of the TFT included in the display device of FIG. 9, following FIG.</figref>

Code description

1 ... Liquid crystal display (display device), 7 ... Scanning line (wiring structure), 10 ... TFT, 20,60 ... Gate electrode (wiring structure), 21,61 ... Gate insulating film 21,62 ... Semiconductor layer, 23,63 ... Source electrode (wiring structure), 24,64 ... Drain electrode (wiring structure), 30 ... Seed layer, 31 .. .Copper alloy seed layer 31 ... Barrier layer, 33 ... Copper wiring layer (wiring structure layer), 34 ... Photoresist mask (resin layer), 35 ... Capping layer, 37 ... Etching Protective layer, 38 ... barrier metal layer, 38a ... second surface to be treated 70,90,100 ... substrate, 70a, 90a ... surface to be treated, 100a ... first surface to be treated