Adaptive demodulator

The present invention relates to the field of demodulators, and more specifically to radio frequency signal demodulators, the results of which are utilized by digital processing units.

An application of the present invention relates to an electromagnetic transponder system in which the transponder communicates with a non-contact read / write terminal.

FIG. 1 shows the reception / demodulation part of the radio frequency signal by the electromagnetic transponder in a block format very roughly.

After being received by the antenna and set up by the combiner (not shown), the radio frequency signal RF is an analog demodulator 1 (ANALOG) capable of providing a demodulated analog signal AS and a sampling clock CK. Processed by DMOD). Generally, the sampling clock is obtained from the transmitting carrier. The signals AS and CK are sent to the microcontroller 3 (CPU) and the interface circuit 2 (INTERF), which has the function of providing the output signal O that can be utilized in other digital circuits. In reality, the signal O is provided to the data bus with which the CPU 3 communicates. In electromagnetic transponder applications, terminal-to-transponder transmission uses 13.56 megahertz carriers to carry encoded information and typically flows 106 kilobits per second in non-zero modulation factor amplitude modulation. Is executed by. On the transponder side, the carrier is used to remotely power the circuit in the absence of the transponder's battery. The same demodulation principle is used in terminals. However, in general, a clock signal exists in the terminal, and if it does not exist, it is necessary to extract the clock signal from the received signal.

FIG. 2 illustrates the principle of demodulation performed in a circuit as shown in FIG. 1 in a timing diagram.

The first timing diagram shows an example of data D transmitted by signal RF and recovered at output O of circuit 2. In this example, the transmission of bits in state 0 corresponds to a low level followed by a high level within bit time T, while the transmission of state 1 corresponds to a high level followed by a low level. To do). This is just an example and different types of coding and transmission may be utilized. In the example of an electromagnetic transponder using a carrier frequency of 13.56 MHz, the time T corresponds to, for example, 106 kHz.

A signal AS (second timing diagram) that roughly follows the shape of signal D is obtained at the output of analog demodulator 1.

The recovered clock signal CK (third timing diagram) corresponds to the carrier signal, a frequency of 13.56 MHz. For clarity, the time scales of the timing diagrams in FIG. 2, especially the timing diagrams AS and CK, are not constant proportions.

The final timing diagram in FIG. 2 shows the signal O.

In conventional circuit 2, the signal AS is sampled only once in the middle of the cycle (time t1 and t2). In practice, the signal AS is sent to the input of the inverter that has the switching threshold TH and conditions the condition provided to the output O.

The first drawback of conventional demodulation systems, as shown in FIGS. 1 and 2, is that when the signal AS is severely disturbed, the time t1 or t2 when the signal level is taken into account provides erroneous results. There is a risk of doing so.

Another drawback is that different time analyzes of the signal AS cannot be close to each other, which means that the CPU has a clock frequency that corresponds to the frequency of the clock CK at most, and that CPU's operation. This is because it leads to a speed that is incompatible with the speed. Therefore, the flow is restricted.

Taking the 13.56 MHz frequency-based electromagnetic transponder system as an example, in reality, 106 kilobits per second is the limit to take into account the time required for software analysis of received data.

It is desirable to be able to increase the transmission speed of such systems. For example, in applications where images are transmitted (photographs, biometrics, prints), a flow of 106 kilobits per second results in a transmission time of a few seconds, which is incompatible with the desired analysis speed.

<p num="0015"> The present invention aims to optimize the demodulation of RF signals, in particular to increase the possible transmission flow for a given clock frequency.</p><p num="0016"> It is also an object of the present invention to provide a solution to the problem of possible disturbance in the signal from the analog demodulator.</p><p num="0017"> It is also an object of the present invention to provide a solution compatible with conventional electromagnetic transponder structures, in particular systems in which a clock is transmitted simultaneously with a radio frequency signal.</p>

<p num="0018"> To achieve these and other objectives, the present invention relates to circuits that determine the binary state supported by analog symbols. An analog-to-digital converter that uses a sampling signal based on a frequency with a period shorter than the symbol period, A means of selecting a number of valid samples that is less than the number of samples obtained by sampling symbols at said frequencies. Provided is a circuit having a means for determining the state of a symbol based on a selected sample.</p><p num="0019"> According to an embodiment of the invention, the determination means receives an odd number of samples and provides a binary state of the symbol by applying a majority criterion.</p><p num="0020"> According to embodiments of the invention, the location of each valid sample is determined during the training or characterization stage.</p><p num="0021"> According to embodiments of the present invention, the sampling signal originates from a position selected for effective sampling.</p><p num="0022"> According to an embodiment of the present invention, the sampling signal corresponds to the frequency.</p><p num="0023"> According to an embodiment of the invention, the output of the analog-to-digital converter is sent to the input of a shift register, which register has a parallel output provided to a multiplexer that selects a valid sample.</p><p num="0024"> According to an embodiment of the invention, the register stores at least the position of a sample that is considered valid in the symbol.</p><p num="0025"> According to an embodiment of the present invention, it is applied to a transmission system between an electromagnetic transponder and a reading / writing terminal.</p><p num="0026"> The present invention also presents in a method of determining the binary states supported by analog symbols. Sampling a symbol with a sampling signal based on a frequency with a period shorter than the period of the symbol, Select a number of valid samples that is less than the number of samples obtained by sampling the symbols at said frequencies. Provides a method of determining the state of a symbol based on a selected sample.</p><p num="0027"> According to embodiments of the present invention, an odd number of samples are selected and the state of the symbol is determined by majority vote based on the respective states of the different samples.</p><p num="0028"> According to embodiments of the present invention, the position of each valid sample is determined by the training stage.</p><p num="0029"> According to embodiments of the present invention, the sample signal originates from a position selected for effective sampling.</p><p num="0030"> According to an embodiment of the present invention, the sampling signal corresponds to the frequency.</p><p num="0031"> The aforementioned objects, features and advantages of the present invention and others will be described in detail in the following, but not limited to, detailed description of embodiments in connection with the accompanying drawings.</p>

In different figures, the same elements are designated by the same reference number. For clarity, only the elements necessary for understanding the present invention are shown in the figure and are described below. In particular, the circuitry downstream of the demodulator is not described in detail and the invention is compatible with any conventional software use of signals. Similarly, the internal structure of the analog demodulator used in the present invention corresponds to a conventional structure and is not described in detail.

A feature of the present invention is to select some samples among the symbols and infer the state 0 or 1 of the symbol from these samples without using the CPU. According to the present invention, the number of samples considered is less than the number of samples obtained by sampling at the frequency on which the sampling signal is based.

Another feature of the present invention is to select a reduced number of samples per symbol, corresponding to a reliable sample at a position (time) determined during the training or characterization stage, and these selected samples. It is to infer the state of the symbol from.

According to the first embodiment (not shown), the analog signal from the analog demodulator is sampled directly in the symbol at a time corresponding to the time to provide the selected sample. This will generate a sampling signal with a number of edges less than the number of edges at that frequency based on a frequency with a period smaller than the period of the symbol.

According to the second embodiment, the sampling signal based on the direct sampling frequency is this frequency. The analog signal from the analog demodulator is preferably sampled at a frequency corresponding to the maximum available frequency. The symbol state 0 or 1 is then inferred from some selected samples.

FIG. 3 shows this second embodiment of a demodulator according to the present invention in block form very schematically.

As mentioned earlier, the radio frequency signal RF is received by analog demodulator 1 (ANALOG DEMOD), which receives the analog signal AS and here the clock signal CK of the carrier frequency forming the sampling signal. Pull out. The signal CK is transmitted to the interface circuit 2, which provides the digital signal O to the CPU 3 as in the conventional circuit of FIG.

According to this embodiment of the invention, a demodulation optimization circuit 4 (DEMOPT) is placed between the output of the analog demodulator 1 providing the signal AS and the input of the corresponding interface circuit 2. The circuit 4 further receives the clock signal CK and the control signal CT from the CPU 3.

The circuit 4 has a function of providing a signal DS corresponding to the state 0 or 1 of the received symbol. Therefore, the interface circuit 2 directly receives the state available in the CPU 3. According to another embodiment, the circuit 2 can be omitted if the signal O is electrically compatible with the connection bus with the CPU 3.

FIG. 4 shows an embodiment of circuit 4 according to the present invention.

The signal AS passes through an analog-to-digital converter 10 (A / D) having a sampling frequency corresponding to the frequency of the clock signal CK. The output of the converter 10 is sent to the serial input of the shift register 11 (SREG) whose word length corresponds to the number of samples contained in the transmitted data symbol.

All bits of register 11 are read in parallel and sent to the input of the multiplexer 12, which has the ability to select some samples that are in a valid symbolic state.

Preferably, as illustrated in FIG. 4, the multiplexer 12 is a decision circuit 13 (DECID) having the ability to select an odd number of samples (eg, 3) and apply a majority voting method to determine the state of the symbol. To provide. The output of circuit 13 provides a bit DS.

According to a preferred embodiment, the selection made by the multiplexer 12 can be parameterized. For example, two registers 14 (NREG) and 15 (dREG) contain words indicating the center sample position N of the sample range considered reliable and the distance d between the two samples in the effective range, respectively. The respective values of registers 14 and 15 are utilized by the arithmetic circuit 16, which provides the multiplexer 12 with the respective positions N of the central sample and the respective positions N + d and Nd of the end sample in that range. .. This is an example of generating the selection signal SEL, but other means may be used. For example, the symmetric distance d may be replaced by different intervals between sample positions.

The contents of registers 14 and 15 are loaded into circuit 4 by CPU 3 according to predetermined parameterized data. In a particular example where register 11 is 16 bits in size, registers 14 and 15 contain quartets indicating the location of valid samples, respectively.

FIG. 5 illustrates the operation of the optimization circuit according to the present invention in a timing diagram format. These timing diagrams show the clock signal CK, the signal AS, the selection signal SEL of the multiplexer 12, and the output DS of the circuit 13 for the transmitted states 1 and 0, respectively.

Suppose the signal AS is in the traditional disordered form. This signal is sampled at the frequency of clock CK, and the multiplexer selects three samples, represented by their respective positions Nd and N + d. In the example of FIG. 5, in the left part thereof, sampling provides state 1 to the signal DS, while the right part (second symbol) provides state 0.

The advantage of the present invention is to prevent detection errors that can occur due to transient disturbances in the demodulated signal. In the right part of FIG. 5, such turbulence is shown in the form of peak p. In this case, although the sample N is considered to be in a high state, it can be confirmed by the majority vote executed by the circuit 13 that the state of the transmitted bits is 0.

According to the first embodiment of the present invention, the most effective sample is determined at the stage of characterization, that is, by testing the product batch in more detail than testing the product. The present invention takes advantage of the fact that the general form of signal AS is almost always iterative for the same integrated circuit chip batch.

According to the second embodiment, training steps are periodically performed during the product lifetime to adapt the demodulator to possible drift. These two embodiments may be combined.

Performing the training or characterization stage does not involve any particular difficulties. Knowing the nature of the transmitted message, performing several different parameterizations of registers 14 and 15 and choosing the first parameterization that provides correct results across a large number of symbols (which are considered valid) do it.

The advantage of the present invention is that the transmission rate for a given clock frequency can be increased while maintaining software interpretation and compatibility of the transmitted data. In fact, the CPU does not interfere with the actual sample selection (except for the control steps in registers 14 and 15). Therefore, the number of transmitted bits can be increased, while the possibility of interpretation by the CPU can be considered.

Thus, taking the example of an electromagnetic transponder, at a carrier of 13.56 MHz, the period T ́ of the symbol according to the invention corresponds to a flow of 847.5 kilobits per second. Such a factor of 8 (as opposed to the traditional 106 kilobits per second flow) seems small but is actually very advantageous. For example, an image that conventionally takes 4 seconds to be transmitted takes only 1/2 second according to the present invention. This speed is compatible with fast analytical needs, especially in authentication or access control applications.

Another advantage of the present invention is that the demodulator thus formed can be parameterized. Therefore, the same hardware circuit may be customized to fit different integrated circuits.

Of course, the present invention has various modifications, modifications and improvements that are readily apparent to those skilled in the art. In particular, frequencies and flows other than the above may be utilized.

Further, although the present invention has been specifically described for accelerating the flow, the reliability of the analog demodulator can be improved even with a constant flow.

Moreover, practical embodiments of the invention made by hardware and / or software means based on the above given functional description are within the ability of those skilled in the art.

Finally, the fit examples shown in the first embodiment, in which the selection is performed directly at the sampling time rather than the actual sample, are within the ability of one of ordinary skill in the art by utilizing known components.

Such modifications, modifications and improvements are part of this disclosure and are within the spirit and scope of the invention. Therefore, the above description is merely an example and is not intended to be limited. The present invention is limited only to the claims and their equivalents.

<figref num="1">It shows a conventional demodulation structure.</figref><figref num="2">The operation of the demodulator in FIG. 1 is illustrated.</figref><figref num="3">A structural example of a demodulator according to the present invention is shown schematically in block format.</figref><figref num="4">An embodiment of a demodulation optimizer according to the present invention is shown.</figref><figref num="5">The operation of the demodulation optimizer according to the present invention is shown in a timing diagram format.</figref>

Code description

1 analog demodulator 2 interface circuit 3 CPU 4 Demodulation optimization circuit 11, 14, 15 registers 12 Multiplexer 13 Decision circuit 16 Arithmetic circuit