Adaptive demodulator
Abstract
L'invention concerne un procédé et un circuit (4) de détection d'un état binaire porté par un symbole analogique (AS), consistant à échantillonner (10) le symbole avec un signal d'échantillonnage basé sur une fréquence (CK) de période inférieure à la durée d'un symbole, sélectionner (11, 12, 14, 15, 16) un nombre d'échantillons significatifs inférieur au nombre d'échantillons qui serait obtenu avec un échantillonnage du symbole à ladite fréquence, et décider (13) de l'état du symbole à partir des échantillons sélectionnés.

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13 claims: 6 independent, 7 dependent
- 1Circuit (4) for detecting a binary state carried by an analog symbol (AS), characterized in that it comprises :a member (10) of analog-digital conversion using a sampling signal based on a frequency (CK) of duration less than the duration of a symbol;means (11, 12, 14, 15, 16) for selecting a number of significant samples less than the number samples which would be obtained with a sampling symbol at said frequency;and means (13) making the status of icon from selected samples.
- 8A circuit according to any one of claims 1 7, applied to a transmission system between a transponder electromagnetic and a read-write terminal.
- 9A method for determining a binary state supported by an analog symbol (AS), characterized in that it consists of :sampling (10) the symbol with a sampling signal based on a frequency (CK) of duration less than the symbol duration;selecting (11, 12, 14, 15, 16) a number of samples significant less than the number of samples that would obtained with a sampling of the symbol at said frequency;and decide (13) of the status symbol from samples selected.
Independent claims6
59 paragraphs, as filed
0001The present invention relates to the field of demodulators and more particularly the signal demodulators RF whose results are to be operated by a digital processing unit.
0002An example of application of the present invention relates to the electromagnetic transponder systems in a transponder which communicates with a terminal read-write without contact.
00031 shows, very schematically and form of blocks, the receiving demodulation section signals by radio frequency electromagnetic transponder.
0004After being received by an antenna and shaped by a coupler (not shown) the RF signals RF are processed by an analog demodulator 1 (ANALOG DEMOD) whose role is to provide an analog signal demodulated AS and a sampling clock CK. The sampling clock is generally recovered from the carrier transmission. AS and CK signals are sent to a circuit 2 Interface (INTERF) whose role is to provide a signal exploitable output O 3 by a microcontroller (CPU) and other digital circuits. In practice, the Y signal is supplied to a data bus which communicates with the CPU 3. In an application to electromagnetic transponders, a transmission a terminal to a transponder is carried out using a 13.56 MHz carrier on which are transmitted coded information, generally with amplitude modulation a non-zero modulation rate, at a rate of 106 kilobits per second. transponder side, the carrier used to remotely supply of circuits of the transponder in the case where the latter is devoid battery. The same principle is used in demodulation a terminal with the difference that the clock signal is generally present therein without the need of extracting the received signal.
0005Figure 2 illustrates, in timing diagrams, the principle demodulation performed in a circuit such as illustrated in Figure 1.
0006The first chart shows an example of data D transmitted by the RF signal and to be recovered at the output O the circuit 2. In this example, it is assumed that the transmission a bit in state 0 corresponds, to within a bit period T, at a low level followed by a high level while the transmission of a 1 corresponds to the inverse (top level monitoring a low level). This is an example, and different types encodings and transmission may be used. In the example of electromagnetic transponders using a carrier frequency at 13.56 MHz, the duration T corresponds, for example, to 106 kHz.
0007The output of the analog demodulator 1, we obtain a AS signal (second timing) following roughly the shape of the signal D.
0008The recovered clock signal CK (third timing) corresponds to the carrier signal, that is to say a frequency of 13.56 MHz. For clarity, the timing diagrams of Figure 2 are not to scale, in particular in the time scale of the AS and CK timing.
0009The last time diagram in Figure 2 shows the O. signal
0010In a classic circuit 2, the AS signal is sampled once in the middle of a cycle (t1 and t2). In fact, the signal AS is sent to an inverter input including TH switching threshold conditions the state provided O. output
0011A first drawback of a demodulation system vector as shown in Figures 1 and 2 is that, if the AS signal is disrupted, or the time t1 t2, decision into account the level of the signal may provide a result wrong.
0012Another disadvantage is that it is not possible to bring the different analysis times in the AS signal Since this would lead to airspeeds with the working speed of the CPU whose frequency clock is the maximum at the frequency of clock CK. Therefore, throughput is limited.
0013Using the example of transponder systems electromagnetic based on a frequency of 13.56 MHz, the limit is in practice of 106 kilobits per second observe the time required for a software analysis data received.
0014It would be desirable to increase the speed transmission of such systems. For example, in a application where you wish to transmit images (photographs, biometric fingerprint), a flow rate of 106 kilobits per second led to several transmission times seconds, incompatible with the desired analysis speeds.
0015The present invention aims to optimize the demodulation RF signals and in particular to increase the flows of possible transmission for a given clock frequency.
0016The invention also aims at providing a solution that free itself from possible problems disturbance in the signal from an analog demodulator.
0017The invention also aims at providing a solution that be compatible with conventional architectures transponders electromagnetic and in particular with systems in wherein the clock is transmitted together with the signal radio frequency.
0018To achieve these objects and other, the present invention provides a circuit for detecting a state binary carried by an analog symbol, comprising:<sl><li>an analog-digital conversion element using a sampling signal based on a frequency period less than the duration of a symbol;</li><li>means for selecting a number of samples significant less than the number of samples that would obtained with a sampling of the symbol at said frequency; and</li><li>decision means the state of the symbol from Selected samples.</li></sl>
0019According to one embodiment of the present invention, said decision means receive an odd number of samples and provide the binary state of the symbol by applying a criterion of majority decision.
0020According to one embodiment of the present invention, the respective positions of the significant samples are determined by a learning phase or characterization.
0021According to one embodiment of the present invention, the sampling signal is derived from the selected positions for significant samples.
0022According to one embodiment of the present invention, the sampling signal corresponds to said frequency.
0023According to one embodiment of the present invention, the output of the analog-digital conversion element is sent to the input of a shift register whose outputs parallel are provided to a multiplexer for selection of the significant samples.
0024According to one embodiment of the present invention, registers store at least the position in a symbol of a sample considered significant.
0025According to one embodiment of the present invention, it is applied to a transmission system between a electromagnetic transponder and a terminal read-write.
0026The invention also provides a method for determining from a binary state supported by an analog symbol, of:<sl><li>sampling the symbol with a sampling signal based on a period of frequency less than the duration a symbol;</li><li>select a number of significant samples less than the number of samples that would be obtained with a sampling of the symbol at said frequency; and</li><li>decide the status symbol from samples selected.</li></sl>
0027According to an embodiment of the present invention, an odd number of samples is selected, the state of symbol being determined by majority decision from the respective states of the different samples.
0028According to one embodiment of the present invention, the respective positions of the significant samples are determined by a learning phase.
0029According to one embodiment of the present invention, the sampling signal is derived from the selected positions for significant samples.
0030According to one embodiment of the present invention, the sampling signal corresponds to said frequency.
0031These objects, features and advantages, as well as others of the present invention will be described in detail in the following description of specific embodiments made in non-limiting in connection with the accompanying drawings among :<sl><li>Figure 1 previously described architecture Classic demodulation;</li><li>Figure 2 illustrates the operation described above the demodulator of Figure 1; </li><li>3 shows, very schematically and in block form, an exemplary architecture of a demodulator according to the invention;</li><li>4 shows one embodiment of a demodulation optimizer of the invention; and</li><li>5 illustrates, in the form of timing, the operation of a demodulation optimizer according to the invention.</li></sl>
0032The same elements have been designated by the same references in the different figures. For reasons of clarity, only those elements that are necessary for the understanding of the invention have been shown in the drawings and will be described thereafter. In particular, the downstream circuits to the demodulator have not been detailed, the present invention being compatible with any conventional software operating signals. Similarly, the internal structure of an analog demodulator used for the invention corresponds to a conventional structure and has not been Detailed.
0033A feature of the present invention is to selecting, in a symbol, a number of samples and inferred from these samples state 0 or 1 symbol without use the CPU. According to the invention, the number of samples taken into account is less than the number samples which would be obtained with sampling at the frequency which is based on the sampling signal.
0034Another feature of the present invention is select a small number of samples per symbol as corresponding to reliable samples at positions (Time) decided during a learning phase or characterization, and deduct the state symbol of these samples selected.
0035According to a first embodiment not shown, the analog signal is directly sampled from a analog demodulator at instants in the symbol correspond to the moments supplying selected samples. This amounts to generating a sampling signal, based on a period of frequency less than the duration of a symbol, but the number of edges is lower than this frequency.
0036According to a second embodiment, the signal Sampling based on the sampling frequency is this frequency directly. The analog signal from the demodulator analog is then sampled at a frequency preferably corresponding to the maximum frequency available. then deduced from several selected samples symbol state 0 or 1 of the latter.
00373 shows, very schematically and form of blocks, this second embodiment of a demodulator of the invention.
0038As before, a radio frequency RF signal is received by an analog demodulator 2 (ANALOG DEMOD) loaded extracting an AS analog signal and a clock signal CK to the frequency of the carrier which constitutes here the signal sampling. The signal CK is sent to a circuit 2 interface that provides the digital signals to a unit O 3 central processing unit (CPU) in the manner of conventional circuit of Figure 1.
0039According to this embodiment of the invention, a optimization demodulation circuit 4 (DEMOPT) is interposed between the output of the analog demodulator 1 providing AS and the corresponding input of the interface circuit 2 signal. This circuit 4 further receives the clock signal CK and that TB control signals from the central unit 3.
0040The circuit 4 has the role of providing a signal DS corresponding to 0 or 1 of the received symbol. Thus the circuit interface 2 directly receives the useful reports by CPU 3. According to an alternative embodiment and under reserve electrical compatibility O signals with the bus connecting with the central unit 3, the circuit 2 can if optionally be omitted.
00414 shows one embodiment of a circuit 4 according to the present invention.
0042The AS signal through an analog 10 digital (A / D) whose sampling frequency corresponds at the frequency of clock signal CK. The output of converter 10 is sent to a series of a register entry offset 11 (SREG) dimensioned so that the length of a word it contains corresponds to the number of samples contained in a symbol of transmitted data.
0043All 11 bits of the register are read in parallel and sent to inputs of a multiplexer 12 whose role is to select multiple samples as significant to status symbol.
0044Preferably and as shown in Figure 4, multiplexer 12 selects an odd number of samples ( example, three) provides that a decision circuit 13 (DECID) whose role is to determine the state of the symbol applying a majority decision process. The output of circuit 13 provides the DS bit.
0045According to a preferred embodiment, the selection operated by the multiplexer 12 is configurable. For example, two registers 13 (NREG) and 14 (dreg) contain words indicators of N of a sample position respectively Central in a sample considered reliable range and the distance d between two samples of the beach significant. The respective values of registers 14 and 15 are then used by a calculation circuit 16 providing the multiplexer 12 the respective positions N of the sample Central to the beach and the positions N + d and Nd end samples. This is an example of generation SEL selection signals but other means may to be used. For example, the symmetrical distance d can be replaced by different distances from each other between the sample locations.
0046The respective contents of the registers 14 and 15 are loaded into the circuit 4 by central processing unit 3 according to predetermined parameter data. In a particular example where the size of the register 11 is 16 bits, registers 14 and 15 respectively contain nibbles indicating the significant samples positions.
00475 illustrates, in the form of timing diagrams, the running an optimizing circuit of the invention. These timing diagrams represent for the states 0 and 1 transmitted, respectively the clock signal CK, the AS signal, the signals SEL selection multiplexer 12 and the output of the circuit DS 13.
0048Assume an AS signal having a disturbed shape conventionally. This signal is sampled at the frequency clock CK and the multiplexer selects three samples appointed by their respective position Nd and N + d. In the example of Figure 5, left part, the sampling provides a state 1 of the DS signal while the right side (second symbol) provides a 0 state.
0049An advantage of the present invention is that it avoids any detection errors due to disturbances transients on the demodulated signals. Such disruption is illustrated in the right part of Figure 5 in the form of a peak p. It is clear that, in this case, despite the fact that Sample N is considered a high state, the decision majority performed by circuit 13 confirms the state 0 of the transmitted bit.
0050According to a first embodiment of the invention, the most significant samples are determined during a phase characterization or testing the product or more precisely batch of product. The invention then takes advantage of the fact that the general shape of the AS signal is the often repetitive for a same batch of integrated circuit chips.
0051According to a second embodiment, a phase Learning is performed periodically during the life of the product in order to adapt the receiver to any drifts. These two embodiments are combined.
0052The implementation of a learning phase or characterization does not cause particular difficulties. he enough to know the nature of the message transmitted to several different settings of the registers 14 and 15 and select the first setting which gives a result correct on a number (considered significant) symbols.
0053An advantage of the invention is that it accelerates the transmission rate for a given clock frequency, while remaining compatible with software interpretation the transmitted data. Indeed, the CPU intervenes not (out of the control phase of the registers 14 and 15) the selection itself of the sample. It is therefore possible increase the number of bits transmitted while respecting the for interpretation by the CPU.
0054Thus, taking the example of electromagnetic transponders, on a carrier of 13.56 MHz, the duration T ' a symbol according to the invention can correspond to a flow rate of 847.5 kilobits per second. One such factor 8 (relative to the classic speed 106 kbits / s) seems low but is actually very advantageous. For example, an image that puts classically 4 seconds to be transmitted no longer places, thanks to the invention half a second. This rate is consistent with the rapid analysis needs, including applications authentication or access control.
0055Another advantage of the present invention is that the demodulator thus formed is configurable. The same circuit equipment can be customized to be adapted to different integrated circuits.
0056Of course, the present invention is capable of variants and modifications which will appear to man art. In particular, other frequencies and speeds than those shown above may be exploited.
0057In addition, although the invention has been described especially in relation to an acceleration of flow, it allows, even at a constant rate, to improve the reliability an analog demodulator.
0058In addition, the practical implementation of the invention is within the reach of the skilled person, either by means hardware and / or software from the functional description given above.
0059Finally, the adaptation of the example shown in the first embodiment in which the selection is directly effected on the sampling instants instead on samples themselves is also within reach of the skilled art using components in themselves known.
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Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| CN114745021A | Cited by | China | – | Search report | – |
| GB2075693A | Cites | United Kingdom | X | Search report | 1,9 |
| US5751884A | Cites | United States of America | X | Search report | 1,9 |
6 members in 3 offices; this record represents the family
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| Document | Office | Kind | Date |
|---|---|---|---|
| 0450746 | France | – | |
| 0450746 | France | A |
Members6
| Document | Office | Kind | |
|---|---|---|---|
| US2005238120A1 | United States of America | A1 | |
| EP1592136A1This record | European Patent Office (EPO) | A1 | |
| JP2005312051A | Japan | A | |
| EP1592136B1 | European Patent Office (EPO) | B1 | |
| US8243856B2 | United States of America | B2 | |
| JP5242000B2 | Japan | B2 |
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Numbers
- Publication
- 1592136
- Application
- 51031490
Titles3
- German
- Adaptiver Demodulator
- English
- Adaptive demodulator
- French
- Démodulateur adaptable
Classification
- CPC, 2
- H04L27/06
- H04L25/069
- IPC, 5
- H03M1 12
- H04L27 06
- H04B1 59
- H04L25 06
- H04L25 49
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and 6 moreShow fewer
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