Adaptive demodulator

p0001The present invention relates to the field of satellite receivers and particularly receivers radio frequency signals whose results are to be operated by a digital processing unit.

p0002The document <patcit id="pcit0001" dnum="US5751884A"><text>US-A-5,751,884</text></patcit> An example of such a demodulator.

p0003An example of application of the present invention relates to electromagnetic transponder systems in which a transponder communicates with a read-write terminal without contact.

p0004The <figref idrefs="f0001">figure 1</figref> represents, very schematically and in block form, the demodulation portion receiving radio frequency signals by an electromagnetic transponder.

p0005After they are received by an antenna and shaped by a coupler (not shown) RF radio frequency signals are processed by an analog demodulator 1 (ANALOG DEMOD) whose role is to provide an analog signal AS and a demodulated clock CK sampling. The sampling clock is generally recovered from the transmission carrier. AS and CK signals are sent to a circuit 2 interface (INTERF) whose role is to provide an output signal usable by a microcontroller O 3 (CPU) and other digital circuits. In practice, the Y signal is supplied to a data bus which communicates with the central processing unit 3. In one application to electromagnetic transponders, a transmission of a terminal to a transponder is carried out using a carrier at 13.56 MHz on which are transmitted encoded information, generally in amplitude modulation with a non-zero modulation rate, at a rate of 106 kilobits per second. transponder side, the carrier is used to remotely supply the circuits of the transponder in the case where the latter has no battery. The same principle of demodulation is used in a terminal with the difference that the clock signal is generally present therein without the need to extract the received signal.

p0006The <figref idrefs="f0001">2</figref> illustrates, in timing diagrams, the principle of demodulation carried out in a circu it as shown by the<figref idrefs="f0001">figure 1</figref>.

p0007The first timing diagram illustrates an example of data D transmitted by the RF signal and to be recovered at the output O of the circuit 2. In this example, it is assumed that the transmission of a bit in state 0 corresponds to the inside a bit time T, at a low level followed by a high level while transmitting a 1 corresponds to the reverse (high level followed by a low level). This is an example, and different types of coding and transmission may be used. In the example of electromagnetic transponders using a carrier frequency at 13.56 MHz, the duration T is, for example, to 106 kHz.

p0008The output of the analog demodulator 1 gives an AS signal (second timing) following roughly the shape of the signal D.

p0009The recovered clock signal CK (third timing) corresponds to the carrier signal, that is to say at a frequency of 13.56 MHz. For reasons of clarity, the timing of the<figref idrefs="f0001">2</figref> are not to scale, especially in the time scale of the AS and CK timing.

p0010The last time chart of <figref idrefs="f0001">2</figref> represents the signal O.

p0011In a conventional circuit 2, the AS signal is sampled once in the middle of a cycle (t1 and t2). In fact, the signal AS is sent to the input of an inverter whose switching threshold TH determines the output state O.

p0012A first drawback of a conventional demodulating system as shown by the <figref idrefs="f0001">Figures 1 and 2</figref> is that if the AS signal is disrupted, the time t1 or t2, taking into account the level of the signal may provide an erroneous result.

p0013Another disadvantage is that it is not possible to reconcile the different analysis times of the AS signal to the extent that this would lead to inconsistent speeds the working speed of the CPU clock frequency which corresponds maximum at the frequency of clock CK. Therefore, throughput is limited.

p0014Using the example of electromagnetic transponder systems based on a frequency of 13.56 MHz, the limit is practically 106 kilobits per second to meet the time required for a software analysis of data received.

p0015It would be desirable to increase the transmission speed of such systems. For example, in an application where it is desired transmit images (photographs, biometric fingerprint), a flow rate of 106 kilobits per second results in transmission of several seconds of time, incompatible with the desired analysis speeds.

p0016The present invention aims to optimize the RF signal demodulation and in particular to increase the possible transmission rates for a given clock frequency.

p0017The invention also aims at providing a solution that frees itself of the potential problems of disturbance on the signal from an analog demodulator.

p0018The invention also aims at providing a solution which is compatible with conventional architectures electromagnetic transponders and in particular with systems in which the clock is transmitted together with the radio frequency signal.

p0019To achieve these objects and other, the present invention provides a circuit for detecting a binary state supported by an analog symbol, comprising:<ul><li>an analog-digital conversion element using a sampling signal based on a period of frequency lower than the symbol duration;</li><li>means for selecting a number of significant samples less than the number of samples that would be obtained with a sampling of the symbol at said frequency; and</li><li>decision means the status symbol from selected samples.</li></ul>

p0020According to one embodiment of the present invention, said decision means receive an odd number of samples and provide the binary state of the symbol in Applying a majority decision.

p0021According to one embodiment of the present invention, the respective positions of the significant samples are determined by a learning phase or characterization.

p0022According to one embodiment of the present invention, the sampling signal is derived from the selected positions for the significant samples.

p0023According to one embodiment of the present invention, the sampling signal corresponds to said frequency.

p0024According to one embodiment of the present invention, the output of the analog-digital conversion element is sent to the input of a shift register whose parallel outputs are provided to a select multiplexer of said significant samples.

p0025According to one embodiment of the present invention, registers store at least the position in a symbol of a sample considered significant.

p0026According to one embodiment of the present invention, it is applied to a transmission system between an electromagnetic transponder and a read-write terminal.

p0027The invention also provides a method of determining a binary state supported by an analog symbol, comprising:<ul><li>sampling the symbol with a sampling signal based on a period of frequency lower than the symbol duration;</li><li>select a number of significant samples less than the number of samples that would be obtained with a sampling of the symbol at said frequency; and</li><li>decide the status symbol from selected samples.</li></ul>

p0028According to an embodiment of the present invention, an odd number of samples is selected, the status symbol being determined by majority decision from the respective states of the different samples.

p0029According to one embodiment of the present invention, the respective positions of the significant samples are determined by a learning phase.

p0030According to one embodiment of the present invention, the sampling signal is derived from the selected positions for the significant samples.

p0031According to one embodiment of the present invention, the sampling signal corresponds to said frequency.

p0032These objects, features and advantages, and others of the present invention will be discussed in detail in the following description of specific embodiments in non-limiting in connection with the accompanying drawings:<ul><li>the <figref idrefs="f0001">figure 1</figref> previously described, shows a conventional demodulation architecture;</li><li>the <figref idrefs="f0001">2</figref> previously described, illustrates the operation of the demodulator of the <figref idrefs="f0001">figure 1</figref> ; </li><li>the <figref idrefs="f0002">3</figref> represents, very schematically and in block form, an example of architecture of a demodulator according to the invention;</li><li>the <figref idrefs="f0002">4</figref> represents an embodiment of a demodulation optimizer according to the invention; and</li><li>the <figref idrefs="f0002">5</figref> illustrates, in timing diagram form, operation of a demodulation optimizer according to the invention.</li></ul>

p0033The same elements have been designated by the same references in the different figures. For reasons of clarity, only the elements which are necessary for understanding the invention have been shown in the drawings and will be described subsequently. In particular, the demodulator downstream circuits have not been described in detail, the invention being compatible with any conventional software operating signals. Similarly, the internal structure of an analog demodulator used for the invention corresponds to a conventional structure and has not been detailed.

p0034A feature of the present invention is to select, in a symbol, a number of samples and to deduce from these samples state 0 or 1 of the symbol without using the CPU. According to the invention, the number of samples taken into account is less than the number of samples that would be obtained with a sampling frequency which is based on the sampling signal.

p0035Another feature of the present invention is to select a small number of samples per symbol as corresponding to reliable samples at positions (time) decided during a learning phase or characterization, and infer the state of the symbol of these selected samples.

p0036According to a first embodiment not shown, directly samples the analog signal from an analog demodulator at instants in the symbol that correspond to the moments supplying selected samples. This amounts to generating a sampling signal based on a period of frequency less than the duration of a symbol, but the number of edges is lower than this frequency.

p0037According to a second embodiment, the sampling signal based on the sampling frequency is that frequency directly. The analog signal from the analog demodulator is then sampled at a corresponding frequency, preferably at the maximum available frequency. then it follows from several selected samples of the symbol state 0 or 1 of the latter.

p0038The <figref idrefs="f0002">3</figref> represents, very schematically and in block form, this second embodiment of a demodulator according to the invention.

p0039As before, a radio frequency RF signal is received by an analog demodulator 2 (ANALOG DEMOD) responsible for extracting an analog signal AS and a clock signal CK to the carrier frequency which is here the sampling signal . The signal CK is transmitted to an interface circuit 2 which supplies the digital signal Y to a central processing unit 3 (CPU) in the manner of the conventional circuit of<figref idrefs="f0001">figure 1</figref>.

p0040According to this embodiment of the invention, an optimization circuit demodulating 4 (DEMOPT) is interposed between the output of the analog demodulator 1 providing the signal AS and the corresponding input of the interface circuit 2. This circuit 4 also receives the clock signal CK and CT control signals of the CPU 3.

p0041The circuit 4 has the role of providing a signal DS corresponding to 0 or 1 of the received symbol. Thus, the interface circuit 2 directly receives the useful reports by the central unit 3. According to an embodiment, and subject to the electrical compatibility of O signals with the connecting bus with the CPU 3, circuit 2 may optionally be omitted.

p0042The <figref idrefs="f0002">4</figref> represents an embodiment of a circuit 4 according to the present invention.

p0043The AS signal passes through an analog digital converter 10 (A / D) whose sampling frequency corresponds to the frequency of the clock signal CK. The output of converter 10 is sent to a serial input of a shift register 11 (SREG) dimensioned so that the length of a word it contains corresponds to the number of samples contained in a transmitted data symbol.

p0044All bits of register 11 are read together and sent to the inputs of a multiplexer 12 whose role is to select multiple samples as significant status symbol.

p0045Preferably and as shown in <figref idrefs="f0002">4</figref>, The multiplexer 12 selects an odd number of samples (e.g., three) that provides a decision circuit 13 (DECID) whose role is to determine the state of the symbol by applying a majority decision method . The output of circuit 13 supplies the bit DS.

p0046According to a preferred embodiment, the selection made by the multiplexer 12 is configurable. For example, two registers 13 (NREG) and 14 (DREG) contain signal words respectively to the N position of a central sample in a range of samples considered reliable and the distance d between two samples of the significant range . The respective values ​​of registers 14 and 15 are then used by a calculation circuit 16 providing the multiplexer 12 the respective positions N of the central sample of the beach and the respective positions N + d and Nd end samples. This is an example of a selection signal SEL generation but any other means may be used. For example, the symmetrical distance d may be replaced by different distances from each other between sample locations.

p0047The respective contents of the registers 14 and 15 are loaded into the system by 4 CPU 3 according to predetermined parameter data. In a particular example where the size of the register 11 is 16 bits, the registers 14 and 15 respectively contain quartets indicating the positions of the significant samples.

p0048The <figref idrefs="f0002">5</figref> illustrates in the form of timing diagrams, the operation of an optimization circuit of the invention. These timing diagrams represent, for states 1 and 0 transmitted, respectively the clock signal CK, the AS signal, the selection signal SEL of the multiplexer 12 and the SD output of the circuit 13.

p0049Assume a signal AS having a disturbed form in conventional manner. This signal is sampled at the frequency of clock CK and the multiplexer selects three samples designated by their respective positions Nd and N + d. In the example of<figref idrefs="f0002">5</figref>Partly left, sampling provides a state 1 on the DS signal while the right side (second symbol) provides a 0 state.

p0050An advantage of the present invention is that it avoids any detection errors due to transient disturbances on the demodulated signals. Such a disturbance is shown in right part of the<figref idrefs="f0002">5</figref> in the form of a peak p. It is clear that in this case, despite the fact that the sample N is considered a high state, the majority decision made by the circuit 13 confirms the state 0 of the transmitted bit.

p0051According to a first embodiment of the invention, the most significant samples are determined during a phase characterization or testing the product, or more precisely of a batch of products. The invention then takes advantage of the fact that the general shape of the AS signal is usually repeated for the same batch of integrated circuit chips.

p0052In a second embodiment, a learning phase is performed periodically during the product life to adapt the demodulator to possible abuses. These two embodiments are combined.

p0053The implementation of a learning phase or characterization does not cause any particular difficulty. Just know the nature of the message transmitted to several different settings of the registers 14 and 15 to select the first setting that gives correct results on a number (considered significant) symbols.

p0054An advantage of the invention is that it speeds up the transmission rate for a given clock frequency, while remaining compatible with a software interpretation of the transmitted data. Indeed, the central unit does not intervene (out of the control phase of the registers 14 and 15) in the selection itself of the sample. It is therefore possible to increase the number of bits transmitted while maintaining the possibility of interpretation by the CPU.

p0055Thus, taking the example of electromagnetic transponders, on a carrier of 13.56 MHz, the duration T 'of a symbol according to the invention can correspond to a rate of 847.5 kilobits per second. One such factor 8 (compared with the conventional flow 106 kbits / s) seems small but is actually very advantageous. For example, an image that typically takes 4 seconds to be transmitted no longer places, thanks to the invention half a second. This rate is consistent with the rapid analysis needs, particularly in authentication applications or access control.

p0056Another advantage of the invention is that the demodulator thus formed is configurable. One hardware system can be customized to be adapted to different integrated circuits.

p0057Of course, the present invention is capable of various variants and modifications that occur to those skilled in the art. In particular, other frequencies and speeds than those listed above may be operated.

p0058In addition, although the invention has been described most particularly in relation to an acceleration of flow, it allows, even at a constant rate, to improve the reliability of an analog demodulator.

p0059In addition, the practical implementation of the invention is within the reach of the art, either by hardware and / or software from the functional description given above.

p0060Finally, the adaptation of the example shown in the first embodiment wherein the selection is carried out directly on the sample times rather than the samples themselves is also within the abilities of those skilled in the art using components in themselves known.