A method and apparatus for signal splitting and synthesizing

An apparatus for separating an asynchronous signal, applicable to an Optical Transport Network, OTN, comprising: a first module, configured to memorize, as a function of a sequence of frames, an asynchronous signal to be separated and a second module, configured to manage the first module to memorize the asynchronous signal to be separated and to send n data frames respectively in n channels in parallel, every time n data frames have been memorized, wherein n is a ratio of a level of asynchronous signal rate before separation to a level of asynchronous signal rate after separation; characterized in that the first module comprises: 2n memories of the type 'First in first out' (FIFO) in two groups, each group comprising n FIFO memories and each FIFO memory storing a data frame each time and the second module that includes: a frequency module divided by n, configured to reduce a frequency of an input clock signal to 1 / n of the frequency of the clock signal at the input, as well as to send a clock signal to the output with a frequency 1 / n of the frequency of the clock signal at the input; a write address generation module, configured to manage a write operation of each FIFO memory to memorize the n data frames of the asynchronous signal based on the frame sequence and a read address generation module, configured to manage a read operation of each FIFO memory to send n data frames respectively in n parallel channels each time n data frames have been memorized; wherein the write address generation module is configured to generate a write address control signal and a write validation control signal based on the frequency of the clock signal at the input, to apply the write direction control signal and the write validation control signal to each FIFO memory as well as to manage the asynchronous signal to be written in series in a group of FIFO memories depending on the frame sequence and the read address generation module is configured to receive the clock signal at the output from the frequency module divided by n, to generate a read direction control signal and a read validation control signal based on the clock signal at the output as well as to send the read direction control signal and the read validation control signal to each FIFO memory and to manage n data frames in the other group of FIFO memories to be read in parallel.