Nova Patents
EP1865632B1

A method and apparatus for signal splitting and synthesizing

Abstract

This record has no abstract on file.

EP1865632B1, drawing sheet 1
Sheet 1 of 13

Term

Term ended

Expired 24 March 2026, 0.5 years ago.

  1. Priority and filed
  2. Granted
  3. Expired
  4. Today

5 claims: 2 independent, 3 dependent

  1. 1
    An apparatus for splitting an asynchronous signal, applicable to an Optical Transport Network, OTN, comprising:a first module, configured to buffer, according to frame sequence, an asynchronous signal to be split;and a second module, configured to manage the first module to buffer the asynchronous signal to be split, and send n frames of data respectively on n channels in parallel whenever n frames of data have been buffered, wherein n is a ratio of a rate level of the asynchronous signal before split to a rate level of the asynchronous signal after split;characterized by the first module comprising: 2n First In First Out (FIFO) memories in two groups, each group comprising n FIFO memories and each FIFO memory storing one frame of data each time;and the second module comprising: a frequency-divided-by-n module, configured to reduce a frequency of an input clock signal to 1/n of the frequency of the input clock signal, and send an output clock signal with a frequency of 1/n of the frequency of the input clock signal;a write address generation module, configured to manage a write operation of each FIFO memory to buffer the n frames of data of the asynchronous signal according to the frame sequence;and a read address generation module, configured to manage a read operation of each FIFO memory to send n frames of data respectively on n channels in parallel whenever n frames of data have been buffered;wherein the write address generation module is configured to generate a write address control signal and a write enabling control signal according to the frequency of the input clock signal, input the write address control signal and the write enabling control signal to each FIFO memory, and manage the asynchronous signal to be serially written into one group of FIFO memories according to the frame sequence;and the read address generation module is configured to receive the output clock signal from the frequency-divided-by-n module, generate a read address control signal and a read enabling control signal according to the output clock signal and send the read address and the read enabling control signal to each FIFO memory, and manage n frames of data in the other group of FIFO memories to be read in parallel.
  2. 3
    An apparatus for signal combination, applicable to an Optical Transport Network, OTN, comprising:a third module, configured to align n channels of parallel signals to be combined and buffer the n channels of the parallel signals to be combined simultaneously according to frame sequence;and a fourth module, configured to manage the third module to buffer the n channels of the parallel signals to be combined simultaneously, and send n channels of frames serially after one frame is buffered for each of the n channels of the parallel signals;wherein n is a ratio of a rate level of the parallel signals after combined to a rate level of the parallel signals before combined;characterized by the third module comprising: 2n First In First Out (FIFO) memories in two groups, each group comprising n FIFO memories and each FIFO memory storing one frame of data each time;the fourth module comprising: a frequency-multiplied-by-n module, configured to convert a frequency of an input clock signal to n times the frequency of the input clock signal, and send an output clock signal with a frequency of n times the frequency of the input clock signal;a write address generation module, configured to manage a write operation of each FIFO memory to buffer the n channels of the parallel signals to be combined simultaneously;and a read address generation module, configured to manage a read operation of each FIFO memory to send the n channels of frames serially after one frame is buffered for each of the n channels of the parallel signals;wherein the write address generation module is configured to generate a write address control signal and a write enabling control signal according to the frequency of the input clock signal, and send the write address control signal and the write enabling control signal to each FIFO memory, and manage the n channels of the parallel signal to be written simultaneously into one group of FIFO memories in parallel according to the frame sequence;and the read address generation module is configured to receive the output clock signal from the frequency-multiplied-by-n module, generate a read address control signal and a read enabling control signal according to the output clock signal, and send the read address control signal and the read enabling control signal to each FIFO memory to manage the other group of FIFO memories to send the n channels of frames serially.
Independent claims2