Nova Patents
EP1865632A1

A method and apparatus for signal splitting and synthesizing

Abstract

A method and apparatus for splitting an asynchronous signal are provided. The method includes: buffering an asynchronous signal to be split on the basis of a frame and frame sequence, sending n frames of data respectively on n channels in parallel whenever n frames of data have been buffered; and buffering next n frames of data of the asynchronous signal to be split, where n is a ratio of a rate level of the asynchronous signal before split to that of the asynchronous signal after split. A method and apparatus for signal combination are provided. The method includes: buffering n channels of parallel signals to be combined simultaneously on the basis of a frame and according to frame sequence; and sending n channels of frames of data serially after one frame is buffered for each of the n channels of the parallel signals.

EP1865632A1, drawing sheet 1
Sheet 1 of 14

Term

Term ended

Projected expiry passed 24 March 2026, 0.5 years ago.

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  4. Today

11 claims: 4 independent, 7 dependent

  1. 1
    A method for splitting an asynchronous signal, comprising:buffering, on the basis of a frame and according to frame sequence, an asynchronous signal to be split;sending n frames of data respectively on n channels in parallel whenever n frames of data have been buffered;and buffering next n frames of data of the asynchronous signal to be split;wherein n is a ratio of a rate level of the asynchronous signal before split to a rate level of the asynchronous signal after split.
  2. 4
    An apparatus for splitting an asynchronous signal, comprising:2n First In First Out (FIFO) memories in two groups, each group comprising n FIFO memories and each FIFO memory storing one frame of data each time;a write address generation module, configured to manage a write operation of each FIFO memory;a read address generation module, configured to manage a read operation of each FIFO memory;a frequency-divided-by-n module, configured to reduce a frequency of an input clock signal to 1/n of the frequency of the input clock signal, and send an output clock signal with a frequency of 1/n of the frequency of the input clock signal;wherein n is a ratio of a rate level of the asynchronous signal before split to a rate level of the asynchronous signal after split;the write address generation module is configured to generate a write address control signal and a write enabling control signal according to the frequency of the input clock signal, input the write address control signal and the write enabling control signal to each FIFO memory, and manage the asynchronous signal to be serially written into one group of FIFO memories;and the read address generation module is configured to receive the output clock signal from the frequency-divided-by-n module, generate a read address control signal and a read enabling control signal according to the output clock signal and send the read address and the read enabling control signal to each FIFO memory, and manage n frames of data in the other group of FIFO memories to be read in parallel.
  3. 6
    A method for signal combination, comprising:buffering n channels of parallel signals to be combined simultaneously on the basis of a frame and according to frame sequence;and sending n channels of frames of data serially after one frame is buffered for each of the n channels of the parallel signals;wherein n is a ratio of a rate level of the parallel signals after combined to a rate level of the parallel signals before split
  4. 9
    An apparatus for signal combination, comprising:2n First In First Out (FIFO) memories in two groups, each group comprising n FIFO memories and each FIFO memory storing one frame of data each time;a write address generation module, configured to manage a write operation of each FIFO memory;and a read address generation module, configured to manage a read operation of each FIFO memory;a frequency-multiplied-by-n module, configured to convert a frequency of an input clock signal to n times the frequency of the input clock signal, and send an output clock signal with a frequency of n times the frequency of the input clock signal;wherein n is a ratio of a rate level of the parallel signals before split to a rate level of the parallel signals after split;wherein the write address generation module is configured to generate a write address control signal and a write enabling control signal according to the frequency of the input clock signal, and send the write address control signal and the write enabling control signal to each FIFO memory, and manage the n channels of the parallel signal to be written simultaneously into one group of FIFO memories in parallel according to the frame sequence;the read address generation module is configured to receive the output clock signal from the frequency-multiplied-by-n module, generate a read address control signal and a read enabling control signal according to the output clock signal, and send the read address control signal and the read enabling control signal to each FIFO memory to manage the other group of FIFO memories to send the n channels of frames serially;the two groups of FIFO memories performed the above processes alternatively.
Independent claims4