Magnetic field sensor comprising a hall element

The invention relates to a magnetic field sensor with a symmetrical vertical Hall element referred to in the preamble of claim 1 Art.

Magnetic field sensors based on a Hall element have been manufactured in large quantities for years and used in industry, household appliances and automotive as position switches or for position measurement. Hall elements fabricated using conventional IC technology have all the advantages of these technologies, in particular the high reproducibility of their magnetic and electrical properties at comparatively low cost. For the measurement of the component of the magnetic field, which is perpendicular to the chip surface, so-called horizontal Hall elements are used, while for the measurement of the components of the magnetic field, which run parallel to the chip surface, so-called vertical Hall elements are used.

A conventional Hall element has four contacts, namely two current contacts for the supply and discharge of a current flowing through the Hall element current and two voltage contacts in order to tap the Hall voltage generated by the magnetic field component to be measured. A fundamental problem of the Hall elements is that even between the two voltage contacts, a voltage is present, the so-called offset voltage when no magnetic field is present. To reduce the offset voltage, two techniques have been developed. One technique, which is used for horizontal Hall elements, uses two horizontal Hall elements, with the two currents flowing through the two Hall elements at an angle of 90 °. At the other, from the<patcit id="pcit0001" dnum="US4037150A"><text>US 4,037,150</text></patcit> known technique, which is suitable for symmetric Hall elements that are electrically opposite to a permutation of the current and voltage contacts are invariant, the current and voltage contacts are electrically commutated. This technique, which was developed for horizontal Hall elements, can be done according to the<patcit id="pcit0002" dnum="US5057890A"><text>US 5 057 890</text></patcit> also be used for vertical Hall elements, in which the position and size of the current and voltage contacts were calculated by means of a conformal image of a symmetrical horizontal Hall element.

The present invention relates to symmetrical vertical Hall elements, which are Hall elements in which four contacts, namely two inner and two outer contacts, are arranged along a line. The two inner contacts are typically the same size and the two outer contacts are the same size. The current flows from an inner contact to the non-adjacent outer contact, respectively, or vice versa. In these symmetrical vertical Hall elements, the current and voltage contacts can be reversed because of their geometric symmetry, that is electrically commutated, without changing the electrical and magnetic properties of the Hall element.

Symmetrical vertical Hall elements are from the above cited <patcit id="pcit0003" dnum="US5057890A"><text>US 5 057 890</text></patcit> and from the article "<nplcit id="ncit0001" npl-type="s"><text>A Symmetrical Vertical Hall-Effect Device "published in the journal Sensors and Actuators, A21-A23 (1990), pages 751-753</text></nplcit>, was published, known, but have hardly been used in practice, since they were previously produced only in a special technology that did not allow to integrate electronic switching elements on the same semiconductor chip in addition to the Hall element.

From the <patcit id="pcit0004" dnum="US5572058A"><text>US 5,572,058</text></patcit> is a vertical Hall element known in bipolar technology. In this technology, the Hall element is insulated from the substrate, so that in addition to the Hall element and electronic elements can be integrated on the same semiconductor chip. However, this vertical Hall element having five contacts arranged along a straight line, namely a central contact and two external contacts which serve as current contacts, and two voltage contacts which are arranged between the central contact and one of the outer contacts, does not belong to the group of symmetrical vertical Hall elements, because the electrical properties of the Hall element change in a permutation of the current and voltage contacts.

The invention has for its object to develop a symmetrical vertical Hall element, which can be realized in an n-type well of a CMOS technology in which the two voltage contacts potential lying approximately in the middle between the potentials of the two power contacts and in which the Offset voltage is as small as possible.

The above object is achieved by the features of claims 1 to 6.

On the one hand, this problem poses the problem that the lengths of the current and voltage contacts calculated using conformal mappings are smaller than the minimum dimensions permitted by the technology. The reason is that the depth of the n-type well is very small compared to the distance between the outer edges of the outer contacts. If the current and voltage contacts are increased in comparison to the calculated ideal values ​​in accordance with the minimum requirements of the technology, then the two voltage contacts are potentially no longer in the middle between the potentials of the two current contacts, the offset voltage becomes comparatively very large and the sensitivity decreases considerably. If the two voltage contacts are potentially no longer in the middle between the potentials of the two current contacts, this means that the commutation of the current and voltage contacts can no longer be meaningfully applied. In addition, the doping of the n-type well is not homogeneous. As a result, first, most of the current flows directly below the surface of the Hall element, typically in a layer of only one to two microns thick, even though the n-type well has a diffusion depth of several microns, and secondly, the Theory of compliant mapping is no longer applicable. In addition, the doping of the n-type well is not homogeneous. As a result, first, most of the current flows directly below the surface of the Hall element, typically in a layer of only one to two microns thick, even though the n-type well has a diffusion depth of several microns, and secondly, the Theory of compliant mapping is no longer applicable. In addition, the doping of the n-type well is not homogeneous. As a result, first, most of the current flows directly below the surface of the Hall element, typically in a layer of only one to two microns thick, even though the n-type well has a diffusion depth of several microns, and secondly, the Theory of compliant mapping is no longer applicable.

The invention is based on a symmetrical vertical Hall element with four contacts, namely two inner and two outer contacts, which are arranged on the surface of a semiconductor chip along a line. The two inner contacts are preferably the same width and the two outer contacts are preferably the same width, the width of the contacts is measured in the direction of the straight line.

The symmetric vertical Hall element comprises a well of a first conductivity type embedded in a substrate of a second conductivity type. The four contacts contact the tub. Such a Hall element with four contacts can be seen in electrical terms as one through four resistors R₁ to R₄ the Hall element formed resistance bridge are considered. During operation of the Hall element as a magnetic field sensor in each case a current flows between two contacts that are not adjacent. The Hall element is considered to be ideal in electrical terms when the four resistors R₁ to R₄ have the same value. In this case, when feeding the Hall element via two power contacts serving as voltage contacts contacts are both at the same electrical potential, namely the potential of half the supply voltage. In addition, then the voltage between the voltage contacts, the so-called offset voltage, equal to zero, ie the offset voltage disappears. The same applies if the role of the current and voltage contacts is reversed.

According to the invention, it is proposed to arrange the four contacts of the Hall element such that three of the four resistors R₁, R₂ and R₃ for geometric reasons are approximately equal. The fourth resistor R₄, namely the electrical resistance between the two external contacts, is greater than the other resistors R₁, R₂ and R₃, In order to symmetrize the resistance bridge, the invention further proposes a further resistor R₅ parallel to the resistor R₄ whose value is determined so that approximately R₁ = R₂ = R₃ = R₄ || R₅ applies. The resistance R₅ is, for example, an external resistor. Preferably, the resistor R₅ However, embedded in the tub of the Hall element or realized as a separate n-type well. In the first case, the resistor has at least one contact, which contacts the trough of the Hall element and is arranged next to one of the two outer contacts on the side of the edge of the trough. The advantage is that the resistor R₅ in this case, the same temperature coefficient as the resistors R₁, R₂, R₃ and R₄ so that the resistance bridge remains in equilibrium even with temperature fluctuations.

Another possibility for electrically matching the resistance bridge is to provide at least one electrode which is electrically insulated with respect to the trough, wherein the at least one electrode is arranged between each two contacts. The at least one electrode serves to locally increase or decrease the electrical conductivity of the well in the area below the electrode.

Yet another way to electrically balance the resistance bridge is to locally increase or decrease the electrical conductivity of the well in the area between two contacts by local implantation of additional or fewer ions.

Yet another possibility, not related to the subject matter of the invention, of electrically adjusting the resistance bridge is to use a magnetic field sensor with a first Hall element and a second Hall element, each having two inner and two outer contacts arranged along a straight line, preferably the two inner contacts are the same width and preferably wherein the two outer contacts are the same width, wherein the straight lines of the two Hall elements are parallel and wherein the contacts of the two Hall elements are wired via conductor tracks such that their Hall voltages are in the same direction and their offset voltages largely compensate, so that the total resulting offset voltage almost disappears.

Embodiments of the invention will be explained in more detail with reference to the drawing. The figures are not drawn to scale.

Show it:<dl id="dl0001" compact="compact"><dt>Fig. 1</dt><dd>a symmetrical vertical Hall element in cross section,</dd><dt>Fig. 2</dt><dd>the symmetrical vertical Hall element in supervision,</dd><dt>Fig. 3</dt><dd>an electrical equivalent circuit diagram for the symmetrical vertical Hall element,</dd><dt>Fig. 4</dt><dd>a symmetrical vertical Hall element with an integrated resistor,</dd><dt>Fig. 5</dt><dd>a symmetrical vertical Hall element with two integrated resistors,</dd><dt>Fig. 6</dt><dd>a symmetrical vertical Hall element with additional electrodes,</dd><dt>Fig. 7</dt><dd>a mask that is used in the implantation of ions for the formation of an n-type well, and</dd><dt>Fig. 8, 9</dt><dd>two anti-parallel Hall elements.</dd></dl>

The <figref idrefs="f0001">Fig. 1 and 2</figref> show a symmetrical vertical Hall element 1 in cross section or in plan view. The Hall element 1 fabricated in a CMOS technology preferably consists of a well 2 of a first conductivity type embedded in a substrate 3 of silicon of a second conductivity type. The Hall element 1 has on the surface four contacts 4-7, namely two inner contacts 5 and 6, and two outer contacts 4 and 7. The contacts 4-7 are along a straight line 8 (FIG.<figref idrefs="f0001">Fig. 2</figref>) arranged. Preferably, the two inner contacts 5 and 6 seen in the direction of the straight line 8 are the same width and the two outer contacts 4 and 7 are the same width. The position and size of the tub 2 and the contacts 4 - 7 is then symmetrical with respect to a plane 9 which is perpendicular to the straight line 8 and in the middle between the two inner contacts 5 and 6. (For technological reasons, it makes sense to make the two inner contacts 5 and 6 the same width and the two outer contacts 4 and 7 the same width, but it is not absolutely necessary.)

Because the mobility of the electrons in silicon is greater than the mobility of the holes, it is advantageous for the Hall element 1 to use an n-conducting well and not a p-conducting well. Although a p-type well could be used for the Hall element 1, the sensitivity of the magnetic field sensor would then be significantly smaller.

The depth t of the tub 2 is typically about 5 microns. Since the doping of the well 2 is not homogeneous, but decreases exponentially with increasing depth, most of the current flows below the surface of the Hall element 1 in a thin layer of typically 1-2 μm thickness. The effective for the electrical and magnetic properties of the Hall element 1 depth t_eff the tub 2 is thus only about 1 - 2 microns. The length L of the Hall element 1 is given by the length of the trough 2. It substantially corresponds to the distance between the outer edges 10 and 11 of the outer contacts 4 and 7. The length L is large compared to the depth t or to the effective Depth t_eff, The electrical properties of the Hall element 1 can by one of four resistors R₁ to R₄ formed resistance bridge are shown. Because of the easier understanding, are in the<figref idrefs="f0001">Fig. 1</figref> the resistances prevailing between each two contacts by a resistance symbol R₁ to R₄ and a line connecting the contacts corresponding to the resistor.

The <figref idrefs="f0001">Fig. 3</figref> shows the electrical diagram of the through the four resistors R₁ to R₄ the Hall element 1 formed resistance bridge. When operating the Hall element 1 as a magnetic field sensor in each case a current flows between two contacts that are not adjacent, for example, between the contacts 4 and 6 or between the contacts 5 and 7. The Hall element 1 is considered to be ideal in electrical terms, if the four Resistors R₁ to R₄ have the same value. In this case, when feeding the Hall element 1 via the contacts 4 and 6, the contacts 5 and 7 serving as voltage contacts are both at the same electrical potential, namely the potential of half the supply voltage. In addition, then the voltage between the voltage contacts is equal to zero, ie the offset voltage disappears. The same applies if the Hall element 1 is fed via the contacts 5 and 7 and the contacts 4 and 6 serve as voltage contacts.

The resistors R₁ and R₃ are the same size for geometric reasons. The resistance R₂ can be changed by increasing or decreasing the distance between the inner contacts 5 and 6. By a suitable choice of the position and size of the contacts 4-7, one can thus achieve that approximately R₁ = R₂ = R₃ applies. In addition, the resistance R₄ larger than the other resistors R₁, R₂ and R₃ is. In order to symmetrize the resistance bridge, the invention proposes a further resistor R₅ parallel to the resistor R₄ whose value is determined so that approximately R₁ = R₂ = R₃ = R₄ || R₅ applies. The resistance R₅ is, for example, an external resistor. Preferably, the resistor R₅ However, embedded in the n-type well 2 of the Hall element 1 or realized as a separate n-type well. The advantage is that the resistor R₅ in this case, the same temperature coefficient as the resistors R₁, R₂, R₃ and R₄ so that the resistance bridge remains in equilibrium even with temperature fluctuations.

The <figref idrefs="f0002">4 and 5</figref> show two examples in which the resistance R₅ is embedded in the trough 2 of the Hall element 1. For ease of understanding, the resistances prevailing between any two contacts are again represented by a resistance symbol and a line connecting the corresponding contacts. In the example according to the<figref idrefs="f0002">Fig. 4</figref> next contact 4, a further contact 12 is arranged, which is connected via a conductor 13 shown only schematically with the contact 7. In the example according to the<figref idrefs="f0002">Fig. 5</figref> In addition to the contact 4, a further contact 12 and next to the contact 7, a further contact 14 are arranged, wherein the two additional contacts 12 and 14 are connected via a again shown only schematically trace 13. In this example, therefore, the resistor R₅ not by a single resistor, but by two resistors with the value ½R₅ realized.

The miniaturization of the Hall element are limited by the fact that between the two inner contacts 5 and 6, a conditional by the technology minimum distance is observed. This minimum distance is currently in the range of about 0.8 microns. The resistance R₂ can therefore not fall below a certain value given by the technology used. In the following, further examples will be explained how the resistors R₁ to R₃ can be increased or decreased.

In the example according to the <figref idrefs="f0002">Fig. 6</figref> between the contacts 4 - 7, three electrodes 15 - 17 are arranged, which are realized, for example, like the gate electrodes of a MOSFET's polysilicon. The electrodes 15-17 are separated from the n-type well eg by a thin oxide layer and thus electrically insulated from the n-type well 2. During operation of the Hall element 1, the electrodes 15-17 are each biased with respect to the n-type well 2 with a predetermined voltage. The electrodes 15 and 17 are biased at the same voltage while the electrode 16 is biased with a voltage of reverse polarity. The bias of an electrode with respect to the n-type well 2 causes, depending on the sign of the bias, the charge carrier density in the area below the electrode either increased or decreased. In order to increase the carrier density, the bias voltage of the electrode must be inverse to the type of carrier of the well 2. If the well 2 is n-type, then the bias of the electrode must be positive with respect to the potential of the well 2. In order to reduce the charge carrier density, the bias voltage of the electrode must be equal to the type of the carrier of the tub 2. In this case, if the well 2 is n-type, then the bias of the electrode in this case must be negative with respect to the potential of the well 2. the bias of the electrode must be equal to the type of carrier of the tub 2. In this case, if the well 2 is n-type, then the bias of the electrode in this case must be negative with respect to the potential of the well 2. the bias of the electrode must be equal to the type of carrier of the tub 2. In this case, if the well 2 is n-type, then the bias of the electrode in this case must be negative with respect to the potential of the well 2.

It is also possible, instead of three electrodes 15, 16 and 17, to provide only a single electrode, namely the electrode 16 between the inner contacts 5 and 6, or only the two electrodes 15 and 17, each between an inner and an outer contact are arranged. It is possible to zoom in the example according to the<figref idrefs="f0002">Fig. 4</figref> to provide a further electrode, which is arranged between the contacts 4 and 12, or in the example according to the <figref idrefs="f0002">Fig. 5</figref> to provide two more electrodes, which are arranged between the contacts 4 and 12 or 7 and 14. By selecting the magnitude and sign of the biases applied to the individual electrodes, the resistors R₁ to R₅ be changed within certain limits. Therefore, electronic voltage sources are provided, which are realized in the same semiconductor chip as the Hall element 1, wherein the bias voltages to be applied to the individual electrodes are once determined in a calibration method such that the resistances R₁ to R₅ formed resistance bridge is optimally balanced.

Another way, the resistors R₁ to R₃ With a given position and size of the contacts 4-7 to reduce or increase, is to increase or decrease the charge carrier density by means of local implantation of additional or fewer ions. This possibility is based on the<figref idrefs="f0003">Fig. 7</figref> explained in more detail. The contacts 4 to 7 are represented by areas which are surrounded by a dashed line 18. In the formation of the n-type well 2, a mask 19 is used for the ion implantation, which does not have a single, the size of the tub 2 corresponding opening 20, but an opening 20, the local islands 21 having a portion of the opening 20th cover, so that the doping of the n-type well 2 varies locally. The dimensions of the islands 21 are chosen so small that the regions separated by the islands 21 connect to the n-type well 2 at the diffusion following the implantation.

The <figref idrefs="f0003">8 and 9</figref> illustrate another possibility not concerning the subject of the invention, which is represented by the resistors R₁ to R₄ formed resistance bridge largely, namely by a parallel connection of two Hall elements 1 and 1 ', which are arranged parallel to each other so that they measure the same component of the magnetic field. The directions of the currents flowing through the two Hall elements 1 and 1 'are symbolically represented by arrows pointing from the contact where the current is fed to the contact where the current is dissipated. The contacts 4 - 7 of the first Hall element 1 and the contacts 4 '- 7' of the second Hall element 1 'are wired in pairs via schematically illustrated interconnects 13. The wiring must meet two criteria, which are described below. First, the Hall voltages generated by the magnetic field of the two Hall elements 1 and 1 'must be in the same direction, otherwise "₄ larger than the other resistors R₁, R₂ and R₃ is. Likewise, in the case of the second Hall element 1 ', one of the two voltage contacts 4' and 6 'would lead to a higher potential than the other voltage contact, because here too the resistance R₄'greater than the other resistors R₁', R₂'and R₃'is. In the example of<figref idrefs="f0003">Fig. 8</figref> leads - at the in the <figref idrefs="f0003">Fig. 8</figref> illustrated direction of the current - the voltage contact 7 of the first Hall element 1, the higher potential than the voltage contact 5. In the second Hall element 1 'leads the voltage contact 4', the higher potential than the voltage contact 6 '. The voltage contacts 7, 5, 4 'and 6' of the two Hall elements 1 and 1 'are now secondly wired such that the voltage contact 7 of the first Hall element 1, which carries the higher potential, with the voltage contact 6' of the second Hall element 1 ' that leads to the smaller potential. Because of this wiring, the currents flowing through the two Hall elements 1 and 1 'divide so that the voltage applied between the voltage contacts 7 and 5 of the first Hall element 1 with a vanishing magnetic field, the so-called offset voltage, is much smaller than they would be without the connection of the second Hall element 1 'in the manner described. In the in the<figref idrefs="f0003">Fig. 8</figref> For example, the contacts 4 - 7 of the first Hall element 1 and the contacts 4 '- 7' of the second Hall element 1 'so wired in pairs as follows: the contact 4 with the contact 7', the contact 5 with the contact 4 ', the Contact 6 with the contact 5 'and the contacts 7 with the contact 6', wherein the currents in both Hall elements 1 and 1 'in each case from an inner contact to the non-adjacent outer contact, but in the opposite direction, flow.

In the in the <figref idrefs="f0003">Fig. 9</figref> In the example shown, the currents flow in the same direction, in the first Hall element 1 from an inner contact to the non-adjacent outer contact, in the second Hall element 1 ', however, from an outer contact to the non-adjacent inner contact. The contacts 4 - 7 of the first Hall element 1 and the contacts 4 '- 7' of the second Hall element 1 'are wired in pairs as follows: the contact 4 with the contact 5', the contact 5 with the contact 6 ', the contact 6 with the contact 7 'and the contact 7 with the contact 4', so that the two criteria given above are met.

In the embodiments described so far, the symmetric vertical Hall element 1 is embedded in the n-type well 2, which was generated by implantation of ions and subsequent diffusion in a p-type substrate. Such technology is commonly referred to as CMOS technology. However, instead of a CMOS technology, a bipolar technology may be used in which the symmetrical vertical Hall element 1 is embedded in an isolated region in an epitaxial layer. Such an isolated area may also be referred to as an n-well. While the bipolar n-type well is homogeneously doped with impurities, doping of the n-type well made in CMOS technology is not homogeneous.