Magnetic field sensor comprising a hall element

p0001The invention relates to a magnetic field sensor with a symmetrical vertical hall element of the type mentioned in the preamble of claim 1.

p0002Magnetic field sensors based on a hall element have been manufactured for many years in large numbers and are used as position switches or for position measurement in industry, in household appliances and in automotive engineering. Hall elements made in conventional IC technology all have advantages of these technologies, in particular the high reproducibility of their magnetic and electrical properties at comparatively low cost. For the measurement of the component of the magnetic field, which is perpendicular to the chip surface, so-called horizontal hall elements are used, while so-called vertical hall elements are used for the measurement of the components of the magnetic field, which run parallel to the chip surface.

p0003A conventional hall element has four contacts, namely two current contacts for the supply and dissipation of a current flowing through the hall element, and two voltage contacts in order to pick up the Hall voltage generated by the magnetic field component to be measured. A fundamental problem of the hall elements is that a voltage is also present between the two voltage contacts, the so-called offset voltage when no magnetic field is present. Two techniques have been developed to reduce the offset voltage. In one technique, which is used in horizontal hall elements, two horizontal hall elements are used, the two streams flowing through the two hall elements enclosing an angle of 90 °. At the other, from the<patcit id="pcit0001" dnum="US4037150A"><text>US 4,037,150</text></patcit> Known technique which is suitable for symmetrical hall elements which are electrically invariant against a reversal of the current and voltage contacts, the current and voltage contacts are electrically commutated. This technique, which has been developed for horizontal hall elements, can be designed according to the<patcit id="pcit0002" dnum="US5057890A"><text>US 5 057 890</text></patcit> Can also be used for vertical hall elements in which the position and size of the current and voltage contacts have been calculated by means of a conformal image of a symmetrical horizontal hall element.

p0004The present invention relates to symmetrical vertical hall elements, which are hall elements in which four contacts, namely two inner and two outer contacts, are arranged along a line. The two inner contacts are typically the same size and the two outer contacts are of the same size. The current flows in each case from an internal contact to the non-adjacent external contact, or vice versa. With these symmetrical vertical hall elements, the current and voltage contacts can be interchanged, that is to say electrically commutated, without the electrical and magnetic properties of the hall element changing.

p0005Symmetrical vertical hall elements are from the above cited <patcit id="pcit0003" dnum="US5057890A"><text>US 5 057 890</text></patcit> And from the article "<nplcit id="ncit0001" npl-type="s"><text>A Symmetrical Vertical Hall Effect Device ", published in the journal Sensors and Actuators, A21-A23 (1990), pages 751-753</text></nplcit>, Have so far hardly been used in practice since they have so far only been produced in a special technology which, in addition to the hall element, also allows for the integration of electronic switching elements on the same semiconductor chip.

p0006From the <patcit id="pcit0004" dnum="US5572058A"><text>US 5 572 058</text></patcit> A vertical hall element is known in bipolar technology. With this technology, the hall element is insulated from the substrate so that, in addition to the hall element, electronic elements can also be integrated on the same semiconductor chip. This vertical hall element, which has five contacts arranged along a straight line, namely a central contact and two external contacts which serve as current contacts, and two voltage contacts, which are arranged between the central contact and one of the external contacts, is not part of the symmetrical vertical group Hall elements because the electrical properties of the hall element change when the current and voltage contacts are interchanged.

p0007The invention is based on the object of developing a symmetrical vertical hall element which can be implemented in an n-conducting trough of a CMOS technology, in which the two voltage contacts lie potentially approximately in the middle between the potentials of the two current contacts, Offset voltage is as small as possible.

p0008The stated object is achieved according to the invention by the features of claims 7 and 7.

p0009In this task, the problem arises that the lengths of the current and voltage contacts computed by means of conformal mappings are smaller than the minimum dimensions permitted by the technology. The reason is that the depth of the n-type well is very small compared to the distance between the outer edges of the outer contacts. If the current and voltage contacts are increased compared to the calculated ideal values ​​according to the minimum requirements of the technology, the two voltage contacts are potentially no longer in the middle between the potentials of the two current contacts, the offset voltage is comparatively very large and the sensitivity is greatly reduced. If the two voltage contacts no longer lie in the middle between the potentials of the two current contacts, this means that the commutation of the current and voltage contacts can no longer be used in a meaningful manner. In addition, the doping of the n-conducting well is not homogeneous. As a result, firstly, most of the current flows directly below the surface of the hall element, typically in a layer of only one to two micrometres thickness, even if the n-conducting well has a depth of diffusion of several micrometers, and secondly, Theory of the conformal image is no longer applicable.

p0010The invention is based on a symmetrical vertical hall element with four contacts, namely two inner and two outer contacts arranged on the surface of a semiconductor chip along a line. The two inner contacts are preferably of the same width and the two outer contacts are preferably of the same width, the width of the contacts being measured in the direction of the straight line.

p0011The symmetrical vertical hall element comprises a tub of a first conductivity type embedded in a substrate of a second conductivity type. The four contacts contact the tub. Such a hall element with four contacts can be electrically connected as one through four resistors R₁ to R₄ Of the hall element. During the operation of the hall element as a magnetic field sensor, in each case a current flows between two contacts which are not adjacent. The hall element is considered as ideal in electrical terms if the four resistors R₁ to R₄ Have the same value. In this case, when the hall element is fed via two current contacts, the contacts serving as voltage contacts are both at the same electrical potential, namely the potential of the half-voltage supply. In addition, the voltage between the voltage contacts, the so-called offset voltage, is then equal to zero, ie the offset voltage disappears. The same also applies when the role of the current and voltage contacts is interchanged.

p0012According to the invention, it is proposed to arrange the four contacts of the hall element such that three of the four resistors R₁, R₂ and R₃ Are approximately the same size for geometrical reasons. The fourth resistor R₄, Namely the electrical resistance between the two external contacts, is greater than the other resistances R₁, R₂ and R₃. In order to symmetrize the resistor bridge, it is further proposed according to the invention to provide a further resistor R₅ Parallel to the resistor R₄ , The value of which is determined such that approximately R₁ = R₂ = R₃ = R₄ || R₅ Is applicable. The resistance R₅ Is, for example, an external resistor. Preferably the resistance is R₅ But embedded in the trough of the hall element or realized as a separate n-conducting trough. In the first case, the resistor has at least one contact which contacts the trough of the hall element and is arranged next to one of the two outer contacts on the side assigned to the edge of the trough. The advantage is that the resistance R₅ In this case the same temperature coefficients as the resistors R₁, R₂, R₃ and R₄ So that the resistance bridge also remains in equilibrium during temperature fluctuations.

p0013A further possibility of electrically dissipating the resistor bridge is to provide at least one electrode electrically insulated from the trough, the at least one electrode being arranged between two contacts each. The at least one electrode serves to locally increase or decrease the electrical conductivity of the well in the region below the electrode.

p0014A further possibility of electrically balancing the resistance bridge is to locally increase or reduce the electrical conductivity of the well in the region between two contacts by local implantation of additional or fewer ions.

p0015A still further possibility of equilibrating the resistance bridge is to use a magnetic field sensor with a first hall element and a second hall element, each having two inner and two outer contacts arranged along a straight line, the two inner contacts being preferably of the same width, Wherein the two outer contacts are of the same width, wherein the straight lines of the two Hall elements are parallel, and wherein the contacts of the two hall elements are wired via conductor tracks such that their Hall voltages are identical and their offset voltages largely compensate for the overall resulting offset voltage disappears.

p0016Exemplary embodiments of the invention are explained in more detail below with reference to the drawing. The figures are not drawn to scale.

p0017Show it:<dl id="dl0001" compact="compact"><dt>FIG</dt><dd>A symmetrical vertical hall element in the cross-section,</dd><dt>FIG</dt><dd>The symmetrical vertical hall element in plan view,</dd><dt>FIG</dt><dd>An electrical equivalent circuit diagram for the symmetrical vertical hall element,</dd><dt>FIG</dt><dd>A symmetrical vertical hall element with an integrated resistor,</dd><dt>FIG</dt><dd>A symmetrical vertical hall element with two integrated resistors,</dd><dt>FIG</dt><dd>A symmetrical vertical hall element with additional electrodes,</dd><dt>FIG</dt><dd>A mask used in the implantation of ions for forming an n-type well, and FIG</dd><dt>Figs. 8, 9</dt><dd>Two antiparallel connected hall elements.</dd></dl>

p0018The <figref idrefs="f0001">FIGS. 1 and 2</figref> Show a symmetrical vertical hall element 1 in the cross section or in the top view. The hall element 1 produced in a CMOS technology preferably consists of a tub 2 of a first conductivity type which is embedded in a substrate 3 made of silicon of a second conductivity type. The hall element 1 has four contacts 4-7 on the surface, namely two inner contacts 5 and 6, as well as two outer contacts 4 and 7. The contacts 4-7 are arranged along a straight line 8 (FIG.<figref idrefs="f0001">FIG</figref>). Preferably, the two inner contacts 5 and 6 are of the same width in the direction of the straight line 8 and the two outer contacts 4 and 7 are of the same width. The position and size of the trough 2 and of the contacts 4-7 is then symmetrical with respect to a plane 9 perpendicular to the straight line 8 and in the middle between the two inner contacts 5 and 6. (For technological reasons, it is useful to make the two inner contacts 5 and 6 equally wide and the two outer contacts 4 and 7 equal in width, but it is not absolutely necessary.)

p0019Since, in the case of silicon, the mobility of the electrons is greater than the mobility of the holes, an n-conducting well and not a p-conducting well is advantageously used for the hall element 1. Although a p-conducting well could be used for the hall element 1, the sensitivity of the magnetic field sensor would be significantly smaller.

p0020The depth t of the well 2 is typically about 5 μm. Since the doping of the well 2 is not homogeneous, but exponentially decreases with increasing depth, most of the current flows below the surface of the hall element 1 in a thin layer of typically 1 to 2 μm thickness. The depth t effective for the electrical and magnetic properties of the hall element 1_eff Of the trough 2 is thus only about 1-2 μm. The length L of the hall element 1 is given by the length of the tub 2. It substantially corresponds to the distance between the outer edges 10 and 11, respectively, of the outer contacts 4 and 7. The length L is large compared to the depth t or the effective one depth t_eff. The electrical properties of the hall element 1 can be determined by a resistor composed of four resistors R₁ to R₄ Can be represented. For the sake of simplicity,<figref idrefs="f0001">FIG</figref> The resistors prevailing between each two contacts are represented by a resistance symbol R₁ to R₄ And a line connecting the contacts corresponding to the resistor.

p0021The <figref idrefs="f0001">FIG</figref> 11 shows the electrical circuit diagram of the four resistors R₁ to R₄ Of the hall element 1. When the hall element 1 is operated as a magnetic field sensor, a current flows in each case between two contacts which are not adjacent, for example, between the contacts 4 and 6 or between the contacts 5 and 7. The hall element 1 is regarded as ideal in electrical terms when the four Resistors R₁ to R₄ Have the same value. In this case, when the hall element 1 is fed via the contacts 4 and 6, the contacts 5 and 7 serving as voltage contacts are both at the same electrical potential, namely the potential of the half-voltage supply. In addition, the voltage between the voltage contacts is then equal to zero, ie the offset voltage disappears. The same applies if the hall element 1 is fed via the contacts 5 and 7 and the contacts 4 and 6 serve as voltage contacts.

p0022The resistors R₁ and R₃ Are the same for geometrical reasons. The resistance R₂ Can be varied by increasing or decreasing the distance between the inner contacts 5 and 6. By suitable choice of the position and size of the contacts 4-7, it is thus possible to achieve approximately R₁ = R₂ = R₃ Is applicable. In addition, the resistance R₄ Larger than the other resistors R₁, R₂ and R₃ Is. In order to symmetrize the resistor bridge, it is proposed according to the invention to provide a further resistor R₅ Parallel to the resistor R₄ , The value of which is determined such that approximately R₁ = R₂ = R₃ = R₄ || R₅ Is applicable. The resistance R₅ Is, for example, an external resistor. Preferably the resistance is R₅ But embedded in the n-conducting well 2 of the hall element 1 or realized as a separate n-conducting trough. The advantage is that the resistance R₅ In this case the same temperature coefficients as the resistors R₁, R₂, R₃ and R₄ So that the resistance bridge also remains in equilibrium during temperature fluctuations.

p0023The <figref idrefs="f0002">FIGS. 4 and 5</figref> Show two examples in which the resistance R₅ Is embedded in the trough 2 of the hall element 1. For the sake of simplicity, the resistors prevailing between two contacts are again represented by a resistance symbol and a line connecting the corresponding contacts. In the example according to FIG<figref idrefs="f0002">FIG</figref> A further contact 12 is arranged next to the contact 4 and is connected to the contact 7 via a conductor track 13, which is shown only schematically. In the example according to FIG<figref idrefs="f0002">FIG</figref> A further contact 12 is arranged next to the contact 4 and a further contact 14 is arranged next to the contact 7, the two additional contacts 12 and 14 being connected via a conductor track 13, which is again shown only schematically. In this example, therefore, the resistance R₅ Not by a single resistor, but by two resistors with the value ½R₅ Is realized.

p0024The miniaturization of the hall element is limited by the fact that between the two inner contacts 5 and 6, a minimum distance determined by the technology is to be observed. This minimum distance is now in the range of approximately 0.8 μm. The resistance R₂ Can thus not be less than a certain value, as determined by the technology used. In the following, further examples are explained of how the resistors R₁ to R₃ Can be increased or decreased.

p0025In the example according to FIG <figref idrefs="f0002">FIG</figref> Three electrodes 15-17 are arranged between the contacts 4-7, which are implemented, for example, like the gate electrodes of a MOSFET made of polysilicon. The electrodes 15-17 are separated from the n-conducting well, for example by a thin oxide layer, and thus electrically insulated from the n-conducting well 2. During operation of the hall element 1, the electrodes 15-17 are biased against the n-conducting well 2 with a predetermined voltage. The electrodes 15 and 17 are biased with the same voltage while the electrode 16 is biased with a voltage of opposite polarity. The bias of an electrode opposite the n-type well 2 causes the charge carrier density in the region below the electrode to be either increased or decreased depending on the sign of the bias voltage. To increase the charge carrier density, the bias of the electrode must be inversely related to the type of charge carriers of the well 2. When the well 2 is n-conducting, then the bias of the electrode must be positive against the potential of the well 2. In order to reduce the carrier density, the bias of the electrode must be equal to the type of charge carriers of the well 2. If the well 2 is n-conducting, the bias of the electrode in this case must therefore be negative compared to the potential of the well 2.

p0026It is also possible to provide instead of three electrodes 15, 16 and 17 only a single electrode, namely the electrode 16 between the inner contacts 5 and 6, or only the two electrodes 15 and 17, which are arranged between an inner and an outer contact Are arranged. It is possible, in the example according to FIG<figref idrefs="f0002">FIG</figref> To provide a further electrode which is arranged between the contacts 4 and 12 or, in the example according to FIG <figref idrefs="f0002">FIG</figref> Two further electrodes are arranged between the contacts 4 and 12, and 7 and 14, respectively. By selecting the size and sign of the bias voltages applied to the individual electrodes, the resistors R₁ to R₅ Within certain limits. Therefore, electronic voltage sources are provided, which are realized in the same semiconductor chip as the hall element 1, the bias voltages to be applied to the individual electrodes being determined in a calibration process once so that the voltages generated by the resistors R₁ to R₅ Is optimally compensated.

p0027Another possibility is to use the resistors R₁ to R₃ With a given position and size of the contacts 4 - 7, is to increase or decrease the charge carrier density by means of local implantation of additional ions or of fewer ions. This possibility is based on the<figref idrefs="f0003">FIG</figref> In more detail. The contacts 4 to 7 are represented by surfaces bordered by a dashed line 18. In the formation of the n-conducting well 2, a mask 19 is used for the ion implantation which does not have a single opening 20 corresponding to the size of the well 2 but an opening 20 which has local islands 21 which form part of the opening 20 So that the doping of the n-type well 2 varies locally. The dimensions of the islands 21 are selected to be so small that the regions separated by the islands 21 are connected to the n-conducting well 2 during the diffusion following the implantation. The doping of the well 2 in the region between the two inner contacts 5 and 6 is thus different from the doping of the well 2 in the regions between an inner contact and an adjacent outer contact.

p0028The <figref idrefs="f0003">FIGS. 8 and 9</figref> Illustrate another possibility, which is represented by the resistors R₁ to R₄ Can be largely compensated by a parallel connection of two Hall elements 1 and 1 'which are arranged parallel to each other so that they measure the same component of the magnetic field. The directions of the currents flowing through the two hall elements 1 and 1 'are symbolically indicated by arrows which point from the contact where the current is fed to the contact where the current is derived. The contacts 4 - 7 of the first hall element 1 and the contacts 4 '- 7' of the second hall element 1 'are wired in pairs by means of schematically illustrated conductor tracks 13. The wiring must meet two criteria as described below. Firstly, the Hall voltages generated by the magnetic field of the two Hall elements 1 and 1 'must be identical, otherwise the magnetic field sensor does not "see" the magnetic field. If the two current contacts are connected by an arrow indicating the direction of the current, a voltage contact is located on the left side of the arrow and a voltage contact is on the right side of the arrow. Equal now means that the two voltage contacts of the two hall elements 1 and 1 ', which lie on the left side of the corresponding arrow, must be connected, and that the two voltage contacts of the two hall elements 1 and 1', which are located on the right side of the corresponding Arrows. If the two hall elements 1 and 1 'were not wired, one of the two voltage contacts 5 and 7 would lead to a higher potential than the other voltage contact in the first hall element 1,₄ Larger than the other resistors R₁, R₂ and R₃ Is. Likewise, in the case of the second hall element 1 ', one of the two voltage contacts 4' and 6 'would have a higher potential than the other voltage contact because the resistor R 1₄'Is larger than the other resistors R₁', R₂'And R₃'. In the example of the<figref idrefs="f0003">FIG</figref> - in the case of the <figref idrefs="f0003">FIG</figref> - the voltage contact 7 of the first hall element 1 has the higher potential than the voltage contact 5. In the second hall element 1 ', the voltage contact 4' carries the higher potential than the voltage contact 6 '. The voltage contacts 7, 5, 4 'and 6' of the two hall elements 1 and 1 'are now to be wired in such a way that the voltage contact 7 of the first hall element 1 which leads to the higher potential is connected to the voltage contact 6' of the second hall element 1 ' , Which leads to the lower potential. Because of this wiring, the currents flowing through the two Hall elements 1 and 1 'are divided so that the voltage applied between the voltage contacts 7 and 5 of the first Hall element 1 with a vanishing magnetic field, the so-called offset voltage, is much smaller than without the second system being switched on Hall element 1 'in the described manner. In the embodiment shown in FIG<figref idrefs="f0003">FIG</figref> The contacts 4 - 7 of the first hall element 1 and the contacts 4 '- 7' of the second hall element 1 'are wired in pairs as follows: the contact 4 with the contact 7', the contact 5 with the contact 4 ', the contact 4' Contact 6 with the contact 5 'and the contacts 7 with the contact 6', whereby the currents in both hall elements 1 and 1 'respectively flow from an inner contact to the non-adjacent external contact, but in the opposite direction.

p0029In the embodiment shown in FIG <figref idrefs="f0003">FIG</figref> The currents flow in the same direction, in the case of the first hall element 1 from an internal contact to the non-adjacent external contact, but in the case of the second hall element 1 'from an external contact to the non-adjacent internal contact. The contacts 4 - 7 of the first hall element 1 and the contacts 4 '- 7' of the second hall element 1 'are wired in pairs as follows: the contact 4 with the contact 5', the contact 5 with the contact 6 ', the contact 6 with The contact 7 'and the contact 7 with the contact 4', so that the two criteria stated above are fulfilled.

p0030In the embodiments described so far, the symmetrical vertical hall element 1 is embedded in the n-conducting well 2, which was produced by implantation of ions and subsequent diffusion in a p-conducting substrate. Such a technology is commonly referred to as CMOS technology. Instead of a CMOS technology, however, it is also possible to use bipolar technology in which the symmetrical vertical hall element 1 is embedded in an insulated region in an epitaxial layer. Such an isolated region may also be referred to as an n-well. While the n-well produced in bipolar technology is homogeneously doped with foreign atoms, the doping of the n-well produced in CMOS technology is not homogeneous.