Single-chip color CMOS image sensor with two or more line reading structure

Related Applications

This is a continuation-in-part of prior application serial No. 09/034,865, filed on March 4, 1998, the benefit of the filing date of which is hereby claimed under 35 U.S.C. § 120.

Field of the Invention

The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, a single-chip CMOS image sensor having a novel two or more line reading structure and a high-sensitivity interlace color structure.

Background of the Invention

Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low-cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic.

Some of the further drawbacks of CCD technology are discussed in "Active Pixel Sensors - Are CCD's Dinosaurs?" by E.R. Fossum, <i>Proceedings of the SPIE - The International Society for Optical Engineering,</i> Vol. 1900, 1993, pp. 2-14. As stated therein, "[a]lthough CCDs have become a technology of choice for present-day implementation of imaging and spectroscopic instruments due to their high-sensitivity, high quantum efficiency, and large format, it is well-known that they are a particularly difficult technology to master. The need for near-perfect charge transfer efficiency makes CCDs (1) radiation 'soft,' (2) difficult to reproducibly manufacture in large array sizes, (3) incompatible with the on-chip electronics integration requirements of miniature instruments, (4) difficult to extend the spectral responsivity range through the use of alternative materials, and (5) limited in their readout rate."

An alternative low-cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS), integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative to CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand-alone imaging device.

Examples of MOS imaging devices are detailed in "A ¼ Inch Format 250K Pixel Amplified MOS Image Sensor Using CMOS Process" by Kawashima et al., IEDM 93-575 (1993), and "A Low Noise Line-Amplified MOS Imaging Devices" by Ozaki et al., <i>IEEE Transactions on Electron Devices,</i> Vol. 38, No. 5, May 1991. In addition, U.S. Patent No. 5,345,266 to Denyer, titled "Matrix Array Image Sensor Chip," describes a MOS image sensor. The devices disclosed in these publications provide a general design approach to MOS imaging devices. In addition, MOS approaches to color imaging devices are described in "Color Filters and Processing Alternatives for One-Chip Cameras," by Parulski, <i>IEEE Transactions on Electron Devices,</i> Vol. ED-32, No. 8, August 1985, and "Single-Chip Color Cameras With Reduced Aliasing" by Imaide et al., <i>Journal of Imaging Technology,</i> Vol. 12, No. 5, Oct. 1986, pp. 258-260.

In the MOS solid-state color image sensors, a complementary color filter pattern is often used. Arrays of pixels may be made to detect color by being covered with a regular pattern of color filter patches, known as a color filter pattern. The filter patches can be fabricated directly on the sensor or on a transparent substrate which is later cemented to the chip. Color filter patterns may include colors such as red (R), green (G), blue (B), yellow (Ye), cyan (Cy) and magenta (Mg). The pixels beneath the color filter pattern emit signals when they are exposed to the type of light indicated by the color filter patch. Thus, a red signal could be obtained from a pixel beneath a red filter patch, a blue signal could come from a pixel beneath a blue filter patch, and so on.

However, some image sensors do not obtain the standard red, green and blue signals from red, green and blue filtered pixels. Instead, they use combinations of other colors to obtain the standard ones. For example, red (R) can be formed according to the equation R = (W+Ye) - (G+Cy), where the color filter pixel signals are W = white, Ye = yellow, G = green, and Cy = cyan. In cases such as this, the four pixel signals being processed are obtained from a 2x2 block of one of each type of pixel sensors, rather than a 1x4 row of pixel sensors which would tend to distort the color image. The 2x2 block presents a problem for standard pixel scanning methods because standard methods scan each row, one at a time. In contrast, the 2x2 block of pixels comes from sections of two separate rows. Thus, the system cannot process the data as it scans each row. It must wait until the next row is also scanned to obtain the remaining information that it needs, and it must somehow save the data from the previous row until it does so.

Just as the color signals in such cases can be a combination of the signals from a 2x2 pixel block, the chrominance signal, which correlates to the color of the image, is also sometimes obtained from a combination of signals from pixels in two separate rows. In fact, this is the case for the chrominance signal in many systems, even those in which R, G and B filters are used to obtain the color signals directly. Therefore, it is required in such systems to somehow have the data from two separate rows available at the same time so that the required combinations can be processed. In most prior art devices, an external one-line delay line (e.g., a CCD delay line) is used for this purpose. The delay line scans in one row and holds the data until the next row can be scanned to provide the needed information.

In the movement from CCD- to MOS-based implementations, methods of implementing the circuitry have been sought that can easily be fabricated on a single MOS chip. The approach of using an external delay line device in the MOS color image sensors, which was carried over from the old CCD technology, has inherently required the use of components that are external to the MOS circuit and that are sometimes required to be on a separate chip, in addition to increasing the relative complexity of the implementation. It is a general principle that power consumption and cost would decrease if the number of chips and complex components necessary to accomplish the task were decreased. The present invention is directed towards a solution that provides the needed data from two rows of pixels at the same time, without using an external delay line device, and which can be integrated on a single-chip with the MOS sensor array.

In addition, the color filter patterns used in the prior art MOS color image sensors, from which the needed data is obtained, are also often not optimized. Any color can be thought of as a mixture of the three primary colors: red, blue, and green. However, as is known in the art, humans do not process red, green, and blue equally. Rather, humans rely upon the three primary colors in approximate accordance with: 0.6Green + 0.3Red + 0.1Blue. Thus, to the human eye, green is the most important color, red is the next most important, and blue is the least most important. Based upon this knowledge, the pixel array should have a color filter pattern (also referred to as a color coding scheme) that is more heavily weighted along the lines of green than red or blue. Prior art color coding schemes have attempted to achieve this in various ways.

The prior art has shown that checkerboard patterns are superior to linear ones. One of the most common schemes uses a matrix in which every other pixel is green (G), and the remaining pixels form a checkerboard pattern in alternating red (R) and blue (B). Another pattern uses a checkerboard pattern of equal amounts of cyan (Cy), yellow (Ye), white (W), and green (G). A noted advantage of using the colors cyan, yellow, and green is that since green is formed by overlapping yellow and cyan, only two filter fabrication mask steps are needed, as opposed to the three needed for a RGB filter. The present invention discloses a different color filter pattern, using green, yellow, and cyan, which it optimized for sensitivity.

We are aware of US Patent Number 5 043 821, which discloses a memory array for a pixel array in which each pixel has a corresponding memory cell. We are also aware of the European Patent Application published as EP 0 757 497, which describes a pixel array with a color mask having colors A, B, C and D with successive rows arranged ABAB, CDCD, ABAB, DCDC et cetera.

Summary of the Invention

The present invention is directed to a single-chip color MOS image sensor with a novel two-line reading structure which allows the simultaneous reading of line signals from two adjacent rows of pixels so that combinations of signals from pixels in adjacent rows may be obtained without the use of an external delay line device. The sensor includes a pixel array having superimposed thereon an improved color filter pattern, a two-line reading structure with a first set of storage capacitors, a first set of switches for selectively placing signals from a first row of the pixel array on the first set of storage capacitors, a second set of storage capacitors, a second set of switches for selectively placing signals from a row adjacent to said first row of the pixel array on the second set of storage capacitors, and at least a third and fourth set of switches for selectively reading out said signals from the storage capacitors on output lines as a set of line signals. The two-line reading structure may be repeated so as to provide four line signals. The capacitors, MOS switches and amplifiers of the reading structure are easily fabricated as part of a MOS image sensor on a single-chip. Also, the improved color filter pattern of the device, which includes green, yellow, and cyan, requires only two filter fabrication mask steps, and is designed for optimal sensitivity. In addition, by using a high-sensitivity interlace color structure, the sensitivity of the device as a whole may be essentially doubled.

According to an aspect of the invention, there is provided a single-chip color MOS image sensor comprising: <ul id="ul0001" list-style="none" compact="compact"><li>a pixel array formed from a plurality of individual pixels organized as rows and columns; and</li><li>a reading structure having at least two output lines and connected to said pixel array to enable simultaneous reading of pixels from a first row and a second row at an initial time, and simultaneous reading of pixels from the second row and a third row at a later time, said reading structure comprising: <ul id="ul0002" list-style="none" compact="compact"><li>(a) a first set of storage capacitors said first set of storage capacitors having at least two capacitors associated with each column of said pixel array;</li><li>(b) a first set of switches for selectively placing signals from a first row of said pixel array on said first set of storage capacitors at the initial time, the signal from each individual pixel of said first row being stored on said storage capacitors from said first set of storage capacitors associated with the column of said individual pixel at said initial time, the first set of switches also selectively placing signals from a third row of said pixel array on said first set of storage capacitors at the later time;</li><li>(c) a second set of storage capacitors, said second set of storage capacitors having at least two capacitors associated with each column of said pixel array; and</li><li>(d) a second set of switches for selectively placing signals from a second row of said pixel array on said second set of storage capacitors, the signal from each individual pixel of said second row being stored on said storage capacitors from said second set of storage capacitors associated with the column of said individual pixel.</li></ul></li></ul>

Brief Description of the Drawings

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: <ul id="ul0003" list-style="none"><li><b>Figure 1</b> is a block diagram of a single-chip CMOS imaging sensor formed in accordance with the present invention;</li><li><b>Figure 2</b> is a schematic diagram of a simplified single-column, two-line pixel reading structure formed in accordance with the present invention and shown for purposes of illustration;</li><li><b>Figure 3</b> is a timing diagram illustrating the operation of the single-column, two-line pixel reading structure shown in Figure 2;</li><li><b>Figure 4A</b> is a diagram of a prior art color filter pattern that may be used in the preferred embodiment of the invention;</li><li><b>Figure 4B</b> is a diagram of a second prior art color filter pattern;</li><li><b>Figure 4C</b> is a diagram of an inventive color filter pattern;</li><li><b>Figures 5A and 5B</b> are schematic diagrams of a six-column, four reading channel, non-interlace reading structure formed in accordance with the present invention;</li><li><b>Figure 6</b> is a timing diagram illustrating the operation of the reading structure shown in Figure 5B;</li><li><b>Figures 7A and 7B</b> are schematic diagrams of a six-column, four reading channel, interlace reading structure formed in accordance with the present invention;</li><li><b>Figure 8A</b> is a timing diagram illustrating the operation of the reading structure of Figure 7B for an even field reading operation;</li><li>FIGURE 8B is a timing diagram illustrating the operation of the reading structure of FIGURE 7B for an odd field reading operation;</li><li>FIGURE 9 is a timing diagram illustrating the overall timing of the even and odd field reading operations of FIGURES 8A and 8B for one frame of TV timing;</li><li>FIGURE 10 is a schematic diagram of a six-column, two reading channel, interlace reading structure formed in accordance with the present invention;</li><li>FIGURE 11A is a timing diagram illustrating the operation of the reading structure of FIGURE 10 for an even field reading operation;</li><li>FIGURE 11B is a timing diagram illustrating the operation of the reading structure of FIGURE 10 for an odd field reading operation;</li><li>FIGURE 12 is a schematic diagram of a six-column pixel array which in combination with the reading structure of FIGURE 5B illustrates a high-sensitivity interlace color structure according to the present invention;</li><li>FIGURE 13A is a timing diagram illustrating the operation of the reading structure of FIGURE 12 for an even field reading operation; and</li><li>FIGURE 13B is a timing diagram illustrating the operation of the reading structure of FIGURE 12 for an odd field reading operation.</li></ul>

Detailed Description of the Preferred Embodiment

With reference to FIGURE 1, a block diagram of a single-chip CMOS imaging sensor includes an image sensor array 101. The retrieval of information from the image sensor array is done by the peripheral circuitry of FIGURE 1 and the output is done in accordance with the well-known NTSC scheme. This scheme allows the output signals from the circuit to be transmitted and displayed by conventional means.

The signals from the sensor array 101 are processed by a sensor reading structure 201, which is formed in accordance with the present invention. As will be later explained, this novel reading structure allows the reading of two line signals from two separate rows of pixels simultaneously, without the use of an external delay line device. The sensor reading structure 201 outputs line signals SIG1, SIG2, SIG3, and SIG4, which are amplified by signal amplifiers 305. In one actual embodiment, the signal amplifiers 305 are formed in accordance with co-pending application serial No.08/538,441 entitled "IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME," of Shyu et al., filed October 3, 1995, and co-pending application serial No. 08/617,313 entitled "IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME," of Shyu et al., filed March 18, 1996, both together published as US 6 351 283 B1.

Amplified line signals SIG1', SIG2', SIG3', and SIG4' from the signal amplifiers 305 are then processed by processor 307 which performs automatic gain control amplification and black level calibration. The black level calibration attempts to eliminate the portion of the signal that exists when no light is being detected, as is known in the art, thus allowing for a truer zero reference signal so that the later signal processing is improved. The automatic gain control amplifiers (AGC) amplify the signals at a controlled level for further processing.

Processed line signals SIG1" to SIG4" from processor 307 go to the color matrix 309. The color matrix 309 combines the line signals in various proportions according to matrix equations and also performs gamma correction so as to derive the output color signals, such as green (G'), red (R'), blue (B'), or the luminance signal (Y'). The "prime" indicates the signal has undergone gamma correction. The red (R') and blue (B') output color signals may be obtained as a function of the difference between two line signals, as will be explained later in more detail. The luminance signal (Y') is formed from a linear matrix function by which the other signals are combined in various proportions. The processor 311, which performs the luminance signal process, takes the signal Y' from the color matrix 309 and outputs the signal YH along with a feedback signal which goes to the AEC detector 317. The YH signal is the luminance signal with high frequency components.

The color signals G', R', and B' go from the color matrix 309 to the processor 313, which performs the chromaticity signal process, where they are processed so as to produce the signals -(R-Y) and -(B-Y), from which the chroma signal is formed. The chroma signal is formed by quadrature modulating the two color difference signals, (R-Y) and (B-Y), on a color subcarrier. In alternate systems, I (in phase) and Q (quadrature) color difference signals are sometimes used rather than (R-Y) and (B-Y), although the latter are what are most often used in consumer cameras. The phase and amplitude of the chroma signal indicate hue and saturation.

The NTSC encoder 315 receives control timing signals SYNC and BLANK from a video timing generator 319, and also receives control signals FSC, HUE, and SATURATION. The YH signal from the luminance signal process 311, and the color difference signals -(R-Y) and -(B-Y) from the chromaticity signal process 313, go to the NTSC encoder 315 where they are processed to produce the output signals CVBS (composite video with blank and sync) and the Y+C combined signal. The baseband luminance signal (Y) correlates to the brightness of the image, and the quadrature-modulated chrominance signal (C) correlates to the color of the image. -

The processor 311, which performs the luminance signal process, outputs a feedback signal to the AEC detector 317, which outputs a control signal to the controller 321 which performs the AEC &amp; AGC control. As is known in the art, AEC refers to automatic exposure control. The video timing generator 319 outputs timing signals SAMPLE and PRECHARGE which go to the sample and precharge areas of the array row controller 151, respectively, for purposes of controlling the scanning of the image sensor array 101. The array row controller 151 also includes a row driver section. The video timing generator 319 also outputs a timing signal to the controller 321 which performs the AEC &amp; AGC control. The controller 321 outputs control signals to the sample timing counter 323 and to the precharge timing counter 325. The sample timing counter 323 and the precharge timing counter 325 are connected to the sample and precharge areas of the array row controller 151, respectively. The image sensor array 101 is controlled by the array row controller 151, the row calibration cells 153, and the column calibration cells 155.

As noted above, it is desirable that the sensor reading structure 201 be able to read two line signals from two separate rows in such a way that the needed portions of data from both rows is available to be processed at the appropriate time. Prior art devices have used delay lines for this purpose, where, for example, one row of pixels would be scanned into the delay line and held for a time necessary until the second row could be scanned. The problem with this approach is that the delay line is often external to the MOS imaging sensor, which can add to the number of chips and the complexity of the implementation. Thus, there is a need for a structure that can be easily fabricated on the same chip as the MOS sensor array and that can make available the needed signals from two separate rows of pixels during a specified processing interval.

Turning now to FIGURE 2, a simplified single-column, two-line sensor pixel reading structure 201 formed in accordance with the present invention is shown for purposes of illustration. This structure illustrates the method by which the present invention may read two line signals from two rows of pixels simultaneously and thus provide the needed portions of data from the two rows during the specified processing interval. As will be seen below, the structure of FIGURE 2 forms the building block of an arbitrarily large image sensor array.

The sensor reading structure 201 reads a pixel sensor array 101, which includes a single column of pixels 103, designated as pixels 103A, 103B, 103C, and 103D. The pixels 103A to 103D are controlled by pixel control signals P1, P2, P3, and P4, respectively. In a color image sensor, each pixel is covered by a color filter patch. The signals from the pixels 103A to 103D are alternately amplified by a signal amplifier 205. The signal amplifier 205 may be formed in accordance with above-mentioned co-pending application serial No. 08/538,441 entitled "IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME," of Shyu et al., filed October 3, 1995, and co-pending application serial No. 08/617,313 entitled "IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME," of Shyu et al., filed March 18, 1996.

The amplified pixel signals are temporarily stored on capacitors C1, C2, C3, and C4. The placement of the amplified pixel signals on the four capacitors is controlled by sets of switches SW1 and SW2. Switch SW1 places signals on capacitors C1 and C2, and switch SW2 places signals on capacitors C3 and C4. The stored pixel signals on the capacitors C1 to C4 are transferred to line signals SIG1 and SIG2 by two sets of output switches SW3 and SW4. Switch set SW3 places signals from capacitor C1 on line signal SIG1 and from capacitor C3 on line signal SIG2. Switch set SW4 places signals from capacitor C2 on line signal SIG1 and from capacitor C4 on line signal SIG2. Line signals SIG1 and SIG2 are further amplified by signal amplifiers 305 and become amplified line signals SIG1' and SIG2'. It should be noted that in the preferred embodiment, capacitors are used to store the amplified pixel signals. However, it can be appreciated that any type of memory cells may be used to store the signal. Indeed, most types of memory cells, such as DRAMs, SRAMs, and EEPROMs, include therein a capacitor or capacitor-like device. Thus, the term capacitor as used herein shall mean any type of memory cell that can be used to store a signal.

In different embodiments, the pixels 103A, 103B, 103C, and 103D may be either passive pixels or active pixels. For passive pixels, amplifier 205 would generally be a charge amplifier, and amplifiers 305 could also be charge amplifiers. However, if pixels 103A, 103B, 103C, and 103D were active pixels, amplifier 205 could be made to be a voltage buffer or voltage amplifier, or could be left out of the circuit altogether. In addition, as illustrated in FIGURE 2, sample buffers 207 are shown to be coupled between the capacitors C1, C2, C3, and C4 and the amplifiers 305. The sample buffers 207 output a voltage rather than a charge, thus allowing the amplifiers 305 to be voltage amplifiers rather than charge amplifiers. In an embodiment where sample buffers 207 were not included, amplifiers 305 would generally be charge amplifiers.

The goal of the circuit in FIGURE 2 is to simultaneously place on the line signals SIG1 and SIG2 signals from two pixels from adjacent rows. For example, pixel 103A will first be simultaneously read with pixel 103B, then pixel 103B will be simultaneously read with pixel 103C, and finally pixel 103C will be simultaneously read with pixel 103D. These simultaneous readings are accomplished by storing the signal from each pixel on two capacitors. Two capacitors are needed for each signal since each pixel signal (with the exception of the first and last pixel in the column) is read twice. For example, pixel 103B is simultaneously read with pixel 103A and then with pixel 103C.

The operation of the circuit in FIGURE 2 is illustrated by the timing diagrams shown in FIGURE 3. As shown in FIGURE 3, at the beginning of time period 1, the pixel control signal P1 goes high at the same time as switch set SW1. This causes the signal from pixel 103A to be amplified by signal amplifier 205 and stored on capacitors C1 and C2. Thus, the signal from pixel 103A is stored on two capacitors, and these two stored signals are referenced as stored pixel signal 103A' on capacitor C1, and stored pixel signal 103A" on capacitor C2. While the timing diagrams of FIGURE 3 show these signals as being transferred instantaneously, it is understood that the actual transfer of these signals involves transient periods, due to the charging of the capacitors and similar phenomena, which are not shown in the diagrams. After pixel signal 103A' and pixel signal 103A" are stored, then output switch set SW3 goes high which causes stored pixel signal 103A' to be transferred from capacitor C1 to line signal SIG1. Although the timing diagrams for line signals SIG1 and SIG2 show the names of the pixel signals which are transferred to the line signals after the output switch sets SW3 or SW4 are activated, it is understood that the named signals do not necessarily remain on the line signals for the full time period shown in the diagram, and are shown there only for purposes of illustration as if the charge from each of the capacitors had been transferred to each of the line signals. Line signal SIG1 and line signal SIG2 are obtained simultaneously, although during time period 1, line signal SIG2 has not been shown to be charged with a signal.

At the beginning of time period 2, the pixel control signal P2 goes high at the same time as switch set SW2. This causes the signal from pixel 103B to be stored on capacitors C3 and C4, and these two stored signals are referenced as stored pixel signal 103B' and stored pixel signal 103B", respectively. Next, output switch set SW4 goes high which causes stored pixel signal 103B" to be transferred from capacitor C4 to line signal SIG2, and also simultaneously causes the stored pixel signal 103A", which was stored during time period 1, to be transferred from capacitor C2 to line signal SIG1 Thus, at the point during time period 2 when SW4 goes high, the line signals SIG1 and SIG2 contain the signals from pixels 103A and 103B, respectively, which are in adjacent rows, as is the goal of the system.

At the beginning of time period 3, the pixel control signal P3 goes high at the same time as switch set SW1. This causes the signal from pixel 103C to be stored on capacitors C1 and C2, and these two stored signals are referenced as stored pixel signal 103C' and stored pixel signal 103C", respectively. Next, output switch set SW3 goes high which causes stored pixel signal 103C' to be transferred from capacitor C1 to line signal SIG1, and also simultaneously causes the stored pixel signal 103B', which was stored during time period 2, to be transferred from capacitor C3 to line signal SIG2. Thus, at the point during time period 3 when SW3 goes high, the line signals SIG1 and SIG2 contain the signals from pixels 103C and 103B, respectively, which are in adjacent rows, as is the goal of the system.

During time period 4, the process repeats as it did during time period 2, so as to cause the line signals SIG1 and SIG2 to contain the signals from pixels 103C and 103D, respectively, which are in adjacent rows, as is the goal of the system. The process of FIGURE 3 is repeated until all of the rows of the pixel array have been processed.

Turning now to FIGURE 4A, a prior art color filter pattern is shown. This prior art color coding scheme is one of the most common and uses a half green (G) pattern, checkerboarded with red (R) and blue (B). The color filter pattern of FIGURE 4A may be used in the preferred embodiment of the invention. FIGURE 4B shows another prior art color coding scheme which uses equal amounts of cyan (Cy), yellow (Ye), white (W), and green (G), with the advantage that since green is formed by overlapping yellow and cyan, only two filter fabrication steps are needed as opposed to the three needed for a RGB filter. In FIGURE 4B, the color red (R) may be derived according to the equation R = (W + Ye) - (G + Cy), and blue (B) may be derived from B = (W + Cy) - (Ye + G).

In contrast, FIGURE 4C shows an inventive color coding scheme of the present invention which uses the same proportion of green (G) components as the prior art color coding scheme of FIGURE 4A, but uses yellow (Y) and cyan (Cy) to fill in the remainder rather than red (R) and blue (B). Similar to the prior art color coding scheme of Figure 4B, in regard to the filter fabrication mask steps, green is formed by overlapping yellow and cyan, thus requiring only two filter fabrication mask steps.

Further, if the color filter has ideal spectral characteristics, then the color yellow can be the combination of green and red. Similarly, cyan can be the combination of green and blue. The specific equations used by the preferred embodiment for the color coding scheme of FIGURE 4C are Ye = Godd + αR (where Ye is yellow pixels, Godd is green pixels next to the yellow pixels which are all in odd numbered rows, R is red and α is a constant), and Cy = Geven + βB (where Cy is cyan pixels, Geven is green pixels next to the cyan pixels which are all in even numbered rows, B is blue and β is a constant) and G = Godd/2 + Geven/2. Solving the first equation for R yields: R = (Ye - Godd)/α, and solving the second equation for B yields: B = (Cy - Geven)/β. Also, with regard to the spatial frequency components, the equations which are used are: for the Y-channel--Fx=1/δx, Fy=1/δy, and for the C-channel--Fx=1/2δx, Fy=1/2δy; where δx is the width of a pixel component and δy is the length of a pixel component.

With reference to FIGURES 5A and 5B, a six-column, two-line non-interlace (progressive scan) reading structure 201 is formed in accordance with the present invention and includes six columns of four rows of pixels 103. Any of the color coding schemes of FIGURES 4A, 4B, or 4C, or others, may be used. As shown, each pixel in each block of four pixels in FIGURE 5A is designated as having one of four colors, CLR1, CLR2, CLR3, or CLR4. In the color coding scheme of FIGURE 4A, colors CLR1 and CLR4 would be the same (green), while in the color coding scheme of FIGURE 4C, colors CLR2 and CLR3 would be the same (green).

In the embodiment illustrated in FIGURE 5B, the two-line reading structure is doubled so as to provide four reading channel line signals. The first column of pixels has pixels 103A to 103D, the second column has pixels 103E to 103H, and so on until the sixth column, which has pixels 103U to 103X. Each row of pixels is controlled by a pixel control signal P1, P2, P3, or P4. All of the pixels in the first row, including pixels 103A, 103E, 103I, 103M, 103Q, and 103U, are controlled by pixel control signal P1. The pixels in the second, third, and fourth rows are similarly controlled by pixel control signals P2, P3, and P4, respectively.

The signals from the pixels in each of the six columns of pixels are alternately amplified by six signal amplifiers 205. As described previously with reference to FIGURE 2, signal amplifiers 205 may be charge amplifiers or voltage amplifiers, and the pixels may be active or passive, and there may also be sample buffers inserted after the capacitors. The amplified pixel signals are temporarily stored on twenty-four capacitors C1 to C24, four for each column, including capacitors C1 to C4 for the first column, capacitors C5 to C8 for the second column, and so on until the sixth column where the signals are stored on capacitors C21 to C24. The placement of the amplified pixel signals on the twenty-four capacitors is controlled by two sets of switches SW1 and SW2. The stored pixel signals on the capacitors C1 to C24 are transferred to line signals SIG1, SIG2, SIG3, and SIG4 by twelve sets of output switches, two for each column, including switch sets SW3 and SW4 for the first column, switch sets SW5 and SW6 for the second column, and so on until the sixth column for which the output is controlled by switch sets SW13 and SW14. Line signals SIG1 and SIG2 receive the outputs from the first, third, and fifth columns, while line signals SIG3 and SIG4 receive the outputs from the second, fourth, and sixth columns. The signals on line signals SIG1 to SIG4 are amplified by signal amplifiers 305 and become amplified line signals SIG1' to SIG4'.

The goal of the circuit in FIGURES 5A and 5B is to simultaneously place on the pairs of line signals SIG1 and SIG2, or SIG3 and SIG4, signals from pixels from adjacent rows so that they can be further processed. For example, during a second time period (assuming the first time period was used to store a first set of values), the first and second pixels from the first column would be simultaneously read, then the first and second pixels from the second column would be simultaneously read, and so on until the sixth column where the first and second pixels from that column would be simultaneously read.

More specifically, with reference to FIGURES 5A and 5B, from the first column, pixel 103A would be simultaneously read with pixel 103B on line signals SIG1 and SIG2, respectively, then from the second column, pixel 103E would be simultaneously read with pixel 103F on line signals SIG3 and SIG4, respectively, then from the third column, pixel 1031 would be simultaneously read with pixel 103J on line signals SIG1 and SIG2, respectively, and so on until the sixth column where pixel 103U would be simultaneously read with pixel 103V on line signals SIG3 and SIG4, respectively.

During the third time period, the second and third pixels from each column would be simultaneously read in a similar manner. Then, in the fourth time period, the third and fourth pixels from each column would be simultaneously read. These simultaneous readings of pixels from different rows are accomplished by the use of storage capacitors C1 to C24 which store the signal from each pixel on two capacitors during different time periods. Two capacitors are needed for each signal since each pixel signal (with the exception of the first and last pixel in each column) is read twice. For example, pixel 103B is simultaneously read with pixel 103A and then later with pixel 103C.

The operation of the circuit of FIGURES 5A and 5B is illustrated by the timing diagrams shown in FIGURE 6. As shown in FIGURE 6, an H-SYNC signal synchronizes the reading times of the processing circuitry. At the beginning of time period 1, the pixel control signal P1 goes high at the same time as switch set SW1. This causes the signals from the first row of pixels, including pixels 103A, 103E, 103I, 103M, 103Q and 103U, to be amplified by signal amplifiers 205 and be stored on capacitors in sets of two. Specifically, capacitors C1 and C2 store the pixel signal 103A, capacitors C5 and C6 store the pixel signal 103E, capacitors C9 and C10 store the pixel signal 103I, and so on until capacitors C21 and C22, which store the pixel signal 103U. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103A' and 103A" for pixel 103A, stored pixel signals 103E' and 103E" for pixel 103E, and so on.

Next, output switches of odd number SW3, SW5, SW7, SW9, SW11, and SW13 are activated in consecutive sequential order, which causes the signals from the capacitors C1, C5, C9, C13, C17, and C21 to be alternately placed on line signals SIG1 and SIG3. Thus, the pixels of a particular row are read sequentially. In this embodiment, the signals that are placed on line signal SIG1 come from capacitors C1, C9, and C17, which in turn come from pixels 103A, 103I, and 103Q, which are all color CLR1 pixels. The signals on line signal SIG3 come from capacitors C5, C13, and C21, which come from pixels 103E, 103M, and 103U, which are all color CLR3 pixels. Thus, line signal SIG1 is receiving first-row color CLR1 signals and line signal SIG3 is receiving first-row color CLR3 signals.

Although the timing diagrams show the names of the pixel signals (signal 103A' is abbreviated as A', etc.) that are transferred to the line signals after the output switch sets SW3 to SW14 are activated, it is understood that the named signals do not necessarily remain on the line signals for the full time period shown in the diagram, and are shown there only for purposes of illustration as if the charge from each of the capacitors had been transferred to each of the line signals. Line signals SIG1 and SIG2 are obtained simultaneously, as are line signals SIG3 and SIG4, although during time period 1 the output lines SIG2 and SIG4 have not been shown to be charged with any signals.

At the beginning of time period 2, the pixel control signal P2 goes high at the same time as switch set SW2. This causes the signals from the second row of pixels 103B, 103F, 103J, 103N, 103R, and 103V (which include color CLR2 and color CLR4 pixels) to be amplified by signal amplifiers 205, and be stored on capacitors in sets of two. Specifically, capacitors C3 and C4 store the pixel signal 103B, capacitors C7 and C8 store the pixel signal 103F, capacitors C11 and C12 store the pixel signal 103J, and so on, until capacitors C23 and C24, which store the pixel signal 103V. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103B' and 103B", respectively, for pixel 103B, stored pixel signals 103F' and 103F" for pixel 103F, and so on. Next, output switches of even number SW4, SW6, SW8, SW10, SW12, and SW14 activate in consecutive order, which cause the signals from capacitors C4, C8, C12, C16, C20, and C24 to be alternately placed on line signals SIG2 and SIG4, and also simultaneously cause the signals from capacitors C2, C6, C10, C14, C18, and C22, which were stored during time period 1, to be alternately placed on line signals SIG1 and SIG3.

The signals that are placed on line signal SIG1 came from capacitors C2, C10, and C18, which were stored during time period 1, which in turn came from first row pixels 103A, 103I, and 103Q, which are all color CLR1 pixels. The signals on line signal SIG2 came from capacitors C4, C12, and C20, which were stored during time period 2, which in turn came from second row pixels 103B, 103J, and 103R, which are all color CLR2 pixels. Thus, at the points in time period 2 when the switch sets SW4, SW8, and SW12 activate, the line signals SIG1 and SIG2 simultaneously contain signals from pixels 103A and 103B, then 103I and 103J, and then 103Q and 103R, respectively. These are all simultaneous readings of first row color CLR1 pixels with adjacent second row color CLR2 pixels, as is the goal of the system.

Similarly, the signals on line signal SIG3, which are being placed at alternating times from the simultaneous signals on output lines SIG1 and SIG2, came from capacitors C6, C14, and C22, which were stored during time period 1, which in turn came from first-row pixels 103E, 103M, and 103U, which are all color CLR3 pixels. The signals on line signal SIG4 came from capacitors C8, C16, and C24, which were stored during time period 2, which in turn came from second-row pixels 103F, 103N, and 103V, which are all color CLR4 pixels. Thus, at the points during time period 2 when switch sets SW6, SW 10, and SW14 activate, line signals SIG3 and SIG4 simultaneously contain signals from pixels 103E and 103F, then 103M and 103N, and then 103U and 103V, respectively. These are all simultaneous readings of first-row color CLR3 pixels with adjacent second-row color CLR4 pixels, as is the goal of the system. Thus, the complete output during time period 2 is simultaneous readings of first-row color CLR1 pixels with adjacent second-row color CLR2 pixels on line signals SIG1 and SIG2, respectively, alternating with simultaneous readings of first-row color CLR3 pixels with adjacent second-row color CLR4 pixels on output lines SIG3 and SIG4, respectively, in consecutive order of the pixels in FIGURE 5A moving from left to right.

At the beginning of time period 3, the pixel control signal P3 goes high at the same time as switch set SW1. This causes the signals from the third row of pixels 103C, 103G, 103K, 1030, 103S, and 103W (which include color CLR1 and color CLR3 pixels), to be amplified by signal amplifiers 205, and be stored on capacitors in sets of two. Specifically, capacitors C1 and C2 store the pixel signal 103C, capacitors C5 and C6 store the pixel signal 103G, and so on until capacitors C21 and C22 which store the pixel signal 103W. Thus, each of the pixel signals is stored on two capacitors, and for pixel 103C these two stored pixel signals are referenced as stored pixel signals 103C' and 103C", respectively, and for pixel 103G they are stored pixel signals 103G' and 103G", and so on. Next, output switches of odd number SW3, SW5, SW7, SW9, SW11 and SW13 activate in consecutive order, which cause the signals from capacitors C1, C5, C9, C13, C17, and C21 to be alternately placed on line signals SIG1 and SIG3, and also simultaneously cause the signals from capacitors C3, C7, C11, C15, C19, and C23, which were stored during time period 2, to be alternately placed on line signals SIG2 and SIG4.

The signals which are placed on line signal SIG1 came from capacitors C1, C9, and C17, which were stored during time period 3, which in turn came from third-row pixels 103C, 103K, and 103S, which are all color CLR1 pixels. The signals on line signal SIG2 came from capacitors C3, C11, and C19, which were stored during time period 2, which in turn came from second-row pixels 103B, 103J, and 103R, which are all color CLR2 pixels. Thus, at the points during time period 3 when switch sets SW3, SW7, and SW11 activate, the line signals SIG1 and SIG2 simultaneously contain signals from pixels 103C and 103B, then 103K and 103J, and then 103S and 103R, respectively. These are all simultaneous readings of third-row color CLR1 pixels with adjacent second-row color CLR2 pixels, as is the goal of the system.

Similarly, the signals on line signal SIG3, which are being placed at alternating times from the simultaneous signals on line signals SIG1 and SIG2, came from capacitors C5, C13, and C21, which were stored during time period 3, which in turn came from third-row pixels 103G, 103O, and 103W, which are all color CLR3 pixels. The signals on line signal SIG4 came from capacitors C7, C15, and C23, which were stored during time period 2, which in turn came from second-row pixels 103F, 103N, and 103V, which are all color CLR4 pixels. Thus, at the points during time period 3 when the switch sets SW5, SW9, and SW13 activate, the line signals SIG3 and SIG4 simultaneously compare signals from pixels 103G and 103F, then 103O and 103N, and then 103W and 103V, respectively. These are all simultaneous readings of third-row color CLR3 pixels with adjacent second-row color CLR4 pixels, as is the goal of the system. Thus, the complete output during time period 3 is simultaneous readings of third-row color CLR1 pixels with adjacent second-row color CLR2 pixels on line signals SIG1 and SIG2, alternating with simultaneous readings of third-row color CLR3 pixels with adjacent second-row color CLR4 pixels on line signals SIG3 and SIG4, in consecutive order of the pixels in FIGURE 5A moving from left to right.

During time period 4 (not shown), the process repeats as it did during time period 2, so as to allow simultaneous readings of third-row color CLR1 pixels with adjacent fourth-row color CLR2 pixels on line signals SIG1 and SIG2, alternating with simultaneous readings of third-row color CLR3 pixels with adjacent fourth-row color CLR4 pixels on line signals SIG3 and SIG4, in consecutive order of the pixels in FIGURE 5A moving from left to right.

FIGURES 7A and 7B illustrate an alternate embodiment of the present invention. FIGURE 7A is identical to FIGURE 5A, with the exception that a new fifth row of pixels has been added, as is needed for the timing descriptions of FIGURES 8A, 8B, 11A, and 11B, as described below. The new fifth row of pixels has been designated as pixels 103Y, 103Z, 103a, 103b, 103c, and 103d, running from left to right. As was described for FIGURES 5A and 5B above, FIGURE 7B is coupled to a pixel array such as that shown in FIGURE 7A, such that signal line SIG1 ultimately carries color CLR1 signals, signal line SIG2 carries color CLR2 signals, signal line SIG3 carries color CLR3 signals, and signal line SIG4 carries color CLR4 signals.

The circuitry of FIGURE 7B may generally be referred to as an interlace reading structure. In general, an interlace reading structure performs separate even and odd field reading operations, as will be described in more detail below. FIGURE 7B is similar to FIGURE 5B, except that only two capacitors are associated with each column of the six column pixel array, rather than four capacitors, as was shown in FIGURE 5B. As was described previously with reference to FIGURE 5B, signal amplifiers 205 may be charge amplifiers or voltage amplifiers, and the pixels may be active or passive, and there may also be sample buffers inserted after the capacitors. For purposes of illustration, the numbering scheme of the capacitors of FIGURE 5B has been maintained, with the even numbered capacitors having been removed. Thus, the first column has capacitors C1 and C3 associated with it, the second column has capacitors C5 and C7 associated with it, and so on until the sixth column, which has the capacitors C21 and C23 associated with it. As a result, only the odd numbered switches SW3, SW5, SW7, SW9, SW11, and SW13, which are coupled to the odd numbered capacitors, are needed for switching the signals from the capacitors. As was described for FIGURE 5B, signal lines SIG1 and SIG2 receive the outputs from the first, third, and fifth columns, while signal lines SIG3 and SIG4 receive the outputs from the second, fourth, and sixth columns.

The operation of the reading structure of FIGURES 7A and 7B is illustrated by the timing diagrams shown in FIGURES 8A, 8B, and 9. FIGURES 8A and 8B are somewhat similar to FIGURE 6, except that FIGURE 8A shows timing diagrams for an even field reading operation and FIGURE 8B shows timing diagrams for an odd field reading operation. FIGURE 9 shows the overall timing diagrams for both FIGURES 8A and 8B for one frame of TV timing.

As shown in FIGURE 8A, an H-SYNC signal synchronizes the reading times of the processing circuitry. At the beginning of time period 1, the pixel control signal P 1 goes high at the same time as switch set SW1. This causes the signals from the first row of pixels, including pixels 103A, 103E, 103I, 103M, 103Q, and 103U, to be amplified by signal amplifiers 205 and be stored on the capacitors C1, C5, C9, C13, C17 and C21, respectively. Next, the pixel control signal P2 goes high at the same time as switch set SW2. This causes the signals from the second row of pixels, including pixels 103B, 103F, 103J, 103N, 103R, and 103V to be amplified by signal amplifiers 205 and be stored on capacitors C3, C7, C11, C15, C19, and C23, respectively. Next, the output switches SW3, SW5, SW7, SW9, SW11, and SW13 are activated in consecutive order, which causes the signals from adjacent pixels that were stored on the capacitors to be simultaneously placed on pairs of the signal lines SIG1 and SIG2, or SIG3 and SIG4. It will be noted that signal line SIG1 receives all of the color CLR1 pixel signals (from pixels 103A, 103I, and 103Q), while signal line SIG2 receives all of the color CLR2 pixel signals (from pixels 103B, 103J, and 103R). Also, signal line SIG3 receives all of the color CLR3 pixel signals (from pixels 103E, 103M, and 103U), while signal line SIG4 receives all of the color CLR4 pixel signals (from pixels 103F, 103N, and 103V). In this manner, during time period 1, the entire first row of pixels is read out onto signal lines SIG1 and SIG3, while the entire second row of pixels is read out onto signal lines SIG2 and SIG4. This accomplishes the goal of the system by simultaneously reading out first-row pixels with adjacent second-row pixels, similar to as was described for FIGURE 6, above, during time period 2.

As illustrated in FIGURE 8A, during time period 2, the process that occurred during time period 1 repeats, except that during time period 2, pixel control signal P3 goes high at the same time as switch set SW1, and thereafter pixel control signal P4 goes high at the same time as switch set SW2. This causes the pixel signals from the third and fourth rows of pixels to be stored on the capacitors in the same manner as the first and second rows during time period 1. Switches SW3, SW5, SW7, SW9, SW11, and SW13 are then again activated in consecutive order, which causes the signals from adjacent pixels in rows three and four to be simultaneously read out onto pairs of signal lines SIG1 and SIG2, or SIG3 and SIG4.

The timing diagrams of FIGURE 8B for the odd field reading operation are similar to those of FIGURE 8A for the even field reading operation, with the exception that the pixel control signals are operated in a different order. During time period 1 of FIGURE 8B, the pixel control signal P3 goes high at the same time as switch set SW1, and thereafter pixel control signal P2 goes high at the same time as switch set SW2. Switches SW3, SW5, SW7, SW9, SW11, and SW13 are then activated in consecutive order. This causes the pixel signals from adjacent pixels in the third and second rows of the pixel array to be read out simultaneously on pairs of signal lines SIG1 and SIG2, or SIG3 and SIG4.

The process repeats in time period 2 of FIGURE 8B, except that pixel control signal P5 goes high at the same time as switch set SW1, after which pixel control signal P4 goes high at the same time as switch set SW2. Switches SW3, SW5, SW7, SW9, SW11, and SW13 are then activated in consecutive order. This causes pixel signals from adjacent pixels in rows five and four of the pixel array to be simultaneously read out on pairs of signal lines SIG1 and SIG2 or SIG3 and SIG4.

FIGURE 9 illustrates the overall timing operations for FIGURES 8A and 8B as coordinated for one frame of TV timing. In the example of FIGURE 9, there are assumed to be approximately 480 rows of pixels in the pixel array that is being read out, thus requiring approximately 240 periods in each of the even and odd fields. As illustrated, a control signal V-SYNC first coordinates the reading out of the even field, and then coordinates the reading out of the odd field. The even field and the odd field combine to form one frame of TV timing.

As described above, the reading operation for the timing diagrams of FIGURES 8A and 8B for the interlace structure differs from that of the timing diagrams for FIGURE 6 for a non-interlace structure, in that in FIGURES 8A and 8B each pixel signal only needs to be stored once, whereas in FIGURE 6 each pixel signal needs to be stored twice. This is because in FIGURE 6, for a non-interlace structure, each pixel is compared first to the adjacent pixel in the row before it, and then in the next timing period is compared to the adjacent pixel in the row after it. Thus, row 1 is first compared to row 2, then row 2 is compared to row 3, then row 3 is compared to row 4, and so on. In contrast, in FIGURES 8A and 8B, for an interlace reading structure each pixel is only compared to an adjacent pixel for a given even or odd field reading. Thus, in the even field, row 1 is compared to row 2, then row 3 is compared to row 4, then row 5 is compared to row 6, and so on, while for the odd field, row 2 is compared to row 3, then row 4 is compared to row 5, and so on. Thus, in both non-interlace and interlace reading structures, each pixel signal is stored twice, although in the non-interlace structure it is stored twice at the same time, while in the interlace structure it is stored once during the even field and once during the odd field. As a result, the circuitry of FIGURE 7B only requires half as many storage capacitors as are required for FIGURE 5B.

Another embodiment of the present invention is illustrated in FIGURE 10. FIGURE 10 illustrates an interlace circuit that is somewhat similar to FIGURE 7B in that only half the number of capacitors of FIGURE 5B are required. FIGURE 10 differs from FIGURE 7B in that only two reading channel signal lines, SIG1 and SIG2, are used rather than the four reading channel signal lines SIG1-SIG4 that were used in FIGURE 7B. Thus, in FIGURE 10, all of the switches SW3, SW5, SW7, SW9, SW11, and SW13 are coupled only to signal lines SIG1 and SIG2. As a result, the signals from all of the pixels 103 are placed on either signal line SIG1 or signal line SIG2.

FIGURES 11A and 11B illustrate the even and odd field timing diagrams for the circuit of FIGURE 10. The timing for the H-SYNC, pixel control signals P1-P4, and switches SW1, SW2, SW3, SW5. SW7, SW9, SW11, and SW13 are identical to those for the even and odd fields of FIGURES 8A and 8B.

As illustrated in FIGURE 11 A, during time period 1, the pixel signals from the entire first row of pixels (from pixels 103A, 103E, 103I, 103M, 103Q, and 103U) are read out onto signal line SIG1, and the signals from the entire second row of adjacent pixels (from pixels 103B, 103F, 103J, 103N, 103R, and 103V) are simultaneously read out onto signal line SIG2. During time period 2, adjacent pixels from the third and fourth rows of pixels are simultaneously read out onto the pair of signal lines SIG1 and SIG2. FIGURE 11B repeats this process, except for reading out the third and second rows of pixels during time period 1, and the fifth and fourth rows of pixels during time period 2.

Thus, FIGURES 5B, 7B, and 10 all illustrate various embodiments of the invention that allow two or more rows of pixels to be simultaneously read out, using technology such as capacitors or other storage cells that are external to the pixels but are also easily fabricated on a MOS chip. The circuitry of FIGURE 7A with four reading channels has several advantages over the circuitry of FIGURE 10 which has only two reading channels. As described above, with four reading channels each of the four colors of the pixel array may be directed to a separate reading channel. This structure allows the color processing circuits to be dramatically simplified over the two reading channel structure. In the two-channel reading structure, each channel reads two colors, which must then be separated before performing color processing.

Another advantage of the circuitry of FIGURE 7B over that of FIGURE 10 is that the speed requirement is cut in half This is because with four channels instead of two each pixel signal can stay on a respective channel for twice as long, and achieve the same overall readout rate. For example, as can be seen for signal line SIG1 during time period 1 in FIGURE 8A, the signal from pixel 103A is placed on signal line SIG1 when switch SW3 goes high, but is not removed until switch SW7 goes high. In contrast, as shown in FIGURE 11A during time period 1, the signal from pixel 103A is placed on signal line SIG1 when switch SW3 goes high and is removed when switch SW5 goes high Thus, the pixel signal from pixel 103A is able to remain on signal line SIG1 twice as long in FIGURE 8A as it is in FIGURE 11A.

FIGURE 12 illustrates an alternate embodiment of the present invention. FIGURE 12 is similar to FIGURE 5A, with the exception that each row of the pixel array has been doubled so as to create the high-sensitivity interlace color structure, as will be described in more detail below. Each row of the pixel array of FIGURE 5A is shown in FIGURE 12 to be repeated in two separate rows, the first row being designated as an even row and the second row being designated as an odd row. Thus, the first row from FIGURE 5A which included pixels 103A, 103E, 103I, 103M, 103Q, and 103U, now in FIGURE 12 is shown as having an even row including pixels 103A_e, 103E_e, 103I_e, 103M_e, 103Q_e, and 103U_e (the subscript "e" designates "even"), and an odd row including pixels 103A_o, 103E_o, 103I_o, 103M_o, 103Q_o, and 103U_o (the subscript "o" designates "odd"). Similarly, the next two rows include pixels 103B_e, 103F_e, 103J_e, 103N_e, 103R_e, and 103V_e; and pixels 103B_o, 103F_o, 103J_o, 103N_o, 103R_o, and 103V_o, respectively, and the next two rows include pixels 103C_e, 103G_e, 103K_e, 1030_e, 103S_e, and 103W_e; and 103C_o, 103G_o,103K_o, 103O_o, 103S_o, and 103W_o, respectively. Similarly, the control signals for reading out the rows have even and odd designations, including control signals P1_e and P1_o for the first and second rows, respectively, control signals P2_e and P2_o for the third and fourth rows, respectively, and control signals P3_e and P3_o for the fifth and sixth rows, respectively. The number of rows and columns shown in FIGURE 12 are for purposes of illustration only, as an actual embodiment could have different numbers of rows and columns.

As illustrated in FIGURE 12, the color designations that were given for each of the pixels from the array of FIGURE 5A have also been doubled with respect to the pixel structure of FIGURE 12. Thus, the pixels of the first and second rows are altematingly designated from left to right as being for colors CLR1 and CLR3, while the pixels from the third and fourth rows are altematingly designated as being for colors CLR2 and CLR4, and the pixels from the fifth and sixth rows are altematingly designated as being for colors CLR1 and CLR3. Additional rows would continue in this pattern.

The pixel array of FIGURE 12 is used in combination with the reading structure of FIGURE 5B as an interlace reading structure in that separate even and odd field reading operations are performed, as will be described below with respect to FIGURES 13A and 13B. FIGURES 13A and 13B illustrate the even and odd field timing diagrams for the pixel array and reading structure of FIGURE 12 as used in combination with the reading structure of FIGURE 5B. All of the timing signals shown in FIGURES 13A and 13B are similar to the timing signals illustrated previously in FIGURE 6. The primary difference between the timing signals for FIGURES 13A and 13B and FIGURE 6 is that while in FIGURE 6 signals from pixels from adjacent rows were simultaneously placed on pairs of lines so that they could be further processed, in FIGURES 13A and 13B signals from pixels from rows that are separated by a single row from one another are simultaneously placed on pairs of lines so that they can be further processed. Thus, while in FIGURE 6 signals were simultaneously read out from the first and second rows and then the second and third rows, in FIGURE 13A, signals are read out from the first and third rows and then the third and fifth rows, while in FIGURE 13B, signals are read out from the second and fourth rows and then the fourth and sixth rows, as will be described in more detail below.

As shown in FIGURE 13A, an H-SYNC signal synchronizes the reading times of the processing circuitry. FIGURE 9 illustrates the overall TV timing. At the beginning of time period 1, the pixel control signal P1_e goes high at the same time as switch set SW1. This causes the signals from the first row of pixels, including pixels 103A_e, 103E_e, 103I_e, 103M_e, 103Q_e, and 103U_e, to be amplified by signal amplifiers 205 and be stored on capacitors in sets of two. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103A_e' and 103A_e" for pixel 103A_e, stored pixel signals 103E_e' and 103E_e" for pixel 103E_e, and so on.

Next, output switches of odd number SW3, SW5, SW7, SW9, SW11, and SW13 are activated in consecutive sequential order, which causes the signals from the first row to be read sequentially. In this embodiment, the signals which are placed on line signal SIG1 are all color CLR1 pixels. The signals on line signal SIG3 are all color CLR3 pixels. Thus, line signal SIG1 is receiving first row color CLR1 signals and line signal SIG3 is receiving first row color CLR3 signals.

At the beginning of time period 2, the pixel control signal P2_e goes high at the same time as switch set SW2. This causes the signals from the third row of pixels 103B_e, 103F_e, 103J_e, 103N_e, 103R_e, and 103V_e (which include color CLR2 and color CLR4 pixels) to be amplified by signal amplifiers 205, and be stored on capacitors in sets of two. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103B_e' and 103B_e", respectively, for pixel 103B_e, stored pixel signals 103F_e' and 103F_e" for pixel 103F_e, and so on. Next, output switches of even number SW4, SW6, SW8, SW10, SW12, and SW14 activate in consecutive order, which cause the signals from the third row to be alternately placed on line signals SIG2 and SIG4, and also simultaneously cause the signals from the first row, which were stored during time period 1, to be alternately placed on line signals SIG1 and SIG3.

The signals that are placed on line signal SIG1 are all color CLR1 pixels. The signals on line signal SIG2 are all color CLR2 pixels. Thus, at the points in time period 2 when the switch sets SW4, SW8, and SW12 activate, the line signals SIGI and SIG2 simultaneously contain signals from pixels 103A_e and 103B_e, then 103I_e and 103J_e, and then 103Q_e and 103R_e, respectively. These are all simultaneous readings of first-row color CLR1 pixels with third-row color CLR2 pixels that are each separated by a single second-row pixel, as is the goal of the system.

Similarly, the signals on line signal SIG3 are all color CLR3 pixels. The signals on line signal SIG4 are all color CLR4 pixels. Thus, at the points during time period 2 when switch sets SW6, SW10, and SW14 activate, line signals SIG3 and SIG4 simultaneously contain signals from pixels 103E_e and 103F_e, then 103M_e and 103N_e, and then 103U_e and 103V_e, respectively. These are all simultaneous readings of first-row color CLR3 pixels with third-row color CLR4 pixels that are separated by a single second-row pixel, as is the goal of the system. Thus, the complete output during time period 2 is simultaneous readings of first row color CLR1 pixels with third-row color CLR2 pixels on line signals SIG1 and SIG2, respectively, alternating with simultaneous readings of first-row color CLR3 pixels with third-row color CLR4 pixels on line signals SIG3 and SIG4, respectively, in consecutive order of the pixels in FIGURE 12 moving from left to right.

The process similarly repeats during time period 3 such that the complete output during time period 3 is simultaneous readings of fifth-row color CLR1 pixels with third-row color CLR2 pixels on line signals SIG1 and SIG2, alternating with simultaneous readings of fifth-row color CLR3 pixels with third-row color CLR4 pixels on line signals SIG3 and SIG4, in consecutive order of the pixels in FIGURE 12 moving from left to right.

The timing signals of FIGURE 13B are identical to those of FIGURE 13A, with the exception that the odd designated rows including the second, fourth, and sixth rows of FIGURE 12 are being read out. Thus, the complete output during time period 2 of FIGURE 13B is the simultaneous readings of second row color CLR1 pixels with fourth-row color CLR2 pixels on line signals SIG1 and SIG2, alternating with simultaneous readings of second row color CLR3 pixels with fourth-row color CLR4 pixels on line signals SIG3 and SIG4, in consecutive order of the pixels in FIGURE 12 moving from left to right. Similarly, the complete output during time period 3 is simultaneous readings of sixth-row color CLR1 pixels with fourth-row color CLR2 pixels on line signals SIG1 and SIG2, alternating with simultaneous readings of sixth-row CLR3 pixels with fourth-row color CLR4 pixels on line signals SIG3 and SIG4, in consecutive order of the pixels in FIGURE 12 moving from left to right.

By doubling the color structure of the rows in the array, the high-sensitivity scheme illustrated in FIGURES 12, 13A, and 13B is able to have the even and odd fields read complementary sets of every other line, rather than requiring each field to read every line. Because each field is thereby only reading half as many lines as would otherwise be required, the maximum exposure time for the pixels, which previously only allowed one field to be read, can now allow two fields to be read in the same amount of time. Alternatively, the exposure time of the pixels for reading each line could be doubled. The end result is that the reading sensitivity of the device as a whole is essentially doubled. In addition, this reading scheme allows the horizontal resolution to remain the same, while the lower vertical resolution that results from reading only every other line can be effectively compensated for by using vertical aperture correction. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the scope of the invention. For example, in the reading structure of FIGURE 5B, by altering the timing and placement of the switches SW3 to SW14, signal lines SIG1 to SIG4 could even be for combinations of colors from more than one pixels, such as SIG1 being for Cy+G, SIG2 being for Ye+Mg, SIG3 being for Cy+Mg and SIG4 being for Ye+G, where Cy is cyan, G is green, Ye is yellow, and Mg is magenta, as is used in many CCD color image sensors.

As another example, the description herein has been made in terms of reading adjacent rows of a pixel array. However, it can be appreciated that adjacent columns may be read just as easily, the distinction between a row and a column being merely semantic for a pixel array. Also, although the storage devices used to store the pixel signals are capacitors, it can be appreciated that any-circuit element that has memory ability may be used, such as DRAMs, SRAMs, EEPROMS, and the like. Also, the structure described herein can easily be applied to more lines than are shown. While color TV processing usually uses two-line structures, other applications may use many more. Also, while the high-sensitivity interlace color structure embodiment has been illustrated as reading every other row during the even and odd fields using the reading structure of FIGURE 5B, the reading could be taken from differently spaced rows or with different reading structures while still applying the same general principles. Thus, the invention should not be limited to the preferred embodiments described herein, but should be limited only by the claims below.